mibuild: make resolve_signals public

diff --git a/mibuild/altera_quartus.py b/mibuild/altera_quartus.py
index 6939eb67dc8d9774623f9ba76c58ac54e9484e63..348596a51af3ae952fa899934f22afe242188bdd 100644 (file)
--- a/mibuild/altera_quartus.py
+++ b/mibuild/altera_quartus.py
@@ -81,7 +81,7 @@ class AlteraQuartusPlatform(GenericPlatform):
                self.finalize(fragment)
 
                v_src, vns = self.get_verilog(fragment)
-               named_sc, named_pc = self._resolve_signals(vns)
+               named_sc, named_pc = self.resolve_signals(vns)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
                sources = self.sources + [(v_file, "verilog")]

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 6bdcbebc1a52398f4e6a11a3eb9d1baaf1b3dcce..b57ba59bf61b1425987a50d4f823cd9b3818edab 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -240,7 +240,7 @@ class GenericPlatform:
        def add_verilog_include_path(self, path):
                self.verilog_include_paths.append(os.path.abspath(path))
 
-       def _resolve_signals(self, vns):
+       def resolve_signals(self, vns):
                # resolve signal names in constraints
                sc = self.constraint_manager.get_sig_constraints()
                named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index d681fbe526f277e7562e1168fd6f36cf00d1839f..d291f72f03e82af5f8cf2524d3e185277e8c116a 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -144,7 +144,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
 
                if mode == "xst" or mode == "yosys":
                        v_src, vns = self.get_verilog(fragment)
-                       named_sc, named_pc = self._resolve_signals(vns)
+                       named_sc, named_pc = self.resolve_signals(vns)
                        v_file = build_name + ".v"
                        tools.write_to_file(v_file, v_src)
                        sources = self.sources + [(v_file, "verilog")]
@@ -162,7 +162,7 @@ class XilinxISEPlatform(xilinx_common.XilinxGenericPlatform):
 
                if mode == "edif" or mode == "mist":
                        e_src, vns = self.get_edif(fragment)
-                       named_sc, named_pc = self._resolve_signals(vns)
+                       named_sc, named_pc = self.resolve_signals(vns)
                        e_file = build_name + ".edif"
                        tools.write_to_file(e_file, e_src)
                        isemode = "edif"

diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index afeb68171c7a684c52f694aeccc397cf28f6d5f6..d55c930e1c321b57e89d3c304575121639ef2e97 100644 (file)
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
@@ -103,7 +103,7 @@ class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
                        fragment = fragment.get_fragment()
                self.finalize(fragment)
                v_src, vns = self.get_verilog(fragment)
-               named_sc, named_pc = self._resolve_signals(vns)
+               named_sc, named_pc = self.resolve_signals(vns)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
                sources = self.sources + [(v_file, "verilog")]