---------- Begin Simulation Statistics ----------
-sim_seconds 1.903548 # Number of seconds simulated
-sim_ticks 1903548166500 # Number of ticks simulated
-final_tick 1903548166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.902683 # Number of seconds simulated
+sim_ticks 1902682770000 # Number of ticks simulated
+final_tick 1902682770000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123505 # Simulator instruction rate (inst/s)
-host_op_rate 123505 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4187441182 # Simulator tick rate (ticks/s)
-host_mem_usage 303204 # Number of bytes of host memory used
-host_seconds 454.59 # Real time elapsed on the host
-sim_insts 56143492 # Number of instructions simulated
-sim_ops 56143492 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 879488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24796480 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2649664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 101696 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 559552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28986880 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 879488 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 101696 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 981184 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7925376 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7925376 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13742 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 387445 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41401 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1589 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8743 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 452920 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 123834 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 123834 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 462026 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13026453 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1391961 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 53424 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 293952 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15227815 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 462026 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 53424 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 515450 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4163475 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4163475 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4163475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 462026 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13026453 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1391961 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 53424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 293952 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19391291 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 346033 # number of replacements
-system.l2c.tagsinuse 65330.743124 # Cycle average of tags in use
-system.l2c.total_refs 2608063 # Total number of references to valid blocks.
-system.l2c.sampled_refs 411178 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.342905 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 6380526000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 53708.225390 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5276.213951 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 6113.589929 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 198.792297 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 33.921558 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.819522 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.080509 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.093286 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.003033 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.000518 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.996868 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 970913 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 780748 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.data 39067 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1898398 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 832636 # number of Writeback hits
-system.l2c.Writeback_hits::total 832636 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 54 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 238 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 27 # number of SCUpgradeReq hits
+host_inst_rate 192931 # Simulator instruction rate (inst/s)
+host_op_rate 192931 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6436506827 # Simulator tick rate (ticks/s)
+host_mem_usage 296908 # Number of bytes of host memory used
+host_seconds 295.61 # Real time elapsed on the host
+sim_insts 57032045 # Number of instructions simulated
+sim_ops 57032045 # Number of ops (including micro ops) simulated
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+system.physmem.bytes_read::cpu1.data 789824 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28940032 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 906816 # Number of instructions bytes read from this memory
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+system.physmem.bytes_inst_read::total 980800 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7895360 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7895360 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 14169 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 383103 # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
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+system.physmem.num_reads::cpu1.data 12341 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 452188 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 123365 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 123365 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 476599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12886327 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide 1393199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 38884 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 415111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15210119 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 476599 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 38884 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 515483 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4149593 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4149593 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4149593 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 476599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12886327 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide 1393199 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 38884 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 415111 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19359713 # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 345291 # number of replacements
+system.l2c.tagsinuse 65280.360301 # Cycle average of tags in use
+system.l2c.total_refs 2575351 # Total number of references to valid blocks.
+system.l2c.sampled_refs 410382 # Sample count of references to valid blocks.
+system.l2c.avg_refs 6.275497 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 6143524000 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 53635.672684 # Average occupied blocks per requestor
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+system.l2c.occ_blocks::cpu0.data 6042.958234 # Average occupied blocks per requestor
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+system.l2c.occ_percent::cpu0.data 0.092208 # Average percentage of cache occupancy
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+system.l2c.occ_percent::cpu1.data 0.001201 # Average percentage of cache occupancy
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+system.l2c.Writeback_hits::writebacks 812223 # number of Writeback hits
+system.l2c.Writeback_hits::total 812223 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 397 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 566 # number of UpgradeReq hits
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system.l2c.SCUpgradeReq_hits::cpu1.data 29 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::total 182105 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst 970913 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 949286 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.data 52634 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.inst 970913 # number of overall hits
-system.l2c.overall_hits::cpu0.data 949286 # number of overall hits
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-system.l2c.overall_hits::cpu1.data 52634 # number of overall hits
-system.l2c.overall_hits::total 2080503 # number of overall hits
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-system.l2c.ReadReq_misses::cpu1.data 887 # number of ReadReq misses
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-system.l2c.ReadReq_miss_latency::cpu1.data 48439997 # number of ReadReq miss cycles
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-system.l2c.ReadReq_accesses::total 2187544 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 832636 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 832636 # number of Writeback accesses(hits+misses)
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-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52070.814814 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53316.313823 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 54611.045096 # average ReadReq miss latency
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-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2354.990584 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1241.774676 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12139.534884 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2032.467532 # average SCUpgradeReq miss latency
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-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 55558.453677 # average ReadExReq miss latency
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-system.l2c.demand_avg_miss_latency::cpu0.inst 53243.888097 # average overall miss latency
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-system.iocache.demand_mshr_miss_latency::tsunami.ide 9338117976 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9338117976 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 9338117976 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9338117976 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide 41729 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 41729 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide 41729 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 41729 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11923998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11923998 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9325812806 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 9325812806 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 9337736804 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 9337736804 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 9337736804 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 9337736804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224447.871968 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 224447.871968 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223785.419287 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 223785.419287 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67367.220339 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67367.220339 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224437.158404 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 224437.158404 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223770.921997 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 223770.921997 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 9377828 # DTB read hits
-system.cpu0.dtb.read_misses 33360 # DTB read misses
-system.cpu0.dtb.read_acv 521 # DTB read access violations
-system.cpu0.dtb.read_accesses 633373 # DTB read accesses
-system.cpu0.dtb.write_hits 6221809 # DTB write hits
-system.cpu0.dtb.write_misses 7167 # DTB write misses
-system.cpu0.dtb.write_acv 341 # DTB write access violations
-system.cpu0.dtb.write_accesses 216042 # DTB write accesses
-system.cpu0.dtb.data_hits 15599637 # DTB hits
-system.cpu0.dtb.data_misses 40527 # DTB misses
-system.cpu0.dtb.data_acv 862 # DTB access violations
-system.cpu0.dtb.data_accesses 849415 # DTB accesses
-system.cpu0.itb.fetch_hits 1073423 # ITB hits
-system.cpu0.itb.fetch_misses 26403 # ITB misses
-system.cpu0.itb.fetch_acv 1051 # ITB acv
-system.cpu0.itb.fetch_accesses 1099826 # ITB accesses
+system.cpu0.dtb.read_hits 8304100 # DTB read hits
+system.cpu0.dtb.read_misses 28307 # DTB read misses
+system.cpu0.dtb.read_acv 549 # DTB read access violations
+system.cpu0.dtb.read_accesses 542239 # DTB read accesses
+system.cpu0.dtb.write_hits 5411904 # DTB write hits
+system.cpu0.dtb.write_misses 5987 # DTB write misses
+system.cpu0.dtb.write_acv 347 # DTB write access violations
+system.cpu0.dtb.write_accesses 182798 # DTB write accesses
+system.cpu0.dtb.data_hits 13716004 # DTB hits
+system.cpu0.dtb.data_misses 34294 # DTB misses
+system.cpu0.dtb.data_acv 896 # DTB access violations
+system.cpu0.dtb.data_accesses 725037 # DTB accesses
+system.cpu0.itb.fetch_hits 908718 # ITB hits
+system.cpu0.itb.fetch_misses 19910 # ITB misses
+system.cpu0.itb.fetch_acv 927 # ITB acv
+system.cpu0.itb.fetch_accesses 928628 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 120667689 # number of cpu cycles simulated
+system.cpu0.numCycles 102599658 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 13362893 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 11185412 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 402804 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 9622475 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 5627170 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 11825647 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 9917652 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 342692 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 8240217 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 5044056 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 884758 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 37477 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 30221705 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 67571030 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 13362893 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 6511928 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 12734942 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1928304 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 41309111 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 28714 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 205220 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 305503 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 8304621 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 277902 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 86063714 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.785128 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.113854 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 768623 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 31919 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 23566044 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 60418395 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 11825647 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5812679 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11434253 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1624928 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 35275815 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 31363 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 170412 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 309547 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7444211 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 224420 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 71849758 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.840899 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.174060 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 73328772 85.20% 85.20% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 837915 0.97% 86.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1666262 1.94% 88.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 768356 0.89% 89.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2658731 3.09% 92.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 585060 0.68% 92.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 622966 0.72% 93.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 967713 1.12% 94.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4627939 5.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 60415505 84.09% 84.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 744936 1.04% 85.12% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1526054 2.12% 87.25% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 669496 0.93% 88.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2482176 3.45% 91.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 513952 0.72% 92.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 559997 0.78% 93.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 746719 1.04% 94.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4190923 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 86063714 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.110741 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.559976 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 31149327 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 41124977 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 11584676 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 985581 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1219152 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 571369 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 39493 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 66407813 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 120728 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1219152 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 32233219 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 16872016 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 20344281 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 10880828 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 4514216 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 62880643 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6942 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 700700 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1661735 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 42005938 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 76144064 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 75702119 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 441945 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 36517182 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 5488748 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1574453 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 239002 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 12018911 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 9888186 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6523659 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1201517 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 824194 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 55665948 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1995313 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 54317533 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 112244 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6696159 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 3338542 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1358752 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 86063714 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.631132 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.280124 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 71849758 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.115260 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.588875 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 24832568 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 34702410 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10423010 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 862232 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1029537 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 502827 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 32976 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 59359454 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 95150 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1029537 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 25748676 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14416729 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 17004300 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9792924 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3857590 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 56337606 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6610 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 598180 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1362975 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 37819724 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 68629747 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 68286150 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 343597 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 33121112 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4698612 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1343902 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 201432 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 10333121 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 8734327 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5677673 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1105299 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 704273 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 50005822 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1695696 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 48865145 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 103608 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5731519 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2860845 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1151664 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 71849758 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.680102 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.326568 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 61486843 71.44% 71.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 11432526 13.28% 84.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 5063556 5.88% 90.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3287093 3.82% 94.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2517985 2.93% 97.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1255115 1.46% 98.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 648079 0.75% 99.57% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 319509 0.37% 99.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 53008 0.06% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 50068220 69.68% 69.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 9955153 13.86% 83.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4454682 6.20% 89.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2911875 4.05% 93.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2358569 3.28% 97.08% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1157257 1.61% 98.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 610758 0.85% 99.54% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 286058 0.40% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 47186 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 86063714 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 71849758 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 73354 10.53% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 1 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 330176 47.38% 57.90% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 293358 42.10% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 80509 12.84% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 1 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.84% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 294043 46.91% 59.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 252280 40.25% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 3296 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 37287239 68.65% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 60152 0.11% 68.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.76% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 15662 0.03% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 1646 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9781142 18.01% 86.80% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6293081 11.59% 98.39% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 875315 1.61% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 2557 0.01% 0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 33918404 69.41% 69.42% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 54116 0.11% 69.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.53% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 12070 0.02% 69.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.55% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8648673 17.70% 87.25% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5478002 11.21% 98.47% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 750056 1.53% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 54317533 # Type of FU issued
-system.cpu0.iq.rate 0.450141 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 696889 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.012830 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 194880881 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 64065914 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 53156794 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 627031 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 303977 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 294706 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 54682626 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 328500 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 571695 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 48865145 # Type of FU issued
+system.cpu0.iq.rate 0.476270 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 626833 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.012828 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 169818867 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 57206555 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 47890608 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 491622 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 238128 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 232129 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 49232078 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 257343 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 523556 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1271953 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2828 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12731 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 517788 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1075506 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2442 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 11895 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 454594 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18545 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 107284 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18421 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 86028 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1219152 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 12163042 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 861940 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 61112544 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 659342 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 9888186 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6523659 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1757966 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 617572 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 9941 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12731 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 210191 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 389993 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 600184 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 53834482 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9436308 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 483050 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1029537 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10326104 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 769928 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 54791843 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 549393 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8734327 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5677673 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1493453 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 559696 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 5669 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 11895 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 183351 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 329192 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 512543 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 48451300 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8354077 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 413845 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3451283 # number of nop insts executed
-system.cpu0.iew.exec_refs 15679571 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 8587439 # Number of branches executed
-system.cpu0.iew.exec_stores 6243263 # Number of stores executed
-system.cpu0.iew.exec_rate 0.446138 # Inst execution rate
-system.cpu0.iew.wb_sent 53546468 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 53451500 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 26356174 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35593959 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3090325 # number of nop insts executed
+system.cpu0.iew.exec_refs 13784796 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7754310 # Number of branches executed
+system.cpu0.iew.exec_stores 5430719 # Number of stores executed
+system.cpu0.iew.exec_rate 0.472236 # Inst execution rate
+system.cpu0.iew.wb_sent 48208648 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 48122737 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24107105 # num instructions producing a value
+system.cpu0.iew.wb_consumers 32426814 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.442964 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.740468 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.469034 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.743431 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 7303960 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 636561 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 562819 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 84844562 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.633202 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.547709 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6216029 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 544032 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 479899 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 70820221 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.684637 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.594318 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 64556270 76.09% 76.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 8510919 10.03% 86.12% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4635841 5.46% 91.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2494817 2.94% 94.52% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1390539 1.64% 96.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 576056 0.68% 96.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 484846 0.57% 97.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 456978 0.54% 97.95% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1738296 2.05% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 52470926 74.09% 74.09% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7676401 10.84% 84.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4235846 5.98% 90.91% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2227139 3.14% 94.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1283042 1.81% 95.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 528527 0.75% 96.61% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 441494 0.62% 97.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 421867 0.60% 97.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1534979 2.17% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 84844562 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 53723778 # Number of instructions committed
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system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu0.commit.loads 8616233 # Number of loads committed
-system.cpu0.commit.membars 216543 # Number of memory barriers committed
-system.cpu0.commit.branches 8113778 # Number of branches committed
-system.cpu0.commit.fp_insts 292474 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 49705714 # Number of committed integer instructions.
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-system.cpu0.commit.bw_lim_events 1738296 # number cycles where commit BW limit reached
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system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu0.rob.rob_writes 123274808 # The number of ROB writes
-system.cpu0.timesIdled 1363780 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 34603975 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3686422279 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 50608732 # Number of Instructions Simulated
-system.cpu0.committedOps 50608732 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 50608732 # Number of Instructions Simulated
-system.cpu0.cpi 2.384325 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.384325 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.419406 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.419406 # IPC: Total IPC of All Threads
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-system.cpu0.int_regfile_writes 38607300 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 144193 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 146198 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1863622 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 886886 # number of misc regfile writes
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+system.cpu0.idleCycles 30749900 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3702120338 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 45684021 # Number of Instructions Simulated
+system.cpu0.committedOps 45684021 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 45684021 # Number of Instructions Simulated
+system.cpu0.cpi 2.245854 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.245854 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.445265 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.445265 # IPC: Total IPC of All Threads
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+system.cpu0.misc_regfile_writes 757779 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 984085 # number of replacements
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-system.cpu0.icache.total_refs 7264923 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 984594 # Sample count of references to valid blocks.
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-system.cpu0.icache.warmup_cycle 23948219000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.993322 # Average occupied blocks per requestor
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-system.cpu0.icache.occ_percent::total 0.996081 # Average percentage of cache occupancy
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 16224.396616 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 16224.396616 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16224.396616 # average overall miss latency
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+system.cpu0.icache.demand_avg_miss_latency::total 13884.448828 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13884.448828 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.overall_mshr_misses::total 984772 # number of overall MSHR misses
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-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13041683494 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 13041683494 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13243.353278 # average ReadReq mshr miss latency
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13243.353278 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13243.353278 # average overall mshr miss latency
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-system.cpu0.dcache.warmup_cycle 23750000 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.LoadLockedReq_misses::total 22429 # number of LoadLockedReq misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1221694 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1221694 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1221694 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1221694 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23357450000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23357450000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8081474275 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8081474275 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 163906000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 163906000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 39490500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 39490500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31438924275 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 31438924275 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31438924275 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 31438924275 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451861000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451861000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2167064498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2167064498 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3618925498 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3618925498 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128055 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128055 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050527 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050527 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088965 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088965 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.022756 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.022756 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.097070 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097070 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097070 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24141.094054 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24141.094054 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31797.423915 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31797.423915 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10747.934426 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10747.934426 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 9721.935007 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 9721.935007 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25733.877939 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25733.877939 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1298594 # DTB read hits
-system.cpu1.dtb.read_misses 11503 # DTB read misses
-system.cpu1.dtb.read_acv 6 # DTB read access violations
-system.cpu1.dtb.read_accesses 332098 # DTB read accesses
-system.cpu1.dtb.write_hits 765153 # DTB write hits
-system.cpu1.dtb.write_misses 2957 # DTB write misses
-system.cpu1.dtb.write_acv 47 # DTB write access violations
-system.cpu1.dtb.write_accesses 125840 # DTB write accesses
-system.cpu1.dtb.data_hits 2063747 # DTB hits
-system.cpu1.dtb.data_misses 14460 # DTB misses
-system.cpu1.dtb.data_acv 53 # DTB access violations
-system.cpu1.dtb.data_accesses 457938 # DTB accesses
-system.cpu1.itb.fetch_hits 372513 # ITB hits
-system.cpu1.itb.fetch_misses 8563 # ITB misses
-system.cpu1.itb.fetch_acv 155 # ITB acv
-system.cpu1.itb.fetch_accesses 381076 # ITB accesses
+system.cpu1.dtb.read_hits 2472786 # DTB read hits
+system.cpu1.dtb.read_misses 14686 # DTB read misses
+system.cpu1.dtb.read_acv 33 # DTB read access violations
+system.cpu1.dtb.read_accesses 413814 # DTB read accesses
+system.cpu1.dtb.write_hits 1645990 # DTB write hits
+system.cpu1.dtb.write_misses 3399 # DTB write misses
+system.cpu1.dtb.write_acv 61 # DTB write access violations
+system.cpu1.dtb.write_accesses 158815 # DTB write accesses
+system.cpu1.dtb.data_hits 4118776 # DTB hits
+system.cpu1.dtb.data_misses 18085 # DTB misses
+system.cpu1.dtb.data_acv 94 # DTB access violations
+system.cpu1.dtb.data_accesses 572629 # DTB accesses
+system.cpu1.itb.fetch_hits 546471 # ITB hits
+system.cpu1.itb.fetch_misses 10636 # ITB misses
+system.cpu1.itb.fetch_acv 251 # ITB acv
+system.cpu1.itb.fetch_accesses 557107 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 10640951 # number of cpu cycles simulated
+system.cpu1.numCycles 20144234 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 1701905 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 1402674 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 62577 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 862370 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 552113 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 3332472 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 2756183 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 108633 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 2168857 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 1160511 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 115027 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 5500 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 3435420 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 8139615 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 1701905 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 667140 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 1472350 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 326710 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 4537469 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 24627 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 73138 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 47601 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1039363 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 39149 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 9806707 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.830005 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.196976 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 228547 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 10150 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 7838813 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 15883595 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 3332472 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1389058 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2861385 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 534677 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 7961253 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 27792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 84864 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 61219 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 2 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1925840 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 71197 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 19177134 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.828257 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.199800 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 8334357 84.99% 84.99% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 78230 0.80% 85.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 173812 1.77% 87.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 130927 1.34% 88.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 215769 2.20% 91.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 90418 0.92% 92.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 98526 1.00% 93.02% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 62686 0.64% 93.66% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 621982 6.34% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 16315749 85.08% 85.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 188313 0.98% 86.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 313367 1.63% 87.70% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 233008 1.22% 88.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 393584 2.05% 90.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 151826 0.79% 91.75% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 167771 0.87% 92.63% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 278696 1.45% 94.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 1134820 5.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 9806707 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.159939 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.764933 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 3510066 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 4639401 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 1367694 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 78184 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 211361 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 75357 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 4832 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 7943726 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 14591 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 211361 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 3646380 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 524692 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 3638231 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 1300485 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 485556 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 7343826 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 139 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 57550 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 136110 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 4921664 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 8958013 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 8905584 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 52429 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 3978815 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 942849 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 306458 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 22346 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 1365387 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 1395502 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 827989 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 138090 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 96967 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 6484639 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 311488 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 6173957 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 24546 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1207593 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 679802 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 236614 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 9806707 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.629565 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.304884 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 19177134 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.165431 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.788493 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 7716271 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 8310209 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2661595 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 156637 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 332421 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 147192 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 9531 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 15577857 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 28018 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 332421 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7986115 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 672083 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6791538 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2542197 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 852778 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 14454091 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 131 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 86206 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 218054 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 9478411 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 17286766 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 17086477 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 200289 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 8045295 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1433108 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 570111 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 60569 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2590157 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2624799 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1738404 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 257229 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 149585 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 12667252 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 630653 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 12308685 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 34992 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1859186 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 963032 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 447479 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 19177134 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.641842 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.313805 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 7075152 72.15% 72.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 1257607 12.82% 84.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 548751 5.60% 90.57% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 366543 3.74% 94.30% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 274418 2.80% 97.10% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 146525 1.49% 98.60% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 78833 0.80% 99.40% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 55100 0.56% 99.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 3778 0.04% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 13743416 71.67% 71.67% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2506419 13.07% 84.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 1066336 5.56% 90.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 706714 3.69% 93.98% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 606260 3.16% 97.14% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 273557 1.43% 98.57% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 174545 0.91% 99.48% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 89739 0.47% 99.95% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 10148 0.05% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 9806707 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 19177134 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2937 2.09% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.09% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 77829 55.26% 57.34% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 60078 42.66% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 4629 1.86% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 131937 52.95% 54.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 112626 45.20% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 3992 0.06% 0.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 3816770 61.82% 61.89% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 10118 0.16% 62.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.05% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 10095 0.16% 62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 1996 0.03% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 1354962 21.95% 84.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 784960 12.71% 96.91% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess 191064 3.09% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 7659302 62.23% 62.27% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 19564 0.16% 62.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 14781 0.12% 62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.54% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.56% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2596890 21.10% 83.66% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1675725 13.61% 97.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess 335297 2.72% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 6173957 # Type of FU issued
-system.cpu1.iq.rate 0.580207 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 140844 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.022813 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 22242262 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 7966601 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 5994284 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 77749 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 38725 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 37333 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 6270612 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 40197 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 68178 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 12308685 # Type of FU issued
+system.cpu1.iq.rate 0.611028 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 249192 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020245 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 43789272 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 15018387 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 11932725 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 289415 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 141077 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 136872 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 12402102 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 151024 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 115183 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 253497 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 450 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1694 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 109535 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 382493 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 2469 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 155910 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 346 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 8387 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 398 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 20099 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 211361 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 294243 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 17071 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 7057887 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 102198 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 1395502 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 827989 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 289869 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 6102 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3806 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1694 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 30581 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 71547 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 102128 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 6103512 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 1313696 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 70445 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 332421 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 409059 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 59053 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 13963733 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 192284 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2624799 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1738404 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 567278 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 49311 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2791 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 2469 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 54746 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 126604 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 181350 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 12183266 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2497630 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 125418 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 261760 # number of nop insts executed
-system.cpu1.iew.exec_refs 2085126 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 894247 # Number of branches executed
-system.cpu1.iew.exec_stores 771430 # Number of stores executed
-system.cpu1.iew.exec_rate 0.573587 # Inst execution rate
-system.cpu1.iew.wb_sent 6061366 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 6031617 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 2917806 # num instructions producing a value
-system.cpu1.iew.wb_consumers 4086073 # num instructions consuming a value
+system.cpu1.iew.exec_nop 665828 # number of nop insts executed
+system.cpu1.iew.exec_refs 4154589 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1827055 # Number of branches executed
+system.cpu1.iew.exec_stores 1656959 # Number of stores executed
+system.cpu1.iew.exec_rate 0.604802 # Inst execution rate
+system.cpu1.iew.wb_sent 12107744 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 12069597 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 5640555 # num instructions producing a value
+system.cpu1.iew.wb_consumers 7931807 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.566831 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.714086 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.599159 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.711131 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1232464 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 74874 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 96289 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 9595346 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.599743 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.518608 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1943114 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 183174 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 170211 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 18844713 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.633421 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.575988 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 7360615 76.71% 76.71% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1091727 11.38% 88.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 382276 3.98% 92.07% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 236221 2.46% 94.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 149500 1.56% 96.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 68368 0.71% 96.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 77096 0.80% 97.61% # Number of insts commited each cycle
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system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
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-system.cpu1.quiesceCycles 3796004491 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 5534760 # Number of Instructions Simulated
-system.cpu1.committedOps 5534760 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 5534760 # Number of Instructions Simulated
-system.cpu1.cpi 1.922568 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.922568 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.520138 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.520138 # IPC: Total IPC of All Threads
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-system.cpu1.icache.ReadReq_misses::total 115346 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 115346 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 115346 # number of overall misses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 16604.450948 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 16604.450948 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16604.450948 # average overall miss latency
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+system.cpu1.cpi_total 1.775131 # CPI: Total CPI of All Threads
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13350.681958 # average overall miss latency
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_misses::total 109308 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 109308 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 109308 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 109308 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 109308 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 1491398999 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::total 1491398999 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1491398999 # number of overall MSHR miss cycles
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-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105168 # mshr miss rate for overall accesses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13644.005919 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13644.005919 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13644.005919 # average overall mshr miss latency
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+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11540.321013 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11540.321013 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.LoadLockedReq_hits::total 16674 # number of LoadLockedReq hits
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-system.cpu1.dcache.LoadLockedReq_misses::total 1520 # number of LoadLockedReq misses
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 36517 # number of writebacks
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1211037987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1211037987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54734500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54734500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 40806500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 40806500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2539786487 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2539786487 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2539786487 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2539786487 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 686558000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 686558000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 717533000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 717533000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.047272 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.047272 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.037669 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.037669 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.123110 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.123110 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085561 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.085561 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.043441 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043441 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.043441 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12228.947320 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12228.947320 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21071.424617 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21071.424617 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8138.959108 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8138.959108 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9529.775806 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9529.775806 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15288.038133 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15288.038133 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 199157 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 71465 40.61% 40.61% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1927 1.10% 41.78% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 9 0.01% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 102444 58.21% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 175976 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 70100 49.28% 49.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.09% 49.37% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1927 1.35% 50.72% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 9 0.01% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 70091 49.27% 100.00% # number of times we switched to this ipl from a different ipl
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-system.cpu0.kern.ipl_ticks::0 1862744375000 97.86% 97.86% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 69542000 0.00% 97.86% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 583001500 0.03% 97.89% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 5982500 0.00% 97.89% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 40144359500 2.11% 100.00% # number of cycles we spent at this ipl
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-system.cpu0.kern.ipl_used::0 0.980900 # fraction of swpipl calls that actually changed the ipl
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+system.cpu0.kern.ipl_count::0 59752 40.24% 40.24% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_count::22 1927 1.30% 41.62% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 283 0.19% 41.81% # number of times we switched to this ipl
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+system.cpu0.kern.ipl_count::total 148505 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 58939 49.14% 49.14% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1927 1.61% 50.86% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 283 0.24% 51.09% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 58656 48.91% 100.00% # number of times we switched to this ipl from a different ipl
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+system.cpu0.kern.ipl_ticks::0 1864736682500 98.02% 98.02% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 62604500 0.00% 98.03% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 575436000 0.03% 98.06% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 137989000 0.01% 98.06% # number of cycles we spent at this ipl
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+system.cpu0.kern.ipl_used::0 0.986394 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684188 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.808394 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 8 3.65% 3.65% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.68% 12.33% # number of syscalls executed
-system.cpu0.kern.syscall::4 3 1.37% 13.70% # number of syscalls executed
-system.cpu0.kern.syscall::6 32 14.61% 28.31% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.46% 28.77% # number of syscalls executed
-system.cpu0.kern.syscall::17 8 3.65% 32.42% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.57% 36.99% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.74% 39.73% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.46% 40.18% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.37% 41.55% # number of syscalls executed
-system.cpu0.kern.syscall::33 6 2.74% 44.29% # number of syscalls executed
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-system.cpu0.kern.syscall::45 36 16.44% 61.64% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.37% 63.01% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.57% 67.58% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.57% 72.15% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.46% 72.60% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.74% 75.34% # number of syscalls executed
-system.cpu0.kern.syscall::71 23 10.50% 85.84% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.37% 87.21% # number of syscalls executed
-system.cpu0.kern.syscall::74 6 2.74% 89.95% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.46% 90.41% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.37% 91.78% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 4.11% 95.89% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.91% 96.80% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.91% 97.72% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.46% 98.17% # number of syscalls executed
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-system.cpu0.kern.syscall::147 2 0.91% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 219 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.678795 # fraction of swpipl calls that actually changed the ipl
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+system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed
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+system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed
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+system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed
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+system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed
+system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed
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+system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed
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+system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed
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+system.cpu0.kern.syscall::total 178 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
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-system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3850 2.08% 2.14% # number of callpals executed
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-system.cpu0.kern.callpal::swpipl 169235 91.57% 93.74% # number of callpals executed
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-system.cpu0.kern.callpal::rdusp 9 0.00% 97.20% # number of callpals executed
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-system.cpu0.kern.callpal::total 184824 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7179 # number of protection mode switches
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+system.cpu0.kern.mode_switch::kernel 6637 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1098 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1250
-system.cpu0.kern.mode_good::user 1251
+system.cpu0.kern.mode_good::kernel 1098
+system.cpu0.kern.mode_good::user 1098
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.174119 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.165436 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.296679 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1901642531000 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1904721500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.283904 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1900423407500 99.92% 99.92% # number of ticks spent at the given mode
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3851 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3189 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2262 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 38430 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 10197 33.29% 33.29% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1926 6.29% 39.58% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 101 0.33% 39.91% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 18406 60.09% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 30630 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 10185 45.68% 45.68% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1926 8.64% 54.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 101 0.45% 54.77% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 10084 45.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 22296 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1876291886000 98.58% 98.58% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 533607500 0.03% 98.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 52904000 0.00% 98.61% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 26445439500 1.39% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1903323837000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.998823 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2560 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 70963 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 22970 38.17% 38.17% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_count::30 383 0.64% 42.01% # number of times we switched to this ipl
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+system.cpu1.kern.ipl_good::0 22406 47.94% 47.94% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1925 4.12% 52.06% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 383 0.82% 52.88% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 22023 47.12% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 46737 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1874192202500 98.50% 98.50% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532510000 0.03% 98.53% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 178162000 0.01% 98.54% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 27779026000 1.46% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1902681900500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.975446 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.547865 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.727914 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::3 11 10.28% 10.28% # number of syscalls executed
-system.cpu1.kern.syscall::4 1 0.93% 11.21% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 9.35% 20.56% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.93% 21.50% # number of syscalls executed
-system.cpu1.kern.syscall::17 7 6.54% 28.04% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.80% 30.84% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.80% 33.64% # number of syscalls executed
-system.cpu1.kern.syscall::33 5 4.67% 38.32% # number of syscalls executed
-system.cpu1.kern.syscall::45 18 16.82% 55.14% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.80% 57.94% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.93% 58.88% # number of syscalls executed
-system.cpu1.kern.syscall::71 31 28.97% 87.85% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 9.35% 97.20% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.80% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 107 # number of syscalls executed
+system.cpu1.kern.ipl_used::31 0.631032 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total 0.776646 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed
+system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed
+system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed
+system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed
+system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed
+system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed
+system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed
+system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed
+system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed
+system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed
+system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed
+system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed
+system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed
+system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed
+system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed
+system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 148 # number of syscalls executed
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 9 0.03% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.04% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 385 1.22% 1.26% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 1.27% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.29% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 26077 82.56% 83.85% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2376 7.52% 91.38% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 91.38% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 5 0.02% 91.39% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 91.40% # number of callpals executed
-system.cpu1.kern.callpal::rti 2525 7.99% 99.40% # number of callpals executed
-system.cpu1.kern.callpal::callsys 142 0.45% 99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb 47 0.15% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 283 0.45% 0.45% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1593 2.54% 3.00% # number of callpals executed
+system.cpu1.kern.callpal::tbi 5 0.01% 3.00% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.01% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 54358 86.66% 89.67% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2709 4.32% 93.99% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 93.99% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 5 0.01% 94.00% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 1 0.00% 94.00% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.01% # number of callpals executed
+system.cpu1.kern.callpal::rti 3511 5.60% 99.60% # number of callpals executed
+system.cpu1.kern.callpal::callsys 200 0.32% 99.92% # number of callpals executed
+system.cpu1.kern.callpal::imb 48 0.08% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 31584 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 861 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 488 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2051 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 514
-system.cpu1.kern.mode_good::user 488
-system.cpu1.kern.mode_good::idle 26
-system.cpu1.kern.mode_switch_good::kernel 0.596980 # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total 62728 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1948 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 639 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2607 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 948
+system.cpu1.kern.mode_good::user 639
+system.cpu1.kern.mode_good::idle 309
+system.cpu1.kern.mode_switch_good::kernel 0.486653 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.012677 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.302353 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 2103355500 0.11% 0.11% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 871184500 0.05% 0.16% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1899849485000 99.84% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 386 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.118527 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.365037 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 6500961500 0.34% 0.34% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 1047066000 0.06% 0.40% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1895133865000 99.60% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1594 # number of times the context was actually changed
---------- End Simulation Statistics ----------
sim_ticks 1855236450500 # Number of ticks simulated
final_tick 1855236450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87142 # Simulator instruction rate (inst/s)
-host_op_rate 87142 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3050446700 # Simulator tick rate (ticks/s)
-host_mem_usage 299400 # Number of bytes of host memory used
-host_seconds 608.19 # Real time elapsed on the host
+host_inst_rate 182093 # Simulator instruction rate (inst/s)
+host_op_rate 182093 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6374280472 # Simulator tick rate (ticks/s)
+host_mem_usage 298212 # Number of bytes of host memory used
+host_seconds 291.05 # Real time elapsed on the host
sim_insts 52998368 # Number of instructions simulated
sim_ops 52998368 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 969536 # Number of bytes read from this memory
system.iocache.demand_avg_miss_latency::total 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 275380.989910 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 275380.989910 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 200042000 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 200042 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24684 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8104.116027 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.104116 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308744998 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 9308744998 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 9320420998 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9320420998 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 9320420998 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9320420998 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9308894806 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 9308894806 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 9320571804 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 9320571804 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 9320571804 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 9320571804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224026.400606 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 224026.400606 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223377.375626 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 223377.375626 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 224030.005920 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 224030.005920 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 223380.989910 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 223380.989910 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.iq.iqSquashedNonSpecRemoved 1416008 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 80977441 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.704819 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.361988 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.361989 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 56039618 69.20% 69.20% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 11066888 13.67% 82.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5221753 6.45% 89.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3374540 4.17% 93.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 56039637 69.20% 69.20% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 11066851 13.67% 82.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5221770 6.45% 89.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3374541 4.17% 93.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 2635998 3.26% 96.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 1459561 1.80% 98.54% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 750162 0.93% 99.47% # Number of insts issued each cycle
system.cpu.icache.demand_avg_miss_latency::total 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13450.989067 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13450.989067 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 1416996 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 2830 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 136 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 10419.088235 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 20.808824 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_mshr_misses::total 1021072 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1021072 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1021072 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930954998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11930954998 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930954998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11930954998 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930954998 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11930954998 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11930955996 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11930955996 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11930955996 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11930955996 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11930955996 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11930955996 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116808 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.116808 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116808 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.116808 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.734277 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.734277 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.734277 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.734277 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11684.735255 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11684.735255 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11684.735255 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11684.735255 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1402622 # number of replacements
system.cpu.dcache.tagsinuse 511.994917 # Cycle average of tags in use
system.cpu.dcache.overall_misses::total 3739889 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35378004500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 35378004500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417912677 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 56417912677 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 56417909184 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 56417909184 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 304480000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 91795917177 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 91795917177 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 91795917177 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 91795917177 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 91795913684 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 91795913684 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 91795913684 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 91795913684 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9072218 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6147230 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.245731 # miss rate for overall accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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---------- Begin Simulation Statistics ----------
-sim_seconds 2.534231 # Number of seconds simulated
-sim_ticks 2534231333000 # Number of ticks simulated
-final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.534230 # Number of seconds simulated
+sim_ticks 2534229746000 # Number of ticks simulated
+final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 44913 # Simulator instruction rate (inst/s)
-host_op_rate 57771 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1878262368 # Simulator tick rate (ticks/s)
-host_mem_usage 387000 # Number of bytes of host memory used
-host_seconds 1349.24 # Real time elapsed on the host
-sim_insts 60598653 # Number of instructions simulated
-sim_ops 77947265 # Number of ops (including micro ops) simulated
+host_inst_rate 65745 # Simulator instruction rate (inst/s)
+host_op_rate 84567 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2749446134 # Simulator tick rate (ticks/s)
+host_mem_usage 380664 # Number of bytes of host memory used
+host_seconds 921.72 # Real time elapsed on the host
+sim_insts 60598794 # Number of instructions simulated
+sim_ops 77947430 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 15049411 # DTB read hits
+system.cpu.checker.dtb.read_hits 15049421 # DTB read hits
system.cpu.checker.dtb.read_misses 7302 # DTB read misses
-system.cpu.checker.dtb.write_hits 11294478 # DTB write hits
+system.cpu.checker.dtb.write_hits 11294481 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 15056713 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11296667 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 15056723 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11296670 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26343889 # DTB hits
+system.cpu.checker.dtb.hits 26343902 # DTB hits
system.cpu.checker.dtb.misses 9491 # DTB misses
-system.cpu.checker.dtb.accesses 26353380 # DTB accesses
-system.cpu.checker.itb.inst_hits 61777417 # ITB inst hits
+system.cpu.checker.dtb.accesses 26353393 # DTB accesses
+system.cpu.checker.itb.inst_hits 61777557 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61781888 # ITB inst accesses
-system.cpu.checker.itb.hits 61777417 # DTB hits
+system.cpu.checker.itb.inst_accesses 61782028 # ITB inst accesses
+system.cpu.checker.itb.hits 61777557 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61781888 # DTB accesses
-system.cpu.checker.numCycles 78237836 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61782028 # DTB accesses
+system.cpu.checker.numCycles 78238000 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51729232 # DTB read hits
-system.cpu.dtb.read_misses 76957 # DTB read misses
-system.cpu.dtb.write_hits 11808980 # DTB write hits
-system.cpu.dtb.write_misses 17307 # DTB write misses
+system.cpu.dtb.read_hits 51729015 # DTB read hits
+system.cpu.dtb.read_misses 77642 # DTB read misses
+system.cpu.dtb.write_hits 11810988 # DTB write hits
+system.cpu.dtb.write_misses 17459 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7736 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 7775 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51806189 # DTB read accesses
-system.cpu.dtb.write_accesses 11826287 # DTB write accesses
+system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51806657 # DTB read accesses
+system.cpu.dtb.write_accesses 11828447 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63538212 # DTB hits
-system.cpu.dtb.misses 94264 # DTB misses
-system.cpu.dtb.accesses 63632476 # DTB accesses
-system.cpu.itb.inst_hits 13079160 # ITB inst hits
-system.cpu.itb.inst_misses 12175 # ITB inst misses
+system.cpu.dtb.hits 63540003 # DTB hits
+system.cpu.dtb.misses 95101 # DTB misses
+system.cpu.dtb.accesses 63635104 # DTB accesses
+system.cpu.itb.inst_hits 13083995 # ITB inst hits
+system.cpu.itb.inst_misses 12083 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5196 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 5178 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13091335 # ITB inst accesses
-system.cpu.itb.hits 13079160 # DTB hits
-system.cpu.itb.misses 12175 # DTB misses
-system.cpu.itb.accesses 13091335 # DTB accesses
-system.cpu.numCycles 475963827 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13096078 # ITB inst accesses
+system.cpu.itb.hits 13083995 # DTB hits
+system.cpu.itb.misses 12083 # DTB misses
+system.cpu.itb.accesses 13096078 # DTB accesses
+system.cpu.numCycles 475967538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued
-system.cpu.iq.rate 0.265193 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued
+system.cpu.iq.rate 0.265188 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 225525 # number of nop insts executed
-system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11734992 # Number of branches executed
-system.cpu.iew.exec_stores 12321310 # Number of stores executed
-system.cpu.iew.exec_rate 0.258373 # Inst execution rate
-system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47712496 # num instructions producing a value
-system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value
+system.cpu.iew.exec_nop 224961 # number of nop insts executed
+system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11733959 # Number of branches executed
+system.cpu.iew.exec_stores 12323243 # Number of stores executed
+system.cpu.iew.exec_rate 0.258361 # Inst execution rate
+system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47712664 # num instructions producing a value
+system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60749034 # Number of instructions committed
-system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60749175 # Number of instructions committed
+system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27515291 # Number of memory references committed
-system.cpu.commit.loads 15716471 # Number of loads committed
+system.cpu.commit.refs 27515313 # Number of memory references committed
+system.cpu.commit.loads 15716490 # Number of loads committed
system.cpu.commit.membars 413125 # Number of memory barriers committed
-system.cpu.commit.branches 10023270 # Number of branches committed
+system.cpu.commit.branches 10023277 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 69135938 # Number of committed integer instructions.
+system.cpu.commit.int_insts 69136099 # Number of committed integer instructions.
system.cpu.commit.function_calls 996018 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2849213 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 2847658 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 249559242 # The number of ROB reads
-system.cpu.rob.rob_writes 208759201 # The number of ROB writes
-system.cpu.timesIdled 1773088 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320203271 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4592410806 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60598653 # Number of Instructions Simulated
-system.cpu.committedOps 77947265 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60598653 # Number of Instructions Simulated
-system.cpu.cpi 7.854363 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.854363 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127318 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127318 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 556742715 # number of integer regfile reads
-system.cpu.int_regfile_writes 89972067 # number of integer regfile writes
+system.cpu.rob.rob_reads 249572720 # The number of ROB reads
+system.cpu.rob.rob_writes 208783952 # The number of ROB writes
+system.cpu.timesIdled 1774345 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320202303 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4592403923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60598794 # Number of Instructions Simulated
+system.cpu.committedOps 77947430 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60598794 # Number of Instructions Simulated
+system.cpu.cpi 7.854406 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.854406 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127317 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.127317 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 556725628 # number of integer regfile reads
+system.cpu.int_regfile_writes 89967061 # number of integer regfile writes
system.cpu.fp_regfile_reads 8371 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2922 # number of floating regfile writes
-system.cpu.misc_regfile_reads 133101437 # number of misc regfile reads
-system.cpu.misc_regfile_writes 912914 # number of misc regfile writes
-system.cpu.icache.replacements 989669 # number of replacements
-system.cpu.icache.tagsinuse 511.593818 # Cycle average of tags in use
-system.cpu.icache.total_refs 12001618 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 990181 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 12.120630 # Average number of references to valid blocks.
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 133111894 # number of misc regfile reads
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+system.cpu.dcache.overall_miss_latency::total 113637271738 # number of overall miss cycles
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+system.cpu.dcache.demand_miss_rate::total 0.148141 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.148141 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12981.138418 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 12981.138418 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35170.640313 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35170.640313 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.273991 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.273991 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21821.428571 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21821.428571 # average StoreCondReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 30796.818165 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30796.818165 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30796.818165 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 25623 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15683 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2532 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.119668 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 56.211470 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 609206 # number of writebacks
-system.cpu.dcache.writebacks::total 609206 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 339325 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 339325 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_hits::total 2713436 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1355 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1355 # number of LoadLockedReq MSHR hits
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-system.cpu.dcache.demand_mshr_hits::total 3052761 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 3052761 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387400 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 387400 # number of ReadReq MSHR misses
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-system.cpu.dcache.WriteReq_mshr_misses::total 249042 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12206 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12206 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 636442 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4757620458 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8541364957 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141415500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141415500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 332500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 332500 # number of StoreCondReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 13298985415 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407548000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407548000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41944273253 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41944273253 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224351821253 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 224351821253 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026423 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026423 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024295 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024295 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040973 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040973 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000066 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000066 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025547 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025547 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025547 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12280.899479 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12280.899479 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34296.885493 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34296.885493 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11585.736523 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11585.736523 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17500 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.832480 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.832480 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 609265 # number of writebacks
+system.cpu.dcache.writebacks::total 609265 # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_hits::total 339927 # number of ReadReq MSHR hits
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+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1356 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1356 # number of LoadLockedReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_misses::total 249061 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12243 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12243 # number of LoadLockedReq MSHR misses
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+system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 636459 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.overall_mshr_misses::total 636459 # number of overall MSHR misses
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+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4758834000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141913000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 277500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 277500 # number of StoreCondReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 13299132916 # number of demand (read+write) MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 13299132916 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182407357500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182407357500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42045203371 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42045203371 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224452560871 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 224452560871 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024296 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024296 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041117 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041117 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000049 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000049 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025552 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025552 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025552 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12284.095426 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12284.095426 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34289.988862 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34289.988862 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11591.358327 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11591.358327 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19821.428571 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19821.428571 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20895.506099 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20895.506099 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64397 # number of replacements
-system.cpu.l2cache.tagsinuse 51351.941492 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1929097 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129792 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.862988 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2499029961500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36885.832563 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 46.221263 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64402 # number of replacements
+system.cpu.l2cache.tagsinuse 51349.814622 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1928941 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129796 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.861329 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2499028808000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36883.442332 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 42.609278 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000238 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8173.888273 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6245.999155 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.562833 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000705 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 8182.264424 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6241.498349 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.562797 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000650 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124724 # Average percentage of cache occupancy
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-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 32529244761 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026667 # mshr miss rate for ReadReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985863 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012481 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222820 # mshr miss rate for overall accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012483 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222781 # mshr miss rate for demand accesses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41054.524670 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40455.603435 # average ReadReq mshr miss latency
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-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40003.926255 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40256.545723 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41054.524670 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40271.286536 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40333.196767 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1307054297856 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307054297856 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1307054297856 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.616879 # Number of seconds simulated
-sim_ticks 2616878893500 # Number of ticks simulated
-final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.004001 # Number of seconds simulated
+sim_ticks 1004001369000 # Number of ticks simulated
+final_tick 1004001369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63327 # Simulator instruction rate (inst/s)
-host_op_rate 81506 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2627232906 # Simulator tick rate (ticks/s)
-host_mem_usage 387740 # Number of bytes of host memory used
-host_seconds 996.06 # Real time elapsed on the host
-sim_insts 63077499 # Number of instructions simulated
-sim_ops 81184436 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory
+host_inst_rate 89245 # Simulator instruction rate (inst/s)
+host_op_rate 114826 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1450204701 # Simulator tick rate (ticks/s)
+host_mem_usage 385792 # Number of bytes of host memory used
+host_seconds 692.32 # Real time elapsed on the host
+sim_insts 61785538 # Number of instructions simulated
+sim_ops 79495701 # Number of ops (including micro ops) simulated
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system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
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-system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 72648 # number of replacements
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.occ_blocks::cpu0.data 2955.984743 # Average occupied blocks per requestor
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-system.l2c.occ_blocks::cpu1.inst 4027.816705 # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::writebacks 585034 # number of Writeback hits
-system.l2c.Writeback_hits::total 585034 # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1.data 803 # number of UpgradeReq hits
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+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253074999 # number of ReadReq MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 248671000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1019091499 # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 149167996 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 354543462 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26341496 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15988493 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 42329989 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2637739492 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3117564497 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5755303989 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu0.data 2890814491 # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.inst 256738000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3366235497 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6774395488 # number of demand (read+write) MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu0.data 2890814491 # number of overall MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::cpu1.data 3366235497 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6774395488 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5539000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12385867978 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2149000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154396291480 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166789847458 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1090238997 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31486348998 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 32576587995 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5539000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13476106975 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2149000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185882640478 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 199366435453 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036270 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030098 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.016977 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.833117 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823790 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.829168 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769591 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.712500 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746996 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569408 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.569498 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.569457 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.096251 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.096251 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40410.677291 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40410.900474 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40736.731792 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.269702 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.514601 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40031.563774 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.165184 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40101.018676 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40049.055233 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41089.568002 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40731.544467 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40893.132300 # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40414.404184 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40401.462226 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40752.249330 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40018.602104 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.352120 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.227139 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40032.668693 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40071.411028 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.293283 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41479.108882 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40522.584254 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40955.438773 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9084291 # DTB read hits
-system.cpu0.dtb.read_misses 36586 # DTB read misses
-system.cpu0.dtb.write_hits 5291622 # DTB write hits
-system.cpu0.dtb.write_misses 6420 # DTB write misses
+system.cpu0.dtb.read_hits 8992964 # DTB read hits
+system.cpu0.dtb.read_misses 35495 # DTB read misses
+system.cpu0.dtb.write_hits 5204763 # DTB write hits
+system.cpu0.dtb.write_misses 6364 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 2149 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1250 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 357 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9120877 # DTB read accesses
-system.cpu0.dtb.write_accesses 5298042 # DTB write accesses
+system.cpu0.dtb.perms_faults 536 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 9028459 # DTB read accesses
+system.cpu0.dtb.write_accesses 5211127 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14375913 # DTB hits
-system.cpu0.dtb.misses 43006 # DTB misses
-system.cpu0.dtb.accesses 14418919 # DTB accesses
-system.cpu0.itb.inst_hits 4432740 # ITB inst hits
-system.cpu0.itb.inst_misses 5766 # ITB inst misses
+system.cpu0.dtb.hits 14197727 # DTB hits
+system.cpu0.dtb.misses 41859 # DTB misses
+system.cpu0.dtb.accesses 14239586 # DTB accesses
+system.cpu0.itb.inst_hits 4345219 # ITB inst hits
+system.cpu0.itb.inst_misses 5468 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1393 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1660 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses
-system.cpu0.itb.hits 4432740 # DTB hits
-system.cpu0.itb.misses 5766 # DTB misses
-system.cpu0.itb.accesses 4438506 # DTB accesses
-system.cpu0.numCycles 73427885 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4350687 # ITB inst accesses
+system.cpu0.itb.hits 4345219 # DTB hits
+system.cpu0.itb.misses 5468 # DTB misses
+system.cpu0.itb.accesses 4350687 # DTB accesses
+system.cpu0.numCycles 69454344 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 6140299 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 4680843 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 325697 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 3967848 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 3011514 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS 689087 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect 31971 # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles 11903950 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 32719278 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 6140299 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3700601 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7697719 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1567081 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 66811 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 21663795 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4784 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 55267 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 90495 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4343360 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 170443 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 42607741 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.991445 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.370542 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34918154 81.95% 81.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 615023 1.44% 83.40% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 811777 1.91% 85.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 689946 1.62% 86.92% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 788421 1.85% 88.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 570027 1.34% 90.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 709248 1.66% 91.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 365635 0.86% 92.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3139510 7.37% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 42607741 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088408 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.471090 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12410407 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 21637687 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6924723 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 574768 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1060156 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 960041 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 65781 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 40808812 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 215037 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1060156 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12993427 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5870248 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13615125 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6864393 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2204392 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 39624437 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2198 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 433654 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1244123 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39987634 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 178950817 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 178916692 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34125 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 31114791 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8872842 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 451750 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 410482 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5405254 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7790925 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5788375 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1121917 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1222446 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 37402937 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 939151 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37702557 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 87742 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6716452 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 14173286 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 260083 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 42607741 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.884876 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.498206 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 27166804 63.76% 63.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5957097 13.98% 77.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3214078 7.54% 85.28% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2477962 5.82% 91.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2111115 4.95% 96.06% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 940986 2.21% 98.26% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 497762 1.17% 99.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 188040 0.44% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 53897 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 42607741 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 24897 2.34% 2.34% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 455 0.04% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 841667 79.11% 81.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 196890 18.51% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22610692 59.97% 60.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 48707 0.13% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9470500 25.12% 85.36% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5519656 14.64% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued
-system.cpu0.iq.rate 0.521198 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37702557 # Type of FU issued
+system.cpu0.iq.rate 0.542839 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1063909 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028218 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 119197860 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 45066260 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34725350 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8284 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4664 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38709880 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4307 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 311315 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1483597 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3551 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13024 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 603760 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2189792 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1060156 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4217100 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 98020 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 38461133 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 95338 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7790925 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5788375 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 610075 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 39436 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2994 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13024 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 172050 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 129143 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 301193 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 37281122 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9309198 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 421435 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 119558 # number of nop insts executed
-system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4996145 # Number of branches executed
-system.cpu0.iew.exec_stores 5564857 # Number of stores executed
-system.cpu0.iew.exec_rate 0.515421 # Inst execution rate
-system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18696932 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value
+system.cpu0.iew.exec_nop 119045 # number of nop insts executed
+system.cpu0.iew.exec_refs 14772448 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4922535 # Number of branches executed
+system.cpu0.iew.exec_stores 5463250 # Number of stores executed
+system.cpu0.iew.exec_rate 0.536772 # Inst execution rate
+system.cpu0.iew.wb_sent 37065432 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34729228 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18441672 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35371865 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.500030 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.521366 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6577828 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 679068 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 261125 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 41583448 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.756316 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.712971 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 29716852 71.46% 71.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5893148 14.17% 85.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1935709 4.65% 90.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 983715 2.37% 92.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 787040 1.89% 94.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 514741 1.24% 95.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 394337 0.95% 96.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 216625 0.52% 97.26% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1141281 2.74% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 24278814 # Number of instructions committed
-system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 41583448 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 23837222 # Number of instructions committed
+system.cpu0.commit.committedOps 31450221 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11706368 # Number of memory references committed
-system.cpu0.commit.loads 6427232 # Number of loads committed
-system.cpu0.commit.membars 234590 # Number of memory barriers committed
-system.cpu0.commit.branches 4349138 # Number of branches committed
+system.cpu0.commit.refs 11491943 # Number of memory references committed
+system.cpu0.commit.loads 6307328 # Number of loads committed
+system.cpu0.commit.membars 231960 # Number of memory barriers committed
+system.cpu0.commit.branches 4279027 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 500279 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 27769802 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 489719 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1141281 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 81269635 # The number of ROB reads
-system.cpu0.rob.rob_writes 78536158 # The number of ROB writes
-system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 24198072 # Number of Instructions Simulated
-system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated
-system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads
-system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 922 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes
-system.cpu0.icache.replacements 405114 # number of replacements
-system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits
-system.cpu0.icache.overall_hits::total 3991755 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses
-system.cpu0.icache.overall_misses::total 439070 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked
+system.cpu0.rob.rob_reads 77601886 # The number of ROB reads
+system.cpu0.rob.rob_writes 77118702 # The number of ROB writes
+system.cpu0.timesIdled 360842 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26846603 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 1938505291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23756480 # Number of Instructions Simulated
+system.cpu0.committedOps 31369479 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 23756480 # Number of Instructions Simulated
+system.cpu0.cpi 2.923596 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.923596 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.342045 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.342045 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 173851540 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34503400 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3265 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 914 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 46745590 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 520572 # number of misc regfile writes
+system.cpu0.icache.replacements 396597 # number of replacements
+system.cpu0.icache.tagsinuse 510.934010 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3914161 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 397109 # Sample count of references to valid blocks.
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+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88840500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 88840500 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.overall_accesses::total 10966722 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062572 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.062572 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.333397 # miss rate for WriteReq accesses
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+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048095 # miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041727 # miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_miss_rate::total 0.179742 # miss rate for demand accesses
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+system.cpu0.dcache.overall_miss_rate::total 0.179742 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10085.196958 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10085.196958 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8830.988746 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8830.988746 # average StoreCondReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 35473.363429 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 35473.363429 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 7710 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 3643 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 580 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.293103 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 38.347368 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks
-system.cpu0.dcache.writebacks::total 256111 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses
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-system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 256563 # number of writebacks
+system.cpu0.dcache.writebacks::total 256563 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201019 # number of ReadReq MSHR hits
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7460 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67402500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 6788344990 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13509879500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13509879500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1216585395 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14726464895 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030264 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030264 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027484 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027484 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045671 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045671 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041705 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041705 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029061 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029061 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8057.680813 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8057.680813 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6835.723861 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6835.723861 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 43437526 # DTB read hits
-system.cpu1.dtb.read_misses 44897 # DTB read misses
-system.cpu1.dtb.write_hits 7020721 # DTB write hits
-system.cpu1.dtb.write_misses 11707 # DTB write misses
+system.cpu1.dtb.read_hits 43128318 # DTB read hits
+system.cpu1.dtb.read_misses 43709 # DTB read misses
+system.cpu1.dtb.write_hits 6848528 # DTB write hits
+system.cpu1.dtb.write_misses 11704 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 3032 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 376 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 43482423 # DTB read accesses
-system.cpu1.dtb.write_accesses 7032428 # DTB write accesses
+system.cpu1.dtb.perms_faults 614 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 43172027 # DTB read accesses
+system.cpu1.dtb.write_accesses 6860232 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 50458247 # DTB hits
-system.cpu1.dtb.misses 56604 # DTB misses
-system.cpu1.dtb.accesses 50514851 # DTB accesses
-system.cpu1.itb.inst_hits 9182577 # ITB inst hits
-system.cpu1.itb.inst_misses 6227 # ITB inst misses
+system.cpu1.dtb.hits 49976846 # DTB hits
+system.cpu1.dtb.misses 55413 # DTB misses
+system.cpu1.dtb.accesses 50032259 # DTB accesses
+system.cpu1.itb.inst_hits 9000425 # ITB inst hits
+system.cpu1.itb.inst_misses 6008 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1553 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1639 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses
-system.cpu1.itb.hits 9182577 # DTB hits
-system.cpu1.itb.misses 6227 # DTB misses
-system.cpu1.itb.accesses 9188804 # DTB accesses
-system.cpu1.numCycles 420121858 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 9006433 # ITB inst accesses
+system.cpu1.itb.hits 9000425 # DTB hits
+system.cpu1.itb.misses 6008 # DTB misses
+system.cpu1.itb.accesses 9006433 # DTB accesses
+system.cpu1.numCycles 411196854 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 9419862 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 7750034 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 456519 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 6563236 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 5515830 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS 808543 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect 49558 # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles 20407169 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 70137907 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9419862 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6324373 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14954252 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4469714 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 69962 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 78537497 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4608 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 48031 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 137349 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 105 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8998373 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 846947 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 117207584 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.722166 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.072596 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 102261187 87.25% 87.25% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 819653 0.70% 87.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 985556 0.84% 88.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 2033886 1.74% 90.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1605966 1.37% 91.89% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 588504 0.50% 92.40% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2242580 1.91% 94.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 432923 0.37% 94.68% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 6237329 5.32% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 117207584 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022908 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.170570 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 22086254 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 78170196 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 13474165 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 527031 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2949938 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1142917 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 100567 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 79224649 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 333390 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2949938 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 23604711 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 32726720 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 41122515 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 12389079 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4414621 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 72870010 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 19270 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 676690 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3162757 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 33999 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 77285870 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 335898709 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 335839792 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 58917 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49079142 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 28206728 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 460869 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 403889 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7994466 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13706939 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8341114 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1036889 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1489334 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 65799753 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1184242 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 90434427 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 105475 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 18495331 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 52692216 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 284904 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 117207584 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.771575 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.509324 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 86216438 73.56% 73.56% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8629120 7.36% 80.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4443515 3.79% 84.71% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3900369 3.33% 88.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10705508 9.13% 97.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1918417 1.64% 98.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1028985 0.88% 99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 292713 0.25% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 72519 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 117207584 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 27077 0.34% 0.34% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 994 0.01% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7551420 96.03% 96.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 284170 3.61% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 313737 0.35% 0.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 38536009 42.61% 42.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59463 0.07% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 3 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1448 0.00% 43.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 44313821 49.00% 92.03% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7209923 7.97% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued
-system.cpu1.iq.rate 0.218398 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 90434427 # Type of FU issued
+system.cpu1.iq.rate 0.219930 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7863661 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.086954 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 306085964 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 85487883 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 54343960 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14808 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8052 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6813 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 97976579 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7772 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 344186 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3955729 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 4256 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17131 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1493245 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31918877 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 1021818 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2949938 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24820563 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 368762 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 67089139 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 132396 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13706939 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8341114 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 882128 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 65563 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3455 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17131 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 238596 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 168339 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 406935 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 87595702 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43496570 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2838725 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 105590 # number of nop insts executed
-system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 7278596 # Number of branches executed
-system.cpu1.iew.exec_stores 7327100 # Number of stores executed
-system.cpu1.iew.exec_rate 0.211640 # Inst execution rate
-system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 30754041 # num instructions producing a value
-system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value
+system.cpu1.iew.exec_nop 105144 # number of nop insts executed
+system.cpu1.iew.exec_refs 50630638 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7094868 # Number of branches executed
+system.cpu1.iew.exec_stores 7134068 # Number of stores executed
+system.cpu1.iew.exec_rate 0.213026 # Inst execution rate
+system.cpu1.iew.wb_sent 86451134 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 54350773 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 30183399 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53726330 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.132177 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.561799 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 18453809 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 357846 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 114304625 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.421644 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.382099 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 97479553 85.28% 85.28% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8276936 7.24% 92.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2163829 1.89% 94.41% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1249082 1.09% 95.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1246649 1.09% 96.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 573488 0.50% 97.10% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1001794 0.88% 97.98% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 527131 0.46% 98.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1786163 1.56% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38949066 # Number of instructions committed
-system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 114304625 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38098697 # Number of instructions committed
+system.cpu1.commit.committedOps 48195861 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 17015256 # Number of memory references committed
-system.cpu1.commit.loads 9993741 # Number of loads committed
-system.cpu1.commit.membars 202364 # Number of memory barriers committed
-system.cpu1.commit.branches 6138465 # Number of branches committed
+system.cpu1.commit.refs 16599079 # Number of memory references committed
+system.cpu1.commit.loads 9751210 # Number of loads committed
+system.cpu1.commit.membars 196398 # Number of memory barriers committed
+system.cpu1.commit.branches 5978782 # Number of branches committed
system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 556456 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 42713997 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 536442 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1786163 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 183919327 # The number of ROB reads
-system.cpu1.rob.rob_writes 139377269 # The number of ROB writes
-system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38879427 # Number of Instructions Simulated
-system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated
-system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads
-system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes
-system.cpu1.icache.replacements 621848 # number of replacements
-system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use
-system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 8507924 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 8507924 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 8507924 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 8507924 # number of overall hits
-system.cpu1.icache.overall_hits::total 8507924 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 672506 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 672506 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 672506 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 672506 # number of demand (read+write) misses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency
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-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 36980.444290 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 29857004 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 5566500 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 6768 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4411.495863 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 33133.928571 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 360631 # number of replacements
+system.cpu1.dcache.tagsinuse 472.241123 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 12789913 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 361011 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 35.428042 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 472.241123 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.922346 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.922346 # Average percentage of cache occupancy
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+system.cpu1.dcache.ReadReq_hits::total 8401496 # number of ReadReq hits
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.044854 # miss rate for ReadReq accesses
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121036 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154 # average ReadReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9186.566102 # average LoadLockedReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6140.568891 # average StoreCondReq miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136 # average overall miss latency
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+system.cpu1.dcache.avg_blocked_cycles::no_targets 66.956790 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks
-system.cpu1.dcache.writebacks::total 328923 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits
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-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 325044 # number of writebacks
+system.cpu1.dcache.writebacks::total 325044 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_hits::total 165979 # number of ReadReq MSHR hits
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+system.cpu1.dcache.WriteReq_mshr_hits::total 1389692 # number of WriteReq MSHR hits
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40847570579 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025985 # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028303 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108721 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108721 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097159 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097159 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.026896 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.026896 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6982.414449 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6982.414449 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4142.499291 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4142.499291 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 479854932995 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 43104 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 52217 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.534231 # Number of seconds simulated
-sim_ticks 2534231333000 # Number of ticks simulated
-final_tick 2534231333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.534230 # Number of seconds simulated
+sim_ticks 2534229746000 # Number of ticks simulated
+final_tick 2534229746000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 58448 # Simulator instruction rate (inst/s)
-host_op_rate 75181 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2444289303 # Simulator tick rate (ticks/s)
-host_mem_usage 386996 # Number of bytes of host memory used
-host_seconds 1036.80 # Real time elapsed on the host
-sim_insts 60598653 # Number of instructions simulated
-sim_ops 77947265 # Number of ops (including micro ops) simulated
+host_inst_rate 72788 # Simulator instruction rate (inst/s)
+host_op_rate 93626 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3043970352 # Simulator tick rate (ticks/s)
+host_mem_usage 380668 # Number of bytes of host memory used
+host_seconds 832.54 # Real time elapsed on the host
+sim_insts 60598794 # Number of instructions simulated
+sim_ops 77947430 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 798016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129434320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9095568 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129434640 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 798016 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784256 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800328 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 57 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12469 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096877 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59129 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.data 142152 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096882 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813147 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47169200 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1439 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47169229 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1313 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 314895 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3588831 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51074390 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589086 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51074548 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 314895 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 314895 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493256 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190133 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2683389 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493256 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47169200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1439 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493383 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190134 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683517 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493383 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47169229 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1313 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 314895 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4778964 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53757779 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4779219 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53758065 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51729232 # DTB read hits
-system.cpu.dtb.read_misses 76957 # DTB read misses
-system.cpu.dtb.write_hits 11808980 # DTB write hits
-system.cpu.dtb.write_misses 17307 # DTB write misses
+system.cpu.dtb.read_hits 51729015 # DTB read hits
+system.cpu.dtb.read_misses 77642 # DTB read misses
+system.cpu.dtb.write_hits 11810988 # DTB write hits
+system.cpu.dtb.write_misses 17459 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4248 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2685 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2642 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 530 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1359 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51806189 # DTB read accesses
-system.cpu.dtb.write_accesses 11826287 # DTB write accesses
+system.cpu.dtb.perms_faults 1366 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51806657 # DTB read accesses
+system.cpu.dtb.write_accesses 11828447 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63538212 # DTB hits
-system.cpu.dtb.misses 94264 # DTB misses
-system.cpu.dtb.accesses 63632476 # DTB accesses
-system.cpu.itb.inst_hits 13079160 # ITB inst hits
-system.cpu.itb.inst_misses 12175 # ITB inst misses
+system.cpu.dtb.hits 63540003 # DTB hits
+system.cpu.dtb.misses 95101 # DTB misses
+system.cpu.dtb.accesses 63635104 # DTB accesses
+system.cpu.itb.inst_hits 13083995 # ITB inst hits
+system.cpu.itb.inst_misses 12083 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2600 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2591 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 3091 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 3112 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 13091335 # ITB inst accesses
-system.cpu.itb.hits 13079160 # DTB hits
-system.cpu.itb.misses 12175 # DTB misses
-system.cpu.itb.accesses 13091335 # DTB accesses
-system.cpu.numCycles 475963827 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 13096078 # ITB inst accesses
+system.cpu.itb.hits 13083995 # DTB hits
+system.cpu.itb.misses 12083 # DTB misses
+system.cpu.itb.accesses 13096078 # DTB accesses
+system.cpu.numCycles 475967538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 15173200 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12164115 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 783934 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10408500 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 8322467 # Number of BTB hits
+system.cpu.BPredUnit.lookups 15172784 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 12163693 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 783478 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 10392072 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 8320250 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1454459 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 82493 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 31372709 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 100925223 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 15173200 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9776926 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 22188702 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5931906 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 131502 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 97682240 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 97772 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 209251 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 367 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 13075329 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1015161 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 6456 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 155760556 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.799528 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.166845 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 1454874 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 82640 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 31374160 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 100930999 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 15172784 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9775124 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 22189039 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5936170 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 131560 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 97680943 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2725 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 99805 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 208737 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 364 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 13080141 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1016234 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 6355 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 155765235 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.799529 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.166844 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 133588722 85.77% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1382794 0.89% 86.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1756872 1.13% 87.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2657278 1.71% 89.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2325995 1.49% 90.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1138064 0.73% 91.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2914708 1.87% 93.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 785042 0.50% 94.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 9211081 5.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 133592933 85.77% 85.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1382764 0.89% 86.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1755577 1.13% 87.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2658359 1.71% 89.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2327487 1.49% 90.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1136384 0.73% 91.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2915896 1.87% 93.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 784165 0.50% 94.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 9211670 5.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 155760556 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031879 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.212044 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 33510183 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 97305420 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 20012915 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 1028503 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3903535 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 2022769 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 174789 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 117637896 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 576974 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3903535 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 35608044 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37583370 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 53602713 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18875511 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6187383 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110135538 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21282 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1015019 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4145584 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 32208 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 114982743 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 504362437 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 504271413 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 91024 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78733155 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 36249587 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 891770 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 797348 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12515452 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 21000461 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13838053 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1958528 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2462024 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 100930109 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2057680 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 126222278 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 188912 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 24421115 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 65012350 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 513116 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 155760556 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.810361 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.523302 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 155765235 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031878 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.212054 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 33515539 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 97301422 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 20013824 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 1028268 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3906182 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 2022458 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 174763 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 117645711 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 578390 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3906182 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 35614317 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37590587 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 53594123 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18875472 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6184554 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 110140296 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21341 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1015182 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4143290 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 32170 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 114983026 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 504387694 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 504296628 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 91066 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78733405 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 36249620 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 891466 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 797109 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12509806 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 21006076 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13841580 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1961226 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2453000 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 100941360 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2057614 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 126221061 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 189445 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 24437015 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 65086313 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 513058 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 155765235 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.810329 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.523325 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 110556788 70.98% 70.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13998731 8.99% 79.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7311876 4.69% 84.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 6076948 3.90% 88.56% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12739380 8.18% 96.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2787527 1.79% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1678652 1.08% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 483348 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 127306 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 110569920 70.98% 70.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13988875 8.98% 79.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7307591 4.69% 84.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 6076063 3.90% 88.56% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12752921 8.19% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2780626 1.79% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1679008 1.08% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 481895 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 128336 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 155760556 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 155765235 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 57641 0.65% 0.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57759 0.65% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 2 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8370517 94.61% 95.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 419308 4.74% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8370724 94.64% 95.29% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 416242 4.71% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 59916595 47.47% 47.76% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 95459 0.08% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 59912166 47.47% 47.75% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 95497 0.08% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.83% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.83% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 53391379 42.30% 90.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12453015 9.87% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 53392141 42.30% 90.13% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12455427 9.87% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 126222278 # Type of FU issued
-system.cpu.iq.rate 0.265193 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8847468 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.070094 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 417312006 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127425546 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 87185779 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12560 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10301 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 134693654 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12426 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 624535 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 126221061 # Type of FU issued
+system.cpu.iq.rate 0.265188 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8844727 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.070073 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 417312910 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 127452442 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 87180232 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23310 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12552 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 134689743 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12379 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 626582 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5283990 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7463 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30379 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2039233 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 5289586 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 7312 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30140 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 2042757 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34106900 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1029053 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34106883 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1034668 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3903535 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28661313 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 449961 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 103213314 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 232487 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 21000461 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13838053 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1466210 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 113940 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30379 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 409944 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 293507 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 703451 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 122976352 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52416933 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 3245926 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3906182 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 28670725 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 450645 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 103223935 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 233802 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 21006076 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13841580 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1466072 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 114504 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3680 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30140 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 409816 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 293009 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 702825 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 122971529 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52416599 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 3249532 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 225525 # number of nop insts executed
-system.cpu.iew.exec_refs 64738243 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11734992 # Number of branches executed
-system.cpu.iew.exec_stores 12321310 # Number of stores executed
-system.cpu.iew.exec_rate 0.258373 # Inst execution rate
-system.cpu.iew.wb_sent 121627349 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 87196080 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47712496 # num instructions producing a value
-system.cpu.iew.wb_consumers 88865437 # num instructions consuming a value
+system.cpu.iew.exec_nop 224961 # number of nop insts executed
+system.cpu.iew.exec_refs 64739842 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11733959 # Number of branches executed
+system.cpu.iew.exec_stores 12323243 # Number of stores executed
+system.cpu.iew.exec_rate 0.258361 # Inst execution rate
+system.cpu.iew.wb_sent 121621677 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 87190526 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47712664 # num instructions producing a value
+system.cpu.iew.wb_consumers 88871095 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.183199 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.536907 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.183186 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.536875 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24286652 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1544564 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 612198 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 151939453 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.514005 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.494998 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24296365 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1544556 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 611758 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 151941485 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.513999 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.495079 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 124139967 81.70% 81.70% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13583489 8.94% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3975420 2.62% 93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2135851 1.41% 94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1949883 1.28% 95.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 999128 0.66% 96.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1578626 1.04% 97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 727876 0.48% 98.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2849213 1.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 124150656 81.71% 81.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13572481 8.93% 90.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3978264 2.62% 93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2132059 1.40% 94.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1949397 1.28% 95.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 999089 0.66% 96.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1584839 1.04% 97.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 727042 0.48% 98.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2847658 1.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 151939453 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60749034 # Number of instructions committed
-system.cpu.commit.committedOps 78097646 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 151941485 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60749175 # Number of instructions committed
+system.cpu.commit.committedOps 78097811 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27515291 # Number of memory references committed
-system.cpu.commit.loads 15716471 # Number of loads committed
+system.cpu.commit.refs 27515313 # Number of memory references committed
+system.cpu.commit.loads 15716490 # Number of loads committed
system.cpu.commit.membars 413125 # Number of memory barriers committed
-system.cpu.commit.branches 10023270 # Number of branches committed
+system.cpu.commit.branches 10023277 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1307562103462 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307562103462 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1307562103462 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 88034 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 88032 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 5.125295 # Number of seconds simulated
-sim_ticks 5125295451000 # Number of ticks simulated
-final_tick 5125295451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.133289 # Number of seconds simulated
+sim_ticks 5133289198000 # Number of ticks simulated
+final_tick 5133289198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 133696 # Simulator instruction rate (inst/s)
-host_op_rate 264282 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1679641336 # Simulator tick rate (ticks/s)
-host_mem_usage 368820 # Number of bytes of host memory used
-host_seconds 3051.42 # Real time elapsed on the host
-sim_insts 407963822 # Number of instructions simulated
-sim_ops 806434654 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2463488 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory
+host_inst_rate 170996 # Simulator instruction rate (inst/s)
+host_op_rate 338013 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2151657827 # Simulator tick rate (ticks/s)
+host_mem_usage 361992 # Number of bytes of host memory used
+host_seconds 2385.74 # Real time elapsed on the host
+sim_insts 407952579 # Number of instructions simulated
+sim_ops 806410876 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2466560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1076608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10836416 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14379776 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1076608 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1076608 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9553280 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9553280 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38492 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1078720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10839424 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14387648 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1078720 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1078720 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9551232 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9551232 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38540 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 39 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16822 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169319 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224684 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149270 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149270 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 480653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 549 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16855 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169366 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224807 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149238 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149238 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 480503 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 486 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 210058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2114301 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2805648 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 210058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 210058 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1863947 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1863947 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1863947 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 480653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 549 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 210142 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2111594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2802813 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 210142 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 210142 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1860646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1860646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1860646 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 480503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 486 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 210058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2114301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4669595 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 210142 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2111594 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4663458 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 47577 # number of replacements
-system.iocache.tagsinuse 0.091712 # Cycle average of tags in use
+system.iocache.tagsinuse 0.116486 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4992311644000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.091712 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.005732 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.005732 # Average percentage of cache occupancy
+system.iocache.occ_blocks::pc.south_bridge.ide 0.116486 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.007280 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.007280 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
system.iocache.overall_misses::total 47632 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138301932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 138301932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9924152160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9924152160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10062454092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10062454092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10062454092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10062454092 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 138482932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 138482932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9931610160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 9931610160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10070093092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10070093092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10070093092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10070093092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151646.855263 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 151646.855263 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212417.640411 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 212417.640411 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 211254.074824 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211254.074824 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 211254.074824 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 71289012 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151845.320175 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 151845.320175 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212577.272260 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 212577.272260 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 211414.450202 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211414.450202 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 211414.450202 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 71516 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 8825 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 8861 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8078.075014 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.070872 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90847000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 90847000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7494384978 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7494384978 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7585231978 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7585231978 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7585231978 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 91058932 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 91058932 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7502170160 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7502170160 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7593229092 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7593229092 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7593229092 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99612.938596 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 99612.938596 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160410.637372 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 160410.637372 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159246.556475 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 159246.556475 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99845.320175 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 99845.320175 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160577.272260 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 160577.272260 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159414.450202 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 159414.450202 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 448616710 # number of cpu cycles simulated
+system.cpu.numCycles 448600431 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86513922 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86513922 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1185612 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81821696 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79447101 # Number of BTB hits
+system.cpu.BPredUnit.lookups 86509944 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 86509944 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1185802 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 81830934 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 79445705 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27982708 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 427301680 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86513922 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79447101 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 164025545 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5056665 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 120243 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63002299 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36683 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 57009 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9269960 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 518545 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3708 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 259058563 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.256074 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.417846 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27983612 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 427293864 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86509944 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79445705 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 164022517 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5056605 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 118707 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 62987614 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36438 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 56602 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 319 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9268852 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 518204 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3676 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 259039385 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.256241 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.417856 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95463641 36.85% 36.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1593246 0.62% 37.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71955070 27.78% 65.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 970468 0.37% 65.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1621274 0.63% 66.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2451045 0.95% 67.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1124441 0.43% 67.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1422902 0.55% 68.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82456476 31.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95447322 36.85% 36.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1594478 0.62% 37.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71953209 27.78% 65.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 971457 0.38% 65.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1620147 0.63% 66.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2451072 0.95% 67.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1123457 0.43% 67.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1423255 0.55% 68.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82454988 31.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 259058563 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192846 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.952487 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31703593 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60473195 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159750936 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3297057 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3833782 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 840221922 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 1208 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3833782 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34472569 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37379630 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10860587 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159949927 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12562068 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 836350803 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21427 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5922094 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4820401 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7659 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 998159477 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1816297556 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1816296596 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 960 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964421570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 33737900 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 466538 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 473424 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28941579 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17313500 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10257423 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1154419 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 952791 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 829902104 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1256068 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 824407567 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 167070 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 23703242 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36101298 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 203347 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 259058563 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.182321 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.385461 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 259039385 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192844 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.952504 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31701157 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60460157 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159747770 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3296725 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3833576 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 840199157 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 1214 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3833576 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34469655 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37373675 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10858241 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159947646 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12556592 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 836331491 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 21404 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5918645 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4820353 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7887 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 998118157 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1816257155 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1816256355 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 800 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964383755 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 33734395 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 466799 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 473697 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28937943 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17313250 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10261817 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1158356 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 954062 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 829878064 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1256439 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 824382236 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167222 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 23705426 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 36106397 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 203573 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 259039385 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.182459 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.385421 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.issued_per_cycle::1 15729256 6.07% 33.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10360511 4.00% 37.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7565386 2.92% 40.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75947592 29.32% 70.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3904357 1.51% 71.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72537575 28.00% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 784064 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 154385 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 72064876 27.82% 27.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15723846 6.07% 33.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10360482 4.00% 37.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7566572 2.92% 40.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75946167 29.32% 70.13% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3904049 1.51% 71.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72535410 28.00% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 783527 0.30% 99.94% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 259058563 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 259039385 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 356821 33.57% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 553408 52.07% 85.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 152587 14.36% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 355366 33.47% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.47% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 553588 52.14% 85.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 152800 14.39% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 305253 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 796599749 96.63% 96.66% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 305432 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 796570576 96.63% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 18032887 2.19% 98.85% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9469678 1.15% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 18033245 2.19% 98.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9472983 1.15% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 824407567 # Type of FU issued
-system.cpu.iq.rate 1.837666 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1062816 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001289 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1909237330 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 854871180 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 819733271 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 242 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 448 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 64 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 825165021 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1650397 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 824382236 # Type of FU issued
+system.cpu.iq.rate 1.837676 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1061754 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001288 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1909166354 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 854849744 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 819707401 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 263 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 374 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 65 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 825138441 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 117 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1650685 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3332196 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 26785 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11385 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1841480 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3332850 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 26850 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11358 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1844760 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932351 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11661 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932315 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11695 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3833782 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26055488 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2116129 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 831158172 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 342184 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17313500 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10257423 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 725671 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1616608 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 15691 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11385 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 710592 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 622404 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1332996 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 822394271 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17607905 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2013295 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3833576 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26046353 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2116686 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 831134503 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 342849 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17313250 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10261817 # Number of dispatched store instructions
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+system.cpu.iew.iewIQFullEvents 1616805 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 16237 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.predictedNotTakenIncorrect 622755 # Number of branches that were predicted not taken incorrectly
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+system.cpu.iew.iewExecutedInsts 822369106 # Number of executed instructions
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+system.cpu.iew.iewExecSquashedInsts 2013129 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26830923 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83287562 # Number of branches executed
-system.cpu.iew.exec_stores 9223018 # Number of stores executed
-system.cpu.iew.exec_rate 1.833178 # Inst execution rate
-system.cpu.iew.wb_sent 821886032 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 819733335 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 640537929 # num instructions producing a value
-system.cpu.iew.wb_consumers 1046481965 # num instructions consuming a value
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+system.cpu.iew.exec_rate 1.833188 # Inst execution rate
+system.cpu.iew.wb_sent 821860005 # cumulative count of insts sent to commit
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.827247 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.612087 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.827255 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.612081 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 24617298 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052719 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1189640 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 255240182 # Number of insts commited each cycle
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-system.cpu.commit.committed_per_cycle::stdev 2.852385 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 24617133 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 83212701 32.60% 32.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11927297 4.67% 37.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4018442 1.57% 38.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74971615 29.37% 68.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2476707 0.97% 69.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1494205 0.59% 69.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1000959 0.39% 70.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70934027 27.79% 97.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5204229 2.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 83203030 32.60% 32.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11920052 4.67% 37.27% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4017826 1.57% 38.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74972744 29.38% 68.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2476508 0.97% 69.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1494072 0.59% 69.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1000652 0.39% 70.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70934036 27.79% 97.96% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 255240182 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407963822 # Number of instructions committed
-system.cpu.commit.committedOps 806434654 # Number of ops (including micro ops) committed
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+system.cpu.commit.committedInsts 407952579 # Number of instructions committed
+system.cpu.commit.committedOps 806410876 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22397244 # Number of memory references committed
-system.cpu.commit.loads 13981301 # Number of loads committed
-system.cpu.commit.membars 473469 # Number of memory barriers committed
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system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735369790 # Number of committed integer instructions.
+system.cpu.commit.int_insts 735346024 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5204229 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5202298 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1081009655 # The number of ROB reads
-system.cpu.rob.rob_writes 1665958243 # The number of ROB writes
-system.cpu.timesIdled 1218536 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 189558147 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9801971615 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407963822 # Number of Instructions Simulated
-system.cpu.committedOps 806434654 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407963822 # Number of Instructions Simulated
-system.cpu.cpi 1.099648 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.099648 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.909382 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.909382 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1508373932 # number of integer regfile reads
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-system.cpu.misc_regfile_writes 402332 # number of misc regfile writes
-system.cpu.icache.replacements 1068558 # number of replacements
-system.cpu.icache.tagsinuse 510.894483 # Cycle average of tags in use
-system.cpu.icache.total_refs 8130546 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1069070 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.605251 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 1080968615 # The number of ROB reads
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+system.cpu.idleCycles 189561046 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9817975385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407952579 # Number of Instructions Simulated
+system.cpu.committedOps 806410876 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407952579 # Number of Instructions Simulated
+system.cpu.cpi 1.099639 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.099639 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.909390 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.909390 # IPC: Total IPC of All Threads
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system.cpu.icache.warmup_cycle 56547532000 # Cycle when the warmup percentage was hit.
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11705.654937 # average ReadReq mshr miss latency
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-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11022.961092 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 108671 # number of overall misses
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+system.cpu.dtb_walker_cache.overall_miss_latency::total 1362724500 # number of overall miss cycles
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+system.cpu.dtb_walker_cache.ReadReq_accesses::total 248045 # number of ReadReq accesses(hits+misses)
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+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 248045 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 248045 # number of overall (read+write) accesses
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+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12539.909451 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12539.909451 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12539.909451 # average overall miss latency
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-system.cpu.dtb_walker_cache.writebacks::total 32856 # number of writebacks
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-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110113 # number of ReadReq MSHR misses
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-system.cpu.dtb_walker_cache.overall_mshr_misses::total 110113 # number of overall MSHR misses
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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1157860508 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1157860508 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1157860508 # number of overall MSHR miss cycles
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-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.442498 # mshr miss rate for ReadReq accesses
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.442498 # mshr miss rate for overall accesses
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-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10515.202637 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10515.202637 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10539.909451 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10539.909451 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.total_refs 19218602 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 32836000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 13978.542228 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 30785.793541 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 16048.784582 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16048.784582 # average overall miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 30776.793435 # average WriteReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1573634 # number of writebacks
-system.cpu.dcache.writebacks::total 1573634 # number of writebacks
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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26066097531 # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000860 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015736 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.065631 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000384 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000878 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015765 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101758 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.065591 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40908.274819 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41477.165630 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41298.990909 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40126.674107 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40126.674107 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40055.554304 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40055.554304 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40500 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40908.274819 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.637059 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40414.434725 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.065631 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40916.018985 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41479.477257 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41303.061659 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40120.194708 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40120.194708 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40054.824973 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40054.824973 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40564.102564 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40916.018985 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40365.629300 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40415.248432 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-
----------- Begin Simulation Statistics ----------
-sim_seconds 1.116889 # Number of seconds simulated
-sim_ticks 2233777512 # Number of ticks simulated
-final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 3140005 # Simulator instruction rate (inst/s)
-host_op_rate 3141240 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3147745 # Simulator tick rate (ticks/s)
-host_mem_usage 511524 # Number of bytes of host memory used
-host_seconds 709.64 # Real time elapsed on the host
-sim_insts 2228284650 # Number of instructions simulated
-sim_ops 2229160714 # Number of ops (including micro ops) simulated
-system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory
-system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory
-system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory
-system.hypervisor_desc.bw_read::cpu.data 15035 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_read::total 15035 # Total read bandwidth from this memory (bytes/s)
-system.hypervisor_desc.bw_total::cpu.data 15035 # Total bandwidth to/from this memory (bytes/s)
-system.hypervisor_desc.bw_total::total 15035 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory
-system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory
-system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory
-system.partition_desc.bw_read::cpu.data 4339 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_read::total 4339 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total::cpu.data 4339 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bw_total::total 4339 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory
-system.rom.bytes_read::total 1128688 # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory
-system.rom.num_reads::total 195123 # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst 387054 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data 623511 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total 1010564 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst 387054 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total 387054 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst 387054 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data 623511 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total 1010564 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory
-system.nvram.bytes_read::total 284 # Number of bytes read from this memory
-system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory
-system.nvram.bytes_written::total 92 # Number of bytes written to this memory
-system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory
-system.nvram.num_reads::total 284 # Number of read requests responded to by this memory
-system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory
-system.nvram.num_writes::total 92 # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data 254 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total 254 # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write::cpu.data 82 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_write::total 82 # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data 337 # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory
-system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory
-system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory
-system.physmem.num_other::total 14 # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst 548211557 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 87326534 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 635538091 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 548211557 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 548211557 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 13788502 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13788502 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 548211557 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 101115036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 649326593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory
-system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory
-system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory
-system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory
-system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory
-system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory
-system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory
-system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory
-system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory
-system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory
-system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory
-system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory
-system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory
-system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory
-system.physmem2.bw_read::cpu.inst 7447569684 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_read::cpu.data 1339332247 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_read::total 8786901931 # Total read bandwidth from this memory (bytes/s)
-system.physmem2.bw_inst_read::cpu.inst 7447569684 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem2.bw_inst_read::total 7447569684 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem2.bw_write::cpu.data 803364182 # Write bandwidth from this memory (bytes/s)
-system.physmem2.bw_write::total 803364182 # Write bandwidth from this memory (bytes/s)
-system.physmem2.bw_total::cpu.inst 7447569684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bw_total::cpu.data 2142696429 # Total bandwidth to/from this memory (bytes/s)
-system.physmem2.bw_total::total 9590266113 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.numCycles 2233777513 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 2228284650 # Number of instructions committed
-system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
-system.cpu.num_func_calls 44037246 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1839325658 # number of integer instructions
-system.cpu.num_fp_insts 14608322 # number of float instructions
-system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written
-system.cpu.num_mem_refs 547951940 # number of memory refs
-system.cpu.num_load_insts 349807670 # Number of load instructions
-system.cpu.num_store_insts 198144270 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 2233777513 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
sim_ticks 271544682500 # Number of ticks simulated
final_tick 271544682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105483 # Simulator instruction rate (inst/s)
-host_op_rate 105483 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47591638 # Simulator tick rate (ticks/s)
-host_mem_usage 219440 # Number of bytes of host memory used
-host_seconds 5705.72 # Real time elapsed on the host
+host_inst_rate 142205 # Simulator instruction rate (inst/s)
+host_op_rate 142205 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64159611 # Simulator tick rate (ticks/s)
+host_mem_usage 212920 # Number of bytes of host memory used
+host_seconds 4232.33 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55134.540117 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55134.540117 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 87500 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 175 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29166.666667 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 58.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits
system.cpu.dcache.demand_avg_miss_latency::total 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14281.915545 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14281.915545 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 21072500 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 2046602500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 42145 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4093205 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 3164 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 211457 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6660.082174 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 9678.575313 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.320164 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 19.357151 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 436902 # number of writebacks
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54104.637337 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56730.545900 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 56646.117674 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 108500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 217 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 13562.500000 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 27.125000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 133202081500 # Number of ticks simulated
final_tick 133202081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 189557 # Simulator instruction rate (inst/s)
-host_op_rate 189557 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44645563 # Simulator tick rate (ticks/s)
-host_mem_usage 220464 # Number of bytes of host memory used
-host_seconds 2983.55 # Real time elapsed on the host
+host_inst_rate 258977 # Simulator instruction rate (inst/s)
+host_op_rate 258977 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60995759 # Simulator tick rate (ticks/s)
+host_mem_usage 213944 # Number of bytes of host memory used
+host_seconds 2183.79 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61312 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 7340.245420 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7340.245420 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7340.245420 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 483496 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 206500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 963 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 413 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 102 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4740.156863 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 18772.727273 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.441176 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 37.545455 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 444931 # number of writebacks
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 34437000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 148748500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 183185500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844656996 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 844656996 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 844655000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 844655000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 34437000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 993405496 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 1027842496 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 993403500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 1027840500 # number of demand (read+write) miss cycles
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system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34657.152842 # average ReadReq miss latency
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system.cpu.l2cache.blocked::no_mshrs 81 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 135795500 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.978550 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.020411 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.024851 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32755.219207 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31639.212488 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31842.857143 # average ReadReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36808.212508 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35935.804011 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32755.219207 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 163008222000 # Number of ticks simulated
final_tick 163008222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 104701 # Simulator instruction rate (inst/s)
-host_op_rate 110635 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29939476 # Simulator tick rate (ticks/s)
-host_mem_usage 234836 # Number of bytes of host memory used
-host_seconds 5444.59 # Real time elapsed on the host
+host_inst_rate 178133 # Simulator instruction rate (inst/s)
+host_op_rate 188229 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50937760 # Simulator tick rate (ticks/s)
+host_mem_usage 228580 # Number of bytes of host memory used
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sim_insts 570052710 # Number of instructions simulated
sim_ops 602360916 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48064 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 8537.033204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 8537.033204 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 8537.033204 # average overall miss latency
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 421091 # number of writebacks
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 818 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 197352 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 198170 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36092.052980 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.870616 # average ReadReq miss latency
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system.cpu.l2cache.blocked::no_mshrs 2920 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24797500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 172259500 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918093 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027839 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031513 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33019.307590 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31354.113578 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31554.363491 # average ReadReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33019.307590 # average overall mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 386986985000 # Number of ticks simulated
final_tick 386986985000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135169 # Simulator instruction rate (inst/s)
-host_op_rate 135595 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37331500 # Simulator tick rate (ticks/s)
-host_mem_usage 223688 # Number of bytes of host memory used
-host_seconds 10366.23 # Real time elapsed on the host
+host_inst_rate 190632 # Simulator instruction rate (inst/s)
+host_op_rate 191233 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52649747 # Simulator tick rate (ticks/s)
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+host_seconds 7350.22 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 78784 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 6577.376711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 6577.376711 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 6577.376711 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
sim_ticks 25432499000 # Number of ticks simulated
final_tick 25432499000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141358 # Simulator instruction rate (inst/s)
-host_op_rate 142373 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39681246 # Simulator tick rate (ticks/s)
-host_mem_usage 367916 # Number of bytes of host memory used
-host_seconds 640.92 # Real time elapsed on the host
+host_inst_rate 191631 # Simulator instruction rate (inst/s)
+host_op_rate 193007 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 361656 # Number of bytes of host memory used
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sim_insts 90599358 # Number of instructions simulated
sim_ops 91249911 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 7044.800890 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 7044.800890 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 7044.800890 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 8960217 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 6519 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
sim_ticks 201852280500 # Number of ticks simulated
final_tick 201852280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114620 # Simulator instruction rate (inst/s)
-host_op_rate 129121 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45458575 # Simulator tick rate (ticks/s)
-host_mem_usage 239092 # Number of bytes of host memory used
-host_seconds 4440.36 # Real time elapsed on the host
+host_inst_rate 135871 # Simulator instruction rate (inst/s)
+host_op_rate 153059 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53886430 # Simulator tick rate (ticks/s)
+host_mem_usage 232836 # Number of bytes of host memory used
+host_seconds 3745.88 # Real time elapsed on the host
sim_insts 508955133 # Number of instructions simulated
sim_ops 573341693 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 218816 # Number of bytes read from this memory
system.cpu.iq.issued_per_cycle::mean 1.671200 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.739620 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 143645817 35.71% 35.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 74204584 18.45% 54.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 68520883 17.03% 71.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 143645798 35.71% 35.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 74204622 18.45% 54.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 68520864 17.03% 71.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 53274856 13.24% 84.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 32167138 8.00% 92.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 16325737 4.06% 96.48% # Number of insts issued each cycle
system.cpu.dcache.overall_avg_miss_latency::cpu.data 12757.829762 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 12757.829762 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 3322000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 6644 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 5964.093357 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 11.928187 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1101507 # number of writebacks
---------- Begin Simulation Statistics ----------
sim_seconds 0.427481 # Number of seconds simulated
-sim_ticks 427481057500 # Number of ticks simulated
-final_tick 427481057500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 427481054500 # Number of ticks simulated
+final_tick 427481054500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 54913 # Simulator instruction rate (inst/s)
-host_op_rate 101540 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28388930 # Simulator tick rate (ticks/s)
-host_mem_usage 267916 # Number of bytes of host memory used
-host_seconds 15058.02 # Real time elapsed on the host
+host_inst_rate 86006 # Simulator instruction rate (inst/s)
+host_op_rate 159036 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44463827 # Simulator tick rate (ticks/s)
+host_mem_usage 261156 # Number of bytes of host memory used
+host_seconds 9614.13 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988699 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 222080 # Number of bytes read from this memory
system.physmem.num_writes::writebacks 324977 # Number of write requests responded to by this memory
system.physmem.num_writes::total 324977 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 519508 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 64585224 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 64585225 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 65104733 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 519508 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 519508 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 48653683 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 48653683 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 48653683 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 48653684 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 48653684 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 48653684 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 519508 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 64585224 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 113758416 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 64585225 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 113758417 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 854962116 # number of cpu cycles simulated
+system.cpu.numCycles 854962110 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 221542687 # Number of BP lookups
system.cpu.fetch.predictedBranches 152734220 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 382634785 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 91865959 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 200356871 # Number of cycles fetch has spent blocked
+system.cpu.fetch.BlockedCycles 200356865 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 29611 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 292723 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 179385748 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4126859 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 847490251 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 847490245 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.698073 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.416409 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 469274174 55.37% 55.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 469274168 55.37% 55.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 25456463 3.00% 58.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 28089429 3.31% 61.69% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 29452206 3.48% 65.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 847490251 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 847490245 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.259126 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.440493 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 242064219 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 159033013 # Number of cycles decode is blocked
+system.cpu.decode.BlockedCycles 159033007 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 325519019 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 43678013 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 77195987 # Number of cycles decode is squashing
system.cpu.decode.SquashedInsts 3 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 77195987 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 275570857 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 34110312 # Number of cycles rename is blocking
+system.cpu.rename.BlockCycles 34110306 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14758 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 334015692 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 126582645 # Number of cycles rename is unblocking
system.cpu.iq.iqSquashedInstsExamined 551393168 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 912351431 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 32844 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 847490251 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 847490245 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.164950 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.897317 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 226384740 26.71% 26.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 226384734 26.71% 26.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 141456799 16.69% 43.40% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 133569524 15.76% 59.16% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 133051620 15.70% 74.86% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 847490251 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 847490245 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 5020198 29.82% 29.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 29.82% # attempts to use FU when none available
system.cpu.iq.rate 2.146030 # Inst issue rate
system.cpu.iq.fu_busy_cnt 16833252 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009175 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4534784465 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 4534784459 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2638023268 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1791909670 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 39673 # Number of floating instruction queue reads
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 77195987 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 3929046 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 3929040 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 530860 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2086453895 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 2572498 # Number of squashed instructions skipped by dispatch
system.cpu.commit.commitSquashedInsts 557495358 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 14453256 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 770294264 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 770294258 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.984941 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.459206 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 276893916 35.95% 35.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 276893910 35.95% 35.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 195328257 25.36% 61.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 61767064 8.02% 69.32% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 90267747 11.72% 81.04% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 770294264 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 770294258 # Number of insts commited each cycle
system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988699 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 68515952 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2788262369 # The number of ROB reads
+system.cpu.rob.rob_reads 2788262363 # The number of ROB reads
system.cpu.rob.rob_writes 4250388650 # The number of ROB writes
system.cpu.timesIdled 191112 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7471865 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 992828832 # number of misc regfile reads
system.cpu.icache.replacements 5688 # number of replacements
-system.cpu.icache.tagsinuse 1035.102627 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1035.102624 # Cycle average of tags in use
system.cpu.icache.total_refs 179169407 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 7297 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 24553.845005 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1035.102627 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 1035.102624 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.505421 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.505421 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 179186003 # number of ReadReq hits
system.cpu.icache.demand_misses::total 199745 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 199745 # number of overall misses
system.cpu.icache.overall_misses::total 199745 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237682000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1237682000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1237682000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1237682000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1237682000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1237682000 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1237681000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1237681000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1237681000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1237681000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1237681000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1237681000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 179385748 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 179385748 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 179385748 # number of demand (read+write) accesses
system.cpu.icache.demand_miss_rate::total 0.001113 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001113 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001113 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.310296 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 6196.310296 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 6196.310296 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.310296 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 6196.310296 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6196.305289 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 6196.305289 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 6196.305289 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 6196.305289 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 6196.305289 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 198172 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 198172 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 198172 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804804500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 804804500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804804500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 804804500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804804500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 804804500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804803500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 804803500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804803500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 804803500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804803500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 804803500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001105 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.001105 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001105 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.001105 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.141332 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.141332 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.141332 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.141332 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4061.136286 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4061.136286 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4061.136286 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 4061.136286 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2529003 # number of replacements
system.cpu.dcache.tagsinuse 4087.729607 # Cycle average of tags in use
system.cpu.dcache.demand_misses::total 3725145 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3725145 # number of overall misses
system.cpu.dcache.overall_misses::total 3725145 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892922500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 29892922500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960185000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 16960185000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 46853107500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 46853107500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 46853107500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 46853107500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 29892904500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 29892904500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 16960182000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 16960182000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 46853086500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 46853086500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 46853086500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 46853086500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 264751521 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 264751521 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.009000 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.009000 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.009000 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.054087 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.054087 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.940033 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.940033 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12577.525841 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.525841 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12577.525841 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10827.047567 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 10827.047567 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17589.936922 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17589.936922 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 12577.520204 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 12577.520204 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 12577.520204 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 2723946 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2723946 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2723946 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993049600 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993049600 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994697002 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994697002 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987746602 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 25987746602 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987746602 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 25987746602 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10993099500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10993099500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14994695000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 14994695000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25987794500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 25987794500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25987794500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 25987794500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006658 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006445 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.006581 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006581 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.006581 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.759555 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.759555 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.963852 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.963852 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.477896 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.477896 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 6236.787865 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 6236.787865 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15597.961769 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15597.961769 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9540.495480 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 9540.495480 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 408687 # number of replacements
-system.cpu.l2cache.tagsinuse 29306.187052 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 29306.187032 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3611934 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 441022 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 8.189918 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 209697302000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21100.579663 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 21100.579684 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 146.976593 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 8058.630796 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 8058.630755 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.643939 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.004485 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.245930 # Average percentage of cache occupancy
system.cpu.l2cache.overall_mshr_misses::cpu.data 431420 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 434890 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111424500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6957189466 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5872774499 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5872774499 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5878812896 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5878812896 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6488320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6488320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111424500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13445509466 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 13556933966 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111424500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445509466 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 13556933966 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13445527430 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 13556951930 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.478885 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.126143 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.127588 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.170313 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.171193 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32110.806916 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.201825 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.512168 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31004.637934 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31004.637934 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31310.282671 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31322.591770 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31036.516957 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31036.516957 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31012.245600 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31012.245600 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32110.806916 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.707352 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.248329 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31165.748992 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31173.289636 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 141180939500 # Number of ticks simulated
final_tick 141180939500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88431 # Simulator instruction rate (inst/s)
-host_op_rate 88431 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31316360 # Simulator tick rate (ticks/s)
-host_mem_usage 225476 # Number of bytes of host memory used
-host_seconds 4508.22 # Real time elapsed on the host
+host_inst_rate 139974 # Simulator instruction rate (inst/s)
+host_op_rate 139974 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49569488 # Simulator tick rate (ticks/s)
+host_mem_usage 218836 # Number of bytes of host memory used
+host_seconds 2848.14 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214592 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 49040.669856 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 49040.669856 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 45000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 45000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 90 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 488 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52755.480984 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 52755.480984 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 85964000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 171928 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1907 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 45078.133193 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
sim_ticks 80354154000 # Number of ticks simulated
final_tick 80354154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 172564 # Simulator instruction rate (inst/s)
-host_op_rate 172564 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36920064 # Simulator tick rate (ticks/s)
-host_mem_usage 226504 # Number of bytes of host memory used
-host_seconds 2176.44 # Real time elapsed on the host
+host_inst_rate 221188 # Simulator instruction rate (inst/s)
+host_op_rate 221188 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47323038 # Simulator tick rate (ticks/s)
+host_mem_usage 219864 # Number of bytes of host memory used
+host_seconds 1697.99 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 222976 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 31189.659864 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31189.659864 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31189.659864 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 7500 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35664.466131 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40136.807818 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 38052.307692 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 3500 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3500 # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 70882487500 # Number of ticks simulated
final_tick 70882487500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119635 # Simulator instruction rate (inst/s)
-host_op_rate 152946 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31056895 # Simulator tick rate (ticks/s)
-host_mem_usage 243232 # Number of bytes of host memory used
-host_seconds 2282.34 # Real time elapsed on the host
+host_inst_rate 146290 # Simulator instruction rate (inst/s)
+host_op_rate 187023 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37976354 # Simulator tick rate (ticks/s)
+host_mem_usage 236976 # Number of bytes of host memory used
+host_seconds 1866.49 # Real time elapsed on the host
sim_insts 273048441 # Number of instructions simulated
sim_ops 349076165 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 194880 # Number of bytes read from this memory
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32843.594242 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 32843.594242 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 313000 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 19562.500000 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1041 # number of writebacks
sim_ticks 644314104000 # Number of ticks simulated
final_tick 644314104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 127860 # Simulator instruction rate (inst/s)
-host_op_rate 127860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45189117 # Simulator tick rate (ticks/s)
-host_mem_usage 230524 # Number of bytes of host memory used
-host_seconds 14258.17 # Real time elapsed on the host
+host_inst_rate 164548 # Simulator instruction rate (inst/s)
+host_op_rate 164548 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58155841 # Simulator tick rate (ticks/s)
+host_mem_usage 223896 # Number of bytes of host memory used
+host_seconds 11079.10 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 190848 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 33793.696324 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33793.696324 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33793.696324 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 167000 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7952.380952 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.904762 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 43 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 109393 # number of writebacks
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35724.010731 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35103.896073 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 35105.146381 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 105500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 211 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5275 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.550000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 659244465000 # Number of ticks simulated
final_tick 659244465000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88407 # Simulator instruction rate (inst/s)
-host_op_rate 120399 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42099861 # Simulator tick rate (ticks/s)
-host_mem_usage 243836 # Number of bytes of host memory used
-host_seconds 15659.07 # Real time elapsed on the host
+host_inst_rate 153116 # Simulator instruction rate (inst/s)
+host_op_rate 208523 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 72914339 # Simulator tick rate (ticks/s)
+host_mem_usage 237584 # Number of bytes of host memory used
+host_seconds 9041.36 # Real time elapsed on the host
sim_insts 1384375635 # Number of instructions simulated
sim_ops 1885330387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 199616 # Number of bytes read from this memory
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33900.527612 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33900.527612 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 52500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 105 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 17500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 108430 # number of writebacks
sim_ticks 46793182500 # Number of ticks simulated
final_tick 46793182500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59681 # Simulator instruction rate (inst/s)
-host_op_rate 59681 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31612654 # Simulator tick rate (ticks/s)
-host_mem_usage 227600 # Number of bytes of host memory used
-host_seconds 1480.20 # Real time elapsed on the host
+host_inst_rate 131801 # Simulator instruction rate (inst/s)
+host_op_rate 131801 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69813482 # Simulator tick rate (ticks/s)
+host_mem_usage 220956 # Number of bytes of host memory used
+host_seconds 670.26 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 514880 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15833.265655 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 15833.265655 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 1025000 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 2050 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 94 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 10904.255319 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 21.808511 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30939 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 50319.544394 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 50319.544394 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 6260683500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 12521367 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 124119 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50440.975999 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 100.881952 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 165811 # number of writebacks
sim_ticks 21083079000 # Number of ticks simulated
final_tick 21083079000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 162660 # Simulator instruction rate (inst/s)
-host_op_rate 162660 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43087037 # Simulator tick rate (ticks/s)
-host_mem_usage 228624 # Number of bytes of host memory used
-host_seconds 489.31 # Real time elapsed on the host
+host_inst_rate 198104 # Simulator instruction rate (inst/s)
+host_op_rate 198104 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52475767 # Simulator tick rate (ticks/s)
+host_mem_usage 221996 # Number of bytes of host memory used
+host_seconds 401.77 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 559552 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 36802.050170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36802.050170 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 36802.050170 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 90500 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 25500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 181 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 51 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6033.333333 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.066667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 51 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 166256 # number of writebacks
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.787144 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40130.278560 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 39898.128604 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 75 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3409.090909 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6.818182 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 23747395500 # Number of ticks simulated
final_tick 23747395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107822 # Simulator instruction rate (inst/s)
-host_op_rate 153002 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36101670 # Simulator tick rate (ticks/s)
-host_mem_usage 242616 # Number of bytes of host memory used
-host_seconds 657.79 # Real time elapsed on the host
+host_inst_rate 142184 # Simulator instruction rate (inst/s)
+host_op_rate 201762 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47606944 # Simulator tick rate (ticks/s)
+host_mem_usage 237384 # Number of bytes of host memory used
+host_seconds 498.82 # Real time elapsed on the host
sim_insts 70924309 # Number of instructions simulated
sim_ops 100643556 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 325888 # Number of bytes read from this memory
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33713.205595 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 33713.205595 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 197000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 394 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 19700 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 39.400000 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 128103 # number of writebacks
sim_ticks 983202553500 # Number of ticks simulated
final_tick 983202553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94547 # Simulator instruction rate (inst/s)
-host_op_rate 94547 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51082649 # Simulator tick rate (ticks/s)
-host_mem_usage 219392 # Number of bytes of host memory used
-host_seconds 19247.29 # Real time elapsed on the host
+host_inst_rate 119503 # Simulator instruction rate (inst/s)
+host_op_rate 119503 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64565869 # Simulator tick rate (ticks/s)
+host_mem_usage 212872 # Number of bytes of host memory used
+host_seconds 15227.90 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54537.140204 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54537.140204 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 105000 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 210 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 26250 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 52.500000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 218 # number of ReadReq MSHR hits
system.cpu.dcache.demand_avg_miss_latency::total 25004.469885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25004.469885 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25004.469885 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 26428500 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 7896367000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 52857 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15792734 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4352 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 208446 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6072.725184 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 37882.074974 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.145450 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 75.764150 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3389692 # number of writebacks
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53849.243306 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52781.925390 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52782.351713 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 540500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 1081 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 42 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 12869.047619 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 25.738095 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
---------- Begin Simulation Statistics ----------
-sim_seconds 0.601884 # Number of seconds simulated
-sim_ticks 601884201500 # Number of ticks simulated
-final_tick 601884201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.601742 # Number of seconds simulated
+sim_ticks 601741522500 # Number of ticks simulated
+final_tick 601741522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 130981 # Simulator instruction rate (inst/s)
-host_op_rate 130981 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45411041 # Simulator tick rate (ticks/s)
-host_mem_usage 220420 # Number of bytes of host memory used
-host_seconds 13254.14 # Real time elapsed on the host
+host_inst_rate 165987 # Simulator instruction rate (inst/s)
+host_op_rate 165987 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 57533745 # Simulator tick rate (ticks/s)
+host_mem_usage 213900 # Number of bytes of host memory used
+host_seconds 10458.93 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 138169152 # Number of bytes read from this memory
-system.physmem.bytes_read::total 138230976 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67208000 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67208000 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2158893 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2159859 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1050125 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1050125 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 102717 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 229561021 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 229663739 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 102717 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 102717 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 111662675 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 111662675 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 111662675 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 102717 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 229561021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 341326414 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 138172352 # Number of bytes read from this memory
+system.physmem.bytes_read::total 138234112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67207424 # Number of bytes written to this memory
+system.physmem.bytes_written::total 67207424 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2158943 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2159908 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1050116 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1050116 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 102635 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 229620770 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 229723406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 102635 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 102635 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 111688194 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 111688194 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 111688194 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 102635 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 229620770 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 341411600 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 610881152 # DTB read hits
-system.cpu.dtb.read_misses 10794363 # DTB read misses
+system.cpu.dtb.read_hits 610863506 # DTB read hits
+system.cpu.dtb.read_misses 10801691 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 621675515 # DTB read accesses
-system.cpu.dtb.write_hits 207421516 # DTB write hits
-system.cpu.dtb.write_misses 6613595 # DTB write misses
+system.cpu.dtb.read_accesses 621665197 # DTB read accesses
+system.cpu.dtb.write_hits 207455295 # DTB write hits
+system.cpu.dtb.write_misses 6623437 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 214035111 # DTB write accesses
-system.cpu.dtb.data_hits 818302668 # DTB hits
-system.cpu.dtb.data_misses 17407958 # DTB misses
+system.cpu.dtb.write_accesses 214078732 # DTB write accesses
+system.cpu.dtb.data_hits 818318801 # DTB hits
+system.cpu.dtb.data_misses 17425128 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 835710626 # DTB accesses
-system.cpu.itb.fetch_hits 399285601 # ITB hits
-system.cpu.itb.fetch_misses 63 # ITB misses
+system.cpu.dtb.data_accesses 835743929 # DTB accesses
+system.cpu.itb.fetch_hits 399244233 # ITB hits
+system.cpu.itb.fetch_misses 57 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 399285664 # ITB accesses
+system.cpu.itb.fetch_accesses 399244290 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
-system.cpu.numCycles 1203768404 # number of cpu cycles simulated
+system.cpu.numCycles 1203483046 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 378661928 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 290874773 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 18850616 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 264881962 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 260540807 # Number of BTB hits
+system.cpu.BPredUnit.lookups 378630674 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 290853975 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 18842896 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 264245889 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 260518236 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 25136701 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 6159 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 410735894 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 3138932224 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 378661928 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 285677508 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 572729793 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 132567804 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 108566970 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 30 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 399285601 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 10259418 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1199047347 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.617855 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.169243 # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS 25134989 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 6201 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 410689836 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 3138690905 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 378630674 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 285653225 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 572677806 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 132533954 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 108403122 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 1285 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 399244233 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 10255002 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1198760050 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.618281 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.169328 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 626317554 52.23% 52.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 42572057 3.55% 55.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22209930 1.85% 57.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 40806426 3.40% 61.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 126340363 10.54% 71.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 63640386 5.31% 76.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 40565082 3.38% 80.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 30197237 2.52% 82.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 206398312 17.21% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 626082244 52.23% 52.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 42560367 3.55% 55.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22212227 1.85% 57.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 40796625 3.40% 61.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 126320083 10.54% 71.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 63645436 5.31% 76.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 40565089 3.38% 80.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 30205669 2.52% 82.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 206372310 17.22% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1199047347 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.314564 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.607588 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 438876145 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95310008 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 542739947 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 15108786 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 107012461 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 60159953 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 978 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 3060008107 # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total 1198760050 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.314612 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.608006 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 438814843 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95153182 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 542714056 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 15090918 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 106987051 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 60150241 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 1010 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 3059802509 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2177 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 107012461 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 459450274 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50562010 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 5044 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 536182540 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 45835018 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2978218339 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 422353 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1724352 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 41499068 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2227532255 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3846059420 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3844664884 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1394536 # Number of floating rename lookups
+system.cpu.rename.SquashCycles 106987051 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 459387866 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 50448288 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 5147 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 536142849 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 45788849 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2978016816 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 421943 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1715322 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 41464029 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2227365150 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3845813324 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3844419965 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1393359 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 851329292 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 212 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 209 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 95534350 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 674543157 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 250165929 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 60031674 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 34641501 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2674307937 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2477606155 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3178446 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 927538702 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 394492556 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1199047347 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.066312 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.969260 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 851162187 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 215 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 214 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 95471202 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 674494217 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 250159031 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 59771171 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 34263403 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2674166611 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 189 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2477607357 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3173205 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 927397839 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 394299937 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 160 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1198760050 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.066808 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.969624 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 374590988 31.24% 31.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 190702947 15.90% 47.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 181537142 15.14% 62.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 153695699 12.82% 75.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 136730734 11.40% 86.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 80190081 6.69% 93.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 61698536 5.15% 98.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 14532490 1.21% 99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 5368730 0.45% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 374466356 31.24% 31.24% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 190640446 15.90% 47.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 181417957 15.13% 62.27% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 153622544 12.82% 75.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 136730069 11.41% 86.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 80254846 6.69% 93.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 61695164 5.15% 98.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 14563469 1.21% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 5369199 0.45% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1199047347 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1198760050 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 2248592 11.88% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12188219 64.39% 76.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 4492341 23.73% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 2251857 11.87% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12201284 64.32% 76.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 4515049 23.80% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1617099394 65.27% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 98 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1617068630 65.27% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 94 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 284 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 297 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 161 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 32 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 171 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 41 0.00% 65.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.27% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.27% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 639262195 25.80% 91.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 221243949 8.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 639258763 25.80% 91.07% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 221279320 8.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2477606155 # Type of FU issued
-system.cpu.iq.rate 2.058208 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 18929152 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.007640 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 6174384179 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3600600502 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 2375948293 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1983076 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 1349305 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 869249 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2495560681 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 974626 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 56273066 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2477607357 # Type of FU issued
+system.cpu.iq.rate 2.058697 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 18968190 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.007656 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 6174132781 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 3600319262 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 2375945234 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 1983378 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 1347629 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 869060 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2495600765 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 974782 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 56278777 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 229947494 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 250240 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 104617 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 89437427 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 229898554 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 250139 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 103830 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 89430529 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 223 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 81293 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 234 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 81236 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 107012461 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 18493719 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 964338 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2816222496 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 17539215 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 674543157 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 250165929 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 222443 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 13054 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 104617 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 13266110 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8853005 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 22119115 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 2426782897 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 621677051 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 50823258 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 106987051 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 18488263 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 963433 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2816062244 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 17529415 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 674494217 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 250159031 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 189 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 221508 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12923 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 103830 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 13260228 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8848776 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 22109004 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 2426798028 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 621666775 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 50809329 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 141914378 # number of nop insts executed
-system.cpu.iew.exec_refs 835712197 # number of memory reference insts executed
-system.cpu.iew.exec_branches 297017404 # Number of branches executed
-system.cpu.iew.exec_stores 214035146 # Number of stores executed
-system.cpu.iew.exec_rate 2.015988 # Inst execution rate
-system.cpu.iew.wb_sent 2405357276 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 2376817542 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1361466858 # num instructions producing a value
-system.cpu.iew.wb_consumers 1724557006 # num instructions consuming a value
+system.cpu.iew.exec_nop 141895444 # number of nop insts executed
+system.cpu.iew.exec_refs 835745555 # number of memory reference insts executed
+system.cpu.iew.exec_branches 297016780 # Number of branches executed
+system.cpu.iew.exec_stores 214078780 # Number of stores executed
+system.cpu.iew.exec_rate 2.016479 # Inst execution rate
+system.cpu.iew.wb_sent 2405369179 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 2376814294 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1361493757 # num instructions producing a value
+system.cpu.iew.wb_consumers 1724612513 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.974481 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.789459 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.974946 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.789449 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 756599351 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 756436478 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 18849719 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1092034886 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.666412 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.514594 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 18841975 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1091772999 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.666812 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.514787 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 565812226 51.81% 51.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 181963708 16.66% 68.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 91431923 8.37% 76.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 53287438 4.88% 81.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 36685843 3.36% 85.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 28834990 2.64% 87.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 22491649 2.06% 89.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 22994830 2.11% 91.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 88532279 8.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 565636558 51.81% 51.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 181878211 16.66% 68.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 91372107 8.37% 76.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 53285897 4.88% 81.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 36714852 3.36% 85.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 28908245 2.65% 87.73% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 22459323 2.06% 89.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 22999009 2.11% 91.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 88518797 8.11% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1092034886 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1091772999 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1819780126 # Number of instructions committed
system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 805525 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1718967519 # Number of committed integer instructions.
system.cpu.commit.function_calls 16767440 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 88532279 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 88518797 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 3494102884 # The number of ROB reads
-system.cpu.rob.rob_writes 5259875951 # The number of ROB writes
-system.cpu.timesIdled 272602 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 4721057 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 3493691606 # The number of ROB reads
+system.cpu.rob.rob_writes 5259524652 # The number of ROB writes
+system.cpu.timesIdled 273067 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 4722996 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.693397 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.693397 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.442174 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.442174 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3262431101 # number of integer regfile reads
-system.cpu.int_regfile_writes 1906790236 # number of integer regfile writes
-system.cpu.fp_regfile_reads 51143 # number of floating regfile reads
-system.cpu.fp_regfile_writes 554 # number of floating regfile writes
+system.cpu.cpi 0.693233 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.693233 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.442516 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.442516 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3262496367 # number of integer regfile reads
+system.cpu.int_regfile_writes 1906751993 # number of integer regfile writes
+system.cpu.fp_regfile_reads 51073 # number of floating regfile reads
+system.cpu.fp_regfile_writes 575 # number of floating regfile writes
system.cpu.misc_regfile_reads 25 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.tagsinuse 770.355491 # Cycle average of tags in use
-system.cpu.icache.total_refs 399284112 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 966 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 413337.590062 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 769.815211 # Cycle average of tags in use
+system.cpu.icache.total_refs 399242763 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 965 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 413723.070466 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 770.355491 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.376150 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.376150 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 399284112 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 399284112 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 399284112 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 399284112 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 399284112 # number of overall hits
-system.cpu.icache.overall_hits::total 399284112 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1489 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1489 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1489 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1489 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1489 # number of overall misses
-system.cpu.icache.overall_misses::total 1489 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 51254000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 51254000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 51254000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 51254000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 51254000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 51254000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 399285601 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 399285601 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 399285601 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 399285601 # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst 769.815211 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.375886 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.375886 # Average percentage of cache occupancy
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+system.cpu.icache.overall_hits::total 399242763 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1470 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1470 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 1470 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1470 # number of overall misses
+system.cpu.icache.overall_misses::total 1470 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 50742000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 50742000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 50742000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 50742000 # number of overall miss cycles
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+system.cpu.icache.demand_accesses::total 399244233 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 399244233 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34421.759570 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 34421.759570 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 34421.759570 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 34421.759570 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 34421.759570 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34518.367347 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34518.367347 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34518.367347 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34518.367347 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34518.367347 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 523 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 523 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 523 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 523 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 523 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 523 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36312000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 36312000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36312000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 36312000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36312000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 36312000 # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_rate::total 0.235247 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33402.173913 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32734.298390 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.766834 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33826.852580 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33826.852580 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33402.173913 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33130.350442 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33130.472015 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.235170 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.235250 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33372.020725 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32733.649392 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32734.096633 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33823.259993 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33823.259993 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33372.020725 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33128.579819 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33128.688583 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.454220 # Number of seconds simulated
-sim_ticks 454219906500 # Number of ticks simulated
-final_tick 454219906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.454149 # Number of seconds simulated
+sim_ticks 454149445000 # Number of ticks simulated
+final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 138720 # Simulator instruction rate (inst/s)
-host_op_rate 154753 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40794382 # Simulator tick rate (ticks/s)
-host_mem_usage 234840 # Number of bytes of host memory used
-host_seconds 11134.37 # Real time elapsed on the host
+host_inst_rate 251011 # Simulator instruction rate (inst/s)
+host_op_rate 280022 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 73805166 # Simulator tick rate (ticks/s)
+host_mem_usage 228580 # Number of bytes of host memory used
+host_seconds 6153.36 # Real time elapsed on the host
sim_insts 1544563043 # Number of instructions simulated
sim_ops 1723073855 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 47808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 156313408 # Number of bytes read from this memory
-system.physmem.bytes_read::total 156361216 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 47808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 47808 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 71943232 # Number of bytes written to this memory
-system.physmem.bytes_written::total 71943232 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 747 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 2442397 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 2443144 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1124113 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1124113 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 105253 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 344135970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 344241223 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 105253 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 105253 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 158388549 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 158388549 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 158388549 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 105253 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 344135970 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 502629772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory
+system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory
+system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 908439814 # number of cpu cycles simulated
+system.cpu.numCycles 908298891 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 299293350 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 245165786 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16042294 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 167415927 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 155291115 # Number of BTB hits
+system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 18349808 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 218 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 291155231 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2147464853 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 299293350 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 173640923 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 427083963 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 82022952 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 117971766 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 81 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 282205512 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 5329978 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 901954385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.649183 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.246512 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 474870538 52.65% 52.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 22740626 2.52% 55.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 38702218 4.29% 59.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 47644255 5.28% 64.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 40322718 4.47% 69.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 46782649 5.19% 74.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38980366 4.32% 78.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 18009770 2.00% 80.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 173901245 19.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 901954385 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.329459 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.363904 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 319244517 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 99044104 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 402843645 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 15079439 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 65742680 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 46017167 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 685 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2336575701 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2448 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 65742680 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 340277658 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 45082178 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 13877 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 395714637 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 55123355 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2280505483 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 18602 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 4635517 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 42073464 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 2255238182 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 10526656383 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 10526652098 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 4285 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle
+system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 548918220 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1694 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1690 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 127506095 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 622196847 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 217942695 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 85227601 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 65382931 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2181344295 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1719 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 2010119502 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 4796816 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 454085036 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1056260113 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1545 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 901954385 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.228627 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.927984 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 241738453 26.80% 26.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 133353594 14.78% 41.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 156367006 17.34% 58.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 115954647 12.86% 71.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 125581942 13.92% 85.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 75899476 8.42% 94.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 39722592 4.40% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 10686145 1.18% 99.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2650530 0.29% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 901954385 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 695241 2.77% 2.77% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 4797 0.02% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.79% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 19085015 76.16% 78.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 5273410 21.04% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1230459115 61.21% 61.21% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 930103 0.05% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 33 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 585119298 29.11% 90.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 193610861 9.63% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 2010119502 # Type of FU issued
-system.cpu.iq.rate 2.212716 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 25058463 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012466 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4952048213 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2635615257 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1952750313 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 455 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 782 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 169 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2035177734 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 63595770 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued
+system.cpu.iq.rate 2.213059 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 136270074 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 285522 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 187812 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 43095646 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 118212 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 65742680 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 20161039 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1080033 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2181346094 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 5536242 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 622196847 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 217942695 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1653 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 177278 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 42353 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 187812 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8595145 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 10187661 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 18782806 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1980860321 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 570725685 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29259181 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 80 # number of nop insts executed
-system.cpu.iew.exec_refs 761335906 # number of memory reference insts executed
-system.cpu.iew.exec_branches 237528825 # Number of branches executed
-system.cpu.iew.exec_stores 190610221 # Number of stores executed
-system.cpu.iew.exec_rate 2.180508 # Inst execution rate
-system.cpu.iew.wb_sent 1961779173 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1952750482 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1293463699 # num instructions producing a value
-system.cpu.iew.wb_consumers 2065510739 # num instructions consuming a value
+system.cpu.iew.exec_nop 81 # number of nop insts executed
+system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed
+system.cpu.iew.exec_branches 237537296 # Number of branches executed
+system.cpu.iew.exec_stores 190660380 # Number of stores executed
+system.cpu.iew.exec_rate 2.180837 # Inst execution rate
+system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1293399468 # num instructions producing a value
+system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.149565 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.626220 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 458335863 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 16041632 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 836211706 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.060571 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.763665 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 346444317 41.43% 41.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 193987468 23.20% 64.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 73877669 8.83% 73.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 35342489 4.23% 77.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 18524109 2.22% 79.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 30984795 3.71% 83.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 19692342 2.35% 85.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 10738999 1.28% 87.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 106619518 12.75% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 836211706 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563061 # Number of instructions committed
system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 106619518 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 2911001325 # The number of ROB reads
-system.cpu.rob.rob_writes 4428720797 # The number of ROB writes
-system.cpu.timesIdled 678798 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 6485429 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 2910643265 # The number of ROB reads
+system.cpu.rob.rob_writes 4428322151 # The number of ROB writes
+system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563043 # Number of Instructions Simulated
system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated
-system.cpu.cpi 0.588153 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.588153 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.700237 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.700237 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 9924440864 # number of integer regfile reads
-system.cpu.int_regfile_writes 1932829114 # number of integer regfile writes
-system.cpu.fp_regfile_reads 176 # number of floating regfile reads
-system.cpu.fp_regfile_writes 197 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2885564305 # number of misc regfile reads
+system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads
+system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes
+system.cpu.fp_regfile_reads 180 # number of floating regfile reads
+system.cpu.fp_regfile_writes 196 # number of floating regfile writes
+system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads
system.cpu.misc_regfile_writes 132 # number of misc regfile writes
-system.cpu.icache.replacements 18 # number of replacements
-system.cpu.icache.tagsinuse 627.769502 # Cycle average of tags in use
-system.cpu.icache.total_refs 282204371 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 777 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 363197.388674 # Average number of references to valid blocks.
+system.cpu.icache.replacements 25 # number of replacements
+system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use
+system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 627.769502 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.306528 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.306528 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 282204371 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 282204371 # number of ReadReq hits
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+system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 21086 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5487.058807 # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1124113 # number of writebacks
-system.cpu.l2cache.writebacks::total 1124113 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits
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system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 831024 # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25029000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54213758000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33085952005 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33085952005 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25029000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87299710005 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25029000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87299710005 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 87324739005 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208534 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208610 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438714 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438714 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for demand accesses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960154 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253851 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.253908 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33506.024096 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33644.449795 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33644.385654 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39813.473504 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39813.473504 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33506.024096 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35743.456123 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35742.772020 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 42001440000 # Number of ticks simulated
final_tick 42001440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75192 # Simulator instruction rate (inst/s)
-host_op_rate 75192 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34364250 # Simulator tick rate (ticks/s)
-host_mem_usage 223172 # Number of bytes of host memory used
-host_seconds 1222.24 # Real time elapsed on the host
+host_inst_rate 134131 # Simulator instruction rate (inst/s)
+host_op_rate 134131 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 61300636 # Simulator tick rate (ticks/s)
+host_mem_usage 216520 # Number of bytes of host memory used
+host_seconds 685.17 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24215.288412 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 24215.288412 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 92000 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 184 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 15333.333333 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1742 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 54653.714005 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 54653.714005 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 41228500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 82457 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 827 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 49853.083434 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 99.706167 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
sim_ticks 23659827000 # Number of ticks simulated
final_tick 23659827000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114539 # Simulator instruction rate (inst/s)
-host_op_rate 114539 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32192844 # Simulator tick rate (ticks/s)
-host_mem_usage 224192 # Number of bytes of host memory used
-host_seconds 734.94 # Real time elapsed on the host
+host_inst_rate 188397 # Simulator instruction rate (inst/s)
+host_op_rate 188397 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52951506 # Simulator tick rate (ticks/s)
+host_mem_usage 217548 # Number of bytes of host memory used
+host_seconds 446.82 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 197632 # Number of bytes read from this memory
system.cpu.dcache.demand_avg_miss_latency::total 35694.911504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35694.911504 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35694.911504 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 11 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5500 # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35341.806995 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38760.286639 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36749.952390 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 75929256000 # Number of ticks simulated
final_tick 75929256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99785 # Simulator instruction rate (inst/s)
-host_op_rate 109254 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43964821 # Simulator tick rate (ticks/s)
-host_mem_usage 238132 # Number of bytes of host memory used
-host_seconds 1727.05 # Real time elapsed on the host
+host_inst_rate 126863 # Simulator instruction rate (inst/s)
+host_op_rate 138901 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55895176 # Simulator tick rate (ticks/s)
+host_mem_usage 231880 # Number of bytes of host memory used
+host_seconds 1358.42 # Real time elapsed on the host
sim_insts 172333091 # Number of instructions simulated
sim_ops 188686573 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 132864 # Number of bytes read from this memory
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31016.696141 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31016.696141 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 4500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 4500 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 18 # number of writebacks
---------- Begin Simulation Statistics ----------
-sim_seconds 1.870336 # Number of seconds simulated
-sim_ticks 1870335522500 # Number of ticks simulated
-final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.870325 # Number of seconds simulated
+sim_ticks 1870325497500 # Number of ticks simulated
+final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3051606 # Simulator instruction rate (inst/s)
-host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 90374561583 # Simulator tick rate (ticks/s)
-host_mem_usage 305448 # Number of bytes of host memory used
-host_seconds 20.70 # Real time elapsed on the host
-sim_insts 63154034 # Number of instructions simulated
-sim_ops 63154034 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory
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system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
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system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 81316 # number of writebacks
-system.l2c.writebacks::total 81316 # number of writebacks
+system.l2c.writebacks::writebacks 81175 # number of writebacks
+system.l2c.writebacks::total 81175 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.iocache.tagsinuse 0.435437 # Cycle average of tags in use
+system.iocache.replacements 41694 # number of replacements
+system.iocache.tagsinuse 0.435353 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 41711 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
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+system.iocache.warmup_cycle 1685787105067 # Cycle when the warmup percentage was hit.
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+system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
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system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
-system.iocache.overall_misses::total 41727 # number of overall misses
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system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
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system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 9154530 # DTB read hits
+system.cpu0.dtb.read_hits 9148429 # DTB read hits
system.cpu0.dtb.read_misses 7079 # DTB read misses
system.cpu0.dtb.read_acv 152 # DTB read access violations
system.cpu0.dtb.read_accesses 508987 # DTB read accesses
-system.cpu0.dtb.write_hits 5936899 # DTB write hits
+system.cpu0.dtb.write_hits 5932048 # DTB write hits
system.cpu0.dtb.write_misses 726 # DTB write misses
system.cpu0.dtb.write_acv 99 # DTB write access violations
system.cpu0.dtb.write_accesses 189050 # DTB write accesses
-system.cpu0.dtb.data_hits 15091429 # DTB hits
+system.cpu0.dtb.data_hits 15080477 # DTB hits
system.cpu0.dtb.data_misses 7805 # DTB misses
system.cpu0.dtb.data_acv 251 # DTB access violations
system.cpu0.dtb.data_accesses 698037 # DTB accesses
-system.cpu0.itb.fetch_hits 3855556 # ITB hits
+system.cpu0.itb.fetch_hits 3854196 # ITB hits
system.cpu0.itb.fetch_misses 3485 # ITB misses
system.cpu0.itb.fetch_acv 127 # ITB acv
-system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
+system.cpu0.itb.fetch_accesses 3857681 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3740670933 # number of cpu cycles simulated
+system.cpu0.numCycles 3740650883 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 57222076 # Number of instructions committed
-system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
-system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 53249924 # number of integer instructions
-system.cpu0.num_fp_insts 299810 # number of float instructions
-system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15135515 # number of memory refs
-system.cpu0.num_load_insts 9184477 # Number of load instructions
-system.cpu0.num_store_insts 5951038 # Number of store instructions
-system.cpu0.num_idle_cycles 3683437089.313678 # Number of idle cycles
-system.cpu0.num_busy_cycles 57233843.686322 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
+system.cpu0.committedInsts 57184467 # Number of instructions committed
+system.cpu0.committedOps 57184467 # Number of ops (including micro ops) committed
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+system.cpu0.num_fp_alu_accesses 299670 # Number of float alu accesses
+system.cpu0.num_func_calls 1398025 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 6803964 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 53214865 # number of integer instructions
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+system.cpu0.num_int_register_reads 73271755 # number of times the integer registers were read
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+system.cpu0.num_fp_register_reads 147658 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 150767 # number of times the floating registers were written
+system.cpu0.num_mem_refs 15124548 # number of memory refs
+system.cpu0.num_load_insts 9178366 # Number of load instructions
+system.cpu0.num_store_insts 5946182 # Number of store instructions
+system.cpu0.num_idle_cycles 3683454679.572560 # Number of idle cycles
+system.cpu0.num_busy_cycles 57196203.427440 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.015290 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.984710 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6280 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 196965 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 70940 40.60% 40.60% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::31 101631 58.16% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 174730 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 69573 49.24% 49.24% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::31 69565 49.23% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 141297 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1852985718000 99.07% 99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
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+system.cpu0.kern.ipl_ticks::total 1870325290000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.980730 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl
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system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 226 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed
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system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed
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system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
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system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
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system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed
system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 183291 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
+system.cpu0.kern.callpal::total 183136 # number of callpals executed
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system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1157
-system.cpu0.kern.mode_good::user 1158
+system.cpu0.kern.mode_good::kernel 1155
+system.cpu0.kern.mode_good::user 1156
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
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system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
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+system.cpu0.kern.mode_switch_good::total 0.280291 # fraction of useful protection mode switches
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system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3761 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 884404 # number of replacements
-system.cpu0.icache.tagsinuse 511.244754 # Cycle average of tags in use
-system.cpu0.icache.total_refs 56345132 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks.
+system.cpu0.icache.replacements 883989 # number of replacements
+system.cpu0.icache.tagsinuse 511.244895 # Cycle average of tags in use
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system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor
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system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits
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-system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
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system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
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system.cpu1.dtb.read_misses 3277 # DTB read misses
system.cpu1.dtb.read_acv 58 # DTB read access violations
system.cpu1.dtb.read_accesses 220342 # DTB read accesses
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system.cpu1.dtb.write_misses 415 # DTB write misses
system.cpu1.dtb.write_acv 58 # DTB write access violations
system.cpu1.dtb.write_accesses 103280 # DTB write accesses
-system.cpu1.dtb.data_hits 1914885 # DTB hits
+system.cpu1.dtb.data_hits 1925043 # DTB hits
system.cpu1.dtb.data_misses 3692 # DTB misses
system.cpu1.dtb.data_acv 116 # DTB access violations
system.cpu1.dtb.data_accesses 323622 # DTB accesses
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system.cpu1.itb.fetch_misses 1539 # ITB misses
system.cpu1.itb.fetch_acv 57 # ITB acv
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+system.cpu1.itb.fetch_accesses 1471216 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
+system.cpu1.numCycles 3740237218 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
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-system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 5550578 # number of integer instructions
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-system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
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-system.cpu1.num_load_insts 1170888 # Number of load instructions
-system.cpu1.num_store_insts 755356 # Number of store instructions
-system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
-system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
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+system.cpu1.not_idle_fraction 0.001597 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.998403 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl
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-system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
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+system.cpu1.kern.ipl_good::31 10267 45.30% 100.00% # number of times we switched to this ipl from a different ipl
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system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
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-system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
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+system.cpu1.kern.ipl_used::0 0.999037 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl
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system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed
system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed
system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed
system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
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system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed
system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed
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-system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed
-system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 26358 81.69% 83.25% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2589 8.02% 91.28% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 91.28% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 91.29% # number of callpals executed
+system.cpu1.kern.callpal::rdusp 2 0.01% 91.30% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.01% 91.31% # number of callpals executed
+system.cpu1.kern.callpal::rti 2608 8.08% 99.39% # number of callpals executed
system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed
system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 32131 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches
+system.cpu1.kern.callpal::total 32267 # number of callpals executed
+system.cpu1.kern.mode_switch::kernel 1034 # number of protection mode switches
system.cpu1.kern.mode_switch::user 580 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 612
+system.cpu1.kern.mode_switch::idle 2048 # number of protection mode switches
+system.cpu1.kern.mode_good::kernel 613
system.cpu1.kern.mode_good::user 580
-system.cpu1.kern.mode_good::idle 32
-system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches
+system.cpu1.kern.mode_good::idle 33
+system.cpu1.kern.mode_switch_good::kernel 0.592843 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
+system.cpu1.kern.mode_switch_good::idle 0.016113 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 0.334790 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 1393260500 0.07% 0.07% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 471 # number of times the context was actually changed
-system.cpu1.icache.replacements 103091 # number of replacements
-system.cpu1.icache.tagsinuse 427.126317 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5832136 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits
-system.cpu1.icache.overall_hits::total 5832136 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses
-system.cpu1.icache.overall_misses::total 103630 # number of overall misses
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses
+system.cpu1.kern.mode_ticks::idle 1867980072500 99.90% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 473 # number of times the context was actually changed
+system.cpu1.icache.replacements 104103 # number of replacements
+system.cpu1.icache.tagsinuse 427.138444 # Cycle average of tags in use
+system.cpu1.icache.total_refs 5865807 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 104615 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 56.070420 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1868930362000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 427.138444 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.834255 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.834255 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 5865807 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 5865807 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 5865807 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 5865807 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 5865807 # number of overall hits
+system.cpu1.icache.overall_hits::total 5865807 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 104648 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 104648 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 104648 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 104648 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 104648 # number of overall misses
+system.cpu1.icache.overall_misses::total 104648 # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 5970455 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 5970455 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 5970455 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 5970455 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::total 5970455 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017528 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.017528 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017528 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.017528 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017528 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.017528 # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 62044 # number of replacements
-system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1836054 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 62382 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 29.432432 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.823365 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses
-system.cpu1.dcache.overall_misses::total 67292 # number of overall misses
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses
+system.cpu1.dcache.replacements 62444 # number of replacements
+system.cpu1.dcache.tagsinuse 421.660465 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 1845254 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 62784 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 29.390514 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1851113732500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 421.660465 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.823556 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.823556 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1114890 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1114890 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 711494 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 711494 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15278 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 15278 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15743 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 15743 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 1826384 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 1826384 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 1826384 # number of overall hits
+system.cpu1.dcache.overall_hits::total 1826384 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 41651 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 41651 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 26091 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 26091 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1291 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 1291 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 751 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 751 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 67742 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 67742 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 67742 # number of overall misses
+system.cpu1.dcache.overall_misses::total 67742 # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1156541 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 1156541 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 737585 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 737585 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16569 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 16569 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16494 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 16494 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 1894126 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 1894126 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1894126 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 1894126 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036013 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.036013 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035374 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.035374 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077917 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.077917 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.045532 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.045532 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035764 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.035764 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035764 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.035764 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks
-system.cpu1.dcache.writebacks::total 41012 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 41317 # number of writebacks
+system.cpu1.dcache.writebacks::total 41317 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.829332 # Number of seconds simulated
-sim_ticks 1829332258000 # Number of ticks simulated
-final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.829331 # Number of seconds simulated
+sim_ticks 1829330593000 # Number of ticks simulated
+final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2962809 # Simulator instruction rate (inst/s)
-host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 90274916526 # Simulator tick rate (ticks/s)
-host_mem_usage 302384 # Number of bytes of host memory used
-host_seconds 20.26 # Real time elapsed on the host
-sim_insts 60038305 # Number of instructions simulated
-sim_ops 60038305 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
+host_inst_rate 2569577 # Simulator instruction rate (inst/s)
+host_op_rate 2569575 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 78294086451 # Simulator tick rate (ticks/s)
+host_mem_usage 295292 # Number of bytes of host memory used
+host_seconds 23.37 # Real time elapsed on the host
+sim_insts 60037737 # Number of instructions simulated
+sim_ops 60037737 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 66839296 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 70349440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 857856 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 857856 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7411136 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7411136 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 13404 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1044364 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.l2cache.replacements 992301 # number of replacements
-system.cpu.l2cache.tagsinuse 65424.374305 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2433239 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 1057464 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 2.301014 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
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-system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
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-system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
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-system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
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-system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
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-system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
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-system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
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-system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
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+system.physmem.bw_read::cpu.inst 468945 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::total 42507667 # Total bandwidth to/from this memory (bytes/s)
system.iocache.replacements 41686 # number of replacements
-system.iocache.tagsinuse 1.225570 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
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system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9710427 # DTB read hits
+system.cpu.dtb.read_hits 9710417 # DTB read hits
system.cpu.dtb.read_misses 10329 # DTB read misses
system.cpu.dtb.read_acv 210 # DTB read access violations
system.cpu.dtb.read_accesses 728856 # DTB read accesses
-system.cpu.dtb.write_hits 6352498 # DTB write hits
+system.cpu.dtb.write_hits 6352487 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
system.cpu.dtb.write_acv 157 # DTB write access violations
system.cpu.dtb.write_accesses 291931 # DTB write accesses
-system.cpu.dtb.data_hits 16062925 # DTB hits
+system.cpu.dtb.data_hits 16062904 # DTB hits
system.cpu.dtb.data_misses 11471 # DTB misses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_accesses 1020787 # DTB accesses
-system.cpu.itb.fetch_hits 4974648 # ITB hits
+system.cpu.itb.fetch_hits 4974615 # ITB hits
system.cpu.itb.fetch_misses 5006 # ITB misses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_accesses 4979654 # ITB accesses
+system.cpu.itb.fetch_accesses 4979621 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 3658664408 # number of cpu cycles simulated
+system.cpu.numCycles 3658661078 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
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+system.cpu.committedOps 60037737 # Number of ops (including micro ops) committed
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system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
-system.cpu.num_func_calls 1484182 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
-system.cpu.num_int_insts 55913521 # number of integer instructions
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system.cpu.num_fp_insts 324460 # number of float instructions
-system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
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system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
-system.cpu.num_mem_refs 16115709 # number of memory refs
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-system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
-system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
+system.cpu.num_mem_refs 16115688 # number of memory refs
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+system.cpu.not_idle_fraction 0.016414 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.983586 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
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system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105620 57.86% 100.00% # number of times we switched to this ipl
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system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
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system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
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+system.cpu.kern.ipl_ticks::31 17304126000 0.95% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1829330385500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
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-system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.695541 # fraction of swpipl calls that actually changed the ipl
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system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
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system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192180 # number of callpals executed
-system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
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-system.cpu.kern.mode_good::kernel 1909
-system.cpu.kern.mode_good::user 1738
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system.cpu.kern.mode_good::idle 171
-system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
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system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 919594 # number of replacements
-system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use
-system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
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-system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
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-system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042702 # number of replacements
+system.cpu.dcache.replacements 2042708 # number of replacements
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038431 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043214 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870759 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
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-system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses
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system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
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-system.cpu.dcache.overall_misses::total 2026069 # number of overall misses
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-system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
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-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
system.cpu.dcache.writebacks::total 833491 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 992297 # number of replacements
+system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2433229 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 1057460 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.301013 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 56309.097195 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 4867.351144 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 4247.927161 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.998297 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 906782 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1718014 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 187234 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 187234 # number of ReadExReq hits
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+system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
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+system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 304349 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.353901 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384805 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.384805 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014567 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.511327 # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014567 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.511327 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
+system.cpu.l2cache.writebacks::total 74287 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 1.962058 # Number of seconds simulated
-sim_ticks 1962057812000 # Number of ticks simulated
-final_tick 1962057812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.955746 # Number of seconds simulated
+sim_ticks 1955746240500 # Number of ticks simulated
+final_tick 1955746240500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1235183 # Simulator instruction rate (inst/s)
-host_op_rate 1235183 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40819911602 # Simulator tick rate (ticks/s)
-host_mem_usage 297060 # Number of bytes of host memory used
-host_seconds 48.07 # Real time elapsed on the host
-sim_insts 59370518 # Number of instructions simulated
-sim_ops 59370518 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 834432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24593280 # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide 2650816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 29312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 572992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28680832 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 834432 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 29312 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 863744 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7715456 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7715456 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13038 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 384270 # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide 41419 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 458 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8953 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 448138 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120554 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120554 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 425284 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12534432 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide 1351039 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 14939 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 292036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14617730 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 425284 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 14939 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 440224 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3932329 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3932329 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3932329 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 425284 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12534432 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide 1351039 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 14939 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 292036 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 18550059 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 341238 # number of replacements
-system.l2c.tagsinuse 65290.171288 # Cycle average of tags in use
-system.l2c.total_refs 2492514 # Total number of references to valid blocks.
-system.l2c.sampled_refs 406253 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.135374 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 7854344000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 55481.148199 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4824.640956 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4855.323185 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 116.032373 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 13.026576 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.846575 # Average percentage of cache occupancy
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-system.l2c.occ_percent::cpu0.data 0.074086 # Average percentage of cache occupancy
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-system.l2c.occ_percent::total 0.996249 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst 902430 # number of ReadReq hits
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-system.l2c.ReadReq_hits::total 1795074 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 820361 # number of Writeback hits
-system.l2c.Writeback_hits::total 820361 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 161 # number of UpgradeReq hits
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+system.cpu0.dtb.data_acv 344 # DTB access violations
+system.cpu0.dtb.data_accesses 678125 # DTB accesses
+system.cpu0.itb.fetch_hits 3500956 # ITB hits
+system.cpu0.itb.fetch_misses 3871 # ITB misses
+system.cpu0.itb.fetch_acv 184 # ITB acv
+system.cpu0.itb.fetch_accesses 3504827 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 3924115624 # number of cpu cycles simulated
+system.cpu0.numCycles 3910167080 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 54116505 # Number of instructions committed
-system.cpu0.committedOps 54116505 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 50087098 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 302903 # Number of float alu accesses
-system.cpu0.num_func_calls 1426970 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 6243728 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 50087098 # number of integer instructions
-system.cpu0.num_fp_insts 302903 # number of float instructions
-system.cpu0.num_int_register_reads 68610814 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 37122288 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 149298 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 152355 # number of times the floating registers were written
-system.cpu0.num_mem_refs 14741096 # number of memory refs
-system.cpu0.num_load_insts 8689646 # Number of load instructions
-system.cpu0.num_store_insts 6051450 # Number of store instructions
-system.cpu0.num_idle_cycles 3676817171.998126 # Number of idle cycles
-system.cpu0.num_busy_cycles 247298452.001874 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.063020 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.936980 # Percentage of idle cycles
+system.cpu0.committedInsts 47719039 # Number of instructions committed
+system.cpu0.committedOps 47719039 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 44257119 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 210954 # Number of float alu accesses
+system.cpu0.num_func_calls 1200899 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 5607083 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 44257119 # number of integer instructions
+system.cpu0.num_fp_insts 210954 # number of float instructions
+system.cpu0.num_int_register_reads 60839484 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 32982631 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 102466 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 104326 # number of times the floating registers were written
+system.cpu0.num_mem_refs 12590587 # number of memory refs
+system.cpu0.num_load_insts 7513713 # Number of load instructions
+system.cpu0.num_store_insts 5076874 # Number of store instructions
+system.cpu0.num_idle_cycles 3701181001.496715 # Number of idle cycles
+system.cpu0.num_busy_cycles 208986078.503285 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.053447 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.946553 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 202757 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 72604 40.61% 40.61% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.07% 40.69% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1979 1.11% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 6 0.00% 41.80% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 104050 58.20% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 178770 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 71235 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1979 1.37% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 71229 49.27% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 144580 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1900688314000 96.87% 96.87% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 102511500 0.01% 96.88% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 795126500 0.04% 96.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 5572000 0.00% 96.92% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 60465450000 3.08% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1962056974000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981144 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce 6789 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 164868 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 56806 40.18% 40.18% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1972 1.39% 41.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 420 0.30% 41.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 82040 58.03% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 141369 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 56268 49.08% 49.08% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1972 1.72% 50.92% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 420 0.37% 51.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 55848 48.72% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 114639 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1899887304000 97.18% 97.18% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 92906000 0.00% 97.18% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 760170500 0.04% 97.22% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 309335500 0.02% 97.24% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 54033794000 2.76% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1955083510000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.990529 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684565 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.808749 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed
-system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed
-system.cpu0.kern.syscall::6 30 13.39% 25.89% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.45% 26.34% # number of syscalls executed
-system.cpu0.kern.syscall::15 1 0.45% 26.79% # number of syscalls executed
-system.cpu0.kern.syscall::17 10 4.46% 31.25% # number of syscalls executed
-system.cpu0.kern.syscall::19 6 2.68% 33.93% # number of syscalls executed
-system.cpu0.kern.syscall::20 4 1.79% 35.71% # number of syscalls executed
-system.cpu0.kern.syscall::23 2 0.89% 36.61% # number of syscalls executed
-system.cpu0.kern.syscall::24 4 1.79% 38.39% # number of syscalls executed
-system.cpu0.kern.syscall::33 8 3.57% 41.96% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.89% 42.86% # number of syscalls executed
-system.cpu0.kern.syscall::45 39 17.41% 60.27% # number of syscalls executed
-system.cpu0.kern.syscall::47 4 1.79% 62.05% # number of syscalls executed
-system.cpu0.kern.syscall::48 7 3.12% 65.18% # number of syscalls executed
-system.cpu0.kern.syscall::54 9 4.02% 69.20% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.45% 69.64% # number of syscalls executed
-system.cpu0.kern.syscall::59 5 2.23% 71.88% # number of syscalls executed
-system.cpu0.kern.syscall::71 32 14.29% 86.16% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.34% 87.50% # number of syscalls executed
-system.cpu0.kern.syscall::74 9 4.02% 91.52% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.45% 91.96% # number of syscalls executed
-system.cpu0.kern.syscall::90 2 0.89% 92.86% # number of syscalls executed
-system.cpu0.kern.syscall::92 7 3.12% 95.98% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.89% 96.87% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.89% 97.77% # number of syscalls executed
-system.cpu0.kern.syscall::132 2 0.89% 98.66% # number of syscalls executed
-system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 224 # number of syscalls executed
+system.cpu0.kern.ipl_used::31 0.680741 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.810920 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
+system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
+system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
+system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
+system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
+system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
+system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
+system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 222 # number of syscalls executed
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 91 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3872 2.06% 2.11% # number of callpals executed
-system.cpu0.kern.callpal::tbi 44 0.02% 2.13% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 171948 91.52% 93.66% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6691 3.56% 97.22% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 4 0.00% 97.22% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 7 0.00% 97.23% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.23% # number of callpals executed
-system.cpu0.kern.callpal::rti 4705 2.50% 99.73% # number of callpals executed
-system.cpu0.kern.callpal::callsys 356 0.19% 99.92% # number of callpals executed
-system.cpu0.kern.callpal::imb 149 0.08% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 187881 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 7233 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1235 # number of protection mode switches
+system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3070 2.05% 2.39% # number of callpals executed
+system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed
+system.cpu0.kern.callpal::wrent 7 0.00% 2.43% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 134512 89.86% 92.29% # number of callpals executed
+system.cpu0.kern.callpal::rdps 6676 4.46% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.75% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed
+system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed
+system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed
+system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed
+system.cpu0.kern.callpal::total 149688 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6889 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1285 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1234
-system.cpu0.kern.mode_good::user 1235
+system.cpu0.kern.mode_good::kernel 1285
+system.cpu0.kern.mode_good::user 1285
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.170607 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.186529 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.291568 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1958395542000 99.81% 99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3661425000 0.19% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.314412 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1951516113500 99.83% 99.83% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3347061000 0.17% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3873 # number of times the context was actually changed
+system.cpu0.kern.swap_context 3071 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 914851 # number of replacements
-system.cpu0.icache.tagsinuse 508.781994 # Cycle average of tags in use
-system.cpu0.icache.total_refs 53209789 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 915362 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 58.129777 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 36528993000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 508.781994 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.993715 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.993715 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 53209789 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 53209789 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 53209789 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 53209789 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 53209789 # number of overall hits
-system.cpu0.icache.overall_hits::total 53209789 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 915491 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 915491 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 915491 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 915491 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 915491 # number of overall misses
-system.cpu0.icache.overall_misses::total 915491 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13646549000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 13646549000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 13646549000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 13646549000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 13646549000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 13646549000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 54125280 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 54125280 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 54125280 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 54125280 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 54125280 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 54125280 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016914 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.016914 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016914 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.016914 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016914 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.016914 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.262323 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.262323 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14906.262323 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.262323 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14906.262323 # average overall miss latency
+system.cpu0.icache.replacements 698187 # number of replacements
+system.cpu0.icache.tagsinuse 508.830635 # Cycle average of tags in use
+system.cpu0.icache.total_refs 47028847 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 698699 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 67.309166 # Average number of references to valid blocks.
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 32591.119165 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10845.138583 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10845.138583 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12421.491389 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12421.491389 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 26661.150760 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26661.150760 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 26661.150760 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 785166 # number of writebacks
-system.cpu0.dcache.writebacks::total 785166 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1037635 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 1037635 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 289296 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 289296 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16772 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16772 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 445 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 445 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326931 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1326931 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1326931 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1326931 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23000669022 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23000669022 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8095339001 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8095339001 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 188317000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 188317000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3531001 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3531001 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31096008023 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 31096008023 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31096008023 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 31096008023 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461823000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461823000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2088243000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3550066000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3550066000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122332 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122332 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049501 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049501 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087087 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087087 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002322 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002322 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.092622 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092622 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.092622 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.435232 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.435232 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27982.892957 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27982.892957 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11228.058669 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11228.058669 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7934.833708 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7934.833708 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23434.532785 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23434.532785 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 679069 # number of writebacks
+system.cpu0.dcache.writebacks::total 679069 # number of writebacks
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+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5458 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 1189892 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21646065000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21646065000 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7698041000 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 120630000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 56880500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56880500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 29344106000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 29344106000 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465334500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465334500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2275733500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3741068000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3741068000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127739 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127739 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051278 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051278 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088602 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088602 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035586 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035586 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.097115 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097115 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.097115 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23070.704046 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 23070.704046 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30591.119165 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30591.119165 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8845.138583 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8845.138583 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 10421.491389 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 10421.491389 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24661.150760 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24661.150760 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 1027530 # DTB read hits
-system.cpu1.dtb.read_misses 2750 # DTB read misses
-system.cpu1.dtb.read_acv 36 # DTB read access violations
-system.cpu1.dtb.read_accesses 205838 # DTB read accesses
-system.cpu1.dtb.write_hits 663193 # DTB write hits
-system.cpu1.dtb.write_misses 356 # DTB write misses
-system.cpu1.dtb.write_acv 48 # DTB write access violations
-system.cpu1.dtb.write_accesses 97040 # DTB write accesses
-system.cpu1.dtb.data_hits 1690723 # DTB hits
-system.cpu1.dtb.data_misses 3106 # DTB misses
-system.cpu1.dtb.data_acv 84 # DTB access violations
-system.cpu1.dtb.data_accesses 302878 # DTB accesses
-system.cpu1.itb.fetch_hits 1394871 # ITB hits
-system.cpu1.itb.fetch_misses 1246 # ITB misses
-system.cpu1.itb.fetch_acv 41 # ITB acv
-system.cpu1.itb.fetch_accesses 1396117 # ITB accesses
+system.cpu1.dtb.read_hits 2425080 # DTB read hits
+system.cpu1.dtb.read_misses 2992 # DTB read misses
+system.cpu1.dtb.read_acv 0 # DTB read access violations
+system.cpu1.dtb.read_accesses 239363 # DTB read accesses
+system.cpu1.dtb.write_hits 1761000 # DTB write hits
+system.cpu1.dtb.write_misses 341 # DTB write misses
+system.cpu1.dtb.write_acv 29 # DTB write access violations
+system.cpu1.dtb.write_accesses 105247 # DTB write accesses
+system.cpu1.dtb.data_hits 4186080 # DTB hits
+system.cpu1.dtb.data_misses 3333 # DTB misses
+system.cpu1.dtb.data_acv 29 # DTB access violations
+system.cpu1.dtb.data_accesses 344610 # DTB accesses
+system.cpu1.itb.fetch_hits 1964871 # ITB hits
+system.cpu1.itb.fetch_misses 1216 # ITB misses
+system.cpu1.itb.fetch_acv 0 # ITB acv
+system.cpu1.itb.fetch_accesses 1966087 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 3923836552 # number of cpu cycles simulated
+system.cpu1.numCycles 3911492481 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 5254013 # Number of instructions committed
-system.cpu1.committedOps 5254013 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 4921025 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 25430 # Number of float alu accesses
-system.cpu1.num_func_calls 157600 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 506865 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 4921025 # number of integer instructions
-system.cpu1.num_fp_insts 25430 # number of float instructions
-system.cpu1.num_int_register_reads 6827399 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 3700117 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 16282 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 16129 # number of times the floating registers were written
-system.cpu1.num_mem_refs 1700348 # number of memory refs
-system.cpu1.num_load_insts 1033584 # Number of load instructions
-system.cpu1.num_store_insts 666764 # Number of store instructions
-system.cpu1.num_idle_cycles 3903107404.303190 # Number of idle cycles
-system.cpu1.num_busy_cycles 20729147.696810 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.005283 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.994717 # Percentage of idle cycles
+system.cpu1.committedInsts 13183934 # Number of instructions committed
+system.cpu1.committedOps 13183934 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 12160396 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 172922 # Number of float alu accesses
+system.cpu1.num_func_calls 412685 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1307407 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 12160396 # number of integer instructions
+system.cpu1.num_fp_insts 172922 # number of float instructions
+system.cpu1.num_int_register_reads 16740645 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 8924669 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 90471 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 92344 # number of times the floating registers were written
+system.cpu1.num_mem_refs 4209624 # number of memory refs
+system.cpu1.num_load_insts 2439377 # Number of load instructions
+system.cpu1.num_store_insts 1770247 # Number of store instructions
+system.cpu1.num_idle_cycles 3861803254.998025 # Number of idle cycles
+system.cpu1.num_busy_cycles 49689226.001975 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.012703 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.987297 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2331 # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei 35942 # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0 9143 31.85% 31.85% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1973 6.87% 38.72% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 91 0.32% 39.04% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17499 60.96% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 28706 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 9135 45.13% 45.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1973 9.75% 54.87% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 9044 44.68% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 20243 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1920766593500 97.90% 97.90% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 726074500 0.04% 97.94% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 67017000 0.00% 97.94% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 40358561000 2.06% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1961918246000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.999125 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei 78634 # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0 26575 38.36% 38.36% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1967 2.84% 41.20% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 503 0.73% 41.93% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 40225 58.07% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 69270 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 25736 48.16% 48.16% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1967 3.68% 51.84% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 503 0.94% 52.78% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 25233 47.22% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 53439 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1909053778500 97.61% 97.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 705460500 0.04% 97.65% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 351339000 0.02% 97.67% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 45634904500 2.33% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1955745482500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.968429 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.516830 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total 0.705184 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed
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-system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed
-system.cpu1.kern.syscall::6 12 11.76% 25.49% # number of syscalls executed
-system.cpu1.kern.syscall::17 5 4.90% 30.39% # number of syscalls executed
-system.cpu1.kern.syscall::19 4 3.92% 34.31% # number of syscalls executed
-system.cpu1.kern.syscall::20 2 1.96% 36.27% # number of syscalls executed
-system.cpu1.kern.syscall::23 2 1.96% 38.24% # number of syscalls executed
-system.cpu1.kern.syscall::24 2 1.96% 40.20% # number of syscalls executed
-system.cpu1.kern.syscall::33 3 2.94% 43.14% # number of syscalls executed
-system.cpu1.kern.syscall::45 15 14.71% 57.84% # number of syscalls executed
-system.cpu1.kern.syscall::47 2 1.96% 59.80% # number of syscalls executed
-system.cpu1.kern.syscall::48 3 2.94% 62.75% # number of syscalls executed
-system.cpu1.kern.syscall::54 1 0.98% 63.73% # number of syscalls executed
-system.cpu1.kern.syscall::59 2 1.96% 65.69% # number of syscalls executed
-system.cpu1.kern.syscall::71 22 21.57% 87.25% # number of syscalls executed
-system.cpu1.kern.syscall::74 7 6.86% 94.12% # number of syscalls executed
-system.cpu1.kern.syscall::90 1 0.98% 95.10% # number of syscalls executed
-system.cpu1.kern.syscall::92 2 1.96% 97.06% # number of syscalls executed
-system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed
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system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
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-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 365 1.24% 1.27% # number of callpals executed
-system.cpu1.kern.callpal::tbi 10 0.03% 1.31% # number of callpals executed
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-system.cpu1.kern.callpal::swpipl 24054 81.82% 83.15% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2165 7.36% 90.51% # number of callpals executed
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-system.cpu1.kern.callpal::rdusp 2 0.01% 90.53% # number of callpals executed
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 29399 # number of callpals executed
-system.cpu1.kern.mode_switch::kernel 879 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 515 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2075 # number of protection mode switches
-system.cpu1.kern.mode_good::kernel 531
-system.cpu1.kern.mode_good::user 515
-system.cpu1.kern.mode_good::idle 16
-system.cpu1.kern.mode_switch_good::kernel 0.604096 # fraction of useful protection mode switches
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+system.cpu1.kern.mode_good::kernel 891
+system.cpu1.kern.mode_good::user 464
+system.cpu1.kern.mode_good::idle 427
+system.cpu1.kern.mode_switch_good::kernel 0.431477 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
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-system.cpu1.kern.mode_switch_good::total 0.306140 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 4075179000 0.21% 0.21% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1593973000 0.08% 0.29% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1955466537000 99.71% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 366 # number of times the context was actually changed
-system.cpu1.icache.replacements 86678 # number of replacements
-system.cpu1.icache.tagsinuse 419.761864 # Cycle average of tags in use
-system.cpu1.icache.total_refs 5169985 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 87190 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 59.295619 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1958463060000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 419.761864 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.819847 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.819847 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 5169985 # number of ReadReq hits
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-system.cpu1.icache.ReadReq_miss_latency::total 1315004000 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 1315004000 # number of demand (read+write) miss cycles
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-system.cpu1.icache.ReadReq_accesses::total 5257203 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 15077.208833 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15077.208833 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15077.208833 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15077.208833 # average overall miss latency
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+system.cpu1.kern.swap_context 1996 # number of times the context was actually changed
+system.cpu1.icache.replacements 316204 # number of replacements
+system.cpu1.icache.tagsinuse 447.456269 # Cycle average of tags in use
+system.cpu1.icache.total_refs 12870545 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 316716 # Sample count of references to valid blocks.
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+system.cpu1.icache.warmup_cycle 1953875803000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 447.456269 # Average occupied blocks per requestor
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+system.cpu1.icache.occ_percent::total 0.873938 # Average percentage of cache occupancy
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+system.cpu1.icache.ReadReq_misses::cpu1.inst 316752 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 316752 # number of ReadReq misses
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+system.cpu1.icache.ReadReq_avg_miss_latency::total 13195.992448 # average ReadReq miss latency
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+system.cpu1.icache.demand_avg_miss_latency::total 13195.992448 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13195.992448 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13195.992448 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87218 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 87218 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 87218 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 87218 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 1053316500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1053316500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 1053316500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1053316500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 1053316500 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016590 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.016590 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016590 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.016590 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12076.824738 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12076.824738 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 12076.824738 # average overall mshr miss latency
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+system.cpu1.icache.ReadReq_mshr_misses::total 316752 # number of ReadReq MSHR misses
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+system.cpu1.icache.demand_mshr_misses::total 316752 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.overall_mshr_misses::total 316752 # number of overall MSHR misses
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+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3546353000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 3546353000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3546353000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 3546353000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024019 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.024019 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024019 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.024019 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11195.992448 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11195.992448 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11195.992448 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 53530 # number of replacements
-system.cpu1.dcache.tagsinuse 416.811223 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1627239 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 53938 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 30.168694 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1941569871000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 416.811223 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.814084 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.814084 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 982758 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 982758 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 626472 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 626472 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11310 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 11310 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11707 # number of StoreCondReq hits
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 35195 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19387500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713392500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713392500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732780000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732780000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049724 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049724 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036763 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036763 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155971 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155971 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103131 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103131 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.044311 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044311 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.044311 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10176.993432 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10176.993432 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15753.136708 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15753.136708 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7135.782389 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7135.782389 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9813.547725 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 9813.547725 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12109.111398 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12109.111398 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
sim_ticks 1914420945000 # Number of ticks simulated
final_tick 1914420945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1284205 # Simulator instruction rate (inst/s)
-host_op_rate 1284205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43773036105 # Simulator tick rate (ticks/s)
-host_mem_usage 295308 # Number of bytes of host memory used
-host_seconds 43.74 # Real time elapsed on the host
+host_inst_rate 1299276 # Simulator instruction rate (inst/s)
+host_op_rate 1299275 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44286723014 # Simulator tick rate (ticks/s)
+host_mem_usage 288696 # Number of bytes of host memory used
+host_seconds 43.23 # Real time elapsed on the host
sim_insts 56164879 # Number of instructions simulated
sim_ops 56164879 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.iocache.demand_avg_miss_latency::total 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 274768.790989 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 274768.790989 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 199052000 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_mshrs 199052 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 24614 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8086.942391 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.086942 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 11676000 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283200000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 9283200000 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 9294876000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 9294876000 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 9294876000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 9294876000 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11676998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 11676998 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 9283350806 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 9283350806 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 9295027804 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 9295027804 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 9295027804 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 9295027804 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223411.628802 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 223411.628802 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222765.152786 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 222765.152786 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67497.098266 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67497.098266 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 223415.258134 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 223415.258134 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 222768.790989 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 222768.790989 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11416158000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 560000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 560000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4675219500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4675219500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 531884000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16091377000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15559493500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16091377500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 531884000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16091377000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15559493500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16091377500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1332180000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1892328500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40020.185094 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 43076.923077 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 43076.923077 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.350739 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.350739 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.355018 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.355018 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40021.369451 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.287365 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.455328 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40016.288651 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40016.456571 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 1.207291 # Number of seconds simulated
-sim_ticks 1207290627000 # Number of ticks simulated
-final_tick 1207290627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.203695 # Number of seconds simulated
+sim_ticks 1203694548000 # Number of ticks simulated
+final_tick 1203694548000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 648322 # Simulator instruction rate (inst/s)
-host_op_rate 826248 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12731770448 # Simulator tick rate (ticks/s)
-host_mem_usage 380152 # Number of bytes of host memory used
-host_seconds 94.83 # Real time elapsed on the host
-sim_insts 61477134 # Number of instructions simulated
-sim_ops 78349023 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 52642784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 394084 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4718772 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 323100 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4791152 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62870404 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 394084 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 323100 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 717184 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4105920 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7133264 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 6580348 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12376 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 5130 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 74888 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6746553 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 64155 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 820991 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 43604069 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 106 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 326420 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3908563 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 212 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 267624 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3968516 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52075617 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 326420 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 267624 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 594044 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3400938 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 14081 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2493471 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 5908490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3400938 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 43604069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 106 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 326420 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3922645 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 212 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 267624 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 6461987 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 57984106 # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate 610810 # Simulator instruction rate (inst/s)
+host_op_rate 778429 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11963163223 # Simulator tick rate (ticks/s)
+host_mem_usage 383784 # Number of bytes of host memory used
+host_seconds 100.62 # Real time elapsed on the host
+sim_insts 61457649 # Number of instructions simulated
+sim_ops 78322983 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 56 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 69267 # number of replacements
-system.l2c.tagsinuse 52917.687101 # Cycle average of tags in use
-system.l2c.total_refs 1645693 # Total number of references to valid blocks.
-system.l2c.sampled_refs 134464 # Sample count of references to valid blocks.
-system.l2c.avg_refs 12.238912 # Average number of references to valid blocks.
+system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 354404 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4259252 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 364636 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5307760 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62191012 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 354404 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 364636 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 719040 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4163840 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7191184 # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 11756 # Number of read requests responded to by this memory
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40072.547403 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40075.805801 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40082.908163 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40098.493304 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40089.647683 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.634446 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40074.226804 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.233397 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40006.444124 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.816422 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40043.288277 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 7076084 # DTB read hits
-system.cpu0.dtb.read_misses 3743 # DTB read misses
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system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 7079827 # DTB read accesses
-system.cpu0.dtb.write_accesses 5661190 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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-system.cpu0.dtb.accesses 12741017 # DTB accesses
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-system.cpu0.itb.inst_misses 2205 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 29576860 # ITB inst accesses
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-system.cpu0.itb.misses 2205 # DTB misses
-system.cpu0.itb.accesses 29576860 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu0.committedOps 37228975 # Number of ops (including micro ops) committed
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-system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses
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-system.cpu0.num_conditional_control_insts 4373527 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 33114839 # number of integer instructions
-system.cpu0.num_fp_insts 3860 # number of float instructions
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-system.cpu0.num_int_register_writes 36238708 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written
-system.cpu0.num_mem_refs 13404188 # number of memory refs
-system.cpu0.num_load_insts 7413537 # Number of load instructions
-system.cpu0.num_store_insts 5990651 # Number of store instructions
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.occ_percent::total 0.995058 # Average percentage of cache occupancy
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system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408647 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 408647 # number of ReadReq MSHR misses
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758303642 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4493366071 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4493366071 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72896006 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72896006 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52131016 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52131016 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1001 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1001 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7251669713 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 7251669713 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7251669713 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 7251669713 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13559876000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13559876000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1253192500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1253192500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14813068500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14813068500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033372 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033372 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025782 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025782 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059295 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059295 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047646 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047646 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029988 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029988 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029988 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12095.011432 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12095.011432 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.494355 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.494355 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7817.266059 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7817.266059 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6961.011617 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6961.011617 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 204960 # number of writebacks
+system.cpu0.dcache.writebacks::total 204960 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 146461 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 146461 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 116958 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 116958 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7880 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7880 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7695 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7695 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 263419 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 263419 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 263419 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 263419 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1698392500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 1698392500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3965725500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3965725500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 54503500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 54503500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50946500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50946500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 5664118000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 5664118000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 5664118000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 5664118000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12130688000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12130688000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1193496500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1193496500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13324184500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13324184500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031847 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031847 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029464 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029464 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062733 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062733 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.061292 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.061292 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.030743 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030743 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.030743 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11596.209913 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11596.209913 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33907.261581 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33907.261581 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 6916.687817 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6916.687817 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6620.727745 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6620.727745 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.032961 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.032961 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21502.313804 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21502.313804 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 8318170 # DTB read hits
-system.cpu1.dtb.read_misses 3663 # DTB read misses
-system.cpu1.dtb.write_hits 5832653 # DTB write hits
-system.cpu1.dtb.write_misses 1435 # DTB write misses
+system.cpu1.dtb.read_hits 10590618 # DTB read hits
+system.cpu1.dtb.read_misses 5230 # DTB read misses
+system.cpu1.dtb.write_hits 7384755 # DTB write hits
+system.cpu1.dtb.write_misses 1835 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1968 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 2257 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 8321833 # DTB read accesses
-system.cpu1.dtb.write_accesses 5834088 # DTB write accesses
+system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 10595848 # DTB read accesses
+system.cpu1.dtb.write_accesses 7386590 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 14150823 # DTB hits
-system.cpu1.dtb.misses 5098 # DTB misses
-system.cpu1.dtb.accesses 14155921 # DTB accesses
-system.cpu1.itb.inst_hits 33211066 # ITB inst hits
-system.cpu1.itb.inst_misses 2171 # ITB inst misses
+system.cpu1.dtb.hits 17975373 # DTB hits
+system.cpu1.dtb.misses 7065 # DTB misses
+system.cpu1.dtb.accesses 17982438 # DTB accesses
+system.cpu1.itb.inst_hits 43340388 # ITB inst hits
+system.cpu1.itb.inst_misses 3017 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1458 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 33213237 # ITB inst accesses
-system.cpu1.itb.hits 33211066 # DTB hits
-system.cpu1.itb.misses 2171 # DTB misses
-system.cpu1.itb.accesses 33213237 # DTB accesses
-system.cpu1.numCycles 2413083038 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 43343405 # ITB inst accesses
+system.cpu1.itb.hits 43340388 # DTB hits
+system.cpu1.itb.misses 3017 # DTB misses
+system.cpu1.itb.accesses 43343405 # DTB accesses
+system.cpu1.numCycles 2407389096 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 32600335 # Number of instructions committed
-system.cpu1.committedOps 41120048 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 37342001 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses
-system.cpu1.num_func_calls 963082 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 3735102 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 37342001 # number of integer instructions
-system.cpu1.num_fp_insts 6793 # number of float instructions
-system.cpu1.num_int_register_reads 213831809 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 39482622 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written
-system.cpu1.num_mem_refs 14689113 # number of memory refs
-system.cpu1.num_load_insts 8640454 # Number of load instructions
-system.cpu1.num_store_insts 6048659 # Number of store instructions
-system.cpu1.num_idle_cycles 1863361359.722463 # Number of idle cycles
-system.cpu1.num_busy_cycles 549721678.277537 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.227809 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.772191 # Percentage of idle cycles
+system.cpu1.committedInsts 42409467 # Number of instructions committed
+system.cpu1.committedOps 53271211 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 47739499 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses
+system.cpu1.num_func_calls 1335008 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 5483103 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 47739499 # number of integer instructions
+system.cpu1.num_fp_insts 5457 # number of float instructions
+system.cpu1.num_int_register_reads 274842107 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 51975033 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written
+system.cpu1.num_mem_refs 18684058 # number of memory refs
+system.cpu1.num_load_insts 11000639 # Number of load instructions
+system.cpu1.num_store_insts 7683419 # Number of store instructions
+system.cpu1.num_idle_cycles 1827105047.254482 # Number of idle cycles
+system.cpu1.num_busy_cycles 580284048.745518 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.241043 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.758957 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 43948 # number of quiesce instructions executed
-system.cpu1.icache.replacements 455071 # number of replacements
-system.cpu1.icache.tagsinuse 479.019014 # Cycle average of tags in use
-system.cpu1.icache.total_refs 32755479 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 455583 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 71.897940 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 94151388000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 479.019014 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.935584 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.935584 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 32755479 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 32755479 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 32755479 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 32755479 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 32755479 # number of overall hits
-system.cpu1.icache.overall_hits::total 32755479 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 455583 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 455583 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 455583 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 455583 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 455583 # number of overall misses
-system.cpu1.icache.overall_misses::total 455583 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6728250000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 6728250000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 6728250000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 6728250000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 6728250000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 6728250000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 33211062 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 33211062 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 33211062 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 33211062 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 33211062 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 33211062 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013718 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.013718 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013718 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.013718 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013718 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.013718 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.439560 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.439560 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14768.439560 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.439560 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14768.439560 # average overall miss latency
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+system.cpu1.dcache.StoreCondReq_accesses::total 124877 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 15856989 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 15856989 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 15856989 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 15856989 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027065 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.027065 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027397 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.027397 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104839 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104839 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083314 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083314 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027201 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.027201 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027201 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.027201 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12947.268957 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12947.268957 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31778.455501 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 31778.455501 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8836.564885 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8836.564885 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6057.333718 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6057.333718 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20724.117785 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20724.117785 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20724.117785 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 266100 # number of writebacks
-system.cpu1.dcache.writebacks::total 266100 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170988 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 170988 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150171 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 150171 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11121 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11121 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 321159 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 321159 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 321159 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 321159 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1860790612 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1860790612 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4686951190 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4686951190 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72983005 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 72983005 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57622011 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57622011 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6547741802 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 6547741802 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6547741802 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 6547741802 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686201000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686201000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39932204000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39932204000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618405000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618405000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024002 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024002 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030142 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030142 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119518 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119518 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108316 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108316 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026529 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026529 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.026529 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10882.580134 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10882.580134 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.760999 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.760999 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6562.629710 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6562.629710 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5722.146077 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5722.146077 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.850884 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.850884 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 366483 # number of writebacks
+system.cpu1.dcache.writebacks::total 366483 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 253200 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 253200 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 178129 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 178129 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13100 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13100 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10399 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10399 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 431329 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 431329 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 431329 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 431329 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2771848500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2771848500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5304406500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5304406500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89559000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89559000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 42226500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 42226500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8076255000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 8076255000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8076255000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 8076255000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170163530000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170163530000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40377042500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40377042500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210540572500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210540572500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027065 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.027065 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027397 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027397 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104839 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104839 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083274 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083274 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027201 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027201 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10947.268957 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10947.268957 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29778.455501 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 29778.455501 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6836.564885 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6836.564885 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4060.630830 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4060.630830 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18724.117785 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18724.117785 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574279130811 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 574279130811 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574279130811 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 574279130811 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 567076826640 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 567076826640 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 567076826640 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 567076826640 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
sim_seconds 2.624688 # Number of seconds simulated
-sim_ticks 2624688029000 # Number of ticks simulated
-final_tick 2624688029000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2624688000000 # Number of ticks simulated
+final_tick 2624688000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 388710 # Simulator instruction rate (inst/s)
-host_op_rate 494628 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16947208284 # Simulator tick rate (ticks/s)
-host_mem_usage 385844 # Number of bytes of host memory used
-host_seconds 154.87 # Real time elapsed on the host
+host_inst_rate 509092 # Simulator instruction rate (inst/s)
+host_op_rate 647812 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 22195691402 # Simulator tick rate (ticks/s)
+host_mem_usage 379628 # Number of bytes of host memory used
+host_seconds 118.25 # Real time elapsed on the host
sim_insts 60201138 # Number of instructions simulated
sim_ops 76605123 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.bw_total::cpu.itb.walker 73 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 268917 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4596999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53608355 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53608356 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cpu.itb.hits 61495107 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61499578 # DTB accesses
-system.cpu.numCycles 5249376058 # number of cpu cycles simulated
+system.cpu.numCycles 5249376000 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60201138 # Number of instructions committed
system.cpu.num_int_insts 68872510 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394780312 # number of times the integer registers were read
-system.cpu.num_int_register_writes 74180713 # number of times the integer registers were written
+system.cpu.num_int_register_writes 74180711 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27395681 # number of memory refs
system.cpu.num_load_insts 15660705 # Number of load instructions
system.cpu.num_store_insts 11734976 # Number of store instructions
-system.cpu.num_idle_cycles 4573668194.612258 # Number of idle cycles
-system.cpu.num_busy_cycles 675707863.387743 # Number of busy cycles
+system.cpu.num_idle_cycles 4573668198.612257 # Number of idle cycles
+system.cpu.num_busy_cycles 675707801.387743 # Number of busy cycles
system.cpu.not_idle_fraction 0.128722 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.871278 # Percentage of idle cycles
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+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1359273920420 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1359273920420 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112043 # Number of seconds simulated
-sim_ticks 5112043255000 # Number of ticks simulated
-final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.112041 # Number of seconds simulated
+sim_ticks 5112040968500 # Number of ticks simulated
+final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1011485 # Simulator instruction rate (inst/s)
-host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25877843451 # Simulator tick rate (ticks/s)
-host_mem_usage 397304 # Number of bytes of host memory used
-host_seconds 197.55 # Real time elapsed on the host
-sim_insts 199813914 # Number of instructions simulated
-sim_ops 409133298 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory
+host_inst_rate 923075 # Simulator instruction rate (inst/s)
+host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23616389220 # Simulator tick rate (ticks/s)
+host_mem_usage 353316 # Number of bytes of host memory used
+host_seconds 216.46 # Real time elapsed on the host
+sim_insts 199810236 # Number of instructions simulated
+sim_ops 409125915 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory
+system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s)
-system.cpu.l2cache.replacements 106561 # number of replacements
-system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses
-system.cpu.l2cache.overall_misses::total 179910 # number of overall misses
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks
-system.cpu.l2cache.writebacks::total 98533 # number of writebacks
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 47570 # number of replacements
-system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
+system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
+system.iocache.replacements 47569 # number of replacements
+system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
+system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
-system.iocache.overall_misses::total 47625 # number of overall misses
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
+system.iocache.overall_misses::total 47624 # number of overall misses
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10224086531 # number of cpu cycles simulated
+system.cpu.numCycles 10224081960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 199813914 # Number of instructions committed
-system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses
+system.cpu.committedInsts 199810236 # Number of instructions committed
+system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374297264 # number of integer instructions
+system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374289906 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read
-system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written
+system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read
+system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 35626517 # number of memory refs
-system.cpu.num_load_insts 27217782 # Number of load instructions
-system.cpu.num_store_insts 8408735 # Number of store instructions
-system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles
-system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
+system.cpu.num_mem_refs 35624588 # number of memory refs
+system.cpu.num_load_insts 27216588 # Number of load instructions
+system.cpu.num_store_insts 8408000 # Number of store instructions
+system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles
+system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles
+system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
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+system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks
+system.cpu.l2cache.writebacks::total 98530 # number of writebacks
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
sim_ticks 5187896410000 # Number of ticks simulated
final_tick 5187896410000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 834857 # Simulator instruction rate (inst/s)
-host_op_rate 1609393 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33766110220 # Simulator tick rate (ticks/s)
-host_mem_usage 354356 # Number of bytes of host memory used
-host_seconds 153.64 # Real time elapsed on the host
+host_inst_rate 812782 # Simulator instruction rate (inst/s)
+host_op_rate 1566838 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32873266023 # Simulator tick rate (ticks/s)
+host_mem_usage 347504 # Number of bytes of host memory used
+host_seconds 157.82 # Real time elapsed on the host
sim_insts 128269216 # Number of instructions simulated
sim_ops 247270559 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2867328 # Number of bytes read from this memory
system.iocache.demand_misses::total 47558 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47558 # number of overall misses
system.iocache.overall_misses::total 47558 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130045932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 130045932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 130086932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 130086932 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10696163160 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 10696163160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10826209092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10826209092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10826209092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10826209092 # number of overall miss cycles
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+system.iocache.demand_miss_latency::total 10826250092 # number of demand (read+write) miss cycles
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+system.iocache.overall_miss_latency::total 10826250092 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 838 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155186.076372 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 155186.076372 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 155235.002387 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 155235.002387 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 228941.848459 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 228941.848459 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 227642.228269 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227642.228269 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 227642.228269 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 90077012 # number of cycles access was blocked
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 227643.090374 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227643.090374 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 227643.090374 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 90078 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11025 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 8170.250522 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 8.170340 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 47558 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47558 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47558 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86439000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 86439000 # number of ReadReq MSHR miss cycles
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-system.iocache.WriteReq_mshr_miss_latency::total 8266468944 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8352907944 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8352907944 # number of demand (read+write) MSHR miss cycles
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-system.iocache.overall_mshr_miss_latency::total 8352907944 # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 8353234092 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 103149.164678 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 103149.164678 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176936.407192 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 176936.407192 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175636.232474 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 175636.232474 # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::total 175643.090374 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.dcache.demand_misses::total 1621067 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1621067 # number of overall misses
system.cpu.dcache.overall_misses::total 1621067 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 18175236500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 8903442500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 8903442500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 27078679000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 27078679000 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total 27078679000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 13298830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13298830 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 8353033 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_miss_rate::total 0.074870 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.074870 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.074870 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843616 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843616 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13913.843999 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13913.843999 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28283.123727 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 28283.123727 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16704.231842 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.231842 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16704.231842 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16704.232151 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16704.232151 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 1621067 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1621067 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1621067 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562696500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562696500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15562697000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 15562697000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8273848500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8273848500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23836545000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23836545000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23836545000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23836545000 # number of overall MSHR miss cycles
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+system.cpu.dcache.overall_mshr_miss_latency::total 23836545500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94146954000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94146954000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469435000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469435000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616389000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616389000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2469434500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2469434500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96616388500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 96616388500 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037687 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.074870 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074870 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.074870 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843616 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843616 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11913.843999 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11913.843999 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26283.123727 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26283.123727 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.231842 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.231842 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14704.232151 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14704.232151 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_mshr_misses::cpu.data 141498 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154425 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 200000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144074500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661603500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 517329500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1144100000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1661629500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 54186500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 54186500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4533030500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4533030500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677105000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6194634000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 517329500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5677130500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6194660000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677105000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6194634000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 517329500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5677130500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6194660000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86587561000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86587561000 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305699000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087447 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063788 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.746943 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40515.422480 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40364.472246 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40034.785637 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40516.325519 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40365.103850 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40287.360595 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40287.360595 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40023.225322 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40023.225322 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.746943 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.450480 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.191355 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40034.785637 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40121.630694 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40114.359722 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
sim_ticks 21628500 # Number of ticks simulated
final_tick 21628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48865 # Simulator instruction rate (inst/s)
-host_op_rate 48859 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 165354272 # Simulator tick rate (ticks/s)
-host_mem_usage 218640 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 34038 # Simulator instruction rate (inst/s)
+host_op_rate 34033 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 115179622 # Simulator tick rate (ticks/s)
+host_mem_usage 212112 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56590.517241 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56590.517241 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1690000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 3380 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 45675.675676 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
sim_ticks 20184000 # Number of ticks simulated
final_tick 20184000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 50290 # Simulator instruction rate (inst/s)
-host_op_rate 50282 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 174536927 # Simulator tick rate (ticks/s)
-host_mem_usage 219492 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 91753 # Simulator instruction rate (inst/s)
+host_op_rate 91718 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 318298211 # Simulator tick rate (ticks/s)
+host_mem_usage 212944 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56098.837209 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 56098.837209 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 57663.385827 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 57663.385827 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 2389 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
sim_ticks 18570500 # Number of ticks simulated
final_tick 18570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 42410 # Simulator instruction rate (inst/s)
-host_op_rate 42404 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 147804999 # Simulator tick rate (ticks/s)
-host_mem_usage 221464 # Number of bytes of host memory used
-host_seconds 0.13 # Real time elapsed on the host
+host_inst_rate 78205 # Simulator instruction rate (inst/s)
+host_op_rate 78177 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 272440141 # Simulator tick rate (ticks/s)
+host_mem_usage 214124 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55220 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55220 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55992.711370 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55992.711370 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 2307000 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4614 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 51266.666667 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 102.533333 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
sim_ticks 14818500 # Number of ticks simulated
final_tick 14818500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71701 # Simulator instruction rate (inst/s)
-host_op_rate 71694 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 83350191 # Simulator tick rate (ticks/s)
-host_mem_usage 220256 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 95139 # Simulator instruction rate (inst/s)
+host_op_rate 95123 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 110579898 # Simulator tick rate (ticks/s)
+host_mem_usage 213740 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38918.400000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44057.746479 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 40780.102041 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 49000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 98 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4083.333333 # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
sim_ticks 25317500 # Number of ticks simulated
final_tick 25317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47783 # Simulator instruction rate (inst/s)
-host_op_rate 47781 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79779918 # Simulator tick rate (ticks/s)
-host_mem_usage 220364 # Number of bytes of host memory used
-host_seconds 0.32 # Real time elapsed on the host
+host_inst_rate 84248 # Simulator instruction rate (inst/s)
+host_op_rate 84237 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 140641450 # Simulator tick rate (ticks/s)
+host_mem_usage 214032 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54837.398374 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54837.398374 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 65500 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 32750 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 65.500000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits
system.cpu.dcache.overall_avg_miss_latency::cpu.data 56182.451253 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 56182.451253 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 4519 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 100.422222 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000114 # Number of seconds simulated
-sim_ticks 113910500 # Number of ticks simulated
-final_tick 113910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000110 # Number of seconds simulated
+sim_ticks 109894000 # Number of ticks simulated
+final_tick 109894000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141669 # Simulator instruction rate (inst/s)
-host_op_rate 141669 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14682125 # Simulator tick rate (ticks/s)
-host_mem_usage 244464 # Number of bytes of host memory used
-host_seconds 7.76 # Real time elapsed on the host
-sim_insts 1099129 # Number of instructions simulated
-sim_ops 1099129 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory
+host_inst_rate 161995 # Simulator instruction rate (inst/s)
+host_op_rate 161994 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16590549 # Simulator tick rate (ticks/s)
+host_mem_usage 228988 # Number of bytes of host memory used
+host_seconds 6.62 # Real time elapsed on the host
+sim_insts 1073027 # Number of instructions simulated
+sim_ops 1073027 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 5376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::total 42944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 5376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 384 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 29248 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 42880 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 29184 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 84 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 671 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 203387747 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 94389894 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 47194947 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 11236892 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 2809223 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7303980 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 3371068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7303980 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 376997731 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 203387747 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 47194947 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 2809223 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 3371068 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 256762985 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 203387747 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 94389894 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 47194947 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11236892 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 2809223 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7303980 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 3371068 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7303980 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 376997731 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total 670 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 209656578 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 97839736 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 51249386 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11647588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 2329518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7570932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 2329518 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7570932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 390194187 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 209656578 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 51249386 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 2329518 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 265564999 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 209656578 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 97839736 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 51249386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11647588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7570932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 2329518 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7570932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 390194187 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 227822 # number of cpu cycles simulated
+system.cpu0.numCycles 219789 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 88179 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 85929 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 1290 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 85894 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 83486 # Number of BTB hits
+system.cpu0.BPredUnit.lookups 85747 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 83485 # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect 1265 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups 83551 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits 81101 # Number of BTB hits
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 517 # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.usedRAS 507 # Number of times the RAS was used to get a target.
system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles 17727 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 523680 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 88179 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 84003 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 172095 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 4009 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 15408 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles 17217 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 509162 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 85747 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 81608 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 167267 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3854 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 13783 # Number of cycles fetch has spent blocked
system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1281 # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines 6036 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 519 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 209087 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.504603 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.209881 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles 1302 # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines 6029 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 502 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 202015 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.520417 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.209670 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 36992 17.69% 17.69% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 85294 40.79% 58.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 585 0.28% 58.77% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1000 0.48% 59.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 484 0.23% 59.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 81297 38.88% 98.36% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 665 0.32% 98.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 355 0.17% 98.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2415 1.16% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 34748 17.20% 17.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 82895 41.03% 58.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 589 0.29% 58.53% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 956 0.47% 59.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 519 0.26% 59.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 78871 39.04% 98.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 675 0.33% 98.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 356 0.18% 98.81% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2406 1.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 209087 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.387052 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.298637 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 18268 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 16880 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 171017 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 351 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2571 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 520658 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 2571 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18993 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2288 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 13870 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 170679 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 686 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 517484 # Number of instructions processed by rename
-system.cpu0.rename.LSQFullEvents 297 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 353459 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1032335 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 1032335 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 339779 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13680 # Number of HB maps that are undone due to squashing
+system.cpu0.fetch.rateDist::total 202015 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.390133 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.316595 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17805 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 15234 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 166234 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 301 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 2441 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 506087 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 2441 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18480 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 1523 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 13039 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 165885 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 647 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 502881 # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 343651 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1003098 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 1003098 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 330631 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13020 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 904 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 933 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4009 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 165974 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 83785 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 81138 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 80830 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 432592 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 951 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 429324 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 270 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 11361 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 11323 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 392 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 209087 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.053327 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.097112 # Number of insts issued each cycle
+system.cpu0.rename.tempSerializingInsts 932 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 3938 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 161147 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 81377 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 78673 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 78441 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 420405 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 949 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 417702 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10651 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 9804 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 390 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 202015 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.067678 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.086169 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 36280 17.35% 17.35% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5325 2.55% 19.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 82668 39.54% 59.44% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 82134 39.28% 98.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1638 0.78% 99.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 661 0.32% 99.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 275 0.13% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 94 0.04% 99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 12 0.01% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33785 16.72% 16.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5274 2.61% 19.33% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 80485 39.84% 59.18% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 79928 39.57% 98.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1527 0.76% 99.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 645 0.32% 99.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 270 0.13% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 87 0.04% 99.99% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 14 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 209087 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 202015 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 52 18.77% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.77% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 113 40.79% 59.57% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 112 40.43% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 46 19.74% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.74% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 73 31.33% 51.07% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 114 48.93% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 180924 42.14% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 165296 38.50% 80.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 83104 19.36% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 176241 42.19% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 160662 38.46% 80.66% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 80799 19.34% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 429324 # Type of FU issued
-system.cpu0.iq.rate 1.884471 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 277 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000645 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1068282 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 444960 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 427393 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 417702 # Type of FU issued
+system.cpu0.iq.rate 1.900468 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 233 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000558 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1037774 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 432063 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 415867 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 429601 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 417935 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 80458 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 78173 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2495 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 56 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1539 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2242 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1418 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.cacheBlocked 20 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2571 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1789 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 515149 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 291 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 165974 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 83785 # Number of dispatched store instructions
+system.cpu0.iew.iewSquashCycles 2441 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1114 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 46 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 500579 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 311 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 161147 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 81377 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 838 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 95 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIQFullEvents 51 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 56 # Number of memory order violations
+system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 383 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1496 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 428216 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 164977 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1108 # Number of squashed instructions skipped in execute
+system.cpu0.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1472 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 416616 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 160343 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1086 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 81606 # number of nop insts executed
-system.cpu0.iew.exec_refs 247935 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 85106 # Number of branches executed
-system.cpu0.iew.exec_stores 82958 # Number of stores executed
-system.cpu0.iew.exec_rate 1.879608 # Inst execution rate
-system.cpu0.iew.wb_sent 427739 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 427393 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 253334 # num instructions producing a value
-system.cpu0.iew.wb_consumers 255736 # num instructions consuming a value
+system.cpu0.iew.exec_nop 79225 # number of nop insts executed
+system.cpu0.iew.exec_refs 241004 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 82800 # Number of branches executed
+system.cpu0.iew.exec_stores 80661 # Number of stores executed
+system.cpu0.iew.exec_rate 1.895527 # Inst execution rate
+system.cpu0.iew.wb_sent 416200 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 415867 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 246464 # num instructions producing a value
+system.cpu0.iew.wb_consumers 248856 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.875995 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.990608 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.892119 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.990388 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 13085 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts 12251 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1290 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 206533 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.430701 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.136521 # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts 1265 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 199591 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.446493 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.132962 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 36757 17.80% 17.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 84830 41.07% 58.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2489 1.21% 60.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 701 0.34% 60.42% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 579 0.28% 60.70% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 80093 38.78% 99.48% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 561 0.27% 99.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 222 0.11% 99.85% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 301 0.15% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 34293 17.18% 17.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 82677 41.42% 58.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2432 1.22% 59.82% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 705 0.35% 60.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 565 0.28% 60.46% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 77961 39.06% 99.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 418 0.21% 99.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 251 0.13% 99.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 289 0.14% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 206533 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 502020 # Number of instructions committed
-system.cpu0.commit.committedOps 502020 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 199591 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 488298 # Number of instructions committed
+system.cpu0.commit.committedOps 488298 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 245725 # Number of memory references committed
-system.cpu0.commit.loads 163479 # Number of loads committed
+system.cpu0.commit.refs 238864 # Number of memory references committed
+system.cpu0.commit.loads 158905 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 84133 # Number of branches committed
+system.cpu0.commit.branches 81846 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 338110 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 328962 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 301 # number cycles where commit BW limit reached
+system.cpu0.commit.bw_lim_events 289 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 720176 # The number of ROB reads
-system.cpu0.rob.rob_writes 1032801 # The number of ROB writes
-system.cpu0.timesIdled 336 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 18735 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 421071 # Number of Instructions Simulated
-system.cpu0.committedOps 421071 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 421071 # Number of Instructions Simulated
-system.cpu0.cpi 0.541054 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.541054 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.848246 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.848246 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 766308 # number of integer regfile reads
-system.cpu0.int_regfile_writes 345106 # number of integer regfile writes
+system.cpu0.rob.rob_reads 698690 # The number of ROB reads
+system.cpu0.rob.rob_writes 1003556 # The number of ROB writes
+system.cpu0.timesIdled 327 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 17774 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 409636 # Number of Instructions Simulated
+system.cpu0.committedOps 409636 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 409636 # Number of Instructions Simulated
+system.cpu0.cpi 0.536547 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.536547 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.863769 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.863769 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 745424 # number of integer regfile reads
+system.cpu0.int_regfile_writes 335847 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 249733 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 242810 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
-system.cpu0.icache.replacements 302 # number of replacements
-system.cpu0.icache.tagsinuse 247.706871 # Cycle average of tags in use
-system.cpu0.icache.total_refs 5276 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 594 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 8.882155 # Average number of references to valid blocks.
+system.cpu0.icache.replacements 299 # number of replacements
+system.cpu0.icache.tagsinuse 247.576197 # Cycle average of tags in use
+system.cpu0.icache.total_refs 5285 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 591 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 8.942470 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 247.706871 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.483802 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.483802 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5276 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 5276 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 5276 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 5276 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 5276 # number of overall hits
-system.cpu0.icache.overall_hits::total 5276 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 760 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 760 # number of ReadReq misses
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+system.cpu0.dcache.overall_accesses::total 162025 # number of overall (read+write) accesses
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+system.cpu0.dcache.ReadReq_miss_rate::total 0.005663 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006920 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.006920 # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006283 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.006283 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006283 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.006283 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30384.946237 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 30384.946237 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47732.336347 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 47732.336347 # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 17619.047619 # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total 17619.047619 # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39808.430255 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39808.430255 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39808.430255 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 319 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 18 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 24 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6222.222222 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.291667 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 351 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 394 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 394 # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 745 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 745 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 745 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 745 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 181 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 169 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 169 # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total 25 # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 350 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 350 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5844010 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5844010 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6652500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6652500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 438500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total 438500 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12496510 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12496510 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12496510 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 12496510 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002143 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002143 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002056 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002056 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.002100 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002100 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.002100 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325 # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17540 # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17540 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 381 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 381 # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 657 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 657 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 657 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 657 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 172 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 172 # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5343500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5343500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6330000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6330000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 328000 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total 328000 # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11673500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 11673500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11673500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 11673500 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002302 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002302 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.002228 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002228 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.002228 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28272.486772 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28272.486772 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36802.325581 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36802.325581 # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15619.047619 # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15619.047619 # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32336.565097 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32336.565097 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 191317 # number of cpu cycles simulated
+system.cpu1.numCycles 184127 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 53059 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 50011 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 46382 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 45427 # Number of BTB hits
+system.cpu1.BPredUnit.lookups 48566 # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted 45425 # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups 41634 # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits 40784 # Number of BTB hits
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 803 # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS 857 # Number of times the RAS was used to get a target.
system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles 31318 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 294530 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 53059 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 46230 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 104588 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4407 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 38684 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles 6733 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines 21833 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 319 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 185209 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.590257 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.119058 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 32363 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 265611 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 48566 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 41641 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 96301 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4375 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 40077 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.NoActiveThreadStallCycles 6455 # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.PendingTrapStallCycles 1055 # Number of stall cycles due to pending traps
+system.cpu1.fetch.CacheLines 23564 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 345 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 179027 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.483637 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.076927 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 80621 43.53% 43.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 53529 28.90% 72.43% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 6903 3.73% 76.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3276 1.77% 77.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 732 0.40% 78.32% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 34514 18.64% 96.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1160 0.63% 97.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 883 0.48% 98.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3591 1.94% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 82726 46.21% 46.21% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 49826 27.83% 74.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 7772 4.34% 78.38% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3158 1.76% 80.15% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 709 0.40% 80.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 29207 16.31% 96.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1125 0.63% 97.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 886 0.49% 97.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3618 2.02% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 185209 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.277336 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.539487 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 37437 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 34588 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 97784 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 5856 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2811 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 290465 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2811 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 38251 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18737 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 14962 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 92242 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 11473 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 288015 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 60 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 201252 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 549512 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 549512 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 185544 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15708 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1231 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 14237 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 80834 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 37999 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 38862 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 32764 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 237666 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 7151 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 239902 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 128 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 12973 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 11962 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 719 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 185209 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.295304 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.311031 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 179027 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.263764 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.442542 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 39330 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 35122 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 88807 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 6541 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2772 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 261671 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2772 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 40116 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 20114 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 14157 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 82544 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 12869 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 259082 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 180494 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 488461 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 488461 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 165372 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15122 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1240 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 15783 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 71004 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 32715 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 34344 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 27479 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 212625 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 7991 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 216005 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 69 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 12464 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 11017 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 179027 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.206550 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.298788 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 78322 42.29% 42.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 24974 13.48% 55.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 38132 20.59% 76.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 38761 20.93% 97.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3339 1.80% 99.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1231 0.66% 99.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 48 0.03% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 80193 44.79% 44.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 27393 15.30% 60.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 32961 18.41% 78.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 33539 18.73% 97.24% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3241 1.81% 99.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1264 0.71% 99.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 324 0.18% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 185209 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 179027 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 21 6.44% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.44% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 95 29.14% 35.58% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 210 64.42% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 20 6.78% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.78% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 65 22.03% 28.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 116849 48.71% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 85748 35.74% 84.45% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 37305 15.55% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 107139 49.60% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.60% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 76812 35.56% 85.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 32054 14.84% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 239902 # Type of FU issued
-system.cpu1.iq.rate 1.253950 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 326 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001359 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 665467 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 257831 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 237819 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 216005 # Type of FU issued
+system.cpu1.iq.rate 1.173131 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001366 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 611401 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 233118 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 214044 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 240228 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 216300 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 32613 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 27354 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2758 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1567 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2609 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1525 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2811 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 2340 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 107 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 284663 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 401 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 80834 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 37999 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1126 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 105 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 2772 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 1710 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 255983 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 380 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 71004 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 32715 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1159 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 52 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 41 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 1185 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1694 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 238552 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 79712 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 1213 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1697 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 214708 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 69981 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1297 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 39846 # number of nop insts executed
-system.cpu1.iew.exec_refs 116931 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 49232 # Number of branches executed
-system.cpu1.iew.exec_stores 37219 # Number of stores executed
-system.cpu1.iew.exec_rate 1.246894 # Inst execution rate
-system.cpu1.iew.wb_sent 238105 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 237819 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 133762 # num instructions producing a value
-system.cpu1.iew.wb_consumers 138617 # num instructions consuming a value
+system.cpu1.iew.exec_nop 35367 # number of nop insts executed
+system.cpu1.iew.exec_refs 101954 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 44806 # Number of branches executed
+system.cpu1.iew.exec_stores 31973 # Number of stores executed
+system.cpu1.iew.exec_rate 1.166086 # Inst execution rate
+system.cpu1.iew.wb_sent 214321 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 214044 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 118861 # num instructions producing a value
+system.cpu1.iew.wb_consumers 123754 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.243063 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.964975 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.162480 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.960462 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 14936 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 6432 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1521 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 175666 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.535334 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.989786 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 14492 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 7251 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1525 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 169801 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.422188 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.937267 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 78046 44.43% 44.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 47129 26.83% 71.26% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6230 3.55% 74.80% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 7351 4.18% 78.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1552 0.88% 79.87% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 32915 18.74% 98.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 634 0.36% 98.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 814 0.46% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 80979 47.69% 47.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 42780 25.19% 72.88% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6215 3.66% 76.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 8147 4.80% 81.34% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1520 0.90% 82.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 27830 16.39% 98.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 515 0.30% 98.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 1002 0.59% 99.52% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 813 0.48% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 175666 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 269706 # Number of instructions committed
-system.cpu1.commit.committedOps 269706 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 169801 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 241489 # Number of instructions committed
+system.cpu1.commit.committedOps 241489 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 114508 # Number of memory references committed
-system.cpu1.commit.loads 78076 # Number of loads committed
-system.cpu1.commit.membars 5720 # Number of memory barriers committed
-system.cpu1.commit.branches 48115 # Number of branches committed
+system.cpu1.commit.refs 99585 # Number of memory references committed
+system.cpu1.commit.loads 68395 # Number of loads committed
+system.cpu1.commit.membars 6536 # Number of memory barriers committed
+system.cpu1.commit.branches 43685 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 184747 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 165393 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 814 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 813 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 458907 # The number of ROB reads
-system.cpu1.rob.rob_writes 572109 # The number of ROB writes
-system.cpu1.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 6108 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 36503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 225079 # Number of Instructions Simulated
-system.cpu1.committedOps 225079 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 225079 # Number of Instructions Simulated
-system.cpu1.cpi 0.849999 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.849999 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.176472 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.176472 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 410678 # number of integer regfile reads
-system.cpu1.int_regfile_writes 191757 # number of integer regfile writes
+system.cpu1.rob.rob_reads 424382 # The number of ROB reads
+system.cpu1.rob.rob_writes 514748 # The number of ROB writes
+system.cpu1.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 5100 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 35660 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 200479 # Number of Instructions Simulated
+system.cpu1.committedOps 200479 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 200479 # Number of Instructions Simulated
+system.cpu1.cpi 0.918435 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.918435 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.088808 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.088808 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 365766 # number of integer regfile reads
+system.cpu1.int_regfile_writes 171568 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 118640 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 103658 # number of misc regfile reads
system.cpu1.misc_regfile_writes 646 # number of misc regfile writes
-system.cpu1.icache.replacements 322 # number of replacements
-system.cpu1.icache.tagsinuse 90.918932 # Cycle average of tags in use
-system.cpu1.icache.total_refs 21316 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 48.889908 # Average number of references to valid blocks.
+system.cpu1.icache.replacements 321 # number of replacements
+system.cpu1.icache.tagsinuse 92.890627 # Cycle average of tags in use
+system.cpu1.icache.total_refs 23041 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 438 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 52.605023 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 90.918932 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.177576 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.177576 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 21316 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 21316 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 21316 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 21316 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 21316 # number of overall hits
-system.cpu1.icache.overall_hits::total 21316 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 517 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 517 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 517 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 517 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 517 # number of overall misses
-system.cpu1.icache.overall_misses::total 517 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11871000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 11871000 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 11871000 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 11871000 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 11871000 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 11871000 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 21833 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 21833 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 21833 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 21833 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 21833 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 21833 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023680 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.023680 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023680 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.023680 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023680 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.023680 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 22961.315280 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 22961.315280 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 32000 # number of cycles access was blocked
+system.cpu1.icache.occ_blocks::cpu1.inst 92.890627 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.181427 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.181427 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 23041 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 23041 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 23041 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 23041 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 23041 # number of overall hits
+system.cpu1.icache.overall_hits::total 23041 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 523 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 523 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 523 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 523 # number of overall misses
+system.cpu1.icache.overall_misses::total 523 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10934000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 10934000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 10934000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 10934000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 10934000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 10934000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 23564 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 23564 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 23564 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 23564 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 23564 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 23564 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022195 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.022195 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022195 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.022195 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022195 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.022195 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20906.309751 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 20906.309751 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 20906.309751 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20906.309751 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 20906.309751 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 66 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 32000 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 66 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8857500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 8857500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8857500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 8857500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8857500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 8857500 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019970 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.019970 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019970 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.019970 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 438 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 438 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 438 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 438 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8718000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 8718000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8718000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 8718000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8718000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 8718000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.018588 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.018588 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018588 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.018588 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19904.109589 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19904.109589 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 19904.109589 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 0 # number of replacements
-system.cpu1.dcache.tagsinuse 27.526466 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 42609 # Total number of references to valid blocks.
+system.cpu1.dcache.tagsinuse 27.499718 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 37345 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 1521.750000 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 1333.750000 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 27.526466 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.053763 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.053763 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 46637 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 46637 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 36226 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 36226 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 82863 # number of demand (read+write) hits
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-system.cpu1.dcache.overall_hits::total 82863 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 446 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 446 # number of ReadReq misses
+system.cpu1.dcache.occ_blocks::cpu1.data 27.499718 # Average occupied blocks per requestor
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+system.cpu1.dcache.occ_percent::total 0.053710 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 42212 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 42212 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 30981 # number of WriteReq hits
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+system.cpu1.dcache.overall_hits::total 73193 # number of overall hits
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system.cpu1.dcache.WriteReq_misses::cpu1.data 140 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 140 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 586 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 586 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 586 # number of overall misses
-system.cpu1.dcache.overall_misses::total 586 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 12735500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 12735500 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3574500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 3574500 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1329500 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 1329500 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 16310000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 16310000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 16310000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 16310000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 47083 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 47083 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 36366 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 36366 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 83449 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 83449 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 83449 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 83449 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009473 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.009473 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003850 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.003850 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.787879 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.787879 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007022 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.007022 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007022 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.007022 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25532.142857 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 25567.307692 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 25567.307692 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 27832.764505 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27832.764505 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 27832.764505 # average overall miss latency
+system.cpu1.dcache.demand_misses::cpu1.data 538 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 538 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 538 # number of overall misses
+system.cpu1.dcache.overall_misses::total 538 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9898500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3138500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 3138500 # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1008000 # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total 1008000 # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 13037000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 13037000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 13037000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 13037000 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 42610 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 42610 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 31121 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 31121 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 73731 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 73731 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 73731 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 73731 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009341 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.009341 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004499 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.004499 # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.753623 # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total 0.753623 # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007297 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.007297 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007297 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.007297 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 24870.603015 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 24870.603015 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22417.857143 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 22417.857143 # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 19384.615385 # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 19384.615385 # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 24232.342007 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24232.342007 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24232.342007 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 238 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 37 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 37 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 275 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 275 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses
system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3164503 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3164503 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1890000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1890000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1168500 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1168500 # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5054503 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 5054503 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5054503 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 5054503 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003398 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003398 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002915 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002915 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.787879 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.787879 # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.003188 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003188 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.003188 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679 # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846 # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977 # average overall mshr miss latency
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2446500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2446500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1653500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1653500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 904000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 904000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4100000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4100000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4100000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4100000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003755 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003755 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003310 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003310 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.753623 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.753623 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.003567 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003567 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.003567 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15290.625000 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15290.625000 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16053.398058 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16053.398058 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17384.615385 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17384.615385 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15589.353612 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15589.353612 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 191010 # number of cpu cycles simulated
+system.cpu2.numCycles 183836 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 57179 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 53988 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 1553 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 50487 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 49441 # Number of BTB hits
+system.cpu2.BPredUnit.lookups 53962 # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted 50907 # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect 1502 # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups 47302 # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits 46374 # Number of BTB hits
system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 815 # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS 814 # Number of times the RAS was used to get a target.
system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles 29527 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 320031 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 57179 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 50256 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 111848 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 4474 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 35937 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles 29545 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 300535 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 53962 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 47188 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 106111 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 4305 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 35885 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles 6751 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1077 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 20539 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 187993 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.702356 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.156955 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.NoActiveThreadStallCycles 6446 # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.PendingTrapStallCycles 1035 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 21240 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 181756 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.653508 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.139245 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 76145 40.50% 40.50% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 56782 30.20% 70.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 6165 3.28% 73.99% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3347 1.78% 75.77% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 731 0.39% 76.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 39077 20.79% 96.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1243 0.66% 97.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 913 0.49% 98.09% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3590 1.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 75645 41.62% 41.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 54116 29.77% 71.39% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 6682 3.68% 75.07% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3224 1.77% 76.84% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 665 0.37% 77.21% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 35775 19.68% 96.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1232 0.68% 97.57% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 880 0.48% 98.05% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3537 1.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 187993 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.299351 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.675467 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 35252 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 32290 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 105597 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 5255 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2848 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 315625 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2848 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 36036 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 16472 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 14955 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 100655 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 10276 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 313299 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 219155 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 602465 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 602465 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 203359 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 15796 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1243 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1365 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 12944 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 89370 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 42679 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 42734 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 37374 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 259618 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 6531 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 261379 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 13068 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 11786 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 697 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 187993 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.390366 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.314588 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 181756 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.293533 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.634799 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 35633 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 31817 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 99530 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 5601 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2729 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 296271 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2729 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 36405 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 17349 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 13658 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 94174 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 10995 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 293755 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents 37 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 205188 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 562117 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 562117 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 190142 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 15046 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1228 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1359 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 13734 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 82915 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 39246 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 39773 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 34011 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 242760 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 6943 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 245051 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 12414 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 11373 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 664 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 181756 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.348242 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.310708 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 73641 39.17% 39.17% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 23139 12.31% 51.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 42800 22.77% 74.25% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 43353 23.06% 97.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3352 1.78% 99.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1252 0.67% 99.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 73115 40.23% 40.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 24368 13.41% 53.63% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 39333 21.64% 75.27% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 39995 22.00% 97.28% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3268 1.80% 99.08% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1268 0.70% 99.77% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 298 0.16% 99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 56 0.03% 99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 187993 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 181756 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 21 6.71% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.71% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 82 26.20% 32.91% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 210 67.09% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 20 6.83% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 63 21.50% 28.33% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 125670 48.08% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.08% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 93767 35.87% 83.95% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 41942 16.05% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 118754 48.46% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.46% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 87780 35.82% 84.28% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 38517 15.72% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 261379 # Type of FU issued
-system.cpu2.iq.rate 1.368405 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 313 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001197 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 711198 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 279252 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 259224 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 245051 # Type of FU issued
+system.cpu2.iq.rate 1.332987 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 293 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 672224 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 262158 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 243059 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 261692 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 245344 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 37218 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 33799 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2690 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1641 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2624 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 1621 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2848 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 1926 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 309970 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 424 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 89370 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 42679 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 72 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 2729 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 1758 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 40 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 290501 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 82915 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 39246 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1163 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 35 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 514 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1208 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1722 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 259980 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 88335 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1399 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 41 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1158 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1671 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 243729 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 81914 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1322 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 43821 # number of nop insts executed
-system.cpu2.iew.exec_refs 130189 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 53302 # Number of branches executed
-system.cpu2.iew.exec_stores 41854 # Number of stores executed
-system.cpu2.iew.exec_rate 1.361081 # Inst execution rate
-system.cpu2.iew.wb_sent 259524 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 259224 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 147020 # num instructions producing a value
-system.cpu2.iew.wb_consumers 151915 # num instructions consuming a value
+system.cpu2.iew.exec_nop 40798 # number of nop insts executed
+system.cpu2.iew.exec_refs 120340 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 50195 # Number of branches executed
+system.cpu2.iew.exec_stores 38426 # Number of stores executed
+system.cpu2.iew.exec_rate 1.325796 # Inst execution rate
+system.cpu2.iew.wb_sent 243343 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 243059 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 137174 # num instructions producing a value
+system.cpu2.iew.wb_consumers 142058 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.357123 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.967778 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.322151 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.965620 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 15032 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 5834 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1553 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 178395 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.653241 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 2.030877 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 14265 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 6279 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1502 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 172582 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.600480 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.009191 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 72759 40.79% 40.79% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 51159 28.68% 69.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 6241 3.50% 72.96% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 6697 3.75% 76.72% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1549 0.87% 77.58% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 37557 21.05% 98.64% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 629 0.35% 98.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 989 0.55% 99.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 815 0.46% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 72897 42.24% 42.24% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 48196 27.93% 70.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 6187 3.58% 73.75% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 7136 4.13% 77.89% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1545 0.90% 78.78% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 34295 19.87% 98.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 518 0.30% 98.95% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 991 0.57% 99.53% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 817 0.47% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 178395 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 294930 # Number of instructions committed
-system.cpu2.commit.committedOps 294930 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 172582 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 276214 # Number of instructions committed
+system.cpu2.commit.committedOps 276214 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 127718 # Number of memory references committed
-system.cpu2.commit.loads 86680 # Number of loads committed
-system.cpu2.commit.membars 5119 # Number of memory barriers committed
-system.cpu2.commit.branches 52122 # Number of branches committed
+system.cpu2.commit.refs 117916 # Number of memory references committed
+system.cpu2.commit.loads 80291 # Number of loads committed
+system.cpu2.commit.membars 5562 # Number of memory barriers committed
+system.cpu2.commit.branches 49152 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 201960 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 189186 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 486955 # The number of ROB reads
-system.cpu2.rob.rob_writes 622786 # The number of ROB writes
-system.cpu2.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3017 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 36810 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 246900 # Number of Instructions Simulated
-system.cpu2.committedOps 246900 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 246900 # Number of Instructions Simulated
-system.cpu2.cpi 0.773633 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.773633 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.292602 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.292602 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 450556 # number of integer regfile reads
-system.cpu2.int_regfile_writes 209704 # number of integer regfile writes
+system.cpu2.rob.rob_reads 461657 # The number of ROB reads
+system.cpu2.rob.rob_writes 583698 # The number of ROB writes
+system.cpu2.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 2080 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles 35951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts 230713 # Number of Instructions Simulated
+system.cpu2.committedOps 230713 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 230713 # Number of Instructions Simulated
+system.cpu2.cpi 0.796817 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.796817 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.254994 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.254994 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 420543 # number of integer regfile reads
+system.cpu2.int_regfile_writes 196056 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 131893 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 121964 # number of misc regfile reads
system.cpu2.misc_regfile_writes 646 # number of misc regfile writes
-system.cpu2.icache.replacements 322 # number of replacements
-system.cpu2.icache.tagsinuse 84.177245 # Cycle average of tags in use
-system.cpu2.icache.total_refs 20042 # Total number of references to valid blocks.
-system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs 45.757991 # Average number of references to valid blocks.
+system.cpu2.icache.replacements 323 # number of replacements
+system.cpu2.icache.tagsinuse 86.140818 # Cycle average of tags in use
+system.cpu2.icache.total_refs 20746 # Total number of references to valid blocks.
+system.cpu2.icache.sampled_refs 436 # Sample count of references to valid blocks.
+system.cpu2.icache.avg_refs 47.582569 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst 84.177245 # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst 0.164409 # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total 0.164409 # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst 20042 # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total 20042 # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst 20042 # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total 20042 # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst 20042 # number of overall hits
-system.cpu2.icache.overall_hits::total 20042 # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst 497 # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total 497 # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst 497 # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total 497 # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst 497 # number of overall misses
-system.cpu2.icache.overall_misses::total 497 # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7614500 # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total 7614500 # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst 7614500 # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total 7614500 # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst 7614500 # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total 7614500 # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst 20539 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total 20539 # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst 20539 # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total 20539 # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst 20539 # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total 20539 # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024198 # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total 0.024198 # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024198 # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total 0.024198 # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024198 # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total 0.024198 # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553 # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553 # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 15320.925553 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 15320.925553 # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst 86.140818 # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst 0.168244 # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total 0.168244 # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst 20746 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 20746 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 20746 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 20746 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 20746 # number of overall hits
+system.cpu2.icache.overall_hits::total 20746 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 494 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 494 # number of ReadReq misses
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+system.cpu2.icache.overall_misses::total 494 # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6486500 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 6486500 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 6486500 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 6486500 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 6486500 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 6486500 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 21240 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 21240 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 21240 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 21240 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 21240 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 21240 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023258 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.023258 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023258 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.023258 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023258 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.023258 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13130.566802 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13130.566802 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency
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+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13130.566802 # average overall miss latency
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-system.cpu2.dcache.overall_mshr_miss_rate::total 0.002813 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226 # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385 # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649 # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815 # average overall mshr miss latency
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 239 # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 34 # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data 273 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total 273 # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data 273 # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total 273 # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 166 # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 107 # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 59 # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total 59 # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data 273 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data 273 # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2062000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2062000 # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1458000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1458000 # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 880500 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total 880500 # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3520000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total 3520000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3520000 # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total 3520000 # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003451 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003451 # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002849 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002849 # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.830986 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.830986 # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total 0.003187 # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003187 # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total 0.003187 # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12421.686747 # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 12421.686747 # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13626.168224 # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13626.168224 # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 14923.728814 # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 14923.728814 # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 12893.772894 # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 12893.772894 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 190730 # number of cpu cycles simulated
+system.cpu3.numCycles 183564 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 50135 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 46886 # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect 1563 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 43380 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 42368 # Number of BTB hits
+system.cpu3.BPredUnit.lookups 54292 # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted 51137 # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect 1552 # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups 47375 # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits 46456 # Number of BTB hits
system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS 844 # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.usedRAS 865 # Number of times the RAS was used to get a target.
system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles 33373 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 273510 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 50135 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 43212 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 99693 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 4441 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles 43703 # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles 29332 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 302436 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 54292 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 47321 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 106466 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 4424 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles 35508 # Number of cycles fetch has spent blocked
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles 6715 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 24485 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 187356 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.459841 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.059659 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.NoActiveThreadStallCycles 6464 # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.PendingTrapStallCycles 1083 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 21183 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 181653 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.664911 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.146175 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 87663 46.79% 46.79% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 51707 27.60% 74.39% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 8154 4.35% 78.74% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3276 1.75% 80.49% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 745 0.40% 80.89% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 30183 16.11% 97.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1182 0.63% 97.63% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 888 0.47% 98.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 3558 1.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 75187 41.39% 41.39% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 54224 29.85% 71.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 6571 3.62% 74.86% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3185 1.75% 76.61% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 729 0.40% 77.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 36075 19.86% 96.87% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1175 0.65% 97.52% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 882 0.49% 98.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3625 2.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 187356 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.262858 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.434017 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 40875 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 38262 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 91696 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 6999 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2809 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 269218 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2809 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 41677 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 21676 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 15745 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 84975 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 13759 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 266737 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands 184789 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 501822 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 501822 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 169578 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 15211 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1292 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1426 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 16516 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 73298 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 33720 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 35666 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 28418 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 218299 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 8477 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 222114 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12726 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 11163 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 773 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 187356 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.185518 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.293170 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 181653 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.295766 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.647578 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 35528 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 31409 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 99893 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 5564 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2795 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 298258 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2795 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 36311 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 17134 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 13439 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 94588 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 10922 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 295479 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands 206753 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 566043 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 566043 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 191392 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 15361 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1256 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1388 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 13950 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 83468 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 39555 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 39943 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 34309 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 244369 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 6827 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 246724 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 12382 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 11033 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 652 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 181653 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.358216 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.312562 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 85320 45.54% 45.54% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 28690 15.31% 60.85% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 33902 18.09% 78.95% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 34456 18.39% 97.34% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3309 1.77% 99.10% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1236 0.66% 99.76% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 327 0.17% 99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 62 0.03% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 72528 39.93% 39.93% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 24126 13.28% 53.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 39707 21.86% 75.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 40305 22.19% 97.25% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3272 1.80% 99.06% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1282 0.71% 99.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 320 0.18% 99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 60 0.03% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 187356 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 181653 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 22 7.17% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.17% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 75 24.43% 31.60% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 210 68.40% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 22 7.41% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 65 21.89% 29.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 210 70.71% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 109540 49.32% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 79567 35.82% 85.14% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 33007 14.86% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 119576 48.47% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.47% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 88284 35.78% 84.25% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 38864 15.75% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 222114 # Type of FU issued
-system.cpu3.iq.rate 1.164547 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 307 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 632004 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 239536 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 220090 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 246724 # Type of FU issued
+system.cpu3.iq.rate 1.344076 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 297 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001204 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 675462 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 263617 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 244690 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 222421 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 247021 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 28294 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 34138 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2578 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1587 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2601 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1592 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2809 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 1854 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 263586 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 366 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 73298 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 33720 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1219 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 53 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2795 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 1688 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 292203 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 375 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 83468 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 39555 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1173 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 48 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 509 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1726 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 220807 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 72290 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1307 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 498 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1226 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1724 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 245374 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 82515 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 1350 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 36810 # number of nop insts executed
-system.cpu3.iew.exec_refs 105220 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 46242 # Number of branches executed
-system.cpu3.iew.exec_stores 32930 # Number of stores executed
-system.cpu3.iew.exec_rate 1.157694 # Inst execution rate
-system.cpu3.iew.wb_sent 220376 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 220090 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 122048 # num instructions producing a value
-system.cpu3.iew.wb_consumers 126919 # num instructions consuming a value
+system.cpu3.iew.exec_nop 41007 # number of nop insts executed
+system.cpu3.iew.exec_refs 121290 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 50490 # Number of branches executed
+system.cpu3.iew.exec_stores 38775 # Number of stores executed
+system.cpu3.iew.exec_rate 1.336722 # Inst execution rate
+system.cpu3.iew.wb_sent 244974 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 244690 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 138171 # num instructions producing a value
+system.cpu3.iew.wb_consumers 143054 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.153935 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.961621 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.332996 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.965866 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 14631 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7704 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1563 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 177833 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.399791 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.928963 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 14351 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 6175 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1552 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 172395 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.611613 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 2.012919 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 86250 48.50% 48.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 44177 24.84% 73.34% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 6214 3.49% 76.84% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8561 4.81% 81.65% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1535 0.86% 82.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 28697 16.14% 98.65% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 590 0.33% 98.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 996 0.56% 99.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 72191 41.88% 41.88% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 48466 28.11% 69.99% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 6229 3.61% 73.60% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 7040 4.08% 77.69% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1522 0.88% 78.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 34600 20.07% 98.64% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 541 0.31% 98.95% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 992 0.58% 99.53% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 177833 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 248929 # Number of instructions committed
-system.cpu3.commit.committedOps 248929 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 172395 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 277834 # Number of instructions committed
+system.cpu3.commit.committedOps 277834 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 102853 # Number of memory references committed
-system.cpu3.commit.loads 70720 # Number of loads committed
-system.cpu3.commit.membars 6986 # Number of memory barriers committed
-system.cpu3.commit.branches 45078 # Number of branches committed
+system.cpu3.commit.refs 118830 # Number of memory references committed
+system.cpu3.commit.loads 80867 # Number of loads committed
+system.cpu3.commit.membars 5460 # Number of memory barriers committed
+system.cpu3.commit.branches 49386 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 170050 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 190336 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached
+system.cpu3.commit.bw_lim_events 814 # number cycles where commit BW limit reached
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads 439993 # The number of ROB reads
-system.cpu3.rob.rob_writes 529937 # The number of ROB writes
-system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 3374 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 37090 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 206079 # Number of Instructions Simulated
-system.cpu3.committedOps 206079 # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total 206079 # Number of Instructions Simulated
-system.cpu3.cpi 0.925519 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.925519 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.080475 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.080475 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 375615 # number of integer regfile reads
-system.cpu3.int_regfile_writes 175714 # number of integer regfile writes
+system.cpu3.rob.rob_reads 463179 # The number of ROB reads
+system.cpu3.rob.rob_writes 587180 # The number of ROB writes
+system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1911 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40224.550000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40166.333333 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40138.611111 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40527.333333 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40263.135135 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42968.085106 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45500 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43166.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42791.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43221.374046 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44250 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40963.888889 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43630.952381 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40681.818182 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 44175 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42923.076923 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 41641.579732 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42576.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 41749.253731 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000269 # Number of seconds simulated
-sim_ticks 268898000 # Number of ticks simulated
-final_tick 268898000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000262 # Number of seconds simulated
+sim_ticks 261623500 # Number of ticks simulated
+final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1131883 # Simulator instruction rate (inst/s)
-host_op_rate 1131850 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 454173870 # Simulator tick rate (ticks/s)
-host_mem_usage 240368 # Number of bytes of host memory used
-host_seconds 0.59 # Real time elapsed on the host
-sim_insts 670104 # Number of instructions simulated
-sim_ops 670104 # Number of ops (including micro ops) simulated
+host_inst_rate 776063 # Simulator instruction rate (inst/s)
+host_op_rate 776047 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 307506962 # Simulator tick rate (ticks/s)
+host_mem_usage 231300 # Number of bytes of host memory used
+host_seconds 0.85 # Real time elapsed on the host
+sim_insts 660239 # Number of instructions simulated
+sim_ops 660239 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory
system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 67832412 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39271397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 14042499 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5236186 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 476017 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 3570127 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 1904068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3808135 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 136140842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 67832412 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 14042499 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 476017 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 1904068 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 84254996 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 67832412 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39271397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 14042499 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 5236186 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 476017 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 3570127 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 1904068 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3808135 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 136140842 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 537796 # number of cpu cycles simulated
+system.cpu0.numCycles 523247 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 160914 # Number of instructions committed
-system.cpu0.committedOps 160914 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 110768 # Number of integer alu accesses
+system.cpu0.committedInsts 158010 # Number of instructions committed
+system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 26422 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 110768 # number of integer instructions
+system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 108832 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 320462 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 112374 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 75191 # number of memory refs
-system.cpu0.num_load_insts 49787 # Number of load instructions
-system.cpu0.num_store_insts 25404 # Number of store instructions
+system.cpu0.num_mem_refs 73739 # number of memory refs
+system.cpu0.num_load_insts 48819 # Number of load instructions
+system.cpu0.num_store_insts 24920 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 537796 # Number of busy cycles
+system.cpu0.num_busy_cycles 523247 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 215 # number of replacements
-system.cpu0.icache.tagsinuse 212.263647 # Cycle average of tags in use
-system.cpu0.icache.total_refs 160510 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use
+system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 343.704497 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 212.263647 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.414577 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.414577 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 160510 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 160510 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 160510 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 160510 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 160510 # number of overall hits
-system.cpu0.icache.overall_hits::total 160510 # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits
+system.cpu0.icache.overall_hits::total 157606 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
system.cpu0.icache.overall_misses::total 467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18554000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 18554000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 18554000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 18554000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 18554000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 18554000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 160977 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 160977 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 160977 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 160977 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 160977 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 160977 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002901 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002901 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002901 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002901 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002901 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002901 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39730.192719 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 39730.192719 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 39730.192719 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39730.192719 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 39730.192719 # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17153000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 17153000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17153000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 17153000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17153000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 17153000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002901 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002901 # mshr miss rate for demand accesses
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 36730.192719 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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-system.cpu0.dcache.demand_avg_miss_latency::total 36176.811594 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36176.811594 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
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system.cpu1.num_fp_insts 0 # number of float instructions
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system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
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-system.cpu1.num_load_insts 42937 # Number of load instructions
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-system.cpu1.num_busy_cycles 466217.998266 # Number of busy cycles
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-system.cpu1.idle_fraction 0.133095 # Percentage of idle cycles
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system.cpu1.icache.replacements 280 # number of replacements
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2570001 # number of ReadReq MSHR miss cycles
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system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 0 # number of replacements
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system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
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system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
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system.cpu3.num_fp_insts 0 # number of float instructions
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system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
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-system.cpu3.num_busy_cycles 465665.998268 # Number of busy cycles
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
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-sim_ticks 757091500 # Number of ticks simulated
-final_tick 757091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 129668365 # Simulator tick rate (ticks/s)
-host_mem_usage 347944 # Number of bytes of host memory used
-host_seconds 5.84 # Real time elapsed on the host
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-system.physmem.num_reads::cpu4 11361 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11298 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11018 # Number of read requests responded to by this memory
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-system.physmem.bw_total::cpu3 122561144 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 128845721 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 129057056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 123020797 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 126064023 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1622117010 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::total 1642367378 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.occ_blocks::cpu0 7.652510 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1 7.207345 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2 7.804802 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3 7.584993 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu4 7.883519 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu5 7.822009 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu6 7.314161 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu7 8.194845 # Average occupied blocks per requestor
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-system.l2c.ReadReq_hits::cpu6 10762 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu7 10884 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 86530 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 77152 # number of Writeback hits
-system.l2c.Writeback_hits::total 77152 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 335 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 345 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 353 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 387 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 361 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 367 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 340 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 332 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2820 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu2 2008 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3 2098 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 2081 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 2029 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 2020 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 2069 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 16443 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu2 12863 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu5 13026 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12782 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12953 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu7 12953 # number of overall hits
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-system.l2c.ReadReq_misses::cpu3 784 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu4 818 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu5 847 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu6 802 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 828 # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu2 1867 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 1892 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1828 # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::cpu7 1876 # number of UpgradeReq misses
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-system.l2c.ReadReq_accesses::total 93022 # number of ReadReq accesses(hits+misses)
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 233129489 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 235046492 # number of WriteReq MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu4 655596105 # number of overall MSHR uncacheable cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu3 0.068665 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.067673 # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.842850 # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838810 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.846435 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.828132 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.821204 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.675196 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672479 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.660886 # mshr miss rate for ReadExReq accesses
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41254.441209 # average UpgradeReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41206.842424 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41244.275807 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41173.818575 # average UpgradeReq mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 98965 # number of read accesses completed
-system.cpu0.num_writes 53188 # number of write accesses completed
+system.cpu0.num_reads 99935 # number of read accesses completed
+system.cpu0.num_writes 53927 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.replacements 22322 # number of replacements
-system.cpu0.l1c.tagsinuse 389.061969 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 13312 # Total number of references to valid blocks.
-system.cpu0.l1c.sampled_refs 22723 # Sample count of references to valid blocks.
-system.cpu0.l1c.avg_refs 0.585838 # Average number of references to valid blocks.
+system.cpu0.l1c.replacements 22552 # number of replacements
+system.cpu0.l1c.tagsinuse 390.299440 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 13259 # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs 22978 # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs 0.577030 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::cpu0 389.061969 # Average occupied blocks per requestor
-system.cpu0.l1c.occ_percent::cpu0 0.759887 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::total 0.759887 # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits::cpu0 8733 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8733 # number of ReadReq hits
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-system.cpu0.l1c.overall_hits::total 9840 # number of overall hits
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-system.cpu0.l1c.ReadReq_misses::total 35619 # number of ReadReq misses
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-system.cpu0.l1c.overall_misses::total 58626 # number of overall misses
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-system.cpu0.l1c.ReadReq_miss_latency::total 4549553769 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 3145624806 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 3145624806 # number of WriteReq miss cycles
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-system.cpu0.l1c.ReadReq_accesses::cpu0 44352 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 44352 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24114 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24114 # number of WriteReq accesses(hits+misses)
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-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.803098 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.803098 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954093 # miss rate for WriteReq accesses
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-system.cpu0.l1c.overall_miss_rate::total 0.856279 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127728.284595 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 127728.284595 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 136724.684053 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 136724.684053 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 131258.802835 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 131258.802835 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 131258.802835 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 131258.802835 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 714656307 # number of cycles access was blocked
+system.cpu0.l1c.occ_blocks::cpu0 390.299440 # Average occupied blocks per requestor
+system.cpu0.l1c.occ_percent::cpu0 0.762304 # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::total 0.762304 # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits::cpu0 8650 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8650 # number of ReadReq hits
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+system.cpu0.l1c.WriteReq_hits::total 1121 # number of WriteReq hits
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+system.cpu0.l1c.overall_hits::total 9771 # number of overall hits
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+system.cpu0.l1c.ReadReq_misses::total 36111 # number of ReadReq misses
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+system.cpu0.l1c.WriteReq_misses::total 23070 # number of WriteReq misses
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+system.cpu0.l1c.overall_misses::total 59181 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 4619304150 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 4619304150 # number of ReadReq miss cycles
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+system.cpu0.l1c.WriteReq_miss_latency::total 3123415012 # number of WriteReq miss cycles
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+system.cpu0.l1c.overall_miss_latency::total 7742719162 # number of overall miss cycles
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+system.cpu0.l1c.ReadReq_accesses::total 44761 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 24191 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 24191 # number of WriteReq accesses(hits+misses)
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+system.cpu0.l1c.demand_accesses::total 68952 # number of demand (read+write) accesses
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+system.cpu0.l1c.overall_accesses::total 68952 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806751 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.806751 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953660 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.953660 # miss rate for WriteReq accesses
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+system.cpu0.l1c.demand_miss_rate::total 0.858293 # miss rate for demand accesses
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+system.cpu0.l1c.overall_miss_rate::total 0.858293 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 127919.585445 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 127919.585445 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 135388.600433 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 135388.600433 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 130831.164766 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 130831.164766 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 130831.164766 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 130831.164766 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 1413270 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 63701 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 64534 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11218.918180 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.899619 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9780 # number of writebacks
-system.cpu0.l1c.writebacks::total 9780 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35619 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 35619 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23007 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23007 # number of WriteReq MSHR misses
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-system.cpu0.l1c.demand_mshr_misses::total 58626 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 58626 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 58626 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4478007425 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4478007425 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3099554441 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3099554441 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7577561866 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 7577561866 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7577561866 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 7577561866 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1380411824 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1380411824 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 995386324 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 995386324 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2375798148 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2375798148 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.803098 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.803098 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954093 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954093 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.856279 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856279 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.856279 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 125719.627867 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125719.627867 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 134722.234146 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 134722.234146 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 129252.581892 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 129252.581892 # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks 9856 # number of writebacks
+system.cpu0.l1c.writebacks::total 9856 # number of writebacks
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+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 125919.751599 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 133389.120590 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 133389.120590 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 128831.468917 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 128831.468917 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 97331 # number of read accesses completed
-system.cpu1.num_writes 52743 # number of write accesses completed
+system.cpu1.num_reads 97805 # number of read accesses completed
+system.cpu1.num_writes 52541 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu1.l1c.replacements 21605 # number of replacements
-system.cpu1.l1c.tagsinuse 388.260770 # Cycle average of tags in use
-system.cpu1.l1c.total_refs 12987 # Total number of references to valid blocks.
-system.cpu1.l1c.sampled_refs 21962 # Sample count of references to valid blocks.
-system.cpu1.l1c.avg_refs 0.591340 # Average number of references to valid blocks.
+system.cpu1.l1c.replacements 21861 # number of replacements
+system.cpu1.l1c.tagsinuse 389.546383 # Cycle average of tags in use
+system.cpu1.l1c.total_refs 12913 # Total number of references to valid blocks.
+system.cpu1.l1c.sampled_refs 22254 # Sample count of references to valid blocks.
+system.cpu1.l1c.avg_refs 0.580255 # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.occ_blocks::cpu1 388.260770 # Average occupied blocks per requestor
-system.cpu1.l1c.occ_percent::cpu1 0.758322 # Average percentage of cache occupancy
-system.cpu1.l1c.occ_percent::total 0.758322 # Average percentage of cache occupancy
-system.cpu1.l1c.ReadReq_hits::cpu1 8534 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8534 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1058 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1058 # number of WriteReq hits
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-system.cpu1.l1c.demand_hits::total 9592 # number of demand (read+write) hits
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-system.cpu1.l1c.overall_hits::total 9592 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 35254 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 35254 # number of ReadReq misses
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-system.cpu1.l1c.WriteReq_misses::total 22627 # number of WriteReq misses
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-system.cpu1.l1c.demand_misses::total 57881 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 57881 # number of overall misses
-system.cpu1.l1c.overall_misses::total 57881 # number of overall misses
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-system.cpu1.l1c.ReadReq_miss_latency::total 4617875359 # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::cpu1 3138675137 # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency::total 3138675137 # number of WriteReq miss cycles
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-system.cpu1.l1c.demand_miss_latency::total 7756550496 # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency::cpu1 7756550496 # number of overall miss cycles
-system.cpu1.l1c.overall_miss_latency::total 7756550496 # number of overall miss cycles
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-system.cpu1.l1c.ReadReq_accesses::total 43788 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 23685 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 23685 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.demand_accesses::total 67473 # number of demand (read+write) accesses
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-system.cpu1.l1c.overall_accesses::total 67473 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805106 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.805106 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955330 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.955330 # miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_miss_rate::total 0.857839 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.857839 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.857839 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 130988.692319 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 130988.692319 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 138713.710921 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 138713.710921 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 134008.577875 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 134008.577875 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 134008.577875 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 134008.577875 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 723339270 # number of cycles access was blocked
+system.cpu1.l1c.occ_blocks::cpu1 389.546383 # Average occupied blocks per requestor
+system.cpu1.l1c.occ_percent::cpu1 0.760833 # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::total 0.760833 # Average percentage of cache occupancy
+system.cpu1.l1c.ReadReq_hits::cpu1 8526 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total 8526 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits
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+system.cpu1.l1c.demand_hits::total 9571 # number of demand (read+write) hits
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+system.cpu1.l1c.overall_hits::total 9571 # number of overall hits
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+system.cpu1.l1c.ReadReq_misses::total 35398 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 22650 # number of WriteReq misses
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+system.cpu1.l1c.demand_misses::total 58048 # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1 58048 # number of overall misses
+system.cpu1.l1c.overall_misses::total 58048 # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1 4577570179 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total 4577570179 # number of ReadReq miss cycles
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+system.cpu1.l1c.WriteReq_miss_latency::total 3175338798 # number of WriteReq miss cycles
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+system.cpu1.l1c.overall_miss_latency::total 7752908977 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 43924 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 43924 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 23695 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 23695 # number of WriteReq accesses(hits+misses)
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+system.cpu1.l1c.overall_accesses::total 67619 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805892 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.805892 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955898 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.955898 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.858457 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.858457 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.858457 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.858457 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129317.198119 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 129317.198119 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140191.558411 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 140191.558411 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 133560.311759 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 133560.311759 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 133560.311759 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 133560.311759 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 1404233 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 62977 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 62944 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11485.768932 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.309243 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9483 # number of writebacks
-system.cpu1.l1c.writebacks::total 9483 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35254 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 35254 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22627 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 22627 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 57881 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 57881 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 57881 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 57881 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4547061522 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4547061522 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3093362268 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3093362268 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7640423790 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 7640423790 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7640423790 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 7640423790 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1364091847 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1364091847 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 932992416 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 932992416 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2297084263 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2297084263 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805106 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805106 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955330 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955330 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857839 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857839 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857839 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 128980.017076 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 128980.017076 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 136711.109206 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 136711.109206 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132002.276913 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132002.276913 # average overall mshr miss latency
+system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks
+system.cpu1.l1c.writebacks::total 9603 # number of writebacks
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+system.cpu1.l1c.ReadReq_mshr_misses::total 35398 # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22650 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total 22650 # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1 58048 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total 58048 # number of demand (read+write) MSHR misses
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+system.cpu1.l1c.overall_mshr_misses::total 58048 # number of overall MSHR misses
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+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4506790179 # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3130040798 # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3130040798 # number of WriteReq MSHR miss cycles
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+system.cpu1.l1c.demand_mshr_miss_latency::total 7636830977 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7636830977 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total 7636830977 # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1394209419 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1394209419 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 928511940 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 928511940 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2322721359 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2322721359 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805892 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805892 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955898 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955898 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total 0.858457 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858457 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.858457 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127317.650121 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127317.650121 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138191.646711 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138191.646711 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 131560.621847 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 131560.621847 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 98360 # number of read accesses completed
-system.cpu2.num_writes 53068 # number of write accesses completed
+system.cpu2.num_reads 100000 # number of read accesses completed
+system.cpu2.num_writes 54114 # number of write accesses completed
system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu2.l1c.replacements 22096 # number of replacements
-system.cpu2.l1c.tagsinuse 389.724593 # Cycle average of tags in use
-system.cpu2.l1c.total_refs 13250 # Total number of references to valid blocks.
-system.cpu2.l1c.sampled_refs 22502 # Sample count of references to valid blocks.
-system.cpu2.l1c.avg_refs 0.588837 # Average number of references to valid blocks.
+system.cpu2.l1c.replacements 22990 # number of replacements
+system.cpu2.l1c.tagsinuse 392.060782 # Cycle average of tags in use
+system.cpu2.l1c.total_refs 13456 # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs 23401 # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs 0.575018 # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::cpu2 389.724593 # Average occupied blocks per requestor
-system.cpu2.l1c.occ_percent::cpu2 0.761181 # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::total 0.761181 # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits::cpu2 8687 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8687 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9808 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9808 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9808 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9808 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 35624 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 35624 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 22874 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 22874 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 58498 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 58498 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 58498 # number of overall misses
-system.cpu2.l1c.overall_misses::total 58498 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 4545456138 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 4545456138 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 3151736803 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 3151736803 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 7697192941 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 7697192941 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 7697192941 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 7697192941 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 44311 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 44311 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 23995 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 23995 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.demand_accesses::total 68306 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 68306 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 68306 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803954 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.803954 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953282 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.953282 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.856411 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.856411 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.856411 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.856411 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 127595.332865 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 127595.332865 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 137786.867317 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 137786.867317 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 131580.446186 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 131580.446186 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 131580.446186 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 131580.446186 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 716129194 # number of cycles access was blocked
+system.cpu2.l1c.occ_blocks::cpu2 392.060782 # Average occupied blocks per requestor
+system.cpu2.l1c.occ_percent::cpu2 0.765744 # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::total 0.765744 # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits::cpu2 8750 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8750 # number of ReadReq hits
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+system.cpu2.l1c.WriteReq_hits::total 1243 # number of WriteReq hits
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+system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits
+system.cpu2.l1c.overall_hits::total 9993 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36203 # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2 23173 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total 23173 # number of WriteReq misses
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+system.cpu2.l1c.demand_misses::total 59376 # number of demand (read+write) misses
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+system.cpu2.l1c.overall_misses::total 59376 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 4641358719 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 4641358719 # number of ReadReq miss cycles
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+system.cpu2.l1c.ReadReq_accesses::cpu2 44953 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 44953 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 24416 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 24416 # number of WriteReq accesses(hits+misses)
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+system.cpu2.l1c.demand_accesses::total 69369 # number of demand (read+write) accesses
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+system.cpu2.l1c.overall_accesses::total 69369 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805352 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.805352 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.949091 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.949091 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.855944 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.855944 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.855944 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.855944 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 128203.704638 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 128203.704638 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 134949.802874 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 134949.802874 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 130836.541717 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 130836.541717 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 130836.541717 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 130836.541717 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 1392289 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 63633 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 64514 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11254.053620 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.581192 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9686 # number of writebacks
-system.cpu2.l1c.writebacks::total 9686 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35624 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 35624 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22874 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 22874 # number of WriteReq MSHR misses
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-system.cpu2.l1c.demand_mshr_misses::total 58498 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 58498 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 58498 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4473878832 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4473878832 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3105924454 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3105924454 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7579803286 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 7579803286 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7579803286 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 7579803286 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1379555288 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1379555288 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 954692892 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 954692892 # number of WriteReq MSHR uncacheable cycles
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-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2334248180 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803954 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803954 # mshr miss rate for ReadReq accesses
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-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953282 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.856411 # mshr miss rate for demand accesses
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-system.cpu2.l1c.overall_mshr_miss_rate::total 0.856411 # mshr miss rate for overall accesses
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-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 135784.054123 # average WriteReq mshr miss latency
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-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 129573.716811 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 129573.716811 # average overall mshr miss latency
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 126203.815126 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 126203.815126 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 132950.234411 # average WriteReq mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128836.777503 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 100000 # number of read accesses completed
-system.cpu3.num_writes 53600 # number of write accesses completed
+system.cpu3.num_reads 98308 # number of read accesses completed
+system.cpu3.num_writes 52892 # number of write accesses completed
system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu3.l1c.replacements 22673 # number of replacements
-system.cpu3.l1c.tagsinuse 391.747074 # Cycle average of tags in use
-system.cpu3.l1c.total_refs 13403 # Total number of references to valid blocks.
-system.cpu3.l1c.sampled_refs 23070 # Sample count of references to valid blocks.
-system.cpu3.l1c.avg_refs 0.580971 # Average number of references to valid blocks.
+system.cpu3.l1c.replacements 21879 # number of replacements
+system.cpu3.l1c.tagsinuse 388.243829 # Cycle average of tags in use
+system.cpu3.l1c.total_refs 13269 # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs 22290 # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs 0.595289 # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.occ_blocks::cpu3 391.747074 # Average occupied blocks per requestor
-system.cpu3.l1c.occ_percent::cpu3 0.765131 # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::total 0.765131 # Average percentage of cache occupancy
-system.cpu3.l1c.ReadReq_hits::cpu3 8720 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8720 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1143 # number of WriteReq hits
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-system.cpu3.l1c.demand_hits::cpu3 9863 # number of demand (read+write) hits
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-system.cpu3.l1c.overall_hits::total 9863 # number of overall hits
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-system.cpu3.l1c.ReadReq_misses::total 36203 # number of ReadReq misses
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-system.cpu3.l1c.WriteReq_misses::total 22978 # number of WriteReq misses
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-system.cpu3.l1c.demand_misses::total 59181 # number of demand (read+write) misses
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-system.cpu3.l1c.overall_misses::total 59181 # number of overall misses
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-system.cpu3.l1c.ReadReq_miss_latency::total 4605371729 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 3121949330 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 3121949330 # number of WriteReq miss cycles
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-system.cpu3.l1c.demand_miss_latency::total 7727321059 # number of demand (read+write) miss cycles
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-system.cpu3.l1c.overall_miss_latency::total 7727321059 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 44923 # number of ReadReq accesses(hits+misses)
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-system.cpu3.l1c.overall_accesses::total 69044 # number of overall (read+write) accesses
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-system.cpu3.l1c.overall_miss_rate::total 0.857149 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 127209.671270 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 127209.671270 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135866.887022 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 135866.887022 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 130570.978169 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 130570.978169 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 130570.978169 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 130570.978169 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 721076565 # number of cycles access was blocked
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+system.cpu3.l1c.occ_percent::total 0.758289 # Average percentage of cache occupancy
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+system.cpu3.l1c.ReadReq_hits::total 8771 # number of ReadReq hits
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+system.cpu3.l1c.overall_hits::total 9837 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 35672 # number of ReadReq misses
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+system.cpu3.l1c.WriteReq_misses::total 22858 # number of WriteReq misses
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+system.cpu3.l1c.overall_misses::total 58530 # number of overall misses
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+system.cpu3.l1c.ReadReq_accesses::total 44443 # number of ReadReq accesses(hits+misses)
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+system.cpu3.l1c.overall_accesses::total 68367 # number of overall (read+write) accesses
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+system.cpu3.l1c.ReadReq_miss_rate::total 0.802646 # miss rate for ReadReq accesses
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+system.cpu3.l1c.WriteReq_miss_rate::total 0.955442 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.856115 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.856115 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.856115 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.856115 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 131901.557832 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 131901.557832 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 135291.971695 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 135291.971695 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 133225.632325 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 133225.632325 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 133225.632325 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 133225.632325 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 1411864 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 64491 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 63831 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11181.041773 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 22.118782 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9961 # number of writebacks
-system.cpu3.l1c.writebacks::total 9961 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36203 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36203 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22978 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 22978 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 59181 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 59181 # number of demand (read+write) MSHR misses
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-system.cpu3.l1c.overall_mshr_misses::total 59181 # number of overall MSHR misses
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-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4532659362 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3075925984 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3075925984 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7608585346 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 7608585346 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7608585346 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 7608585346 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1393944138 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1393944138 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 919834390 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 919834390 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2313778528 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2313778528 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805890 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805890 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952614 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952614 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.overall_mshr_miss_rate::total 0.857149 # mshr miss rate for overall accesses
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-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 125201.208795 # average ReadReq mshr miss latency
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-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 133863.956132 # average WriteReq mshr miss latency
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-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128564.663422 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128564.663422 # average overall mshr miss latency
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+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 129901.894231 # average ReadReq mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 131226.008201 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 131226.008201 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99186 # number of read accesses completed
-system.cpu4.num_writes 53232 # number of write accesses completed
+system.cpu4.num_reads 99646 # number of read accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu4.l1c.replacements 22556 # number of replacements
-system.cpu4.l1c.tagsinuse 391.523203 # Cycle average of tags in use
-system.cpu4.l1c.total_refs 13363 # Total number of references to valid blocks.
-system.cpu4.l1c.sampled_refs 22976 # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs 0.581607 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22486 # number of replacements
+system.cpu4.l1c.tagsinuse 389.564427 # Cycle average of tags in use
+system.cpu4.l1c.total_refs 13323 # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs 22871 # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs 0.582528 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu4.l1c.occ_percent::total 0.764694 # Average percentage of cache occupancy
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-system.cpu4.l1c.ReadReq_miss_latency::total 4605243494 # number of ReadReq miss cycles
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-system.cpu4.l1c.WriteReq_miss_latency::total 3106119837 # number of WriteReq miss cycles
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-system.cpu4.l1c.ReadReq_avg_miss_latency::total 128190.493918 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 135313.432237 # average WriteReq miss latency
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-system.cpu4.l1c.demand_avg_miss_latency::total 130967.447877 # average overall miss latency
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-system.cpu4.l1c.overall_avg_miss_latency::total 130967.447877 # average overall miss latency
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+system.cpu4.l1c.occ_percent::total 0.760868 # Average percentage of cache occupancy
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+system.cpu4.l1c.ReadReq_hits::total 8662 # number of ReadReq hits
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+system.cpu4.l1c.overall_miss_rate::total 0.857572 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 127248.692989 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 127248.692989 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 136663.022170 # average WriteReq miss latency
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+system.cpu4.l1c.overall_avg_miss_latency::cpu4 130902.300340 # average overall miss latency
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+system.cpu4.l1c.blocked_cycles::no_mshrs 1409065 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 64157 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9838 # number of writebacks
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-system.cpu4.l1c.overall_mshr_misses::total 58880 # number of overall MSHR misses
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-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3060147977 # number of WriteReq MSHR miss cycles
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-system.cpu4.l1c.demand_mshr_miss_latency::total 7593241104 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7593241104 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 7593241104 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1402247556 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1402247556 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 894394941 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 894394941 # number of WriteReq MSHR uncacheable cycles
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-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2296642497 # number of overall MSHR uncacheable cycles
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-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804970 # mshr miss rate for ReadReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.856299 # mshr miss rate for demand accesses
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-system.cpu4.l1c.overall_mshr_miss_rate::total 0.856299 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 126182.132971 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 133310.737399 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 133310.737399 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128961.295924 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128961.295924 # average overall mshr miss latency
+system.cpu4.l1c.writebacks::writebacks 9768 # number of writebacks
+system.cpu4.l1c.writebacks::total 9768 # number of writebacks
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+system.cpu4.l1c.ReadReq_mshr_misses::total 36129 # number of ReadReq MSHR misses
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+system.cpu4.l1c.WriteReq_mshr_misses::total 22914 # number of WriteReq MSHR misses
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+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857572 # mshr miss rate for overall accesses
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+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 125249.080489 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 125249.080489 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 134663.196736 # average WriteReq mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 128902.605203 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 128902.605203 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 99811 # number of read accesses completed
-system.cpu5.num_writes 54122 # number of write accesses completed
+system.cpu5.num_reads 99510 # number of read accesses completed
+system.cpu5.num_writes 53712 # number of write accesses completed
system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu5.l1c.replacements 22776 # number of replacements
-system.cpu5.l1c.tagsinuse 391.477551 # Cycle average of tags in use
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-system.cpu5.l1c.sampled_refs 23147 # Sample count of references to valid blocks.
-system.cpu5.l1c.avg_refs 0.575539 # Average number of references to valid blocks.
+system.cpu5.l1c.replacements 22704 # number of replacements
+system.cpu5.l1c.tagsinuse 391.715809 # Cycle average of tags in use
+system.cpu5.l1c.total_refs 13238 # Total number of references to valid blocks.
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+system.cpu5.l1c.avg_refs 0.572850 # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu5.l1c.WriteReq_miss_latency::total 3131851801 # number of WriteReq miss cycles
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-system.cpu5.l1c.ReadReq_avg_miss_latency::total 126495.185207 # average ReadReq miss latency
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-system.cpu5.l1c.demand_avg_miss_latency::total 130027.245872 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 130027.245872 # average overall miss latency
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu5.l1c.writebacks::total 10068 # number of writebacks
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-system.cpu5.l1c.demand_mshr_miss_latency::total 7590976400 # number of demand (read+write) MSHR miss cycles
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-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1396623229 # number of ReadReq MSHR uncacheable cycles
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-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2366682910 # number of overall MSHR uncacheable cycles
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-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951485 # mshr miss rate for WriteReq accesses
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-system.cpu5.l1c.demand_mshr_miss_rate::total 0.857186 # mshr miss rate for demand accesses
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-system.cpu5.l1c.overall_mshr_miss_rate::total 0.857186 # mshr miss rate for overall accesses
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-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 124486.113893 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 133557.328745 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 133557.328745 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128020.514377 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128020.514377 # average overall mshr miss latency
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+system.cpu5.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses
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+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125857.612231 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134805.048526 # average WriteReq mshr miss latency
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+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 129346.829435 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 129346.829435 # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 52167 # number of write accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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-system.cpu6.l1c.sampled_refs 21936 # Sample count of references to valid blocks.
-system.cpu6.l1c.avg_refs 0.586205 # Average number of references to valid blocks.
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system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.ReadReq_miss_latency::total 4508353371 # number of ReadReq miss cycles
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-system.cpu6.l1c.WriteReq_miss_latency::total 3154254558 # number of WriteReq miss cycles
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-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 128110.976414 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 128110.976414 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 139915.478974 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 139915.478974 # average WriteReq miss latency
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-system.cpu6.l1c.demand_avg_miss_latency::total 132720.324396 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 132720.324396 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 132720.324396 # average overall miss latency
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+system.cpu6.l1c.ReadReq_avg_miss_latency::total 129799.500848 # average ReadReq miss latency
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+system.cpu6.l1c.overall_avg_miss_latency::cpu6 132241.429140 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.writebacks::total 9499 # number of writebacks
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-system.cpu6.l1c.overall_mshr_misses::total 57735 # number of overall MSHR misses
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-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4437636067 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3109111203 # number of WriteReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency::total 7546747270 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7546747270 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 7546747270 # number of overall MSHR miss cycles
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-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1416513847 # number of ReadReq MSHR uncacheable cycles
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-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 907986926 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2324500773 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2324500773 # number of overall MSHR uncacheable cycles
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-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808617 # mshr miss rate for ReadReq accesses
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-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859536 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859536 # mshr miss rate for overall accesses
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-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 126101.448296 # average ReadReq mshr miss latency
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-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 137913.023554 # average WriteReq mshr miss latency
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-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130713.557980 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130713.557980 # average overall mshr miss latency
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+system.cpu6.l1c.WriteReq_mshr_misses::total 23081 # number of WriteReq MSHR misses
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+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127799.778788 # average ReadReq mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130241.835506 # average overall mshr miss latency
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 98233 # number of read accesses completed
-system.cpu7.num_writes 53134 # number of write accesses completed
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system.cpu7.num_copies 0 # number of copy accesses completed
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-system.cpu7.l1c.tagsinuse 390.077286 # Cycle average of tags in use
-system.cpu7.l1c.total_refs 13228 # Total number of references to valid blocks.
-system.cpu7.l1c.sampled_refs 22658 # Sample count of references to valid blocks.
-system.cpu7.l1c.avg_refs 0.583811 # Average number of references to valid blocks.
+system.cpu7.l1c.replacements 22510 # number of replacements
+system.cpu7.l1c.tagsinuse 390.052988 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 13451 # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs 22924 # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs 0.586765 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::cpu7 390.077286 # Average occupied blocks per requestor
-system.cpu7.l1c.occ_percent::cpu7 0.761870 # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::total 0.761870 # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits::cpu7 8637 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8637 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
projects / gem5.git / commitdiff