+2018-04-09 Maciej W. Rozycki <macro@mips.com>
+
+ * testsuite/binutils-all/strip-15.d: New test.
+ * testsuite/binutils-all/strip-15rel.s: New test source.
+ * testsuite/binutils-all/strip-15rela.s: New test source.
+ * testsuite/binutils-all/strip-15mips64.s: New test source.
+ * testsuite/binutils-all/objcopy.exp: Run the new test.
+
2018-04-09 Maciej W. Rozycki <macro@mips.com>
* testsuite/binutils-all/strip-14.d: New test.
[list as "--defsym RELOC=${reloc}"] \
[list as [expr {[is_elf64 tmpdir/bintest.o] \
? "--defsym ELF64=1" : ""}]]]
+ run_dump_test "strip-15" [list \
+ [list source strip-15${reloc_format}.s] \
+ [list as "--defsym RELOC=${reloc}"] \
+ [list as [expr {[is_elf64 tmpdir/bintest.o] \
+ ? "--defsym ELF64=1" : ""}]]]
# This requires STB_GNU_UNIQUE support with OSABI set to GNU.
if { [supports_gnu_unique] } {
--- /dev/null
+#PROG: strip
+#strip: -g
+#readelf: -r
+
+Relocation section '\.rela?\.text' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\. *Value * Sym\. *Name(?: * \+ * Addend)?
+0+00 * 0+0(?:1|32|103) * R_[^ ]* *(?: * 55aa)?
+#pass
--- /dev/null
+ .text
+foo:
+ .dc.l 0x12345678
+
+ .section .rela.text
+ .dc.a 0
+ .dc.l 0x00000000
+ .dc.b 0, 0, 0, RELOC
+ .dc.a 0x000055aa
+
+ .dc.a 0
+ .dc.l 0
+ .dc.b 0, 0, 0, 0
+ .dc.a 0
--- /dev/null
+ .text
+foo:
+ .dc.l 0x12345678
+
+ .section .rel.text
+ .ifdef ELF64
+
+ .dc.a 0
+ .dc.a RELOC
+
+ .dc.a 0
+ .dc.a 0
+ .else
+
+ # Some targets, such as `m68hc11-*', use 16-bit addresses.
+ # With them `.dc.a' emits 16-bit quantities, so we need to use
+ # `.dc.l' for 32-bit relocation data.
+ .dc.l 0
+ .dc.l RELOC
+
+ .dc.l 0
+ .dc.l 0
+ .endif
--- /dev/null
+ .text
+foo:
+ .dc.l 0x12345678
+
+ .section .rela.text
+ .ifdef ELF64
+
+ .dc.a 0
+ .dc.a RELOC
+ .dc.a 0x00000000000055aa
+
+ .dc.a 0
+ .dc.a 0
+ .dc.a 0
+ .else
+
+ # Some targets, such as `h8300-*' or `ip2k-*', use 16-bit addresses.
+ # With them `.dc.a' emits 16-bit quantities, so we need to use
+ # `.dc.l' for 32-bit relocation data.
+ .dc.l 0
+ .dc.l RELOC
+ .dc.l 0x000055aa
+
+ .dc.l 0
+ .dc.l 0
+ .dc.l 0
+ .endif