anlogic: add support for Eagle Distributed RAM

The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 750dced311b6ac8b5a55517c3cc9c36ad3945321..59be83fd012dc30748f1ae67db1dd30ee471ef10 100644 (file)
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -5,4 +5,5 @@ OBJS += techlibs/anlogic/anlogic_eqn.o
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))

diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
new file mode 100644 (file)
index 0000000..2bff14a
--- /dev/null
+++ b/techlibs/anlogic/drams.txt
@@ -0,0 +1,16 @@
+bram $__ANLOGIC_DRAM16X4
+  init 0
+  abits 4
+  dbits 2
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 1
+endbram
+
+match $__ANLOGIC_DRAM16X4
+  make_outreg
+endmatch

diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v
new file mode 100644 (file)
index 0000000..87cbb6a
--- /dev/null
+++ b/techlibs/anlogic/drams_map.v
@@ -0,0 +1,19 @@
+module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+       input CLK1;
+
+       input [3:0] A1ADDR;
+       output [3:0] A1DATA;
+
+       input [3:0] B1ADDR;
+       input [3:0] B1DATA;
+       input B1EN;
+
+       EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+               .di(B1DATA),
+               .waddr(B1ADDR),
+               .wclk(CLK1),
+               .we(B1EN),
+               .raddr(A1ADDR),
+               .do(A1DATA)
+       );
+endmodule

diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index f4ef8877032afb8eb44aecd9b48928f92044daf3..a4eafeddf4406b2a4a211a3d97bab94a0a4864ca 100644 (file)
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -150,6 +150,12 @@ struct SynthAnlogicPass : public ScriptPass
                        run("synth -run coarse");
                }
 
+               if (check_label("dram"))
+               {
+                       run("memory_bram -rules +/anlogic/drams.txt");
+                       run("techmap -map +/anlogic/drams_map.v");
+               }
+
                if (check_label("fine"))
                {
                        run("opt -fast -mux_undef -undriven -fine");