(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 47d012092b1f709d614223ef990363a84c823311..a93d29390a24980a1b3e82ce81e69708446333c1 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -234,6 +234,12 @@ of magnitude increase in the number of hand-written lines of assembler
 compared to a well-designed Cray-style Vector ISA with a `setvl`
 instruction.
 
+*Packed SIMD looped algorithms actually have to
+contain multiple implementations processing fragments of data at
+different SIMD widths: Cray-style Vectors have one, covering not
+just current architectural implementations but future ones with
+wider back-end ALUs as well.*
+
 Assuming then that variable-length Vectors are obviously desirable,
 it becomes a matter of how, not if.  Both Cray and NEC SX Aurora
 went the way of adding explicit Vector opcodes, a style which RVV