sync.md (load_locked_<mode>): Use Z for memory_operand constraint.

        * config/rs6000/sync.md (load_locked_<mode>): Use Z for
        memory_operand constraint.
        (store_conditional_<mode>): Same.
        (sync_compare_and_swap<mode>): Same.
        (sync_lock_test_and_set<mode>): Same.

From-SVN: r101813

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6c5e2bb54e37a677e84c760fb83efac5096dd176..ed5f975e44fdbdd9874056fb024de7b04559cdb5 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2005-07-08  David Edelsohn  <edelsohn@gnu.org>
+
+       * config/rs6000/sync.md (load_locked_<mode>): Use Z for
+       memory_operand constraint.
+       (store_conditional_<mode>): Same.
+       (sync_compare_and_swap<mode>): Same.
+       (sync_lock_test_and_set<mode>): Same.
+
 2005-07-08  Hans-Peter Nilsson  <hp@axis.com>
 
        Rewrite PIC support to more closely model actual instructions.

diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md
index a98dc1545d350574fbec24dbcb2df0d33d669796..cef64787b14b01e9501e519f1e46f13eddde9303 100644 (file)
--- a/gcc/config/rs6000/sync.md
+++ b/gcc/config/rs6000/sync.md
@@ -41,7 +41,7 @@
 (define_insn "load_locked_<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
        (unspec_volatile:GPR
-         [(match_operand:GPR 1 "memory_operand" "m")] UNSPECV_LL))]
+         [(match_operand:GPR 1 "memory_operand" "Z")] UNSPECV_LL))]
   "TARGET_POWERPC"
   "<larx> %0,%y1"
   [(set_attr "type" "load_l")])
@@ -49,7 +49,7 @@
 (define_insn "store_conditional_<mode>"
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
        (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
-   (set (match_operand:GPR 1 "memory_operand" "=m")
+   (set (match_operand:GPR 1 "memory_operand" "=Z")
        (match_operand:GPR 2 "gpc_reg_operand" "r"))]
   "TARGET_POWERPC"
   "<stcx> %2,%y1"
@@ -57,7 +57,7 @@
 
 (define_insn_and_split "sync_compare_and_swap<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
-       (match_operand:GPR 1 "memory_operand" "+m"))
+       (match_operand:GPR 1 "memory_operand" "+Z"))
    (set (match_dup 1)
        (unspec_volatile:GPR
          [(match_operand:GPR 2 "reg_or_short_operand" "rI")
@@ -77,7 +77,7 @@
 
 (define_insn_and_split "sync_lock_test_and_set<mode>"
   [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r")
-        (match_operand:GPR 1 "memory_operand" "+m"))
+        (match_operand:GPR 1 "memory_operand" "+Z"))
    (set (match_dup 1)
        (unspec_volatile:GPR
          [(match_operand:GPR 2 "reg_or_short_operand" "rL")]