Merge remote-tracking branch 'origin/xaig' into xc7mux

diff --cc CHANGELOG
index 18dfcf38968be12d93ca686af9c1f30bac46ddfb,0636e6bad465540a3dbc50036980fd8ff15d0687..abfbb7f7914ff13612ede10999fb22da8b4666f6
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -18,16 -18,15 +18,17 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "equiv_opt" pass
      - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
-     - Added "shregmap -tech xilinx"
+     - Added "muxcover -mux{4,8,16}=<cost>"
+     - Added "muxcover -dmux=<cost>"
+     - Added "muxcover -nopartial"
++    - Added "muxpack" pass
      - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
      - Added "synth_xilinx -abc9" (experimental)
      - Added "synth_ice40 -abc9" (experimental)
      - Added "synth -abc9" (experimental)
-     - Added "muxpack" pass
-     - Extended "muxcover -mux{4,8,16}=<cost>"
-     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
      - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
  
  
  Yosys 0.7 .. Yosys 0.8

diff --cc techlibs/xilinx/abc_xc7.box
index a312646f7b115a85ac7f27f6002d4a53819f27f2,b5817a6e0aa188698c0a12ae02a43ce4c15a417c..5e6ce2ea3d2f115254cb2bd7598c5b7ec04a567c
--- 1/techlibs/xilinx/abc_xc7.box
--- 2/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@@ -1,67 -1,31 +1,36 @@@
  # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
  
 -# F7BMUX slower than F7AMUX
+ # NB: Inputs/Outputs must be ordered alphabetically
+ #     (with exceptions for carry in/out)
+ 
 +# Average across F7[AB]MUX
  # Inputs: I0 I1 S0
  # Outputs: O
 -F7BMUX 1 1 3 1
 -217 223 296
 +F7MUX 1 1 3 1
 +204 208 286
  
  # Inputs: I0 I1 S0
  # Outputs: O
  MUXF8 2 1 3 1
  104 94 273
  
 +# Inputs: I0 I1 I2 I3 S0 S1
 +# Outputs: O
 +MUXF78 10 1 6 1
 +190 193 217 223 296 273
 +
  # CARRY4 + CARRY4_[ABCD]X
- # Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI
+ # Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
  # Outputs:  O0 O1 O2 O3 CO0 CO1 CO2 CO3
- #   (NB: carry chain input/output must be last input/output,
- #        swapped with what normally would have been the last
- #        output, here: CI <-> S, CO <-> O
+ #   (NB: carry chain input/output must be last
+ #        input/output and have been moved there
+ #        overriding the alphabetical ordering)
  CARRY4 3 1 10 8
- 223 -   -   -   482 -   -   -   -   222
- 400 205 -   -   598 407 -   -   -   334
- 523 558 226 -   584 556 537 -   -   239
- 582 618 330 227 642 615 596 438 -   313
- 340 -   -   -   536 379 -   -   -   271
- 433 469 -   -   494 465 445 -   -   157
- 512 548 292 -   592 540 520 356 -   228
- 508 528 378 380 580 526 507 398 385 114
- 
- # SLICEM/A6LUT
- # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
- # Outputs: DPO SPO
- RAM64X1D 4 0 15 2
- -   -   -   -   -   -   - 124 124 124 124 124 124 - -
- 124 124 124 124 124 124 - -   -   -   -   -   124 - -
- 
- # SLICEM/A6LUT + F7[AB]MUX
- # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
- # Outputs: DPO SPO
- RAM128X1D 5 0 17 2
- -   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
- 347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
- 
- # Inputs: C CE D R
- # Outputs: Q
- FDRE 6 0 4 1
- - - - -
- 
- # Inputs: C CE D S
- # Outputs: Q
- FDSE 7 0 4 1
- - - - -
- 
- # Inputs: C CE CLR D
- # Outputs: Q
- FDCE 8 0 4 1
- - - - -
- 
- # Inputs: C CE D PRE
- # Outputs: Q
- FDPE 9 0 4 1
- - - - -
+ 482 -   -   -   -   223 -   -   -   222
+ 598 407 -   -   -   400 205 -   -   334
+ 584 556 537 -   -   523 558 226 -   239
+ 642 615 596 438 -   582 618 330 227 313
+ 536 379 -   -   -   340 -   -   -   271
+ 494 465 445 -   -   433 469 -   -   157
+ 592 540 520 356 -   512 548 292 -   228
+ 580 526 507 398 385 508 528 378 380 114

diff --cc techlibs/xilinx/cells_sim.v
Simple merge