re PR target/81616 (Update -mtune=generic for the current Intel and AMD processors)

	PR target/81616
	* config/i386/x86-tune-costs.h: Increase cost of integer load costs
	for generic 4->6.

From-SVN: r256073

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57e31cb85eef7fed370ac21ec05c6187546d03ee..522573ffb903509fb7807b2783b5a2bc033f7b65 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,13 @@
 2018-01-02  Jan Hubicka  <hubicka@ucw.cz>
 
        PR target/81616
+       * config/i386/x86-tune-costs.h: Increase cost of integer load costs
+       for generic 4->6.
+
+2018-01-02  Jan Hubicka  <hubicka@ucw.cz>
+
+       PR target/81616
+       Generic tuning.
        * x86-tune-costs.h (generic_cost): Reduce cost of FDIV 20->17,
        cost of sqrt 20->14, DIVSS 18->13, DIVSD 32->17, SQRtSS 30->14
        and SQRTsD 58->18, cond_not_taken_branch_cost. 2->1. Increase

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index eff7f7f6bbfc2e32e6905108d97a847291cf6c0b..ac0645fc9f76b6496e8923c1e053557559f6fcb1 100644 (file)
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -2259,8 +2259,8 @@ struct processor_costs generic_cost = {
 
   /* All move costs are relative to integer->integer move times 2 and thus
      they are latency*2. */
-  4,                                /* cost for loading QImode using movzbl */
-  {4, 4, 4},                           /* cost of loading integer registers
+  6,                                /* cost for loading QImode using movzbl */
+  {6, 6, 6},                           /* cost of loading integer registers
                                           in QImode, HImode and SImode.
                                           Relative to reg-reg move (2).  */
   {6, 6, 6},                           /* cost of storing integer registers */