RISC-V: Add support for the Zvksc ISA extension

Zvksc is part of the vector crypto extensions.

Zvksc is shorthand for the following set of extensions:
- Zvks
- Zvbc

bfd/ChangeLog:

	* elfxx-riscv.c: Define Zvksc extension.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksc.d: New test.
	* testsuite/gas/riscv/zvksc.s: New test.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 95b3ab3c2c712fb60349e9322cc9877207000430..d6c8e046e3e687876640fb56245f4180bd14dccd 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1169,6 +1169,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "zvbb",     check_implicit_always},
   {"zvksg", "zvks",    check_implicit_always},
   {"zvksg", "zvkg",    check_implicit_always},
+  {"zvksc", "zvks",    check_implicit_always},
+  {"zvksc", "zvbc",    check_implicit_always},
   {"smaia", "ssaia",           check_implicit_always},
   {"smstateen", "ssstateen",   check_implicit_always},
   {"smepmp", "zicsr",          check_implicit_always},
@@ -1288,6 +1290,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksh",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvks",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvksg",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvksc",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl32b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl64b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl128b",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },

diff --git a/gas/testsuite/gas/riscv/zvksc.d b/gas/testsuite/gas/riscv/zvksc.d
new file mode 100644 (file)
index 0000000..8614ede
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.d
@@ -0,0 +1,18 @@
+#as: -march=rv64gc_zvksc
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+86802277[     ]+vsm4k.vi[     ]+v4,v8,0
+[      ]+[0-9a-f]+:[   ]+ae802277[     ]+vsm3c.vi[     ]+v4,v8,0
+[      ]+[0-9a-f]+:[   ]+32862257[     ]+vclmul.vv[    ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+30862257[     ]+vclmul.vv[    ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+3285e257[      ]+vclmul.vx[   ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+3085e257[      ]+vclmul.vx[   ]+v4,v8,a1,v0.t
+[      ]+[0-9a-f]+:[   ]+36862257[      ]+vclmulh.vv[  ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+34862257[      ]+vclmulh.vv[  ]+v4,v8,v12,v0.t
+[      ]+[0-9a-f]+:[   ]+3685e257[      ]+vclmulh.vx[  ]+v4,v8,a1
+[      ]+[0-9a-f]+:[   ]+3485e257[      ]+vclmulh.vx[  ]+v4,v8,a1,v0.t

diff --git a/gas/testsuite/gas/riscv/zvksc.s b/gas/testsuite/gas/riscv/zvksc.s
new file mode 100644 (file)
index 0000000..aed6010
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksc.s
@@ -0,0 +1,10 @@
+       vsm4k.vi v4, v8, 0
+       vsm3c.vi v4, v8, 0
+       vclmul.vv v4, v8, v12
+       vclmul.vv v4, v8, v12, v0.t
+       vclmul.vx v4, v8, a1
+       vclmul.vx v4, v8, a1, v0.t
+       vclmulh.vv v4, v8, v12
+       vclmulh.vv v4, v8, v12, v0.t
+       vclmulh.vx v4, v8, a1
+       vclmulh.vx v4, v8, a1, v0.t