vendor.fpga.lattice_ice40: enable SystemVerilog when reading .sv files.

diff --git a/nmigen/vendor/fpga/lattice_ice40.py b/nmigen/vendor/fpga/lattice_ice40.py
index 9a8469c523e99e6595ecd45f84f10a107d06de2d..c80076d1c26ec8d70ea03518ceedeeda0e80f04d 100644 (file)
--- a/nmigen/vendor/fpga/lattice_ice40.py
+++ b/nmigen/vendor/fpga/lattice_ice40.py
@@ -51,7 +51,7 @@ class LatticeICE40Platform(TemplatedPlatform):
                 {% if file.endswith(".v") -%}
                     read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
                 {% elif file.endswith(".sv") -%}
-                    read_verilog {{get_override("read_opts")|join(" ")}} {{file}}
+                    read_verilog -sv {{get_override("read_opts")|join(" ")}} {{file}}
                 {% endif %}
             {% endfor %}
             read_ilang {{name}}.il