[AArch64] PR 61749: Do not ICE in lane intrinsics when passed non-constant lane number

	PR target/61749
	* config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
	Use qualifier_immediate for last operand.  Rename to...
	(aarch64_types_ternop_lane_qualifiers): ... This.
	(TYPES_QUADOP): Rename to...
	(TYPES_TERNOP_LANE): ... This.
	(aarch64_simd_expand_args): Return const0_rtx when encountering user
	error.  Change return of 0 to return of NULL_RTX.
	(aarch64_crc32_expand_builtin): Likewise.
	(aarch64_expand_builtin): Return NULL_RTX instead of 0.
	ICE when expanding unknown builtin.
	* config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use
	TERNOP_LANE qualifiers.
	(sqdmlsl_lane): Likewise.
	(sqdmlal_laneq): Likewise.
	(sqdmlsl_laneq): Likewise.
	(sqdmlal2_lane): Likewise.
	(sqdmlsl2_lane): Likewise.
	(sqdmlal2_laneq): Likewise.
	(sqdmlsl2_laneq): Likewise.

	* gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test.

From-SVN: r215046

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 724f164ed40430eecc77167f796bc8fd6b41d3ed..9a22220ee475c0044297a2d0482d189054369ba6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,26 @@
+2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/61749
+       * config/aarch64/aarch64-builtins.c (aarch64_types_quadop_qualifiers):
+       Use qualifier_immediate for last operand.  Rename to...
+       (aarch64_types_ternop_lane_qualifiers): ... This.
+       (TYPES_QUADOP): Rename to...
+       (TYPES_TERNOP_LANE): ... This.
+       (aarch64_simd_expand_args): Return const0_rtx when encountering user
+       error.  Change return of 0 to return of NULL_RTX.
+       (aarch64_crc32_expand_builtin): Likewise.
+       (aarch64_expand_builtin): Return NULL_RTX instead of 0.
+       ICE when expanding unknown builtin.
+       * config/aarch64/aarch64-simd-builtins.def (sqdmlal_lane): Use
+       TERNOP_LANE qualifiers.
+       (sqdmlsl_lane): Likewise.
+       (sqdmlal_laneq): Likewise.
+       (sqdmlsl_laneq): Likewise.
+       (sqdmlal2_lane): Likewise.
+       (sqdmlsl2_lane): Likewise.
+       (sqdmlal2_laneq): Likewise.
+       (sqdmlsl2_laneq): Likewise.
+
 2014-09-09  Nick Clifton  <nickc@redhat.com>
 
        * doc/invoke.texi (Optimization Options): Add missing @gol to the

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 6973df21cf1dac12d144f7ded74363497fca3a6f..0fc6ef491f2e55d57ef8452de77c29fafa3eaa83 100644 (file)
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -175,10 +175,10 @@ aarch64_types_ternopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
 #define TYPES_TERNOPU (aarch64_types_ternopu_qualifiers)
 
 static enum aarch64_type_qualifiers
-aarch64_types_quadop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
+aarch64_types_ternop_lane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
   = { qualifier_none, qualifier_none, qualifier_none,
-      qualifier_none, qualifier_none };
-#define TYPES_QUADOP (aarch64_types_quadop_qualifiers)
+      qualifier_none, qualifier_immediate };
+#define TYPES_TERNOP_LANE (aarch64_types_ternop_lane_qualifiers)
 
 static enum aarch64_type_qualifiers
 aarch64_types_getlane_qualifiers[SIMD_MAX_BUILTIN_ARGS]
@@ -901,8 +901,11 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
            case SIMD_ARG_CONSTANT:
              if (!(*insn_data[icode].operand[argc + have_retval].predicate)
                  (op[argc], mode[argc]))
+             {
                error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
                       "expected %<const int%>", argc + 1);
+               return const0_rtx;
+             }
              break;
 
            case SIMD_ARG_STOP:
@@ -967,7 +970,7 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval,
       }
 
   if (!pat)
-    return 0;
+    return NULL_RTX;
 
   emit_insn (pat);
 
@@ -1058,8 +1061,9 @@ aarch64_crc32_expand_builtin (int fcode, tree exp, rtx target)
     op1 = copy_to_mode_reg (mode1, op1);
 
   pat = GEN_FCN (icode) (target, op0, op1);
-  if (! pat)
-    return 0;
+  if (!pat)
+    return NULL_RTX;
+
   emit_insn (pat);
   return target;
 }
@@ -1111,7 +1115,7 @@ aarch64_expand_builtin (tree exp,
   else if (fcode >= AARCH64_CRC32_BUILTIN_BASE && fcode <= AARCH64_CRC32_BUILTIN_MAX)
     return aarch64_crc32_expand_builtin (fcode, exp, target);
 
-  return NULL_RTX;
+  gcc_unreachable ();
 }
 
 tree

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 67f05d93d90fac3ecd4101441fc7467335530c8f..e7b2df42da3c6296c08eafca6d9cbc3248b5b036 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -157,16 +157,16 @@
   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 
-  BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
-  BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_lane, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_lane, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlal_laneq, 0)
+  BUILTIN_VSD_HSI (TERNOP_LANE, sqdmlsl_laneq, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
-  BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_lane, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_lane, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlal2_laneq, 0)
+  BUILTIN_VQ_HSI (TERNOP_LANE, sqdmlsl2_laneq, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a53d96585921e53dd2113a77b9e4b414d973c3aa..81d4f311fdd3470f7f15f327aade6cd7d4da6f39 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-09-09  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/61749
+       * gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c: New test.
+
 2014-09-09  Zhenqiang Chen  <zhenqiang.chen@arm.com>
 
        * gcc.target/arm/split-live-ranges-for-shrink-wrap.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c b/gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
new file mode 100644 (file)
index 0000000..314a624
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/vqdml_lane_intrinsics-bad_1.c
@@ -0,0 +1,54 @@
+/* { dg-do compile } */
+
+#include "arm_neon.h"
+
+int32x4_t
+foo (int32x4_t a, int16x4_t b, int16x4_t c, int d)
+{
+  return vqdmlal_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo1 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
+{
+  return vqdmlal_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo2 (int32x4_t a, int16x4_t b, int16x4_t c, int d)
+{
+  return vqdmlsl_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo3 (int32x4_t a, int16x4_t b, int16x8_t c, int d)
+{
+  return vqdmlsl_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo4 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
+{
+  return vqdmlal_high_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo5 (int32x4_t a, int16x8_t b, int16x4_t c, int d)
+{
+  return vqdmlsl_high_lane_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo6 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
+{
+  return vqdmlal_high_laneq_s16 (a, b, c, d);
+}
+
+int32x4_t
+foo7 (int32x4_t a, int16x8_t b, int16x8_t c, int d)
+{
+  return vqdmlsl_high_laneq_s16 (a, b, c, d);
+}
+
+
+/* { dg-excess-errors "incompatible type for argument" } */