Document AMD btver2

From-SVN: r190151

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9292c7b651abdffef75443184941cab14af68048..e228bfb2c6dc29630e4b9fcd1668be2e831081e6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2012-08-05  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       * doc/invoke.texi: Document AMD btver2.
+       * doc/extend.texi: Document AMD btver1 and btver2.
+
 2012-08-04  Sandra Loosemore  <sandra@codesourcery.com>
            Richard Sandiford  <rdsandiford@googlemail.com>
 

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 5d851a7386b79feb658c5586f06cdee25a615cf2..615321fcf837e7edec7ecaaa30c43b1b1b9c6989 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -9560,6 +9560,9 @@ AMD family 10h Shanghai CPU.
 @item istanbul
 AMD family 10h Istanbul CPU.
 
+@item btver1
+AMD family 14h CPU.
+
 @item amdfam15h
 AMD family 15h CPU.
 
@@ -9568,6 +9571,9 @@ AMD family 15h Bulldozer version 1.
 
 @item bdver2
 AMD family 15h Bulldozer version 2.
+
+@item btver2
+AMD family 16h CPU.
 @end table
 
 Here is an example:

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 857fc4029a89807233bca5ce1cdb21e40dea8326..379761c59edd1fc90a87384979a0eb088cb1594e 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -13304,6 +13304,11 @@ CPUs based on AMD Family 14h cores with x86-64 instruction set support.  (This
 supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
 instruction set extensions.)
 
+@item btver2
+CPUs based on AMD Family 16h cores with x86-64 instruction set support. This
+includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM,
+SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
+
 @item winchip-c6
 IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction
 set support.