rename PLL pins to match LIP6.fr PLL

diff --git a/libresoc/core.py b/libresoc/core.py
index 01465117a03ae80f69d5e6fa7487a6193bdbbd0a..c305d021f26bfaaad1487856f6156bb2653fd28e 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -272,10 +272,10 @@ class LibreSoC(CPU):
         if "ls180" in variant and "pll" not in variant:
             self.pll_18_o = Signal()
             self.clk_sel = Signal(2)
-            self.pll_lck_o = Signal()
-            self.cpu_params['i_clk_sel_i'] = self.clk_sel
+            self.pll_ana_o = Signal()
+            self.cpu_params['i_clk__i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_pll_lck_o'] = self.pll_lck_o
+            self.cpu_params['o_vco_test_ana_o'] = self.pll_ana_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))

diff --git a/libresoc/ls180.py b/libresoc/ls180.py
index ab8fb33e7926136a10d684fb729f91f114bf3936..a03eef9a9408be3d876fa135b2dcebded0e5b41d 100644 (file)
--- a/libresoc/ls180.py
+++ b/libresoc/ls180.py
@@ -57,8 +57,8 @@ def io():
         ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2"), IOStandard("LVCMOS33")),
-        ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
-        ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_testout_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
+        ("sys_pll_vco_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
         # JTAG0: 4 pins
         ("jtag", 0,

diff --git a/ls180soc.py b/ls180soc.py
index acf2e58714ea9fe4b43e016b9af9b99ea3908851..d1d8dfef31f7a2ef36466c80c705d25cc45781ed 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -427,12 +427,12 @@ class LibreSoCSim(SoCCore):
         if hasattr(self.cpu, "clk_sel"):
             # PLL/Clock Select
             clksel_i = platform.request("sys_clksel_i")
-            pll18_o = platform.request("sys_pll_18_o")
-            pll_lck_o = platform.request("sys_pll_lck_o")
+            pll18_o = platform.request("sys_pll_testout_o")
+            pll_ana_o = platform.request("sys_pll_vco_o")
 
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
             self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL
-            self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag
+            self.comb += pll_ana_o.eq(self.cpu.pll_ana_o) # PLL lock flag
 
         #ram_init = []