re PR tree-optimization/68961 (Test case gcc.target/powerpc/pr60203.c fails since...

	PR rtl-optimization/68961
	* config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new
	peephole variant.  Use sse_reg_operand predicates.

From-SVN: r238268

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6cb8da203fafd278fad3a2f492077c7fca4be320..0b7518f24b1ef8e3e4e3a682293ec7b8720e550d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2016-07-13  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR rtl-optimization/68961
+       * config/i386/sse.md (movsd/movhpd to movupd peephole2s): Add new
+       peephole variant.  Use sse_reg_operand predicates.
+
 2016-07-12  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/predicates.md (x86_64_immediate_operand)
@@ -41,7 +47,7 @@
        loops.
 
 2016-07-12  Steven Bosscher  <steven@gcc.gnu.org>
-       Richard Biener  <rguenther@suse.de>
+           Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/23286
        PR tree-optimization/70159

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c1ea04ffca8aa04ec210d926d25b8d1d2c0f96ae..6b898dc05135a2406e8eea3151380011f836eb77 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1169,10 +1169,10 @@
 
 ;; Merge movsd/movhpd to movupd for TARGET_SSE_UNALIGNED_LOAD_OPTIMAL targets.
 (define_peephole2
-  [(set (match_operand:V2DF 0 "register_operand")
+  [(set (match_operand:V2DF 0 "sse_reg_operand")
        (vec_concat:V2DF (match_operand:DF 1 "memory_operand")
                         (match_operand:DF 4 "const0_operand")))
-   (set (match_operand:V2DF 2 "register_operand")
+   (set (match_operand:V2DF 2 "sse_reg_operand")
        (vec_concat:V2DF (vec_select:DF (match_dup 2)
                                        (parallel [(const_int 0)]))
                         (match_operand:DF 3 "memory_operand")))]
@@ -1181,13 +1181,25 @@
   [(set (match_dup 2) (match_dup 4))]
   "operands[4] = adjust_address (operands[1], V2DFmode, 0);")
 
+(define_peephole2
+  [(set (match_operand:DF 0 "sse_reg_operand")
+       (match_operand:DF 1 "memory_operand"))
+   (set (match_operand:V2DF 2 "sse_reg_operand")
+       (vec_concat:V2DF (match_operand:DF 4 "sse_reg_operand")
+                        (match_operand:DF 3 "memory_operand")))]
+  "TARGET_SSE2 && TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
+   && REGNO (operands[4]) == REGNO (operands[2])
+   && ix86_operands_ok_for_move_multiple (operands, true, DFmode)"
+  [(set (match_dup 2) (match_dup 4))]
+  "operands[4] = adjust_address (operands[1], V2DFmode, 0);")
+
 ;; Merge movlpd/movhpd to movupd for TARGET_SSE_UNALIGNED_STORE_OPTIMAL targets.
 (define_peephole2
   [(set (match_operand:DF 0 "memory_operand")
-       (vec_select:DF (match_operand:V2DF 1 "register_operand")
+       (vec_select:DF (match_operand:V2DF 1 "sse_reg_operand")
                       (parallel [(const_int 0)])))
    (set (match_operand:DF 2 "memory_operand")
-       (vec_select:DF (match_operand:V2DF 3 "register_operand")
+       (vec_select:DF (match_operand:V2DF 3 "sse_reg_operand")
                       (parallel [(const_int 1)])))]
   "TARGET_SSE2 && TARGET_SSE_UNALIGNED_STORE_OPTIMAL
    && ix86_operands_ok_for_move_multiple (operands, false, DFmode)"