Cleanup

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 31469ddeb30c8d4a24c303de6a2d4249ee94d58a..9da778ace978d063842eeb86e5675d53da94a6f6 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -97,25 +97,23 @@ module \$__mul_gen (A, B, Y);
 `else  \r
                        localparam sign_headroom = 0;\r
 `endif\r
-                       localparam n_floored = A_WIDTH/(`DSP_A_MAXWIDTH - sign_headroom);\r
-                       localparam n = n_floored + (n_floored*(`DSP_A_MAXWIDTH - sign_headroom) < A_WIDTH ? 1 : 0);\r
-                       wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];\r
+                       localparam n = (A_WIDTH + `DSP_A_MAXWIDTH - sign_headroom - 1)/(`DSP_A_MAXWIDTH - sign_headroom);\r
+                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);\r
+                       wire [partial_Y_WIDTH-1:0] partial [n-1:1];\r
                        wire [Y_WIDTH-1:0] partial_sum [n-2:0];\r
-                       localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);\r
 \r
                        \$__mul_gen #(\r
                                .A_SIGNED(0),\r
                                .B_SIGNED(B_SIGNED),\r
                                .A_WIDTH(`DSP_A_MAXWIDTH),\r
                                .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(int_yw)\r
+                               .Y_WIDTH(partial_Y_WIDTH)\r
                        ) mul_slice_first (\r
                                .A({{sign_headroom{1'b0}}, A[`DSP_A_MAXWIDTH-sign_headroom-1:0]}),\r
                                .B(B),\r
-                               .Y(partial_sum[0][int_yw-1:0])\r
+                               .Y(partial[0])\r
                        );\r
-                       if (Y_WIDTH > int_yw)\r
-                               assign partial_sum[0][Y_WIDTH-1:int_yw]=0;\r
+                       assign partial_sum[0] = partial[0];\r
 \r
                        for (i = 1; i < n-1; i=i+1) begin:slice\r
                                \$__mul_gen #(\r
@@ -123,18 +121,18 @@ module \$__mul_gen (A, B, Y);
                                        .B_SIGNED(B_SIGNED),\r
                                        .A_WIDTH(`DSP_A_MAXWIDTH),\r
                                        .B_WIDTH(B_WIDTH),\r
-                                       .Y_WIDTH(int_yw)\r
+                                       .Y_WIDTH(partial_Y_WIDTH)\r
                                ) mul_slice (\r
-                                       .A({{sign_headroom{1'b0}}, A[(i+1)*(`DSP_A_MAXWIDTH-sign_headroom)-1:i*(`DSP_A_MAXWIDTH-sign_headroom)]}),\r
+                                       .A({{sign_headroom{1'b0}}, A[i*(`DSP_A_MAXWIDTH-sign_headroom) +: `DSP_A_MAXWIDTH-sign_headroom]}),\r
                                        .B(B),\r
-                                       .Y(partial[i][int_yw-1:0])\r
+                                       .Y(partial[i])\r
                                );\r
-                               //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1];\r
-                               assign partial_sum[i] = {\r
-                                       partial[i][int_yw-1:0]\r
-                                       + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))],\r
-                                       partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0]\r
-                               };\r
+                               assign partial_sum[i] = (partial[i] << i*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[i-1];\r
+                               //assign partial_sum[i] = {\r
+                               //      partial[i][partial_Y_WIDTH-1:0]\r
+                               //      + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_A_MAXWIDTH-sign_headroom))],\r
+                               //      partial_sum[i-1][(i*(`DSP_A_MAXWIDTH-sign_headroom))-1:0]\r
+                               //};\r
                        end\r
 \r
                        \$__mul_gen #(\r
@@ -148,12 +146,12 @@ module \$__mul_gen (A, B, Y);
                                .B(B),\r
                                .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH)-1:0])\r
                        );\r
-                       //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2];\r
-                       assign Y = {\r
-                               partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0]\r
-                               + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))],\r
-                               partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0]\r
-                       };\r
+                       assign Y = (partial[n-1] << (n-1)*(`DSP_A_MAXWIDTH-sign_headroom)) + partial_sum[n-2];\r
+                       //assign Y = {\r
+                       //      partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*(`DSP_A_MAXWIDTH-sign_headroom)+B_WIDTH):0]\r
+                       //      + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))],\r
+                       //      partial_sum[n-2][((n-1)*(`DSP_A_MAXWIDTH-sign_headroom))-1:0]\r
+                       //};\r
                end\r
                else if (B_WIDTH > `DSP_B_MAXWIDTH) begin\r
 `ifdef DSP_B_SIGNEDONLY\r
@@ -161,25 +159,23 @@ module \$__mul_gen (A, B, Y);
 `else  \r
                        localparam sign_headroom = 0;\r
 `endif\r
-                       localparam n_floored = B_WIDTH/(`DSP_B_MAXWIDTH - sign_headroom);\r
-                       localparam n = n_floored + (n_floored*(`DSP_B_MAXWIDTH - sign_headroom) < B_WIDTH ? 1 : 0);\r
-                       wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1];\r
+                       localparam n = (B_WIDTH + `DSP_B_MAXWIDTH - sign_headroom - 1)/(`DSP_B_MAXWIDTH - sign_headroom);\r
+                       localparam partial_Y_WIDTH = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);\r
+                       wire [partial_Y_WIDTH-1:0] partial [n-1:1];\r
                        wire [Y_WIDTH-1:0] partial_sum [n-2:0];\r
-                       localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);\r
 \r
                        \$__mul_gen #(\r
                                .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(0),\r
                                .A_WIDTH(A_WIDTH),\r
                                .B_WIDTH(`DSP_B_MAXWIDTH),\r
-                               .Y_WIDTH(int_yw)\r
+                               .Y_WIDTH(partial_Y_WIDTH)\r
                        ) mul_first (\r
                                .A(A),\r
-                               .B({{sign_headroom{1'b0}}, B[(`DSP_B_MAXWIDTH - sign_headroom)-1:0]}),\r
-                               .Y(partial_sum[0][int_yw-1:0])\r
+                               .B({{sign_headroom{1'b0}}, B[`DSP_B_MAXWIDTH-sign_headroom-1:0]}),\r
+                               .Y(partial[0])\r
                        );\r
-                       if (Y_WIDTH > int_yw)\r
-                               assign partial_sum[0][Y_WIDTH-1:int_yw]=0;\r
+                       assign partial_sum[0] = partial[0];\r
 \r
                        for (i = 1; i < n-1; i=i+1) begin:slice\r
                                \$__mul_gen #(\r
@@ -187,23 +183,23 @@ module \$__mul_gen (A, B, Y);
                                        .B_SIGNED(0),\r
                                        .A_WIDTH(A_WIDTH),\r
                                        .B_WIDTH(`DSP_B_MAXWIDTH),\r
-                                       .Y_WIDTH(int_yw)\r
+                                       .Y_WIDTH(partial_Y_WIDTH)\r
                                ) mul (\r
                                        .A(A),\r
-                                       .B({{sign_headroom{1'b0}}, B[(i+1)*(`DSP_B_MAXWIDTH - sign_headroom)-1:i*(`DSP_B_MAXWIDTH - sign_headroom)]}),\r
-                                       .Y(partial[i][int_yw-1:0])\r
+                                       .B({{sign_headroom{1'b0}}, B[i*(`DSP_B_MAXWIDTH-sign_headroom) +: `DSP_B_MAXWIDTH-sign_headroom]}),\r
+                                       .Y(partial[i])\r
                                );\r
-                               //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1];\r
-                               // was:\r
+                               assign partial_sum[i] = (partial[i] <<< i*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[i-1];\r
+                               //// was:\r
+                               ////assign partial_sum[i] = {\r
+                               ////  partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], \r
+                               ////    partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],\r
+                               ////    partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]\r
                                //assign partial_sum[i] = {\r
-                               //  partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH], \r
-                               //      partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],\r
-                               //      partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]\r
-                               assign partial_sum[i] = {\r
-                                       partial[i][int_yw-1:0]\r
-                                       + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))],\r
-                                       partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] \r
-                               };\r
+                               //      partial[i][partial_Y_WIDTH-1:0]\r
+                               //      + partial_sum[i-1][Y_WIDTH-1:(i*(`DSP_B_MAXWIDTH - sign_headroom))],\r
+                               //      partial_sum[i-1][(i*(`DSP_B_MAXWIDTH - sign_headroom))-1:0] \r
+                               //};\r
                        end\r
 \r
                        \$__mul_gen #(\r
@@ -217,36 +213,28 @@ module \$__mul_gen (A, B, Y);
                                .B(B[B_WIDTH-1:(n-1)*(`DSP_B_MAXWIDTH - sign_headroom)]),\r
                                .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0])\r
                        );\r
-                       // AMD: this came comment out -- looks closer to right answer\r
-                       //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2];\r
-                       // was (looks broken)\r
+                       assign Y = (partial[n-1] << (n-1)*(`DSP_B_MAXWIDTH - sign_headroom)) + partial_sum[n-2];\r
+                       //// was (looks broken)\r
+                       ////assign Y = {\r
+                       ////    partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],\r
+                       ////    partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],\r
+                       ////    partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]\r
                        //assign Y = {\r
-                       //      partial[n-1][A_WIDTH+`DSP_B_MAXWIDTH-1:`DSP_B_MAXWIDTH],\r
-                       //      partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],\r
-                       //      partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]\r
-                       assign Y = {\r
-                               partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]\r
-                               + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))],\r
-                               partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]\r
-                       };\r
+                       //      partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]\r
+                       //      + partial_sum[n-2][Y_WIDTH-1:((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))],\r
+                       //      partial_sum[n-2][((n-1)*(`DSP_B_MAXWIDTH - sign_headroom))-1:0]\r
+                       //};\r
                end\r
                else begin \r
-                       wire [A_WIDTH+B_WIDTH-1:0] out;\r
-                       wire [(`DSP_A_MAXWIDTH+`DSP_B_MAXWIDTH)-(A_WIDTH+B_WIDTH)-1:0] dummy;\r
-                       wire Asign, Bsign;\r
-                       assign Asign = (A_SIGNED ? A[A_WIDTH-1] : 1'b0);\r
-                       assign Bsign = (B_SIGNED ? B[B_WIDTH-1] : 1'b0);\r
+                       (* keep *) wire [Y_WIDTH-1:0] Yunsigned;\r
+                       wire signed [`DSP_A_MAXWIDTH-1:0] Asigned = $signed(A);\r
+                       wire signed [`DSP_A_MAXWIDTH-1:0] Bsigned = $signed(B);\r
                        `DSP_NAME _TECHMAP_REPLACE_ (\r
-                               .A({ {{`DSP_A_MAXWIDTH-A_WIDTH}{Asign}}, A }),\r
-                               .B({ {{`DSP_B_MAXWIDTH-B_WIDTH}{Bsign}}, B }),\r
-                               .Y({dummy, out})\r
+                               .A(Asigned),\r
+                               .B(Bsigned),\r
+                               .Y(Yunsigned)\r
                        );\r
-                       if (Y_WIDTH < A_WIDTH+B_WIDTH)\r
-                               assign Y = out[Y_WIDTH-1:0];\r
-                       else begin\r
-                               wire Ysign = (A_SIGNED || B_SIGNED ? out[A_WIDTH+B_WIDTH-1] : 1'b0);\r
-                               assign Y = { {{Y_WIDTH-(A_WIDTH+B_WIDTH)}{Ysign}}, out[A_WIDTH+B_WIDTH-1:0] };\r
-                       end\r
+                       assign Y = $signed(Yunsigned[A_WIDTH+B_WIDTH-1:0]);\r
                end\r
        endgenerate\r
 endmodule\r