---------- Begin Simulation Statistics ----------
-sim_seconds 47.397611 # Number of seconds simulated
-sim_ticks 47397610926500 # Number of ticks simulated
-final_tick 47397610926500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.443139 # Number of seconds simulated
+sim_ticks 47443139283500 # Number of ticks simulated
+final_tick 47443139283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 110253 # Simulator instruction rate (inst/s)
-host_op_rate 129665 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5829907242 # Simulator tick rate (ticks/s)
-host_mem_usage 703216 # Number of bytes of host memory used
-host_seconds 8130.08 # Real time elapsed on the host
-sim_insts 896366789 # Number of instructions simulated
-sim_ops 1054186264 # Number of ops (including micro ops) simulated
+host_inst_rate 174986 # Simulator instruction rate (inst/s)
+host_op_rate 205797 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9320406551 # Simulator tick rate (ticks/s)
+host_mem_usage 765676 # Number of bytes of host memory used
+host_seconds 5090.24 # Real time elapsed on the host
+sim_insts 890723033 # Number of instructions simulated
+sim_ops 1047557701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 107072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 78336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 7782464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 12802520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 15762560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 159744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 154688 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3994240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12481056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 14503040 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 448448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 68274168 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 7782464 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3994240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11776704 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 79542656 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 111744 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 7668224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 13156952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 13340800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 149248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 146240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3865344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 11856672 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 13765376 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 430976 # Number of bytes read from this memory
+system.physmem.bytes_read::total 64583224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 7668224 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3865344 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11533568 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 75782720 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 79563472 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1673 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1224 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 121601 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 200061 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 246290 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2496 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2417 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 62410 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 195031 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 226610 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 7007 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1066820 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1242854 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 75803536 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1746 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 119816 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 205599 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 208450 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2332 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2285 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 60396 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 185275 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 215084 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6734 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1009149 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1184105 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1245457 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2259 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 164195 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 270109 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 332560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 3370 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 3264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 84271 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 263327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 305987 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 9461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1440456 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 164195 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 84271 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 248466 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1678200 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1186708 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2355 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 1932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 161630 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 277320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 281196 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 3082 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 81473 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 249913 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 290145 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9084 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1361276 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 161630 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 81473 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 243103 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1597338 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1678639 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1678200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 2259 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1653 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 164195 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 270548 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 332560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 3370 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 3264 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 84271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 263327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 305987 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 9461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3119095 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1066820 # Number of read requests accepted
-system.physmem.writeReqs 1912174 # Number of write requests accepted
-system.physmem.readBursts 1066820 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1912174 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 68253568 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 22912 # Total number of bytes read from write queue
-system.physmem.bytesWritten 119234048 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 68274168 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 122233360 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 358 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 49121 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 113360 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 61922 # Per bank write bursts
-system.physmem.perBankRdBursts::1 70972 # Per bank write bursts
-system.physmem.perBankRdBursts::2 57667 # Per bank write bursts
-system.physmem.perBankRdBursts::3 64982 # Per bank write bursts
-system.physmem.perBankRdBursts::4 65050 # Per bank write bursts
-system.physmem.perBankRdBursts::5 70572 # Per bank write bursts
-system.physmem.perBankRdBursts::6 72322 # Per bank write bursts
-system.physmem.perBankRdBursts::7 67337 # Per bank write bursts
-system.physmem.perBankRdBursts::8 57787 # Per bank write bursts
-system.physmem.perBankRdBursts::9 110760 # Per bank write bursts
-system.physmem.perBankRdBursts::10 57283 # Per bank write bursts
-system.physmem.perBankRdBursts::11 63297 # Per bank write bursts
-system.physmem.perBankRdBursts::12 60054 # Per bank write bursts
-system.physmem.perBankRdBursts::13 63124 # Per bank write bursts
-system.physmem.perBankRdBursts::14 62259 # Per bank write bursts
-system.physmem.perBankRdBursts::15 61074 # Per bank write bursts
-system.physmem.perBankWrBursts::0 110998 # Per bank write bursts
-system.physmem.perBankWrBursts::1 120192 # Per bank write bursts
-system.physmem.perBankWrBursts::2 114368 # Per bank write bursts
-system.physmem.perBankWrBursts::3 118573 # Per bank write bursts
-system.physmem.perBankWrBursts::4 116138 # Per bank write bursts
-system.physmem.perBankWrBursts::5 119482 # Per bank write bursts
-system.physmem.perBankWrBursts::6 124701 # Per bank write bursts
-system.physmem.perBankWrBursts::7 122822 # Per bank write bursts
-system.physmem.perBankWrBursts::8 112747 # Per bank write bursts
-system.physmem.perBankWrBursts::9 113706 # Per bank write bursts
-system.physmem.perBankWrBursts::10 111725 # Per bank write bursts
-system.physmem.perBankWrBursts::11 114999 # Per bank write bursts
-system.physmem.perBankWrBursts::12 115986 # Per bank write bursts
-system.physmem.perBankWrBursts::13 114347 # Per bank write bursts
-system.physmem.perBankWrBursts::14 116931 # Per bank write bursts
-system.physmem.perBankWrBursts::15 115317 # Per bank write bursts
+system.physmem.bw_write::total 1597777 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1597338 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2355 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1932 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 161630 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 277759 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 281196 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 3082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 81473 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 249913 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::realview.ide 9084 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2959053 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1009149 # Number of read requests accepted
+system.physmem.writeReqs 1850399 # Number of write requests accepted
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+system.physmem.writeBursts 1850399 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 64564224 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue
+system.physmem.bytesWritten 115242304 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 64583224 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 118279760 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 49721 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 115106 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 57845 # Per bank write bursts
+system.physmem.perBankRdBursts::1 61929 # Per bank write bursts
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+system.physmem.perBankRdBursts::13 64090 # Per bank write bursts
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+system.physmem.perBankWrBursts::8 110047 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 110504 # Per bank write bursts
+system.physmem.perBankWrBursts::15 115893 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 309 # Number of times write queue was full causing retry
-system.physmem.totGap 47397609004000 # Total gap between requests
+system.physmem.numWrRetry 251 # Number of times write queue was full causing retry
+system.physmem.totGap 47443137361000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1066778 # Read request sizes (log2)
+system.physmem.readPktSize::6 1009107 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1909571 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 706521 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 126151 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 49462 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::16 346 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19 82 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1847796 # Write request sizes (log2)
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 176.818458 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::640-767 11998 1.13% 93.15% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 56177 5.30% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1060336 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 12.888404 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 137.186201 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 22.515342 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev 20.554947 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 82745 # Writes before turning the bus around for reads
-system.physmem.totQLat 40375015102 # Total ticks spent queuing
-system.physmem.totMemAccLat 60371177602 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5332310000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 37858.84 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::total 78960 # Writes before turning the bus around for reads
+system.physmem.totQLat 36416381887 # Total ticks spent queuing
+system.physmem.totMemAccLat 55331681887 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5044080000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 36098.14 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 56608.84 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.44 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.52 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 54848.14 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.36 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.49 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.99 # Average write queue length when enqueuing
-system.physmem.readRowHits 803348 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1065807 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.21 # Row buffer hit rate for writes
-system.physmem.avgGap 15910609.09 # Average gap between requests
-system.physmem.pageHitRate 63.80 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 4142388600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2260231875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4140419400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 6138335520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1201204741230 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27384875125500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31698542432445 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.779401 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45556660870724 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1582710220000 # Time in different power states
+system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
+system.physmem.readRowHits 756126 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1035585 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.95 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 57.51 # Row buffer hit rate for writes
+system.physmem.avgGap 16591131.66 # Average gap between requests
+system.physmem.pageHitRate 63.77 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3944550960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2152284750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3829511400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5947512480 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1192681206900 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27419667632250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31726977439380 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.736993 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45614623336779 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1584230440000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 258234748026 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 244280410221 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3873751560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2113654125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4177906200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5934111840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3095781190320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1188231262785 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27396255369750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31696367246580 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.733509 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45575630122499 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1582710220000 # Time in different power states
+system.physmem_1.actEnergy 3749639040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2045934000 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4039144200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5720654160 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1188668792790 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27423187293750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31726166198580 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.719894 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45620445429017 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1584230440000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 239268979001 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 238458431983 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 133516333 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 94941201 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6028887 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 100948341 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 73074204 # Number of BTB hits
+system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 130059643 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 92054393 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 5970282 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 98035548 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 70777475 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.387722 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 15498997 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1074405 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 72.195725 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 15296635 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1065115 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 274493 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 274493 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8574 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 74935 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 274493 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 274493 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 274493 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 83509 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 18665.041972 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 16952.057368 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 12810.377808 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 82824 99.18% 99.18% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 578 0.69% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 32 0.04% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 36 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 268213 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 268213 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8180 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73055 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 268213 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 268213 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 268213 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 81235 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 80487 99.08% 99.08% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 639 0.79% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 31 0.04% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 83509 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 81235 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 74935 89.73% 89.73% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8574 10.27% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 83509 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 274493 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 73055 89.93% 89.93% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8180 10.07% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 81235 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 268213 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 274493 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 83509 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 268213 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81235 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 83509 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 358002 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81235 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 349448 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 84777209 # DTB read hits
-system.cpu0.dtb.read_misses 227212 # DTB read misses
-system.cpu0.dtb.write_hits 75760151 # DTB write hits
-system.cpu0.dtb.write_misses 47281 # DTB write misses
+system.cpu0.dtb.read_hits 82876233 # DTB read hits
+system.cpu0.dtb.read_misses 221834 # DTB read misses
+system.cpu0.dtb.write_hits 73950839 # DTB write hits
+system.cpu0.dtb.write_misses 46379 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 33980 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2153 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9225 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 33850 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2174 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9634 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 11068 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 85004421 # DTB read accesses
-system.cpu0.dtb.write_accesses 75807432 # DTB write accesses
+system.cpu0.dtb.perms_faults 10897 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 83098067 # DTB read accesses
+system.cpu0.dtb.write_accesses 73997218 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 160537360 # DTB hits
-system.cpu0.dtb.misses 274493 # DTB misses
-system.cpu0.dtb.accesses 160811853 # DTB accesses
+system.cpu0.dtb.hits 156827072 # DTB hits
+system.cpu0.dtb.misses 268213 # DTB misses
+system.cpu0.dtb.accesses 157095285 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 61212 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 61212 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 587 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52411 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 61212 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 61212 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 61212 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 52998 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21062.649289 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19099.820516 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 14417.313367 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 48615 91.73% 91.73% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 3682 6.95% 98.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 228 0.43% 99.11% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 379 0.72% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 9 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 59559 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 59559 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 562 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52025 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 59559 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 59559 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 59559 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 52587 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 47969 91.22% 91.22% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 3703 7.04% 98.26% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 280 0.53% 98.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 523 0.99% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 24 0.05% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 24 0.05% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 16 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 52998 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 52587 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 52411 98.89% 98.89% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 587 1.11% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 52998 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 52025 98.93% 98.93% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 562 1.07% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 52587 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61212 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61212 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59559 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59559 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52998 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52998 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 114210 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 238748421 # ITB inst hits
-system.cpu0.itb.inst_misses 61212 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52587 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52587 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 112146 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 232580630 # ITB inst hits
+system.cpu0.itb.inst_misses 59559 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 24001 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
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system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 196095 # Number of TLB faults due to permissions restrictions
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system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
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-system.cpu0.itb.misses 61212 # DTB misses
-system.cpu0.itb.accesses 238809633 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu0.numFetchSuspends 3855 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93846100118 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.159943 # CPI: cycles per instruction
-system.cpu0.ipc 0.462975 # IPC: instructions per cycle
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.dcache.tags.avg_refs 27.564634 # Average number of references to valid blocks.
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system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 16862.469903 # average overall miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::total 15084.107904 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 3800112 # number of writebacks
-system.cpu0.dcache.writebacks::total 3800112 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429398 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 429398 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1005493 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1005493 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 83 # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 83 # number of WriteInvalidateReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41403 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41403 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 51 # number of StoreCondReq MSHR hits
-system.cpu0.dcache.StoreCondReq_mshr_hits::total 51 # number of StoreCondReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1434891 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1434891 # number of demand (read+write) MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 1434891 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2897775 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 2897775 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1380774 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1380774 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 667964 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 667964 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 787957 # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 787957 # number of WriteInvalidateReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 107548 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 107548 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180515 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 180515 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 4278549 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 4278549 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 4946513 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 4946513 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37570974686 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37570974686 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24854865946 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24854865946 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14971801156 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14971801156 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31379224673 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31379224673 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1379388880 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1379388880 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3557992992 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3557992992 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2840500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 62425840632 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 62425840632 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77397641788 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 77397641788 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5923264746 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5923264746 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5701581250 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5701581250 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11624845996 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11624845996 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035801 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035801 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019051 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019051 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.709253 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.709253 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759304 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759304 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057196 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057196 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.096064 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.096064 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027888 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.027888 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032045 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032045 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12965.456147 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12965.456147 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18000.676393 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18000.676393 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22414.083927 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22414.083927 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39823.524219 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39823.524219 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12825.797597 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12825.797597 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19710.234562 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19710.234562 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 3714069 # number of writebacks
+system.cpu0.dcache.writebacks::total 3714069 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 414551 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 414551 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total 973091 # number of WriteReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40213 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.demand_mshr_hits::total 1387642 # number of demand (read+write) MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 1387642 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 2839979 # number of ReadReq MSHR misses
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+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 635024 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 635024 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 788383 # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 788383 # number of WriteInvalidateReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104432 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104432 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180642 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 180642 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 4817696 # number of overall MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37224821633 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14430000107 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31505168022 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31505168022 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1352929391 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1352929391 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3566593771 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3566593771 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3248500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3248500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61545107041 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 61545107041 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75975107148 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 75975107148 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918601247 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5918601247 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692373000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692373000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11610974247 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11610974247 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035888 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035888 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018986 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018986 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.699879 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.699879 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759908 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759908 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057067 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057067 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098769 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098769 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027911 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.027911 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031956 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.031956 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14590.423209 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14590.423209 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15646.909608 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15646.909608 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 9444901 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.930140 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 229100961 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 9445413 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 24.255261 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 9298569 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.930207 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 223083541 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 9299081 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 23.989848 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930140 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930207 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36349246072 # number of overall MSHR miss cycles
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system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5656823753 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10047894503 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452375000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5452375000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5652021253 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10043092003 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443565000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443565000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11109198753 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15500269503 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266241 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.127536 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11095586253 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15486657003 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264207 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126293 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741477 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741477 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.538902 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.538902 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817105 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817105 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741100 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741100 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548089 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548089 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823139 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823139 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224862 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224862 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.135114 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023759 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052115 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080130 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256301 # mshr miss rate for overall accesses
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+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for demand accesses
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+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.184057 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26709.503385 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25473.948849 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 52502.734204 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43489.607650 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43489.607650 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20266.143903 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20266.143903 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.483112 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.483112 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1165000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1165000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39938.078665 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39938.078665 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27348.089069 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27882.175477 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 28758.784845 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23806.415194 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29497.482424 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 52502.734204 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34037.079428 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181983 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 907166 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 907166 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 16517621 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 14068332 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 33225 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 33225 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3800110 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1086057 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1148168 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786224 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 477409 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332434 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 482483 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1303516 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1171227 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18995457 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16182353 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 335795 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1061304 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 36574909 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 607854592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 610383865 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1223600 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3866424 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1223328481 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4849156 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 24579773 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.184734 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.388082 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 16236238 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 13810704 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 33172 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33172 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3714064 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1025800 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1145042 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786829 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 475552 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336189 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 478151 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1267323 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1138296 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18702794 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15835764 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326673 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1038123 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 35903354 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 598489344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 596885449 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3791640 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1200356609 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 4763261 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 24114639 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 3.184867 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.388190 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 20039056 81.53% 81.53% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 4540717 18.47% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 19656632 81.51% 81.51% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 4458007 18.49% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 24579773 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 14682015163 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 24114639 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 14405309409 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 205334987 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 207723992 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 14272912820 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 14053020534 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7968080178 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7776245419 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 183071466 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 178137962 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 578323929 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 564500428 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 139172899 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 99233401 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6252869 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 105205307 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 76618629 # Number of BTB hits
+system.cpu1.branchPred.lookups 140284857 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 99939687 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6358953 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 105820632 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 77032296 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.827722 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16237430 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 1026400 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 72.795158 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16359380 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 1035022 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 295412 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 295412 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11437 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91734 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 295412 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 295412 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 295412 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 103171 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19450.829041 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17494.566732 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15964.350233 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 101752 98.62% 98.62% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1198 1.16% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 80 0.08% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 103171 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 298079 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 298079 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11270 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91179 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 298079 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 298079 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 298079 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 102449 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 101103 98.69% 98.69% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1144 1.12% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 102449 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 91734 88.91% 88.91% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 11437 11.09% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 103171 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 295412 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 91179 89.00% 89.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 11270 11.00% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 102449 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298079 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 295412 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 103171 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298079 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102449 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 103171 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 398583 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102449 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 400528 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 90130445 # DTB read hits
-system.cpu1.dtb.read_misses 246227 # DTB read misses
-system.cpu1.dtb.write_hits 78064785 # DTB write hits
-system.cpu1.dtb.write_misses 49185 # DTB write misses
+system.cpu1.dtb.read_hits 91176680 # DTB read hits
+system.cpu1.dtb.read_misses 248433 # DTB read misses
+system.cpu1.dtb.write_hits 79002879 # DTB write hits
+system.cpu1.dtb.write_misses 49646 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 41873 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 864 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 7939 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 41482 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 884 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7879 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11435 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 90376672 # DTB read accesses
-system.cpu1.dtb.write_accesses 78113970 # DTB write accesses
+system.cpu1.dtb.perms_faults 11586 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 91425113 # DTB read accesses
+system.cpu1.dtb.write_accesses 79052525 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 168195230 # DTB hits
-system.cpu1.dtb.misses 295412 # DTB misses
-system.cpu1.dtb.accesses 168490642 # DTB accesses
+system.cpu1.dtb.hits 170179559 # DTB hits
+system.cpu1.dtb.misses 298079 # DTB misses
+system.cpu1.dtb.accesses 170477638 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 68039 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 68039 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 556 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57997 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 68039 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 68039 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 68039 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 58553 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 22020.763957 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19263.180418 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18942.782929 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 56928 97.22% 97.22% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 1459 2.49% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 45 0.08% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 89 0.15% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 58553 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 68407 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 68407 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 609 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58709 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 68407 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 68407 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 68407 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 59318 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 54668 92.16% 92.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 3100 5.23% 97.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 594 1.00% 98.39% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 801 1.35% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.05% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.02% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.10% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 59318 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 57997 99.05% 99.05% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 556 0.95% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 58553 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 58709 98.97% 98.97% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 609 1.03% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 59318 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68039 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68039 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68407 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68407 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58553 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58553 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 126592 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 249268487 # ITB inst hits
-system.cpu1.itb.inst_misses 68039 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59318 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59318 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 127725 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 251160195 # ITB inst hits
+system.cpu1.itb.inst_misses 68407 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 42378 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1052 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 30522 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 30244 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 226060 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 224879 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 249336526 # ITB inst accesses
-system.cpu1.itb.hits 249268487 # DTB hits
-system.cpu1.itb.misses 68039 # DTB misses
-system.cpu1.itb.accesses 249336526 # DTB accesses
-system.cpu1.numCycles 932637373 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 251228602 # ITB inst accesses
+system.cpu1.itb.hits 251160195 # DTB hits
+system.cpu1.itb.misses 68407 # DTB misses
+system.cpu1.itb.accesses 251228602 # DTB accesses
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu1.discardedOps 48077866 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 5781 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93863478723 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.042360 # CPI: cycles per instruction
-system.cpu1.ipc 0.489630 # IPC: instructions per cycle
+system.cpu1.committedInsts 461578271 # Number of instructions committed
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+system.cpu1.numFetchSuspends 5811 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 93949323576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.031848 # CPI: cycles per instruction
+system.cpu1.ipc 0.492163 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5811 # number of quiesce instructions executed
-system.cpu1.tickCycles 738281563 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 194355810 # Total number of cycles that the object has spent stopped
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-system.cpu1.dcache.tags.tagsinuse 462.121005 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 159889231 # Total number of references to valid blocks.
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-system.cpu1.dcache.tags.avg_refs 29.046006 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 5892 # number of quiesce instructions executed
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+system.cpu1.dcache.tags.tagsinuse 462.401458 # Cycle average of tags in use
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+system.cpu1.dcache.tags.avg_refs 29.422287 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
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system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu1.dcache.SoftPFReq_hits::total 234096 # number of SoftPFReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 1835233 # number of StoreCondReq hits
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-system.cpu1.dcache.ReadReq_misses::total 3601145 # number of ReadReq misses
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-system.cpu1.dcache.WriteInvalidateReq_misses::total 453115 # number of WriteInvalidateReq misses
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20661.064859 # average StoreCondReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3506045 # number of writebacks
-system.cpu1.dcache.writebacks::total 3506045 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 409825 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 409825 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 940543 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 940543 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 72 # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 72 # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45181 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45181 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1350368 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1350368 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1350368 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1350368 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3191320 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3191320 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1360095 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1360095 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 661949 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 661949 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 453043 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 453043 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 140893 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 140893 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193713 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 193713 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4551415 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4551415 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5213364 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5213364 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42631813644 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42631813644 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22019784779 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22019784779 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605448576 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605448576 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12141090903 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12141090903 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1806083972 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1806083972 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3702335044 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3702335044 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2795500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2795500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64651598423 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 64651598423 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78257046999 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 78257046999 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 498907500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 498907500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 556628501 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 556628501 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1055536001 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1055536001 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037045 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037045 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018091 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018091 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.738495 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.738495 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.857138 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.857138 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069391 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069391 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095472 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095472 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028212 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028212 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032137 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032137 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.677176 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.677176 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16189.887309 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16189.887309 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20553.620560 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20553.620560 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26798.981340 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26798.981340 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12818.833952 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12818.833952 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19112.475900 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19112.475900 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 3514313 # number of writebacks
+system.cpu1.dcache.writebacks::total 3514313 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 402319 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 402319 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 938195 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 938195 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 62 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 62 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44601 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44601 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 41 # number of StoreCondReq MSHR hits
+system.cpu1.dcache.StoreCondReq_mshr_hits::total 41 # number of StoreCondReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1340514 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1340514 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1340514 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1340514 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3190099 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 3190099 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1353133 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 1353133 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 658162 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 658162 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 456894 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 456894 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141121 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141121 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195959 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 195959 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 4543232 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 4543232 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 5201394 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 5201394 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41952700254 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41952700254 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21819340170 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21819340170 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13178817169 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13178817169 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11885329605 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11885329605 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1778237950 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1778237950 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3771476218 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3771476218 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2255500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2255500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63772040424 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 63772040424 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76950857593 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 76950857593 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 517375000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 517375000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 587265498 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 587265498 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1104640498 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1104640498 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036585 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036585 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017778 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017778 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.737066 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.737066 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.858147 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.858147 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069518 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069518 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096605 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096605 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027820 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031677 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.031677 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14204.724997 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14204.724997 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15010.854220 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15010.854220 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 9392574 # number of replacements
-system.cpu1.icache.tags.tagsinuse 507.206734 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 239643264 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 9393086 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 25.512730 # Average number of references to valid blocks.
+system.cpu1.icache.tags.replacements 9531492 # number of replacements
+system.cpu1.icache.tags.tagsinuse 507.211334 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 241397065 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 9532004 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 25.324902 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.206734 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990638 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.990638 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.211334 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990647 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.990647 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 507465788 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 507465788 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 239643264 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 239643264 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 239643264 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 239643264 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 239643264 # number of overall hits
-system.cpu1.icache.overall_hits::total 239643264 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 9393087 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 9393087 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 9393087 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 9393087 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 9393087 # number of overall misses
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 976472 # number of prefetches not generated due to page crossing
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-system.cpu1.l2cache.tags.warmup_cycle 9806300117000 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 4972.841269 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.331762 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.569688 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4463.050805 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3225.843213 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14638 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 684 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 569 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2664 # Occupied blocks per task id
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-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 519410999 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 476808000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 484168000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 548574002 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 548574002 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7360000 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 978573999 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 985933999 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.261514 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133003 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1025382002 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1032742002 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256780 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.131022 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.582696 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.582696 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.656981 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.656981 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784553 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784553 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.570813 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.570813 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.667138 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.667138 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794030 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.794030 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207555 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207555 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138603 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024052 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053808 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.086174 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249486 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207860 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207860 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136733 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186252 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26660.088082 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25037.672304 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46384.470766 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32812.266011 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32812.266011 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19486.318153 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19486.318153 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14796.710109 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14796.710109 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 261333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 261333.333333 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33792.425824 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33792.425824 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26022.436146 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.415711 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36658.953499 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22722.421260 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27982.771658 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46384.470766 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31231.631271 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183418 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26115.946165 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32101.818529 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14787.980462 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 235874.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33359.452778 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25567.068002 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 16687989 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 14334572 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 4962 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 4962 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3506045 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 1053826 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1133141 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 451918 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 452249 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 341136 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 469204 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1304040 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1151075 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18786353 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15676887 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 371904 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1206650 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 36041794 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 601163264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587975003 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1349240 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4407712 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1194895219 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5002181 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 24473447 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.192626 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.394362 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 16743915 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 14472665 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 5158 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5158 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3514312 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1035959 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1137929 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 455738 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 448749 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344575 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 466415 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1299611 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1147815 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 19064189 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15671741 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370835 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1205745 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 36312510 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610054016 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588145619 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1332264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4367048 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1203898947 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4911557 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 24519969 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 3.188170 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.390848 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 19759234 80.74% 80.74% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 4714213 19.26% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 19906035 81.18% 81.18% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 4613934 18.82% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 24473447 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 13845201909 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 24519969 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 13930930666 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 163397980 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 160378480 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 14102728136 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 14310919255 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8209870082 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8198844119 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 203661942 # Layer occupancy (ticks)
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system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
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-system.iocache.demand_avg_mshr_miss_latency::realview.ide 134635.287145 # average overall mshr miss latency
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+system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency
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-system.l2c.ReadReq_mshr_miss_rate::total 0.212817 # mshr miss rate for ReadReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.765143 # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.484776 # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.678929 # mshr miss rate for WriteInvalidateReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.600521 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586709 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.593738 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.596623 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.586703 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591741 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.575848 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.512878 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.547492 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.231370 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.196315 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.203255 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091569 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.238947 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.454261 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.265278 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.368333 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077021 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.232334 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.420072 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.231370 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80848.279354 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77016.382199 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 99617.771443 # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33583.928144 # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32063.710201 # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33250.137211 # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17840.886677 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17796.886334 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17819.536552 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17860.137471 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.412203 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17840.755008 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77480.654562 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72287.514629 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75289.979524 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79438.272564 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80712.196078 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71996.654931 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79571.498531 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123809.973523 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76234.872997 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75817.128672 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71919.235275 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75673.036756 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 114625.422288 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 96426.453406 # average overall mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 829870000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 13853800000 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191218 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184765 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.204495 # mshr miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770297 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464517 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677367 # mshr miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.607754 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.616874 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.612228 # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.591376 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.598113 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590095 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517982 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.557864 # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.224210 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.224210 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80558.829037 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76617.147137 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 97889.611530 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33579.020650 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32048.054457 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33259.945559 # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.885507 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17791.659815 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17804.923446 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17847.137919 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17802.416206 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17824.861169 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76873.835674 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71448.956603 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 74622.497967 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 979077 # Transaction distribution
-system.membus.trans_dist::ReadResp 979077 # Transaction distribution
-system.membus.trans_dist::WriteReq 38187 # Transaction distribution
-system.membus.trans_dist::WriteResp 38187 # Transaction distribution
-system.membus.trans_dist::Writeback 1242854 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 666717 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 666717 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 428866 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 287024 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 113399 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
-system.membus.trans_dist::ReadExReq 145453 # Transaction distribution
-system.membus.trans_dist::ReadExResp 128623 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122530 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 921958 # Transaction distribution
+system.membus.trans_dist::ReadResp 921958 # Transaction distribution
+system.membus.trans_dist::WriteReq 38330 # Transaction distribution
+system.membus.trans_dist::WriteResp 38330 # Transaction distribution
+system.membus.trans_dist::Writeback 1184105 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 663691 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 663691 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 435500 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 292205 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 115129 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
+system.membus.trans_dist::ReadExReq 144960 # Transaction distribution
+system.membus.trans_dist::ReadExResp 128452 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122846 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5227832 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5375480 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336065 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 336065 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5711545 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25278 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5060662 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5208838 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336578 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 336578 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5545416 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155884 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50132 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176401096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 176608212 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14106432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14106432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 190714644 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 622043 # Total snoops (count)
-system.membus.snoop_fanout::samples 3659684 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50556 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168740232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 168947996 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14122752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14122752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 183070748 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 632037 # Total snoops (count)
+system.membus.snoop_fanout::samples 3551920 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3659684 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3551920 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3659684 # Request fanout histogram
-system.membus.reqLayer0.occupancy 109555497 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3551920 # Request fanout histogram
+system.membus.reqLayer0.occupancy 109974000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20982498 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21181500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 11300972211 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 10917620106 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6484776493 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6186347625 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151978377 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 152234718 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 5072106 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 5064869 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38187 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38187 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2487202 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 936242 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 829317 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 482057 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 299353 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 781410 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 127 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 127 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 300573 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 300573 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8029813 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6984147 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15013960 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269549433 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 226408539 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 495957972 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1618057 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9487188 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012211 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.109827 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 4966231 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4959010 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38330 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38330 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2396374 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 933256 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 826108 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 485771 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 304174 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 789945 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 295867 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 295867 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7796872 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899953 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 14696825 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260005833 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222466259 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 482472092 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1634381 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9291173 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012493 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.111071 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9371339 98.78% 98.78% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115849 1.22% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9175099 98.75% 98.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 116074 1.25% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9487188 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8381122122 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 9291173 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8184497542 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2527500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2554500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4575963989 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4445775595 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4435446795 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4394903352 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 1962612686500 # Number of ticks simulated
final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1121045 # Simulator instruction rate (inst/s)
-host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36128483856 # Simulator tick rate (ticks/s)
-host_mem_usage 373592 # Number of bytes of host memory used
-host_seconds 54.32 # Real time elapsed on the host
+host_inst_rate 1051716 # Simulator instruction rate (inst/s)
+host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
+host_mem_usage 374244 # Number of bytes of host memory used
+host_seconds 57.90 # Real time elapsed on the host
sim_insts 60898638 # Number of instructions simulated
sim_ops 60898638 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads
-system.physmem.totQLat 2137453500 # Total ticks spent queuing
-system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2137457500 # Total ticks spent queuing
+system.physmem.totMemAccLat 9763982500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5254.99 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24004.99 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s
system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy 66287824245 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1119418910250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1316300550720 # Total energy per rank (pJ)
system.physmem_0.averagePower 670.688732 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 1862013796212 # Time in different power states
system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35060565038 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ)
+system.physmem_1.actBackEnergy 66523575105 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1119212111250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1316364135975 # Total energy per rank (pJ)
system.physmem_1.averagePower 670.721130 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states
+system.physmem_1.memoryStateTime::IDLE 1861673236216 # Time in different power states
system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 35401125034 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906402435 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 10906402435 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 39966793434 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 39966793434 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 39966793434 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 39966793434 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.674232 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.674232 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33577.104101 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.104101 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33577.104101 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476952065 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003535066 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 38003535066 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003535066 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 38003535066 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293892500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293892500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768308500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768308500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1901998326 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 728722500 # Number of ticks simulated
-final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000730 # Number of seconds simulated
+sim_ticks 729906500 # Number of ticks simulated
+final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 162031375 # Simulator tick rate (ticks/s)
-host_mem_usage 277108 # Number of bytes of host memory used
-host_seconds 4.50 # Real time elapsed on the host
+host_tick_rate 158517498 # Simulator tick rate (ticks/s)
+host_mem_usage 277860 # Number of bytes of host memory used
+host_seconds 4.60 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory
-system.physmem.bytes_read::total 634443 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory
-system.physmem.bytes_written::total 443379 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory
+system.physmem.bytes_read::total 621042 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory
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+system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory
+system.physmem.bytes_written::total 430089 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 100000 # number of read accesses completed
-system.cpu0.num_writes 54791 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22240 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks.
+system.cpu0.num_reads 99153 # number of read accesses completed
+system.cpu0.num_writes 54942 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22508 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 393.884164 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13343 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22908 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.582460 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9793 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60366 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1074391 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 393.884164 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.769305 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.769305 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 337372 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 337372 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8651 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8651 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1083 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1083 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9734 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9734 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9734 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9734 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36335 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36335 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 24086 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 24086 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60421 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60421 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60421 # number of overall misses
+system.cpu0.l1c.overall_misses::total 60421 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 1008804376 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 1008804376 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 935467464 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 935467464 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 1944271840 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 1944271840 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1944271840 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1944271840 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 44986 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 44986 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 25169 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 70155 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 70155 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 70155 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 70155 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807696 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.807696 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956971 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.956971 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.861250 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.861250 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.861250 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.861250 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27763.984478 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 27763.984478 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38838.639209 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 38838.639209 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 32178.743152 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 32178.743152 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 32178.743152 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 1068204 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 61717 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.308100 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9656 # number of writebacks
-system.cpu0.l1c.writebacks::total 9656 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36727 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36727 # number of ReadReq MSHR misses
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-system.cpu0.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60366 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60366 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60366 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60366 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 960514497 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 960514497 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 882874166 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 882874166 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1843388663 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1843388663 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1843388663 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1843388663 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1939842714 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2695429549 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808804 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency
+system.cpu0.l1c.writebacks::writebacks 9915 # number of writebacks
+system.cpu0.l1c.writebacks::total 9915 # number of writebacks
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+system.cpu0.l1c.ReadReq_mshr_miss_latency::total 953224016 # number of ReadReq MSHR miss cycles
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+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807696 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807696 # mshr miss rate for ReadReq accesses
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+system.cpu0.l1c.overall_mshr_miss_rate::total 0.861250 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26234.319967 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26234.319967 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37319.247115 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37319.247115 # average WriteReq mshr miss latency
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+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30653.173599 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30653.173599 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99410 # number of read accesses completed
-system.cpu1.num_writes 55132 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22295 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 393.820804 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13496 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks.
+system.cpu1.num_reads 100000 # number of read accesses completed
+system.cpu1.num_writes 54938 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22377 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 394.468790 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13456 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.590564 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 393.820804 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.769181 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.769181 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338268 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338268 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8726 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8726 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1171 # number of WriteReq hits
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-system.cpu1.l1c.demand_hits::cpu1 9897 # number of demand (read+write) hits
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-system.cpu1.l1c.overall_hits::total 9897 # number of overall hits
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-system.cpu1.l1c.demand_misses::total 60470 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60470 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60470 # number of overall misses
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-system.cpu1.l1c.demand_miss_latency::total 1942356440 # number of demand (read+write) miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 1942356440 # number of overall miss cycles
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-system.cpu1.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.demand_accesses::total 70367 # number of demand (read+write) accesses
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-system.cpu1.l1c.overall_accesses::total 70367 # number of overall (read+write) accesses
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-system.cpu1.l1c.ReadReq_miss_rate::total 0.807369 # miss rate for ReadReq accesses
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-system.cpu1.l1c.WriteReq_miss_rate::total 0.953287 # miss rate for WriteReq accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.859352 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373 # average WriteReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 1066797 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::total 0.770447 # Average percentage of cache occupancy
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+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 338150 # Number of tag accesses
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+system.cpu1.l1c.ReadReq_hits::total 8709 # number of ReadReq hits
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+system.cpu1.l1c.overall_misses::total 60443 # number of overall misses
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+system.cpu1.l1c.ReadReq_miss_latency::total 1017715976 # number of ReadReq miss cycles
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+system.cpu1.l1c.WriteReq_accesses::total 25035 # number of WriteReq accesses(hits+misses)
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+system.cpu1.l1c.demand_accesses::total 70331 # number of demand (read+write) accesses
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+system.cpu1.l1c.overall_accesses::total 70331 # number of overall (read+write) accesses
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+system.cpu1.l1c.ReadReq_miss_rate::total 0.807731 # miss rate for ReadReq accesses
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+system.cpu1.l1c.WriteReq_miss_rate::total 0.952906 # miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_miss_rate::total 0.859408 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27816.327548 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 27816.327548 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38745.540074 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 38745.540074 # average WriteReq miss latency
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+system.cpu1.l1c.demand_avg_miss_latency::total 32129.933657 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 32129.933657 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 32129.933657 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 1075887 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 61607 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 62059 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.316165 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.336518 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9694 # number of writebacks
-system.cpu1.l1c.writebacks::total 9694 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36573 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36573 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23897 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23897 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60470 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60470 # number of demand (read+write) MSHR misses
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-system.cpu1.l1c.overall_mshr_misses::total 60470 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 964784026 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 964784026 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 885327122 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 885327122 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1850111148 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1850111148 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1850111148 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1850111148 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740106955 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1954561172 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2694668127 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles
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-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26286.281138 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37225.439135 # average WriteReq mshr miss latency
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99274 # number of read accesses completed
-system.cpu2.num_writes 54884 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22456 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 393.843880 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13581 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22857 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks.
+system.cpu2.num_reads 99515 # number of read accesses completed
+system.cpu2.num_writes 55356 # number of write accesses completed
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+system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 393.843880 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.769226 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.769226 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id
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system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 337451 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 337451 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8813 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8813 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1134 # number of WriteReq hits
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-system.cpu2.l1c.overall_hits::total 9947 # number of overall hits
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-system.cpu2.l1c.ReadReq_misses::total 36457 # number of ReadReq misses
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-system.cpu2.l1c.WriteReq_misses::total 23816 # number of WriteReq misses
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-system.cpu2.l1c.demand_misses::total 60273 # number of demand (read+write) misses
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-system.cpu2.l1c.overall_misses::total 60273 # number of overall misses
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-system.cpu2.l1c.ReadReq_miss_latency::total 1014308258 # number of ReadReq miss cycles
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-system.cpu2.l1c.overall_miss_latency::total 1939218488 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45270 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.overall_accesses::total 70220 # number of overall (read+write) accesses
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-system.cpu2.l1c.ReadReq_miss_rate::total 0.805324 # miss rate for ReadReq accesses
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-system.cpu2.l1c.overall_miss_rate::total 0.858345 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1061117 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 338294 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 338294 # Number of data accesses
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+system.cpu2.l1c.ReadReq_hits::total 8726 # number of ReadReq hits
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+system.cpu2.l1c.overall_misses::total 60459 # number of overall misses
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+system.cpu2.l1c.overall_accesses::total 70360 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806810 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.806810 # miss rate for ReadReq accesses
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+system.cpu2.l1c.overall_miss_rate::total 0.859281 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27824.164096 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 27824.164096 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38562.480077 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 38562.480077 # average WriteReq miss latency
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+system.cpu2.l1c.demand_avg_miss_latency::total 32089.900131 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 32089.900131 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 1067763 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 61178 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 61601 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.344748 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.333534 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9940 # number of writebacks
-system.cpu2.l1c.writebacks::total 9940 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36457 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36457 # number of ReadReq MSHR misses
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-system.cpu2.l1c.WriteReq_mshr_misses::total 23816 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60273 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60273 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60273 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60273 # number of overall MSHR misses
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-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958559384 # number of ReadReq MSHR miss cycles
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-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 888663772 # number of WriteReq MSHR miss cycles
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-system.cpu2.l1c.demand_mshr_miss_latency::total 1847223156 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847223156 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1847223156 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 735013046 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 735013046 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1939097223 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1939097223 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2674110269 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2674110269 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805324 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805324 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954549 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954549 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858345 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858345 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency
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+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1919549279 # number of WriteReq MSHR uncacheable cycles
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+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859281 # mshr miss rate for overall accesses
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26294.751166 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26294.751166 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37042.138902 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37042.138902 # average WriteReq mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30564.090905 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30564.090905 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99869 # number of read accesses completed
-system.cpu3.num_writes 54874 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22370 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 393.431339 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13240 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22771 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.581441 # Average number of references to valid blocks.
+system.cpu3.num_reads 99509 # number of read accesses completed
+system.cpu3.num_writes 55322 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22357 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 394.352238 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13564 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.596403 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 393.431339 # Average occupied blocks per requestor
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-system.cpu3.l1c.tags.occ_percent::total 0.768421 # Average percentage of cache occupancy
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-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 336829 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 336829 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8648 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8648 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1128 # number of WriteReq hits
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-system.cpu3.l1c.overall_hits::total 9776 # number of overall hits
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-system.cpu3.l1c.WriteReq_misses::total 23788 # number of WriteReq misses
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-system.cpu3.l1c.demand_misses::total 60246 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60246 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60246 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 1012578921 # number of ReadReq miss cycles
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-system.cpu3.l1c.demand_miss_latency::total 1933038089 # number of demand (read+write) miss cycles
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-system.cpu3.l1c.overall_miss_latency::total 1933038089 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45106 # number of ReadReq accesses(hits+misses)
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-system.cpu3.l1c.overall_accesses::total 70022 # number of overall (read+write) accesses
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-system.cpu3.l1c.demand_miss_rate::total 0.860387 # miss rate for demand accesses
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-system.cpu3.l1c.overall_miss_rate::total 0.860387 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194 # average ReadReq miss latency
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-system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671 # average WriteReq miss latency
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-system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1072737 # number of cycles access was blocked
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+system.cpu3.l1c.tags.occ_percent::total 0.770219 # Average percentage of cache occupancy
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+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 338647 # Number of tag accesses
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+system.cpu3.l1c.overall_misses::total 60473 # number of overall misses
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+system.cpu3.l1c.overall_miss_latency::total 1946360391 # number of overall miss cycles
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+system.cpu3.l1c.overall_accesses::total 70457 # number of overall (read+write) accesses
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+system.cpu3.l1c.overall_miss_rate::total 0.858297 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27954.903360 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 27954.903360 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38690.197088 # average WriteReq miss latency
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+system.cpu3.l1c.demand_avg_miss_latency::total 32185.609958 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 32185.609958 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 32185.609958 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 1061792 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 61848 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 61430 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.344732 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.284584 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9757 # number of writebacks
-system.cpu3.l1c.writebacks::total 9757 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36458 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23788 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60246 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60246 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60246 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60246 # number of overall MSHR misses
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-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 956791627 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 884289164 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 884289164 # number of WriteReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 1841080791 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1841080791 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1841080791 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 756050699 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 756050699 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1926314708 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1926314708 # number of WriteReq MSHR uncacheable cycles
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-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2682365407 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808274 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808274 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954728 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954728 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.demand_mshr_miss_rate::total 0.860387 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.860387 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30659.864750 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 54829 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22505 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 395.050000 # Cycle average of tags in use
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-system.cpu4.l1c.tags.sampled_refs 22916 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.583566 # Average number of references to valid blocks.
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+system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588 # average overall miss latency
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-system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588 # average overall miss latency
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+system.cpu4.l1c.overall_avg_miss_latency::cpu4 32128.244720 # average overall miss latency
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.writebacks::total 9914 # number of writebacks
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-system.cpu4.l1c.demand_mshr_misses::total 60519 # number of demand (read+write) MSHR misses
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1859801369 # number of demand (read+write) MSHR miss cycles
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-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 728267014 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1921671690 # number of WriteReq MSHR uncacheable cycles
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952043 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.861370 # mshr miss rate for demand accesses
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-system.cpu4.l1c.overall_mshr_miss_rate::total 0.861370 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252 # average ReadReq mshr miss latency
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-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200 # average WriteReq mshr miss latency
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-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30601.937316 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 54996 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22529 # number of replacements
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 54686 # number of write accesses completed
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-system.cpu7.l1c.tags.sampled_refs 22591 # Sample count of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu7.l1c.demand_mshr_miss_latency::total 1834752041 # number of demand (read+write) MSHR miss cycles
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-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use
-system.l2c.tags.total_refs 150276 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks.
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+system.l2c.tags.replacements 12974 # number of replacements
+system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use
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+system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 725.457797 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.718013 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.568954 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.219418 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.731947 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.474998 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.998802 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.991847 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 7.001453 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.708455 # Average percentage of cache occupancy
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-system.l2c.UpgradeReq_hits::cpu4 356 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 330 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 346 # number of UpgradeReq hits
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-system.l2c.UpgradeReq_misses::cpu4 1968 # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::cpu6 1963 # number of UpgradeReq misses
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-system.l2c.demand_misses::cpu5 5191 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu6 5098 # number of overall misses
-system.l2c.overall_misses::cpu7 5088 # number of overall misses
-system.l2c.overall_misses::total 40906 # number of overall misses
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-system.l2c.ReadReq_miss_latency::cpu6 42434429 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu7 44394419 # number of ReadReq miss cycles
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-system.l2c.UpgradeReq_miss_latency::cpu5 57084499 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu6 56659000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu7 56222499 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 453160997 # number of UpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu7 238492966 # number of ReadExReq miss cycles
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-system.l2c.demand_miss_latency::cpu4 286125394 # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu7 282887385 # number of demand (read+write) miss cycles
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-system.l2c.overall_miss_latency::cpu4 286125394 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu5 288620893 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu6 283510893 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu7 282887385 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 2275086151 # number of overall miss cycles
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-system.l2c.ReadReq_accesses::total 91446 # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::total 75598 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1 2258 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu3 2166 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2324 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2284 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2324 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2265 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18238 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0 6239 # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total 50460 # number of ReadExReq accesses(hits+misses)
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-system.l2c.overall_accesses::total 141906 # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.856953 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.852076 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.845799 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.846816 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.855517 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.844664 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.847241 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.849490 # miss rate for UpgradeReq accesses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.698161 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.695576 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.695780 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.287000 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.287265 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.286010 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.287028 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.284717 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.287561 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.286880 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.288566 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.287992 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.287000 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49027.101208 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50060.902128 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49440.893805 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49444.918958 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49079.093514 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49589.264402 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50408.490937 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50010.496464 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 49637.365473 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41847.602519 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41908.803709 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41926.437633 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41932.098335 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41934.007161 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41995.144461 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41868.713855 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41893.742755 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41912.990383 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42549.256693 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42592.260227 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42578.562357 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42657.417907 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42534.975169 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42605.869159 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42556.394055 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42455.650558 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42566.171534 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 43388.953789 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 43623.678942 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 43498.787975 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43584.694148 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 43386.879835 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 43539.470774 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 43575.027827 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43504.193168 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 43512.647714 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 84424 # Transaction distribution
-system.membus.trans_dist::ReadResp 84420 # Transaction distribution
-system.membus.trans_dist::WriteReq 43379 # Transaction distribution
-system.membus.trans_dist::WriteResp 43377 # Transaction distribution
-system.membus.trans_dist::Writeback 6250 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50299 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3116 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 58193 # Total snoops (count)
-system.membus.snoop_fanout::samples 123722 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84079 # Transaction distribution
+system.membus.trans_dist::ReadResp 84076 # Transaction distribution
+system.membus.trans_dist::WriteReq 43401 # Transaction distribution
+system.membus.trans_dist::WriteResp 43399 # Transaction distribution
+system.membus.trans_dist::Writeback 6042 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50251 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3038 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58073 # Total snoops (count)
+system.membus.snoop_fanout::samples 123330 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123722 # Request fanout histogram
-system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 48.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 42.9 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total 123330 # Request fanout histogram
+system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 47.8 # Layer utilization (%)
+system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 42.6 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 322707 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 323559 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000476 # Number of seconds simulated
-sim_ticks 475552000 # Number of ticks simulated
-final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000473 # Number of seconds simulated
+sim_ticks 473250000 # Number of ticks simulated
+final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 102852654 # Simulator tick rate (ticks/s)
-host_mem_usage 276856 # Number of bytes of host memory used
-host_seconds 4.62 # Real time elapsed on the host
+host_tick_rate 101630905 # Simulator tick rate (ticks/s)
+host_mem_usage 277340 # Number of bytes of host memory used
+host_seconds 4.66 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory
-system.physmem.bytes_read::total 649301 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory
-system.physmem.bytes_written::total 454846 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory
+system.physmem.bytes_read::total 659012 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
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+system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory
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+system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory
+system.physmem.bytes_written::total 462904 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 100000 # number of read accesses completed
-system.cpu0.num_writes 55373 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22370 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks.
+system.cpu0.num_reads 98988 # number of read accesses completed
+system.cpu0.num_writes 54550 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22171 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 391.248330 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13318 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22569 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.590101 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9779 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60701 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 391.248330 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.764157 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.764157 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 335805 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 335805 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8501 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8501 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1143 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1143 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9644 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9644 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9644 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9644 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36474 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36474 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 23719 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 23719 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60193 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60193 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60193 # number of overall misses
+system.cpu0.l1c.overall_misses::total 60193 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 587864141 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 587864141 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 652231215 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 652231215 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 1240095356 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 1240095356 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1240095356 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1240095356 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 44975 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 44975 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 24862 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 24862 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 69837 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 69837 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 69837 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 69837 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810984 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.810984 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954026 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.954026 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.861907 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.861907 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.861907 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.861907 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16117.347727 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16117.347727 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27498.259412 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 27498.259412 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 20601.986211 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 20601.986211 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 20601.986211 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 773904 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 66096 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.708787 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks
-system.cpu0.l1c.writebacks::total 9788 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency
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+system.cpu0.l1c.writebacks::total 9687 # number of writebacks
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+system.cpu0.l1c.WriteReq_mshr_misses::total 23719 # number of WriteReq MSHR misses
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+system.cpu0.l1c.ReadReq_mshr_miss_latency::total 531003039 # number of ReadReq MSHR miss cycles
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+system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1146656340 # number of overall MSHR miss cycles
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+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 646054384 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 646054384 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 971060215 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1617114599 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810984 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810984 # mshr miss rate for ReadReq accesses
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+system.cpu0.l1c.overall_mshr_miss_rate::total 0.861907 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14558.398832 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14558.398832 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25956.123825 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25956.123825 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19049.662585 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19049.662585 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99552 # number of read accesses completed
-system.cpu1.num_writes 55312 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22247 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks.
+system.cpu1.num_reads 99262 # number of read accesses completed
+system.cpu1.num_writes 54743 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22415 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 391.761420 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13414 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22814 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.587972 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits
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-system.cpu1.l1c.overall_hits::total 9815 # number of overall hits
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-system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses
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-system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses
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-system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60648 # number of overall misses
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-system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles
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-system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses)
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-system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses)
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-system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses
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-system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses
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-system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses
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-system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency
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-system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked
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+system.cpu1.l1c.tags.occ_percent::total 0.765159 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 336589 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 336589 # Number of data accesses
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+system.cpu1.l1c.ReadReq_hits::total 8598 # number of ReadReq hits
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+system.cpu1.l1c.ReadReq_misses::total 36477 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 23776 # number of WriteReq misses
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+system.cpu1.l1c.overall_misses::total 60253 # number of overall misses
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+system.cpu1.l1c.overall_miss_latency::total 1244610600 # number of overall miss cycles
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+system.cpu1.l1c.WriteReq_accesses::cpu1 24938 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24938 # number of WriteReq accesses(hits+misses)
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+system.cpu1.l1c.demand_accesses::total 70013 # number of demand (read+write) accesses
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+system.cpu1.l1c.overall_accesses::total 70013 # number of overall (read+write) accesses
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+system.cpu1.l1c.ReadReq_miss_rate::total 0.809251 # miss rate for ReadReq accesses
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+system.cpu1.l1c.WriteReq_miss_rate::total 0.953404 # miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_miss_rate::total 0.860597 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16324.281821 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16324.281821 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27302.732672 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 27302.732672 # average WriteReq miss latency
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+system.cpu1.l1c.demand_avg_miss_latency::total 20656.408810 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20656.408810 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20656.408810 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 769857 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 65915 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.679542 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks
-system.cpu1.l1c.writebacks::total 9776 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles
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-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses
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-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency
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-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.809251 # mshr miss rate for ReadReq accesses
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+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14761.141925 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14761.141925 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25761.225269 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25761.225269 # average WriteReq mshr miss latency
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+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19101.805155 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19101.805155 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99606 # number of read accesses completed
-system.cpu2.num_writes 55482 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22450 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks.
+system.cpu2.num_reads 99661 # number of read accesses completed
+system.cpu2.num_writes 54617 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22463 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 392.489979 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13594 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22875 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.594273 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits
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-system.cpu2.l1c.overall_hits::total 9940 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60530 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles
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-system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles
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-system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses)
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-system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses)
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-system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses
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-system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked
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+system.cpu2.l1c.tags.occ_percent::total 0.766582 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 412 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.804688 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 338191 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 338191 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8852 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8852 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1132 # number of WriteReq hits
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+system.cpu2.l1c.overall_hits::total 9984 # number of overall hits
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+system.cpu2.l1c.overall_misses::total 60388 # number of overall misses
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+system.cpu2.l1c.demand_miss_latency::total 1242570282 # number of demand (read+write) miss cycles
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+system.cpu2.l1c.overall_miss_latency::total 1242570282 # number of overall miss cycles
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+system.cpu2.l1c.ReadReq_accesses::total 45449 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 24923 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 24923 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 70372 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses
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+system.cpu2.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805232 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.805232 # miss rate for ReadReq accesses
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+system.cpu2.l1c.overall_miss_rate::cpu2 0.858125 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.858125 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16288.451567 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16288.451567 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27172.536674 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 27172.536674 # average WriteReq miss latency
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+system.cpu2.l1c.demand_avg_miss_latency::total 20576.443697 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 20576.443697 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 20576.443697 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 768951 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 65985 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.653421 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks
-system.cpu2.l1c.writebacks::total 9975 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency
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-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency
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-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14726.891385 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14726.891385 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 25630.468328 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 25630.468328 # average WriteReq mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19022.562695 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19022.562695 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99549 # number of read accesses completed
-system.cpu3.num_writes 55104 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22310 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks.
+system.cpu3.num_reads 100000 # number of read accesses completed
+system.cpu3.num_writes 55095 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22209 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 391.627346 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13529 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22601 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.598602 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits
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-system.cpu3.l1c.overall_hits::total 9836 # number of overall hits
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-system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses
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-system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses
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-system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60543 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles
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-system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles
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-system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles
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-system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses)
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-system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses
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-system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency
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-system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency
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-system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked
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+system.cpu3.l1c.tags.occ_percent::total 0.764897 # Average percentage of cache occupancy
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+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
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+system.cpu3.l1c.overall_accesses::total 70425 # number of overall (read+write) accesses
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+system.cpu3.l1c.overall_miss_rate::total 0.858971 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16232.762092 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 16232.762092 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27377.371782 # average WriteReq miss latency
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+system.cpu3.l1c.demand_avg_miss_latency::total 20620.193361 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 20620.193361 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 20620.193361 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 774947 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 66468 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.658949 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks
-system.cpu3.l1c.writebacks::total 9907 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles
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-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19065.086985 # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 55257 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22302 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses
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-system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency
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-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency
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+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14632.237391 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25971.888917 # average WriteReq mshr miss latency
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+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19121.127363 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19121.127363 # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 54912 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22132 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use
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-system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks.
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 55188 # number of write accesses completed
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
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system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 55743 # number of write accesses completed
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-system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles
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-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles
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-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency
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-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use
-system.l2c.tags.total_refs 151949 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks.
+system.l2c.tags.replacements 13851 # number of replacements
+system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use
+system.l2c.tags.total_refs 151322 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14625 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.346803 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor
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-system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.UpgradeReq_mshr_miss_rate::total 0.844710 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682064 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.683444 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.698365 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.687344 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.686041 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.691476 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.697173 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.690698 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.286289 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.288901 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.282394 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.281620 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.289580 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.285355 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.290630 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.289106 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.282738 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.286289 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 50975.966667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49507.911765 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50144.421853 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49593.434783 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 50602.878398 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 50227.347594 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 50054.372414 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50980.876231 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 50246.331208 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42199.572880 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42202.151316 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42270.442812 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42346.233075 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42422.192096 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42303.154076 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42231.640812 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42247.458207 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42278.156966 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43032.309824 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43077.969173 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42964.423113 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 43028.158672 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42985.343311 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 43048.004447 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43097.293904 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42842.012142 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43009.637407 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 44101.171607 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 44034.151491 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 43994.206705 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43994.239434 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 44027.554512 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 44071.865014 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 44078.975866 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43982.030339 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 44035.771411 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 84922 # Transaction distribution
-system.membus.trans_dist::ReadResp 84916 # Transaction distribution
-system.membus.trans_dist::WriteReq 43774 # Transaction distribution
-system.membus.trans_dist::WriteResp 43771 # Transaction distribution
-system.membus.trans_dist::Writeback 6423 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50059 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3238 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57586 # Total snoops (count)
-system.membus.snoop_fanout::samples 124108 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84510 # Transaction distribution
+system.membus.trans_dist::ReadResp 84504 # Transaction distribution
+system.membus.trans_dist::WriteReq 43512 # Transaction distribution
+system.membus.trans_dist::WriteResp 43509 # Transaction distribution
+system.membus.trans_dist::Writeback 6553 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58529 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47554 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49190 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3281 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 421142 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 56880 # Total snoops (count)
+system.membus.snoop_fanout::samples 123632 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 124108 # Request fanout histogram
-system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 60.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 64.5 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 322486 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram
+system.membus.snoop_fanout::total 123632 # Request fanout histogram
+system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 60.4 # Layer utilization (%)
+system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 64.7 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161030 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 320901 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff