Update CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 149443c746cd122af4c7645adfea907d2eb404ee..c1b548aebbcb4c416733b71fc922987876acfe55 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -16,12 +16,10 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "gate2lut.v" techmap rule
     - Added "rename -src"
     - Added "equiv_opt" pass
-<<<<<<< HEAD
-    - Added "muxpack" pass
-=======
     - Added "read_aiger" frontend
->>>>>>> origin/master
+    - Added "muxpack" pass
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+    - "synth_xilinx" to now infer wide multiplexers
 
 
 Yosys 0.7 .. Yosys 0.8