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update photo for stlinkv2 JTAG wires in HDL_Workflow/ECP5_FPGA
authorCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)
committerCole Poirier <colepoirier@gmail.com>
Wed, 4 Nov 2020 00:55:59 +0000 (16:55 -0800)
HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg patch | blob | history

diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg
index d56adc85024da97f4f8b41c9d0a371c3c8ad75da..c03ef96ee177b321b7be4e80296ebe1215b5d42f 100644 (file)
Binary files a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg differ
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