mibuild/lattice: use new Toolchain/Platform architecture

diff --git a/mibuild/lattice/__init__.py b/mibuild/lattice/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..02116134a72cf13cc73f12f3b931d2c10fca5bae 100644 (file)
--- a/mibuild/lattice/__init__.py
+++ b/mibuild/lattice/__init__.py
@@ -0,0 +1,2 @@
+from mibuild.lattice.platform import LatticePlatform
+from mibuild.lattice.programmer import LatticeProgrammer

diff --git a/mibuild/lattice/common.py b/mibuild/lattice/common.py
new file mode 100644 (file)
index 0000000..2eef69d
--- /dev/null
+++ b/mibuild/lattice/common.py
@@ -0,0 +1 @@
+lattice_special_overrides = {}

diff --git a/mibuild/lattice/diamond.py b/mibuild/lattice/diamond.py
index f39ddd325e3e614a16daca6fac5edb3fd49b1a4c..dbbc99ae18d6040eb977ec4e988c36a549ff1b47 100644 (file)
--- a/mibuild/lattice/diamond.py
+++ b/mibuild/lattice/diamond.py
@@ -5,7 +5,9 @@ import os, subprocess, shutil
 
 from migen.fhdl.structure import _Fragment
 from mibuild.generic_platform import *
+
 from mibuild import tools
+from mibuild.lattice import common
 
 def _format_constraint(c):
        if isinstance(c, Pins):
@@ -61,23 +63,22 @@ def _run_diamond(build_name, source, ver=None):
        if r != 0:
                raise OSError("Subprocess failed")
 
-class LatticeDiamondPlatform(GenericPlatform):
-       bitstream_ext = ".bit"
-       def build(self, fragment, build_dir="build", build_name="top",
+class LatticeDiamondToolchain:
+       def build(self, platform, fragment, build_dir="build", build_name="top",
                        diamond_path="/opt/Diamond", run=True):
                tools.mkdir_noerror(build_dir)
                os.chdir(build_dir)
 
                if not isinstance(fragment, _Fragment):
                        fragment = fragment.get_fragment()
-               self.finalize(fragment)
+               platform.finalize(fragment)
 
-               v_src, vns = self.get_verilog(fragment)
-               named_sc, named_pc = self.resolve_signals(vns)
+               v_src, vns = platform.get_verilog(fragment)
+               named_sc, named_pc = platform.resolve_signals(vns)
                v_file = build_name + ".v"
                tools.write_to_file(v_file, v_src)
-               sources = self.sources + [(v_file, "verilog")]
-               _build_files(self.device, sources, self.verilog_include_paths, build_name)
+               sources = platform.sources + [(v_file, "verilog")]
+               _build_files(platform.device, sources, platform.verilog_include_paths, build_name)
 
                tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
 
@@ -88,6 +89,6 @@ class LatticeDiamondPlatform(GenericPlatform):
 
                return vns
 
-       def add_period_constraint(self, clk, period):
+       def add_period_constraint(self, platform, clk, period):
                # TODO: handle differential clk
-               self.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
\ No newline at end of file
+               platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)

diff --git a/mibuild/lattice/platform.py b/mibuild/lattice/platform.py
new file mode 100644 (file)
index 0000000..f3586da
--- /dev/null
+++ b/mibuild/lattice/platform.py
@@ -0,0 +1,25 @@
+from mibuild.generic_platform import GenericPlatform
+from mibuild.lattice import common, diamond
+
+class LatticePlatform(GenericPlatform):
+       bitstream_ext = ".bit"
+
+       def __init__(self, *args, toolchain="diamond", **kwargs):
+               GenericPlatform.__init__(self, *args, **kwargs)
+               if toolchain == "diamond":
+                       self.toolchain = diamond.LatticeDiamondToolchain()
+               else:
+                       raise ValueError("Unknown toolchain")
+
+       def get_verilog(self, *args, special_overrides=dict(), **kwargs):
+               so = dict(common.lattice_special_overrides)
+               so.update(special_overrides)
+               return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
+
+       def build(self, *args, **kwargs):
+               return self.toolchain.build(self, *args, **kwargs)
+
+       def add_period_constraint(self, clk, period):
+               if hasattr(clk, "p"):
+                       clk = clk.p
+               self.toolchain.add_period_constraint(self, clk, period)

diff --git a/mibuild/platforms/versa.py b/mibuild/platforms/versa.py
index 6cd58bf946809a9a88de34aef143cbaba14bb799..050afb4f9c5b429aadda9536f74089314f96f4f0 100644 (file)
--- a/mibuild/platforms/versa.py
+++ b/mibuild/platforms/versa.py
@@ -2,7 +2,7 @@
 # License: BSD
 
 from mibuild.generic_platform import *
-from mibuild.lattice.diamond import LatticeDiamondPlatform
+from mibuild.lattice import LatticePlatform
 from mibuild.lattice.programmer import LatticeProgrammer
 
 _io = [
@@ -23,12 +23,12 @@ _io = [
        ),
 ]
 
-class Platform(LatticeDiamondPlatform):
+class Platform(LatticePlatform):
        default_clk_name = "clk100"
        default_clk_period = 10
 
        def __init__(self):
-               LatticeDiamondPlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
+               LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
 
        def create_programmer(self):
                return LatticeProgrammer()