xilinx pcie: put buffers before the outputs to the controller

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index bd3b1ef9fd8c818a87b940cda88e0cd3c67274c7..b82186c31c34594233460be568f2f31f4f4b3cfb 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -26,8 +26,8 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val intnode = IntSourceNode(1)
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
-  axi_to_pcie_x1.slave   := TLToAXI4(idBits=4)(slave)
-  axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
+  axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
+  axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
   master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
 
   lazy val module = new LazyModuleImp(this) {