Device: Update stats for PIO and PCI latency change
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 10 Sep 2012 15:57:37 +0000 (11:57 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 10 Sep 2012 15:57:37 +0000 (11:57 -0400)
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.

12 files changed:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

index a7a1d7396ce235104ce5cd801ad6a7a0dfd598dd..082ffde7cdec1d5fea1b5a653ed3e8e5009ba41c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.900530                       # Number of seconds simulated
-sim_ticks                                1900530295500                       # Number of ticks simulated
-final_tick                               1900530295500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.903503                       # Number of seconds simulated
+sim_ticks                                1903503020500                       # Number of ticks simulated
+final_tick                               1903503020500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128893                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128893                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4273489918                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 307500                       # Number of bytes of host memory used
-host_seconds                                   444.73                       # Real time elapsed on the host
-sim_insts                                    57321882                       # Number of instructions simulated
-sim_ops                                      57321882                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           875200                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         24658176                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           108032                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data           692736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28984960                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       875200                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       108032                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          983232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7922432                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7922432                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             13675                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            385284                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              1688                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             10824                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                452890                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          123788                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               123788                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              460503                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12974366                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1394777                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               56843                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              364496                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15250986                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         460503                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          56843                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             517346                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4168538                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4168538                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4168538                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             460503                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12974366                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1394777                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              56843                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             364496                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19419523                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        345965                       # number of replacements
-system.l2c.tagsinuse                     65264.028554                       # Cycle average of tags in use
-system.l2c.total_refs                         2565305                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        411137                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.239538                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    6370050000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53566.065326                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          5313.128544                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          6099.641645                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst           209.824884                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data            75.368156                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.817353                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.081072                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.093073                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.003202                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.001150                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.995850                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             778193                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             689575                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             314248                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             100958                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1882974                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          806039                       # number of Writeback hits
-system.l2c.Writeback_hits::total               806039                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             174                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             439                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 613                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            52                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            31                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                83                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           128167                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            44386                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               172553                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              778193                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              817742                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              314248                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              145344                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2055527                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             778193                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             817742                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             314248                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             145344                       # number of overall hits
-system.l2c.overall_hits::total                2055527                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            13677                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           272973                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             1705                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              853                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               289208                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2871                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          1574                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              4445                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          724                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          747                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1471                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         113108                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          10072                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             123180                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             13677                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            386081                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              1705                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             10925                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                412388                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            13677                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           386081                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             1705                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            10925                       # number of overall misses
-system.l2c.overall_misses::total               412388                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    728382998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14214430499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst     91270500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     46668499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15080752496                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      2584000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     19818914                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     22402914                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      2792500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       314000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      3106500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   6061979997                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data    549631499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6611611496                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    728382998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  20276410496                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst     91270500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data    596299998                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21692363992                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    728382998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  20276410496                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst     91270500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data    596299998                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21692363992                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         791870                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         962548                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         315953                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         101811                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2172182                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       806039                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           806039                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         3045                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         2013                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            5058                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          776                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          778                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1554                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       241275                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data        54458                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           295733                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          791870                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data         1203823                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          315953                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          156269                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2467915                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         791870                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data        1203823                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         315953                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         156269                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2467915                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.017272                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.283594                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.005396                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.008378                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.133142                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.942857                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.781918                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.878806                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.932990                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.960154                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.946589                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.468793                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.184950                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.416524                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.017272                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.320712                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.005396                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.069911                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.167100                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.017272                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.320712                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.005396                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.069911                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.167100                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53256.050157                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.661029                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53531.085044                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 54711.018757                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52145.004620                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   900.034831                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 12591.432020                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  5040.025647                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3857.044199                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data   420.348059                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  2111.828688                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53594.617507                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54570.244142                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53674.391102                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52601.831266                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53256.050157                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52518.540141                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53531.085044                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 54581.235515                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52601.831266                       # average overall miss latency
+host_inst_rate                                 196271                       # Simulator instruction rate (inst/s)
+host_op_rate                                   196271                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6657053225                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 303260                       # Number of bytes of host memory used
+host_seconds                                   285.94                       # Real time elapsed on the host
+sim_insts                                    56121257                       # Number of instructions simulated
+sim_ops                                      56121257                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           882432                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24721216                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2649664                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           100416                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           648960                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             29002688                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       882432                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       100416                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          982848                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7936064                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7936064                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13788                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            386269                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41401                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              1569                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             10140                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                453167                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          124001                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               124001                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              463583                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12987222                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1391994                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               52753                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              340929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15236481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         463583                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          52753                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             516336                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4169189                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4169189                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4169189                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             463583                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12987222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1391994                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              52753                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             340929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19405670                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        346253                       # number of replacements
+system.l2c.tagsinuse                     65331.229324                       # Cycle average of tags in use
+system.l2c.total_refs                         2603754                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        411399                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.329024                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    6380524000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        53709.821247                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          5286.136461                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          6105.466815                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           198.491400                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data            31.313401                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.819547                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.080660                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.093162                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.003029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000478                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.996875                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             965065                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             779439                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             111820                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              39391                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1895715                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          831921                       # number of Writeback hits
+system.l2c.Writeback_hits::total               831921                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              73                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 245                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            28                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           165704                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            16093                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               181797                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              965065                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              945143                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              111820                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               55484                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2077512                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             965065                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             945143                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             111820                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              55484                       # number of overall hits
+system.l2c.overall_hits::total                2077512                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            13790                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           273025                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1586                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              787                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               289188                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2478                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           547                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              3025                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           39                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           78                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             117                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113756                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           9451                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             123207                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             13790                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            386781                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1586                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             10238                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                412395                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13790                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           386781                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1586                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            10238                       # number of overall misses
+system.l2c.overall_misses::total               412395                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    734208497                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  14217029000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     84954500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     43255499                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15079447496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      2117000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      2247500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      4364500                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       418000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       626000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   6097259996                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    516851999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6614111995                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    734208497                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  20314288996                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     84954500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    560107498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21693559491                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    734208497                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  20314288996                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     84954500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    560107498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21693559491                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         978855                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1052464                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         113406                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          40178                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2184903                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       831921                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           831921                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2650                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          620                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3270                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           67                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          106                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           173                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       279460                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        25544                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           305004                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          978855                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1331924                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          113406                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           65722                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2489907                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         978855                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1331924                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         113406                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          65722                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2489907                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014088                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.259415                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.013985                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.019588                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.132357                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935094                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.882258                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.925076                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.582090                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.735849                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.676301                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.407056                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.369989                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.403952                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014088                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.290393                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.013985                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.155777                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.165627                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014088                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.290393                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.013985                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.155777                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.165627                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53242.095504                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52072.260782                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53565.258512                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 54962.514612                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52144.098289                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   854.317998                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4108.775137                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1442.809917                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 10717.948718                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2666.666667                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  5350.427350                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53599.458455                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 54687.546186                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53682.923819                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53242.095504                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52521.424258                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53565.258512                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 54708.683141                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52603.837319                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53242.095504                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52521.424258                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53565.258512                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 54708.683141                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52603.837319                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -221,8 +221,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               82268                       # number of writebacks
-system.l2c.writebacks::total                    82268                       # number of writebacks
+system.l2c.writebacks::writebacks               82481                       # number of writebacks
+system.l2c.writebacks::total                    82481                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu1.inst            17                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
@@ -232,111 +232,111 @@ system.l2c.demand_mshr_hits::total                 18                       # nu
 system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            17                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        13676                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       272973                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         1688                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data          853                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          289190                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2871                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         1574                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         4445                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          724                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          747                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1471                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       113108                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        10072                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        123180                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        13676                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       386081                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         1688                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        10925                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           412370                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        13676                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       386081                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         1688                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        10925                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          412370                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    561190998                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10939303500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     69880000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     36325000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11606699498                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    114956000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     62989500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    177945500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     29007500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     29880000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     58887500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4696029997                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    427574999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5123604996                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    561190998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  15635333497                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     69880000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    463899999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16730304494                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    561190998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  15635333497                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     69880000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    463899999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16730304494                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    820944530                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     16650000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    837594530                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1194274500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    359420000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1553694500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2015219030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    376070000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2391289030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.283594                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.008378                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.133133                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.942857                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.781918                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.878806                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.932990                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.960154                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.946589                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.468793                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.184950                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.416524                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167092                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.017271                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.320712                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005343                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.069911                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167092                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40074.672220                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42584.994138                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40135.203493                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.404040                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40018.742058                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.733408                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40065.607735                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        13789                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       273025                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1569                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          787                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          289170                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2478                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          547                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3025                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           39                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           78                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          117                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       113756                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         9451                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        123207                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13789                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       386781                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1569                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        10238                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           412377                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13789                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       386781                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1569                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        10238                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          412377                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    565634498                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10948899500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     65008500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     33728000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11613270498                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     99222000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     21905000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    121127000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1560000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      4680000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4723374496                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    402418000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5125792496                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    565634498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  15672273996                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     65008500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    436146000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16739062994                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    565634498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  15672273996                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     65008500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    436146000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16739062994                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1361916000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     24780000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1386696000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1936832500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    518088500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2454921000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3298748500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    542868500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3841617000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259415                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.019588                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.132349                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.935094                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.882258                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.925076                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.582090                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.735849                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.676301                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.407056                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.369989                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.403952                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.290393                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.155777                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.165619                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014087                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.290393                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.013835                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.155777                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.165619                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40102.186613                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 42856.416773                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40160.703040                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.162228                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40045.703839                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40041.983471                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40032.290959                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41518.106562                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42451.846604                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41594.455236                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41034.732232                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40497.547139                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41398.104265                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42462.242471                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40571.099968                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41521.981223                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42579.409586                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41603.094759                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40519.761819                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42600.703262                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40591.650344                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41020.704765                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40519.761819                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41433.078394                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42600.703262                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40591.650344                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -347,39 +347,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     41698                       # number of replacements
-system.iocache.tagsinuse                     0.465235                       # Cycle average of tags in use
+system.iocache.replacements                     41696                       # number of replacements
+system.iocache.tagsinuse                     0.468001                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     41712                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1711281170000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       0.465235                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.029077                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.029077                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
+system.iocache.warmup_cycle              1712293423000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       0.468001                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.029250                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.029250                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
-system.iocache.overall_misses::total            41730                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21238998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21238998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7637828806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7637828806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7659067804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7659067804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7659067804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7659067804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
+system.iocache.overall_misses::total            41728                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21012998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21012998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7634627806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7634627806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7655640804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7655640804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7655640804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7655640804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
@@ -388,40 +388,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119320.213483                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119320.213483                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183813.746775                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183813.746775                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183538.648550                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183538.648550                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183538.648550                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7685000                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119392.034091                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119392.034091                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183736.710772                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183736.710772                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183465.318347                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183465.318347                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183465.318347                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183465.318347                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7744000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7152                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7100                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1074.524609                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1090.704225                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           41520                       # number of writebacks
 system.iocache.writebacks::total                41520                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11982000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     11982000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5476969000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5476969000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5488951000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5488951000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5488951000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5488951000                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11860000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11860000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5473770000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5473770000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5485630000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5485630000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5485630000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5485630000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -430,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67314.606742                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67314.606742                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131809.997112                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131809.997112                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131534.890966                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131534.890966                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67386.363636                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67386.363636                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131733.009241                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131733.009241                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131461.608512                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131461.608512                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131461.608512                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131461.608512                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -455,22 +455,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     8334041                       # DTB read hits
-system.cpu0.dtb.read_misses                     29708                       # DTB read misses
-system.cpu0.dtb.read_acv                          432                       # DTB read access violations
-system.cpu0.dtb.read_accesses                  650283                       # DTB read accesses
-system.cpu0.dtb.write_hits                    5360343                       # DTB write hits
-system.cpu0.dtb.write_misses                     6029                       # DTB write misses
-system.cpu0.dtb.write_acv                         281                       # DTB write access violations
-system.cpu0.dtb.write_accesses                 211361                       # DTB write accesses
-system.cpu0.dtb.data_hits                    13694384                       # DTB hits
-system.cpu0.dtb.data_misses                     35737                       # DTB misses
-system.cpu0.dtb.data_acv                          713                       # DTB access violations
-system.cpu0.dtb.data_accesses                  861644                       # DTB accesses
-system.cpu0.itb.fetch_hits                     975254                       # ITB hits
-system.cpu0.itb.fetch_misses                    26821                       # ITB misses
-system.cpu0.itb.fetch_acv                         801                       # ITB acv
-system.cpu0.itb.fetch_accesses                1002075                       # ITB accesses
+system.cpu0.dtb.read_hits                     9362822                       # DTB read hits
+system.cpu0.dtb.read_misses                     32776                       # DTB read misses
+system.cpu0.dtb.read_acv                          407                       # DTB read access violations
+system.cpu0.dtb.read_accesses                  655429                       # DTB read accesses
+system.cpu0.dtb.write_hits                    6177998                       # DTB write hits
+system.cpu0.dtb.write_misses                     6927                       # DTB write misses
+system.cpu0.dtb.write_acv                         263                       # DTB write access violations
+system.cpu0.dtb.write_accesses                 211643                       # DTB write accesses
+system.cpu0.dtb.data_hits                    15540820                       # DTB hits
+system.cpu0.dtb.data_misses                     39703                       # DTB misses
+system.cpu0.dtb.data_acv                          670                       # DTB access violations
+system.cpu0.dtb.data_accesses                  867072                       # DTB accesses
+system.cpu0.itb.fetch_hits                    1071612                       # ITB hits
+system.cpu0.itb.fetch_misses                    26818                       # ITB misses
+system.cpu0.itb.fetch_acv                         827                       # ITB acv
+system.cpu0.itb.fetch_accesses                1098430                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -483,279 +483,279 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                       107505653                       # number of cpu cycles simulated
+system.cpu0.numCycles                       120285579                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                11783453                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           9875598                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            345606                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              8356965                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 5072042                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                13328375                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted          11156715                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            403301                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              9703007                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 5627426                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  768478                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              29315                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          25158431                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      60438649                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                   11783453                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           5840520                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                     11478099                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1678793                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles              36446213                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles               35059                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles       187963                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles       310129                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          172                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  7506544                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               232672                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples          74721559                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.808852                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.135528                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  881916                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              36485                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          30082863                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      67323144                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                   13328375                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           6509342                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                     12704270                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1925792                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles              41150259                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles               29396                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles       190626                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles       307717                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          171                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  8274450                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               278264                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples          85724819                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.785340                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.113356                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                63243460     84.64%     84.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  740935      0.99%     85.63% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                 1559450      2.09%     87.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  686263      0.92%     88.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                 2492339      3.34%     91.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  528695      0.71%     92.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  568727      0.76%     93.44% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  718688      0.96%     94.40% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 4183002      5.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                73020549     85.18%     85.18% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  838460      0.98%     86.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                 1676934      1.96%     88.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  765061      0.89%     89.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                 2646040      3.09%     92.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  584012      0.68%     92.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  626464      0.73%     93.51% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  965763      1.13%     94.63% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 4601536      5.37%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            74721559                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.109608                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.562190                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                26241114                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             36078495                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                 10432905                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               895868                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1073176                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              504459                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                32663                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              59394337                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts                93513                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1073176                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                27177088                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles               15322085                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      17293060                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  9793199                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              4062949                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              56409108                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 7164                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                656382                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1492215                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands           37953965                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups             68862069                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups        68509500                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups           352569                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             33051447                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 4902518                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts           1333146                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        200213                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                 10586539                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             8773665                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5638420                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1132750                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores          738704                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  50116530                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded            1671338                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 48856724                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued           108345                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        5942974                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined      3041199                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved       1133867                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     74721559                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.653850                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.297886                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            85724819                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.110806                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.559694                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                31004655                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             40959879                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                 11547285                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               992195                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1220804                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              569651                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                39042                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              66162079                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               119714                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1220804                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                32084617                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles               16798713                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      20265121                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                 10859034                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              4496528                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              62667463                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 6952                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                714166                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1644224                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands           41889226                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups             75909055                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups        75455060                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups           453995                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             36387256                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 5501970                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts           1564601                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        238699                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                 11969460                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             9870474                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            6474014                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1213478                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores          815744                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  55487857                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded            1996787                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 54121133                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued           111429                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6732221                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined      3352698                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved       1361171                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     85724819                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.631336                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.279357                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           52677257     70.50%     70.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1           10184833     13.63%     84.13% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            4563049      6.11%     90.24% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2984127      3.99%     94.23% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2257312      3.02%     97.25% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5            1142410      1.53%     98.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             582471      0.78%     99.56% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             283512      0.38%     99.94% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              46588      0.06%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           61209229     71.40%     71.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1           11417613     13.32%     84.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            5048858      5.89%     90.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            3283375      3.83%     94.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2508461      2.93%     97.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5            1248570      1.46%     98.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             634570      0.74%     99.56% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             321579      0.38%     99.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              52564      0.06%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       74721559                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       85724819                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  73394     11.97%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     11.97% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                287556     46.90%     58.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               252163     41.13%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  72995     10.68%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     10.68% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                324242     47.46%     58.14% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               285988     41.86%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass             4467      0.01%      0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             33933939     69.46%     69.47% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               53607      0.11%     69.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     69.57% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd              16546      0.03%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv               2231      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     69.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             8676123     17.76%     87.37% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5426873     11.11%     98.48% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess            742938      1.52%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass             4465      0.01%      0.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             37158612     68.66%     68.67% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               60272      0.11%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     68.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd              18564      0.03%     68.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.81% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv               2231      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.82% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9761868     18.04%     86.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            6247803     11.54%     98.40% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess            867318      1.60%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              48856724                       # Type of FU issued
-system.cpu0.iq.rate                          0.454457                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                     613113                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.012549                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         172655307                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         57499462                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     47860573                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads             501158                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes            243682                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses       236026                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              49203092                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                 262278                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          518007                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              54121133                       # Type of FU issued
+system.cpu0.iq.rate                          0.449939                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                     683225                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.012624                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         194116788                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         63916247                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     52959668                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads             644951                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes            312925                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses       303605                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              54462198                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                 337695                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          568272                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1116542                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         2532                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        12656                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       476196                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1280116                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         2462                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        12570                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       515440                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads        18844                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked        94055                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads        18537                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked       100807                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1073176                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles               10803844                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               780020                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           54838073                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts           560128                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              8773665                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5638420                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts           1470903                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                544426                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                 8361                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         12656                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        186168                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       328100                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              514268                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             48431034                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              8384906                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           425690                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1220804                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles               12124657                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               860720                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           60917526                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts           643294                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              9870474                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             6474014                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts           1758330                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                617908                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                 8871                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         12570                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        212626                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       388253                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              600879                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             53642657                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9419598                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           478476                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                      3050205                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    13763900                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 7759085                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5378994                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.450498                       # Inst execution rate
-system.cpu0.iew.wb_sent                      48183963                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     48096599                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 24100955                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 32404442                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                      3432882                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    15618436                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 8560068                       # Number of branches executed
+system.cpu0.iew.exec_stores                   6198838                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.445961                       # Inst execution rate
+system.cpu0.iew.wb_sent                      53356597                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     53263273                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 26352404                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 35613133                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.447387                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.743755                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.442807                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.739963                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      48294855                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        48294855                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        6449755                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         537471                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           480800                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     73648383                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.655749                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.560255                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      53500498                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        53500498                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        7330810                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         635616                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           562628                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     84504015                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.633112                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.546448                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     55233499     75.00%     75.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      7733418     10.50%     85.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      4278651      5.81%     91.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      2283988      3.10%     94.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4      1242605      1.69%     96.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       524240      0.71%     96.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       434900      0.59%     97.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       385505      0.52%     97.92% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1531577      2.08%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     64274948     76.06%     76.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      8494337     10.05%     86.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      4620943      5.47%     91.58% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      2493253      2.95%     94.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4      1382716      1.64%     96.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       578306      0.68%     96.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       482831      0.57%     97.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       448312      0.53%     97.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1728369      2.05%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     73648383                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            48294855                       # Number of instructions committed
-system.cpu0.commit.committedOps              48294855                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     84504015                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            53500498                       # Number of instructions committed
+system.cpu0.commit.committedOps              53500498                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      12819347                       # Number of memory references committed
-system.cpu0.commit.loads                      7657123                       # Number of loads committed
-system.cpu0.commit.membars                     181890                       # Number of memory barriers committed
-system.cpu0.commit.branches                   7325688                       # Number of branches committed
-system.cpu0.commit.fp_insts                    233448                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 44748779                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              610967                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1531577                       # number cycles where commit BW limit reached
+system.cpu0.commit.refs                      14548932                       # Number of memory references committed
+system.cpu0.commit.loads                      8590358                       # Number of loads committed
+system.cpu0.commit.membars                     216685                       # Number of memory barriers committed
+system.cpu0.commit.branches                   8083038                       # Number of branches committed
+system.cpu0.commit.fp_insts                    301061                       # Number of committed floating point instructions.
+system.cpu0.commit.int_insts                 49495422                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              700509                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1728369                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                   126676900                       # The number of ROB reads
-system.cpu0.rob.rob_writes                  110562172                       # The number of ROB writes
-system.cpu0.timesIdled                        1222053                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       32784094                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  3693280483                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   45533193                       # Number of Instructions Simulated
-system.cpu0.committedOps                     45533193                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             45533193                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.361039                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.361039                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.423542                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.423542                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                63859411                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               34945756                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                   117042                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                  117632                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads                1550181                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                750158                       # number of misc regfile writes
+system.cpu0.rob.rob_reads                   143428116                       # The number of ROB reads
+system.cpu0.rob.rob_writes                  122883641                       # The number of ROB writes
+system.cpu0.timesIdled                        1359099                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       34560760                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  3686357913                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   50400239                       # Number of Instructions Simulated
+system.cpu0.committedOps                     50400239                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             50400239                       # Number of Instructions Simulated
+system.cpu0.cpi                              2.386607                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        2.386607                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.419005                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.419005                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                70355564                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               38486142                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                   150309                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                  151918                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads                1870359                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                881938                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -787,245 +787,245 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                791282                       # number of replacements
-system.cpu0.icache.tagsinuse               510.000823                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 6671308                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                791794                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  8.425560                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           23654486000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   510.000823                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.996095                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.996095                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      6671308                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        6671308                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      6671308                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         6671308                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      6671308                       # number of overall hits
-system.cpu0.icache.overall_hits::total        6671308                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       835236                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       835236                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       835236                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        835236                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       835236                       # number of overall misses
-system.cpu0.icache.overall_misses::total       835236                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13775160993                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total  13775160993                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst  13775160993                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total  13775160993                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst  13775160993                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total  13775160993                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      7506544                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      7506544                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      7506544                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      7506544                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      7506544                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      7506544                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.111268                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.111268                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.111268                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.111268                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.111268                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.111268                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16492.537430                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 16492.537430                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 16492.537430                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16492.537430                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 16492.537430                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1463996                       # number of cycles access was blocked
+system.cpu0.icache.replacements                978272                       # number of replacements
+system.cpu0.icache.tagsinuse               509.990128                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 7239988                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                978784                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  7.396921                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           23947377000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   509.990128                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.996074                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.996074                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7239988                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        7239988                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      7239988                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         7239988                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      7239988                       # number of overall hits
+system.cpu0.icache.overall_hits::total        7239988                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1034461                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total      1034461                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst      1034461                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total       1034461                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst      1034461                       # number of overall misses
+system.cpu0.icache.overall_misses::total      1034461                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  16768248492                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  16768248492                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  16768248492                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  16768248492                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  16768248492                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  16768248492                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8274449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      8274449                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      8274449                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      8274449                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8274449                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      8274449                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125019                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.125019                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125019                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.125019                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125019                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.125019                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16209.647819                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16209.647819                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16209.647819                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16209.647819                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16209.647819                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16209.647819                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1517995                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              158                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              159                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs  9265.797468                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  9547.138365                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        43249                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        43249                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        43249                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        43249                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        43249                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        43249                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       791987                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       791987                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       791987                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       791987                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       791987                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       791987                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10696262996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total  10696262996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10696262996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total  10696262996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10696262996                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total  10696262996                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.105506                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.105506                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105506                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.105506                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13505.604254                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13505.604254                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13505.604254                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        55484                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        55484                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        55484                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        55484                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        55484                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        55484                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       978977                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       978977                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       978977                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       978977                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       978977                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       978977                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  12951368495                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  12951368495                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  12951368495                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  12951368495                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  12951368495                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  12951368495                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.118313                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.118313                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.118313                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.118313                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13229.492108                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13229.492108                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13229.492108                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13229.492108                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements               1206262                       # number of replacements
-system.cpu0.dcache.tagsinuse               505.874752                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 9821312                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs               1206702                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                  8.138971                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              19675000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   505.874752                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.988037                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.988037                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6113380                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6113380                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3377082                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3377082                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       150588                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       150588                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171660                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       171660                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9490462                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9490462                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9490462                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9490462                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data      1478592                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total      1478592                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1593723                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1593723                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        18660                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total        18660                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         4698                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         4698                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      3072315                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       3072315                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      3072315                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      3072315                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  41280324500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  41280324500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  65318664554                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  65318664554                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    315332000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    315332000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     68573000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     68573000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 106598989054                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 106598989054                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 106598989054                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 106598989054                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      7591972                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      7591972                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4970805                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4970805                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       169248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       169248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       176358                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       176358                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12562777                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12562777                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12562777                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12562777                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.194757                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.194757                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.320617                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.320617                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.110252                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.110252                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.026639                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.026639                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.244557                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.244557                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.244557                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.244557                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27918.671615                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 27918.671615                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40984.954446                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 40984.954446                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16898.821008                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16898.821008                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14596.211154                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14596.211154                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34696.633989                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34696.633989                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34696.633989                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs    716919646                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs            65391                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              7                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10963.582848                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
+system.cpu0.dcache.replacements               1336500                       # number of replacements
+system.cpu0.dcache.tagsinuse               506.465908                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                11143271                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1336941                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  8.334901                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle              23748000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   506.465908                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.989191                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.989191                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6824660                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6824660                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3928020                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3928020                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       181318                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       181318                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       208014                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       208014                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     10752680                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        10752680                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     10752680                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       10752680                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1708787                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1708787                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1807599                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1807599                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        22179                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        22179                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          632                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          632                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      3516386                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       3516386                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      3516386                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      3516386                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  46211851500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  46211851500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  69878054952                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  69878054952                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    400322000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    400322000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6190000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      6190000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 116089906452                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 116089906452                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 116089906452                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 116089906452                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8533447                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8533447                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5735619                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5735619                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       203497                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       203497                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       208646                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       208646                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     14269066                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14269066                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14269066                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14269066                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.200246                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.200246                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.315153                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.315153                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.108989                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.108989                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003029                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.003029                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.246434                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.246434                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.246434                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.246434                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27043.658162                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27043.658162                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38657.940700                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38657.940700                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 18049.596465                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 18049.596465                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9794.303797                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9794.303797                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33013.982666                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33013.982666                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33013.982666                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33013.982666                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs    743236979                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets       140000                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs            67742                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets              5                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10971.583050                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets        28000                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       693314                       # number of writebacks
-system.cpu0.dcache.writebacks::total           693314                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       515793                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       515793                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1344404                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1344404                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         3762                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total         3762                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1860197                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1860197                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1860197                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1860197                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       962799                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       962799                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       249319                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       249319                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        14898                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total        14898                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         4698                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         4698                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data      1212118                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total      1212118                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data      1212118                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total      1212118                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  25944695097                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  25944695097                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8701407966                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8701407966                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    186837501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    186837501                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     53961001                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     53961001                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  34646103063                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  34646103063                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  34646103063                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  34646103063                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    918480000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    918480000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1327721998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1327721998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2246201998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2246201998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.126818                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.126818                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.050157                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.050157                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.088025                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.088025                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.026639                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.026639                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.096485                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.096485                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.096485                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26947.156257                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26947.156257                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34900.701375                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34900.701375                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12541.112968                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12541.112968                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11485.951682                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11485.951682                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 28583.110772                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 28583.110772                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       787469                       # number of writebacks
+system.cpu0.dcache.writebacks::total           787469                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       665447                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       665447                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1525035                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1525035                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4877                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4877                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2190482                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2190482                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2190482                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2190482                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1043340                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1043340                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       282564                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       282564                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        17302                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        17302                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          632                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          632                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1325904                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1325904                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1325904                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1325904                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  27425552538                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  27425552538                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   9314976366                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   9314976366                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    247730500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    247730500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4222000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4222000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  36740528904                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  36740528904                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  36740528904                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  36740528904                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1454814000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1454814000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2057449498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2057449498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3512263498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3512263498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122265                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122265                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049265                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049265                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085023                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.085023                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003029                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.003029                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092922                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.092922                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092922                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.092922                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26286.304118                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26286.304118                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32965.899287                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32965.899287                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14318.026818                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14318.026818                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6680.379747                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6680.379747                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27709.795659                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27709.795659                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27709.795659                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 27709.795659                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1037,22 +1037,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     2497958                       # DTB read hits
-system.cpu1.dtb.read_misses                     12385                       # DTB read misses
-system.cpu1.dtb.read_acv                          105                       # DTB read access violations
-system.cpu1.dtb.read_accesses                  312687                       # DTB read accesses
-system.cpu1.dtb.write_hits                    1734137                       # DTB write hits
-system.cpu1.dtb.write_misses                     3404                       # DTB write misses
-system.cpu1.dtb.write_acv                         137                       # DTB write access violations
-system.cpu1.dtb.write_accesses                 131810                       # DTB write accesses
-system.cpu1.dtb.data_hits                     4232095                       # DTB hits
-system.cpu1.dtb.data_misses                     15789                       # DTB misses
-system.cpu1.dtb.data_acv                          242                       # DTB access violations
-system.cpu1.dtb.data_accesses                  444497                       # DTB accesses
-system.cpu1.itb.fetch_hits                     488697                       # ITB hits
-system.cpu1.itb.fetch_misses                     8773                       # ITB misses
-system.cpu1.itb.fetch_acv                         366                       # ITB acv
-system.cpu1.itb.fetch_accesses                 497470                       # ITB accesses
+system.cpu1.dtb.read_hits                     1316259                       # DTB read hits
+system.cpu1.dtb.read_misses                     12259                       # DTB read misses
+system.cpu1.dtb.read_acv                          114                       # DTB read access violations
+system.cpu1.dtb.read_accesses                  313045                       # DTB read accesses
+system.cpu1.dtb.write_hits                     810694                       # DTB write hits
+system.cpu1.dtb.write_misses                     3210                       # DTB write misses
+system.cpu1.dtb.write_acv                         140                       # DTB write access violations
+system.cpu1.dtb.write_accesses                 130863                       # DTB write accesses
+system.cpu1.dtb.data_hits                     2126953                       # DTB hits
+system.cpu1.dtb.data_misses                     15469                       # DTB misses
+system.cpu1.dtb.data_acv                          254                       # DTB access violations
+system.cpu1.dtb.data_accesses                  443908                       # DTB accesses
+system.cpu1.itb.fetch_hits                     378821                       # ITB hits
+system.cpu1.itb.fetch_misses                     8734                       # ITB misses
+system.cpu1.itb.fetch_acv                         397                       # ITB acv
+system.cpu1.itb.fetch_accesses                 387555                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -1065,518 +1065,518 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                        22715640                       # number of cpu cycles simulated
+system.cpu1.numCycles                        10995031                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 3441563                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           2848590                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            108508                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              2344214                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 1191088                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 1761936                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           1452774                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect             65512                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups               889011                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                  565473                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  236176                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              10617                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles           9035553                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      16314409                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    3441563                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           1427264                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                      2922038                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                 525528                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles               8308395                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles               28029                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        86548                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles        64086                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles           30                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  1962045                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                75286                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples          20775175                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.785284                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.154306                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  118681                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect               6179                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles           3538328                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                       8413663                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    1761936                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches            684154                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                      1515563                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                 337074                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles               4688566                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles               24381                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        85396                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles        48035                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           31                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  1081640                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                43091                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples          10121394                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.831275                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.201855                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                17853137     85.93%     85.93% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  203247      0.98%     86.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                  300737      1.45%     88.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                  225181      1.08%     89.44% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                  403762      1.94%     91.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  151742      0.73%     92.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                  164996      0.79%     92.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  308573      1.49%     94.40% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 1163800      5.60%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                 8605831     85.03%     85.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   83210      0.82%     85.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                  170185      1.68%     87.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                  136768      1.35%     88.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                  220692      2.18%     91.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   89992      0.89%     91.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                  103416      1.02%     92.97% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                   63845      0.63%     93.60% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                  647455      6.40%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total            20775175                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.151506                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.718202                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                 8809071                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles              8765539                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                  2707216                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               172890                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                320458                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved              151147                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred                10158                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              16014026                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts                29482                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles                320458                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                 9091295                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                 884150                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles       6951341                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                  2592964                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles               934965                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              14837454                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                  127                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                 84091                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents               280482                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands            9656446                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups             17623003                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups        17415204                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups           207799                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps              8330618                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                 1325820                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            594023                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts         64559                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  2775443                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads             2639269                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            1825014                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads           248716                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores          160479                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  12970444                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded             664664                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 12696455                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued            35550                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined        1743951                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined       828101                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        468923                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples     20775175                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.611136                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.284217                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total            10121394                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.160248                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.765224                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                 3636179                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles              4783124                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                  1407347                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                79113                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                215630                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved               78857                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred                 5594                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts               8201368                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts                16988                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles                215630                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                 3774532                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                 581193                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles       3715501                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                  1338240                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles               496296                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts               7575516                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                  144                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                 44770                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents               149873                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands            5044245                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups              9199948                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups         9159980                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            39968                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps              4092104                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                  952133                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            317142                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts         23346                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  1397635                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads             1414528                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores             877825                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads           136527                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores          116556                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                   6675821                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded             314231                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                  6372058                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued            25577                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined        1212482                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined       668533                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        238569                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples     10121394                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.629563                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.309947                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           15113498     72.75%     72.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            2653136     12.77%     85.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            1113601      5.36%     90.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3             723121      3.48%     94.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4             602829      2.90%     97.26% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5             288191      1.39%     98.65% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6             181892      0.88%     99.52% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7              88125      0.42%     99.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              10782      0.05%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0            7322432     72.35%     72.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            1274873     12.60%     84.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2             565463      5.59%     90.53% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3             381432      3.77%     94.30% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4             276297      2.73%     97.03% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5             150290      1.48%     98.51% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6              93014      0.92%     99.43% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7              53503      0.53%     99.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8               4090      0.04%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total       20775175                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total       10121394                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                   3857      1.52%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                134714     53.16%     54.69% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               114823     45.31%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                   2751      1.84%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      1.84% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                 83898     56.09%     57.93% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                62938     42.07%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass             2823      0.02%      0.02% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu              7925481     62.42%     62.45% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               20760      0.16%     62.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.61% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd              10544      0.08%     62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.69% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv               1411      0.01%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.70% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead             2621698     20.65%     83.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            1764339     13.90%     97.25% # Type of FU issued
-system.cpu1.iq.FU_type_0::IprAccess            349399      2.75%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass             2823      0.04%      0.04% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu              3945332     61.92%     61.96% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                9935      0.16%     62.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     62.12% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd               7188      0.11%     62.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     62.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     62.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     62.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv               1411      0.02%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     62.25% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead             1374762     21.57%     83.83% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite             831632     13.05%     96.88% # Type of FU issued
+system.cpu1.iq.FU_type_0::IprAccess            198975      3.12%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              12696455                       # Type of FU issued
-system.cpu1.iq.rate                          0.558930                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                     253394                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.019958                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads          46157750                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         15236198                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     12337265                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads             299278                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes            145041                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses       140795                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              12790304                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                 156722                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          115188                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total               6372058                       # Type of FU issued
+system.cpu1.iq.rate                          0.579540                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                     149587                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.023475                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads          22982123                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes          8175044                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses      6195827                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              58550                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes             29266                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses        28229                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses               6488697                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                  30125                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads           71376                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads       346106                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses          806                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation         2268                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores       152574                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads       250758                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses          518                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation         1865                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores       114138                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads          376                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked        11381                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads          364                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked        10621                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                320458                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                 536973                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                73252                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           14361364                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           205800                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts              2639269                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             1825014                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            596393                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 55379                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 5710                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents          2268                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect         53644                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       129908                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              183552                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             12575424                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts              2521777                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts           121030                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles                215630                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                 327250                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                19053                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts            7270048                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           103390                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts              1414528                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts              877825                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            292634                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                  6157                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                 4769                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents          1865                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect         31136                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect        75519                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              106655                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts              6299419                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts              1333225                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts            72638                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       726256                       # number of nop insts executed
-system.cpu1.iew.exec_refs                     4267761                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 1886646                       # Number of branches executed
-system.cpu1.iew.exec_stores                   1745984                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.553602                       # Inst execution rate
-system.cpu1.iew.wb_sent                      12512047                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     12478060                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                  5698826                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                  8037620                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       279996                       # number of nop insts executed
+system.cpu1.iew.exec_refs                     2150860                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                  922163                       # Number of branches executed
+system.cpu1.iew.exec_stores                    817635                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.572933                       # Inst execution rate
+system.cpu1.iew.wb_sent                       6254968                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                      6224056                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                  2925555                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                  4065237                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.549316                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.709019                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.566079                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.719652                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      12432644                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps        12432644                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts        1853978                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         195741                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           172939                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples     20454717                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.607813                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.554325                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts       5954935                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps         5954935                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts        1244518                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls          75662                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts            99560                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples      9905764                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.601159                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.526173                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     15840554     77.44%     77.44% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      2123906     10.38%     87.83% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2       810748      3.96%     91.79% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3       497113      2.43%     94.22% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4       362163      1.77%     95.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       133438      0.65%     96.64% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6       130960      0.64%     97.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       152379      0.74%     98.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8       403456      1.97%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0      7610675     76.83%     76.83% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      1117297     11.28%     88.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2       392466      3.96%     92.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3       237967      2.40%     94.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4       150669      1.52%     96.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        70627      0.71%     96.71% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6        80896      0.82%     97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7        63718      0.64%     98.17% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8       181449      1.83%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total     20454717                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            12432644                       # Number of instructions committed
-system.cpu1.commit.committedOps              12432644                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total      9905764                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts             5954935                       # Number of instructions committed
+system.cpu1.commit.committedOps               5954935                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                       3965603                       # Number of memory references committed
-system.cpu1.commit.loads                      2293163                       # Number of loads committed
-system.cpu1.commit.membars                      64660                       # Number of memory barriers committed
-system.cpu1.commit.branches                   1777364                       # Number of branches committed
-system.cpu1.commit.fp_insts                    139699                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 11487490                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              194670                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events               403456                       # number cycles where commit BW limit reached
+system.cpu1.commit.refs                       1927457                       # Number of memory references committed
+system.cpu1.commit.loads                      1163770                       # Number of loads committed
+system.cpu1.commit.membars                      20047                       # Number of memory barriers committed
+system.cpu1.commit.branches                    840841                       # Number of branches committed
+system.cpu1.commit.fp_insts                     27263                       # Number of committed floating point instructions.
+system.cpu1.commit.int_insts                  5573216                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls               89926                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events               181449                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                    34231845                       # The number of ROB reads
-system.cpu1.rob.rob_writes                   28892260                       # The number of ROB writes
-system.cpu1.timesIdled                         230897                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                        1940465                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  3778342351                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   11788689                       # Number of Instructions Simulated
-system.cpu1.committedOps                     11788689                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             11788689                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.926901                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.926901                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.518968                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.518968                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                16191128                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                8793643                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                    73550                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                   74224                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 699686                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                299450                       # number of misc regfile writes
-system.cpu1.icache.replacements                315418                       # number of replacements
-system.cpu1.icache.tagsinuse               471.006638                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 1633897                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                315930                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                  5.171706                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1877367216000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   471.006638                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.919935                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.919935                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      1633897                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        1633897                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      1633897                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         1633897                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      1633897                       # number of overall hits
-system.cpu1.icache.overall_hits::total        1633897                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       328148                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       328148                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       328148                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        328148                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       328148                       # number of overall misses
-system.cpu1.icache.overall_misses::total       328148                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   5323185498                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   5323185498                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   5323185498                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   5323185498                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   5323185498                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   5323185498                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      1962045                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      1962045                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      1962045                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      1962045                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      1962045                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      1962045                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.167248                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.167248                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.167248                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.167248                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.167248                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.167248                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16221.904439                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 16221.904439                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 16221.904439                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16221.904439                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 16221.904439                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs       248998                       # number of cycles access was blocked
+system.cpu1.rob.rob_reads                    16822912                       # The number of ROB reads
+system.cpu1.rob.rob_writes                   14613272                       # The number of ROB writes
+system.cpu1.timesIdled                          86532                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                         873637                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  3796008743                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                    5721018                       # Number of Instructions Simulated
+system.cpu1.committedOps                      5721018                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total              5721018                       # Number of Instructions Simulated
+system.cpu1.cpi                              1.921866                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        1.921866                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.520328                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.520328                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                 8196384                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                4468767                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                    18086                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                   17123                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads                 275818                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                138963                       # number of misc regfile writes
+system.cpu1.icache.replacements                112877                       # number of replacements
+system.cpu1.icache.tagsinuse               455.325853                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                  961616                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                113389                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                  8.480682                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1880828738000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   455.325853                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.889308                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.889308                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst       961616                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         961616                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       961616                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          961616                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       961616                       # number of overall hits
+system.cpu1.icache.overall_hits::total         961616                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       120024                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       120024                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       120024                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        120024                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       120024                       # number of overall misses
+system.cpu1.icache.overall_misses::total       120024                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1993076499                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   1993076499                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   1993076499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   1993076499                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   1993076499                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   1993076499                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1081640                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      1081640                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      1081640                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      1081640                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1081640                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      1081640                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.110965                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.110965                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.110965                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.110965                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.110965                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.110965                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16605.649695                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 16605.649695                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16605.649695                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 16605.649695                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16605.649695                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 16605.649695                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs       288999                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs               42                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs               50                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  5928.523810                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  5779.980000                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        12162                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        12162                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        12162                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        12162                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        12162                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        12162                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       315986                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       315986                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       315986                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       315986                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       315986                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       315986                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   4183764998                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   4183764998                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   4183764998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   4183764998                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   4183764998                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   4183764998                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.161049                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.161049                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.161049                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.161049                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13240.349250                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13240.349250                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13240.349250                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         6586                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         6586                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         6586                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         6586                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         6586                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         6586                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       113438                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       113438                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       113438                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       113438                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       113438                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       113438                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1550619499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   1550619499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1550619499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   1550619499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1550619499                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   1550619499                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.104876                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.104876                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.104876                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.104876                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13669.312744                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13669.312744                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13669.312744                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13669.312744                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                159031                       # number of replacements
-system.cpu1.dcache.tagsinuse               488.853384                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 3387429                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                159543                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 21.232075                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           42819944000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   488.853384                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.954792                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.954792                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      2021122                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        2021122                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      1250999                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       1250999                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        49956                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        49956                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        48601                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        48601                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      3272121                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         3272121                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      3272121                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        3272121                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       307358                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       307358                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       360875                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       360875                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         8692                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total         8692                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data         5047                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total         5047                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       668233                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        668233                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       668233                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       668233                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   6376981500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   6376981500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  11324805298                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  11324805298                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    121402000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    121402000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     68410000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     68410000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  17701786798                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  17701786798                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  17701786798                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  17701786798                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      2328480                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      2328480                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      1611874                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      1611874                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        58648                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        58648                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        53648                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        53648                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      3940354                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      3940354                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      3940354                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      3940354                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.131999                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.131999                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223885                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.223885                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.148206                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.148206                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.094076                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.094076                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.169587                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.169587                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.169587                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.169587                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20747.732286                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 20747.732286                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31381.517972                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 31381.517972                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.096180                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13967.096180                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13554.586883                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13554.586883                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 26490.440906                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26490.440906                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 26490.440906                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     57267488                       # number of cycles access was blocked
+system.cpu1.dcache.replacements                 66353                       # number of replacements
+system.cpu1.dcache.tagsinuse               422.855509                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1693567                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                 66865                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 25.328154                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1880297916000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   422.855509                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.825890                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.825890                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1103263                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        1103263                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       554602                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        554602                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        16904                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        16904                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        15090                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        15090                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      1657865                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1657865                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      1657865                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1657865                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       120863                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       120863                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       188065                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       188065                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1871                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         1871                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          714                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          714                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       308928                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        308928                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       308928                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       308928                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2422870500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2422870500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   7680920661                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   7680920661                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     31721000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     31721000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8263500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      8263500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  10103791161                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  10103791161                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  10103791161                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  10103791161                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1224126                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1224126                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       742667                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       742667                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        18775                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        18775                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        15804                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        15804                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      1966793                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      1966793                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      1966793                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      1966793                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.098734                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.098734                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.253229                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.253229                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099654                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.099654                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.045178                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.045178                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.157072                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.157072                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.157072                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.157072                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20046.420327                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 20046.420327                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40841.840114                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 40841.840114                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16954.035275                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16954.035275                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 11573.529412                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 11573.529412                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32705.974081                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 32705.974081                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32705.974081                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 32705.974081                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     54269989                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6761                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6147                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8470.268895                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  8828.695136                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       112725                       # number of writebacks
-system.cpu1.dcache.writebacks::total           112725                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       197085                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       197085                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       298748                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total       298748                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1016                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1016                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data       495833                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total       495833                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data       495833                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total       495833                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       110273                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       110273                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        62127                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total        62127                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         7676                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total         7676                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         5047                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total         5047                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       172400                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       172400                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       172400                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       172400                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1761266064                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1761266064                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   1471935334                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   1471935334                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     78208000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     78208000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52884501                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52884501                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   3233201398                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   3233201398                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   3233201398                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   3233201398                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     18624000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     18624000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    400633000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    400633000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    419257000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    419257000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.047358                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.047358                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.038543                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.038543                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.130883                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.130883                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.094076                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.094076                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.043752                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.043752                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.043752                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15971.870394                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15971.870394                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23692.361357                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23692.361357                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10188.639917                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10188.639917                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10478.403210                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10478.403210                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.068434                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18754.068434                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks        44452                       # number of writebacks
+system.cpu1.dcache.writebacks::total            44452                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        76735                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        76735                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       160629                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       160629                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          625                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          625                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       237364                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       237364                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       237364                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       237364                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        44128                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        44128                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        27436                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        27436                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1246                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1246                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          712                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          712                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data        71564                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total        71564                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data        71564                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total        71564                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    680335003                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    680335003                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    908440847                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    908440847                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     14899501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     14899501                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6048501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6048501                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1588775850                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1588775850                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1588775850                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1588775850                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     26654500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     26654500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    549434000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    549434000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    576088500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    576088500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.036049                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.036049                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.036943                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.036943                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.066365                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.066365                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.045052                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.045052                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.036386                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.036386                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.036386                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.036386                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15417.308806                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15417.308806                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33111.271577                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33111.271577                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11957.865971                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.865971                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  8495.085674                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  8495.085674                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22200.769242                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22200.769242                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22200.769242                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22200.769242                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1585,171 +1585,171 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    6699                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    167511                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   58590     40.24%     40.24% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    238      0.16%     40.40% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1924      1.32%     41.72% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                    340      0.23%     41.96% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  84510     58.04%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              145602                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    57892     49.08%     49.08% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     238      0.20%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1924      1.63%     50.92% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                     340      0.29%     51.20% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   57552     48.80%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total               117946                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1862592154000     98.01%     98.01% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               96215500      0.01%     98.02% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              394866000      0.02%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30              155183500      0.01%     98.04% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            37157983500      1.96%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1900396402500                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.988087                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6363                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    198040                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   71346     40.60%     40.60% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    130      0.07%     40.67% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1927      1.10%     41.77% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      6      0.00%     41.77% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 102331     58.23%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              175740                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    69979     49.28%     49.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     130      0.09%     49.37% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1927      1.36%     50.72% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   69973     49.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               142015                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1862552849000     97.86%     97.86% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21               68272000      0.00%     97.86% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              582924500      0.03%     97.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                4256000      0.00%     97.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            40116611000      2.11%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1903324912500                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.980840                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.681008                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.810058                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.syscall::2                         5      2.38%      2.38% # number of syscalls executed
-system.cpu0.kern.syscall::3                        18      8.57%     10.95% # number of syscalls executed
-system.cpu0.kern.syscall::4                         3      1.43%     12.38% # number of syscalls executed
-system.cpu0.kern.syscall::6                        28     13.33%     25.71% # number of syscalls executed
-system.cpu0.kern.syscall::12                        1      0.48%     26.19% # number of syscalls executed
-system.cpu0.kern.syscall::15                        1      0.48%     26.67% # number of syscalls executed
-system.cpu0.kern.syscall::17                        9      4.29%     30.95% # number of syscalls executed
-system.cpu0.kern.syscall::19                        5      2.38%     33.33% # number of syscalls executed
-system.cpu0.kern.syscall::20                        4      1.90%     35.24% # number of syscalls executed
-system.cpu0.kern.syscall::23                        2      0.95%     36.19% # number of syscalls executed
-system.cpu0.kern.syscall::24                        4      1.90%     38.10% # number of syscalls executed
-system.cpu0.kern.syscall::33                        7      3.33%     41.43% # number of syscalls executed
-system.cpu0.kern.syscall::41                        2      0.95%     42.38% # number of syscalls executed
-system.cpu0.kern.syscall::45                       35     16.67%     59.05% # number of syscalls executed
-system.cpu0.kern.syscall::47                        4      1.90%     60.95% # number of syscalls executed
-system.cpu0.kern.syscall::48                        6      2.86%     63.81% # number of syscalls executed
-system.cpu0.kern.syscall::54                        9      4.29%     68.10% # number of syscalls executed
-system.cpu0.kern.syscall::58                        1      0.48%     68.57% # number of syscalls executed
-system.cpu0.kern.syscall::59                        4      1.90%     70.48% # number of syscalls executed
-system.cpu0.kern.syscall::71                       32     15.24%     85.71% # number of syscalls executed
-system.cpu0.kern.syscall::73                        3      1.43%     87.14% # number of syscalls executed
-system.cpu0.kern.syscall::74                        9      4.29%     91.43% # number of syscalls executed
-system.cpu0.kern.syscall::87                        1      0.48%     91.90% # number of syscalls executed
-system.cpu0.kern.syscall::90                        1      0.48%     92.38% # number of syscalls executed
-system.cpu0.kern.syscall::92                        7      3.33%     95.71% # number of syscalls executed
-system.cpu0.kern.syscall::97                        2      0.95%     96.67% # number of syscalls executed
-system.cpu0.kern.syscall::98                        2      0.95%     97.62% # number of syscalls executed
-system.cpu0.kern.syscall::132                       2      0.95%     98.57% # number of syscalls executed
-system.cpu0.kern.syscall::144                       1      0.48%     99.05% # number of syscalls executed
-system.cpu0.kern.syscall::147                       2      0.95%    100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total                   210                       # number of syscalls executed
+system.cpu0.kern.ipl_used::31                0.683791                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808097                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.syscall::2                         5      2.35%      2.35% # number of syscalls executed
+system.cpu0.kern.syscall::3                        18      8.45%     10.80% # number of syscalls executed
+system.cpu0.kern.syscall::4                         3      1.41%     12.21% # number of syscalls executed
+system.cpu0.kern.syscall::6                        28     13.15%     25.35% # number of syscalls executed
+system.cpu0.kern.syscall::12                        1      0.47%     25.82% # number of syscalls executed
+system.cpu0.kern.syscall::15                        1      0.47%     26.29% # number of syscalls executed
+system.cpu0.kern.syscall::17                        9      4.23%     30.52% # number of syscalls executed
+system.cpu0.kern.syscall::19                        5      2.35%     32.86% # number of syscalls executed
+system.cpu0.kern.syscall::20                        4      1.88%     34.74% # number of syscalls executed
+system.cpu0.kern.syscall::23                        2      0.94%     35.68% # number of syscalls executed
+system.cpu0.kern.syscall::24                        4      1.88%     37.56% # number of syscalls executed
+system.cpu0.kern.syscall::33                        7      3.29%     40.85% # number of syscalls executed
+system.cpu0.kern.syscall::41                        2      0.94%     41.78% # number of syscalls executed
+system.cpu0.kern.syscall::45                       38     17.84%     59.62% # number of syscalls executed
+system.cpu0.kern.syscall::47                        4      1.88%     61.50% # number of syscalls executed
+system.cpu0.kern.syscall::48                        6      2.82%     64.32% # number of syscalls executed
+system.cpu0.kern.syscall::54                        9      4.23%     68.54% # number of syscalls executed
+system.cpu0.kern.syscall::58                        1      0.47%     69.01% # number of syscalls executed
+system.cpu0.kern.syscall::59                        4      1.88%     70.89% # number of syscalls executed
+system.cpu0.kern.syscall::71                       32     15.02%     85.92% # number of syscalls executed
+system.cpu0.kern.syscall::73                        3      1.41%     87.32% # number of syscalls executed
+system.cpu0.kern.syscall::74                        9      4.23%     91.55% # number of syscalls executed
+system.cpu0.kern.syscall::87                        1      0.47%     92.02% # number of syscalls executed
+system.cpu0.kern.syscall::90                        1      0.47%     92.49% # number of syscalls executed
+system.cpu0.kern.syscall::92                        7      3.29%     95.77% # number of syscalls executed
+system.cpu0.kern.syscall::97                        2      0.94%     96.71% # number of syscalls executed
+system.cpu0.kern.syscall::98                        2      0.94%     97.65% # number of syscalls executed
+system.cpu0.kern.syscall::132                       2      0.94%     98.59% # number of syscalls executed
+system.cpu0.kern.syscall::144                       1      0.47%     99.06% # number of syscalls executed
+system.cpu0.kern.syscall::147                       2      0.94%    100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total                   213                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                  439      0.29%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.29% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 3076      2.00%      2.29% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      37      0.02%      2.32% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.00%      2.32% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               138811     90.43%     92.75% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6361      4.14%     96.89% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.89% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     3      0.00%     96.89% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     6      0.00%     96.90% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.90% # number of callpals executed
-system.cpu0.kern.callpal::rti                    4288      2.79%     99.69% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 327      0.21%     99.90% # number of callpals executed
-system.cpu0.kern.callpal::imb                     146      0.10%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                153508                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             6690                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1099                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                  103      0.06%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.06% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3753      2.03%      2.09% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      37      0.02%      2.11% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.12% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               169151     91.71%     93.83% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6371      3.45%     97.28% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.28% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     3      0.00%     97.28% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     6      0.00%     97.29% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.29% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4525      2.45%     99.74% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 331      0.18%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     146      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                184440                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             6935                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1104                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1099                      
-system.cpu0.kern.mode_good::user                 1099                      
+system.cpu0.kern.mode_good::kernel               1104                      
+system.cpu0.kern.mode_good::user                 1104                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.164275                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.159193                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.282193                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1897960603000     99.90%     99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          1864923000      0.10%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.274661                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1900909928000     99.90%     99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          1870692000      0.10%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3077                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3754                       # number of times the context was actually changed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    2601                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                     74469                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   24566     38.36%     38.36% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1923      3.00%     41.37% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                    439      0.69%     42.05% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  37109     57.95%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total               64037                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    23887     48.07%     48.07% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1923      3.87%     51.93% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                     439      0.88%     52.82% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   23448     47.18%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                49697                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1870827131500     98.44%     98.44% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              343570500      0.02%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30              182754500      0.01%     98.46% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            29175936000      1.54%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1900529392500                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.972360                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2268                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     39512                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                   10294     33.41%     33.41% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1926      6.25%     39.66% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                    103      0.33%     40.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  18486     60.00%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               30809                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                    10284     45.72%     45.72% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1926      8.56%     54.28% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                     103      0.46%     54.74% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                   10181     45.26%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                22494                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1876458068500     98.58%     98.58% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              533952000      0.03%     98.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               54130500      0.00%     98.61% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            26455983000      1.39%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1903502134000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.999029                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.631868                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.776067                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.syscall::2                         3      2.59%      2.59% # number of syscalls executed
-system.cpu1.kern.syscall::3                        12     10.34%     12.93% # number of syscalls executed
-system.cpu1.kern.syscall::4                         1      0.86%     13.79% # number of syscalls executed
-system.cpu1.kern.syscall::6                        14     12.07%     25.86% # number of syscalls executed
-system.cpu1.kern.syscall::17                        6      5.17%     31.03% # number of syscalls executed
-system.cpu1.kern.syscall::19                        5      4.31%     35.34% # number of syscalls executed
-system.cpu1.kern.syscall::20                        2      1.72%     37.07% # number of syscalls executed
-system.cpu1.kern.syscall::23                        2      1.72%     38.79% # number of syscalls executed
-system.cpu1.kern.syscall::24                        2      1.72%     40.52% # number of syscalls executed
-system.cpu1.kern.syscall::33                        4      3.45%     43.97% # number of syscalls executed
-system.cpu1.kern.syscall::45                       19     16.38%     60.34% # number of syscalls executed
-system.cpu1.kern.syscall::47                        2      1.72%     62.07% # number of syscalls executed
-system.cpu1.kern.syscall::48                        4      3.45%     65.52% # number of syscalls executed
-system.cpu1.kern.syscall::54                        1      0.86%     66.38% # number of syscalls executed
-system.cpu1.kern.syscall::59                        3      2.59%     68.97% # number of syscalls executed
-system.cpu1.kern.syscall::71                       22     18.97%     87.93% # number of syscalls executed
-system.cpu1.kern.syscall::74                        7      6.03%     93.97% # number of syscalls executed
-system.cpu1.kern.syscall::90                        2      1.72%     95.69% # number of syscalls executed
-system.cpu1.kern.syscall::92                        2      1.72%     97.41% # number of syscalls executed
-system.cpu1.kern.syscall::132                       2      1.72%     99.14% # number of syscalls executed
-system.cpu1.kern.syscall::144                       1      0.86%    100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total                   116                       # number of syscalls executed
+system.cpu1.kern.ipl_used::31                0.550741                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.730111                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.syscall::2                         3      2.65%      2.65% # number of syscalls executed
+system.cpu1.kern.syscall::3                        12     10.62%     13.27% # number of syscalls executed
+system.cpu1.kern.syscall::4                         1      0.88%     14.16% # number of syscalls executed
+system.cpu1.kern.syscall::6                        14     12.39%     26.55% # number of syscalls executed
+system.cpu1.kern.syscall::17                        6      5.31%     31.86% # number of syscalls executed
+system.cpu1.kern.syscall::19                        5      4.42%     36.28% # number of syscalls executed
+system.cpu1.kern.syscall::20                        2      1.77%     38.05% # number of syscalls executed
+system.cpu1.kern.syscall::23                        2      1.77%     39.82% # number of syscalls executed
+system.cpu1.kern.syscall::24                        2      1.77%     41.59% # number of syscalls executed
+system.cpu1.kern.syscall::33                        4      3.54%     45.13% # number of syscalls executed
+system.cpu1.kern.syscall::45                       16     14.16%     59.29% # number of syscalls executed
+system.cpu1.kern.syscall::47                        2      1.77%     61.06% # number of syscalls executed
+system.cpu1.kern.syscall::48                        4      3.54%     64.60% # number of syscalls executed
+system.cpu1.kern.syscall::54                        1      0.88%     65.49% # number of syscalls executed
+system.cpu1.kern.syscall::59                        3      2.65%     68.14% # number of syscalls executed
+system.cpu1.kern.syscall::71                       22     19.47%     87.61% # number of syscalls executed
+system.cpu1.kern.syscall::74                        7      6.19%     93.81% # number of syscalls executed
+system.cpu1.kern.syscall::90                        2      1.77%     95.58% # number of syscalls executed
+system.cpu1.kern.syscall::92                        2      1.77%     97.35% # number of syscalls executed
+system.cpu1.kern.syscall::132                       2      1.77%     99.12% # number of syscalls executed
+system.cpu1.kern.syscall::144                       1      0.88%    100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total                   113                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                  340      0.51%      0.51% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.51% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.52% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 1824      2.74%      3.26% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      16      0.02%      3.28% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      3.29% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                57994     87.22%     90.51% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2394      3.60%     94.11% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     94.12% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     4      0.01%     94.12% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     3      0.00%     94.13% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     94.13% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3680      5.53%     99.66% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 188      0.28%     99.95% # number of callpals executed
-system.cpu1.kern.callpal::imb                      34      0.05%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  478      1.50%      1.53% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      16      0.05%      1.58% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.60% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                26108     81.82%     83.42% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2389      7.49%     90.91% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.91% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     4      0.01%     90.92% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     3      0.01%     90.93% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     90.94% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2671      8.37%     99.31% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 184      0.58%     99.89% # number of callpals executed
+system.cpu1.kern.callpal::imb                      34      0.11%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                 66492                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2119                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                641                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2717                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel               1003                      
-system.cpu1.kern.mode_good::user                  641                      
-system.cpu1.kern.mode_good::idle                  362                      
-system.cpu1.kern.mode_switch_good::kernel     0.473336                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 31908                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel             1099                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                634                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2051                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                660                      
+system.cpu1.kern.mode_good::user                  634                      
+system.cpu1.kern.mode_good::idle                   26                      
+system.cpu1.kern.mode_switch_good::kernel     0.600546                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.133235                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.366259                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel        7877089500      0.41%      0.41% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user           911545000      0.05%      0.46% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1891740750000     99.54%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    1825                       # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle      0.012677                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.348837                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        2247097500      0.12%      0.12% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user           912883500      0.05%      0.17% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1900342145000     99.83%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     479                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 0374f29eafad80a02e80a5e26d8970e7e997988f..76702c28f9d3f9930ce3ba6500caf41495c708f0 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.864424                       # Number of seconds simulated
-sim_ticks                                1864423957500                       # Number of ticks simulated
-final_tick                               1864423957500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.864443                       # Number of seconds simulated
+sim_ticks                                1864443445500                       # Number of ticks simulated
+final_tick                               1864443445500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 128916                       # Simulator instruction rate (inst/s)
-host_op_rate                                   128916                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4527170908                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303408                       # Number of bytes of host memory used
-host_seconds                                   411.83                       # Real time elapsed on the host
-sim_insts                                    53091408                       # Number of instructions simulated
-sim_ops                                      53091408                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            967616                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24878144                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2652032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28497792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       967616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          967616                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7517760                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7517760                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15119                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388721                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41438                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                445278                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          117465                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               117465                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               518989                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             13343609                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1422440                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                15285039                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          518989                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             518989                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           4032216                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                4032216                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           4032216                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              518989                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            13343609                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1422440                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               19317254                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        338334                       # number of replacements
-system.l2c.tagsinuse                     65348.280232                       # Cycle average of tags in use
-system.l2c.total_refs                         2564971                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        403499                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.356821                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    4861120000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        53937.270475                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           5353.133006                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6057.876752                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.823017                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.081682                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.092436                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.997136                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst             1009873                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              829098                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1838971                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          842689                       # number of Writeback hits
-system.l2c.Writeback_hits::total               842689                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               35                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  35                       # number of UpgradeReq hits
+host_inst_rate                                 198323                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198323                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6987525181                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 299164                       # Number of bytes of host memory used
+host_seconds                                   266.82                       # Real time elapsed on the host
+sim_insts                                    52917560                       # Number of instructions simulated
+sim_ops                                      52917560                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            968960                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24880000                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2652288                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28501248                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       968960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          968960                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7519232                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7519232                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              15140                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388750                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41442                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                445332                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          117488                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               117488                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               519705                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             13344465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1422563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                15286732                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          519705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             519705                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           4032963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                4032963                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           4032963                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              519705                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            13344465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1422563                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               19319696                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        338394                       # number of replacements
+system.l2c.tagsinuse                     65347.941058                       # Cycle average of tags in use
+system.l2c.total_refs                         2558628                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        403561                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.340127                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    4870004000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        53835.098828                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5353.738970                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6159.103260                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.821458                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.081692                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.093980                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.997130                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst             1006554                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              827784                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1834338                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          840935                       # number of Writeback hits
+system.l2c.Writeback_hits::total               840935                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu.data              3                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 3                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            185872                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               185872                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst              1009873                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1014970                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2024843                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst             1009873                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1014970                       # number of overall hits
-system.l2c.overall_hits::total                2024843                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             15121                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            273859                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               288980                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            185458                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               185458                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst              1006554                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1013242                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2019796                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst             1006554                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1013242                       # number of overall hits
+system.l2c.overall_hits::total                2019796                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.inst             15142                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            273892                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               289034                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu.data             50                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                50                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            1                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               1                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          115376                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             115376                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              15121                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             389235                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                404356                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             15121                       # number of overall misses
-system.l2c.overall_misses::cpu.data            389235                       # number of overall misses
-system.l2c.overall_misses::total               404356                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    805852997                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14261584000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    15067436997                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       397000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       397000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6192128996                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6192128996                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    805852997                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20453712996                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21259565993                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    805852997                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20453712996                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21259565993                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst         1024994                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1102957                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2127951                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       842689                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           842689                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data           85                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              85                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data            4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total             4                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        301248                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           301248                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst          1024994                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1404205                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2429199                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1024994                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1404205                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2429199                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014752                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.248295                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.135802                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.588235                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.588235                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.250000                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.382993                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.382993                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014752                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.277192                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.166457                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014752                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.277192                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.166457                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53293.631175                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52076.375069                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52140.068506                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data         7940                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total         7940                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53669.125260                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53669.125260                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53293.631175                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52548.493830                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52576.358439                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53293.631175                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52548.493830                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52576.358439                       # average overall miss latency
+system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          115356                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             115356                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.inst              15142                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             389248                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                404390                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.inst             15142                       # number of overall misses
+system.l2c.overall_misses::cpu.data            389248                       # number of overall misses
+system.l2c.overall_misses::total               404390                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.inst    806626498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  14262568500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15069194998                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       506000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       506000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6193261496                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6193261496                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    806626498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20455829996                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21262456494                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    806626498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  20455829996                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21262456494                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst         1021696                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1101676                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2123372                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       840935                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           840935                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           81                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              81                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total             5                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        300814                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           300814                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst          1021696                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1402490                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2424186                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1021696                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1402490                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2424186                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.014820                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.248614                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.136120                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.617284                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.617284                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.400000                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.400000                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383479                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383479                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.014820                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.277541                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.166815                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.014820                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.277541                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.166815                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53270.802932                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52073.695106                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52136.409550                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data        10120                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total        10120                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53688.247651                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53688.247651                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53270.802932                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52552.177522                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52579.085769                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53270.802932                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52552.177522                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52579.085769                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -149,80 +149,80 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               75953                       # number of writebacks
-system.l2c.writebacks::total                    75953                       # number of writebacks
+system.l2c.writebacks::writebacks               75976                       # number of writebacks
+system.l2c.writebacks::total                    75976                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                  1                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.inst        15120                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       273859                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          288979                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        15141                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       273892                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          289033                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu.data           50                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total           50                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            1                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       115376                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        115376                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         15120                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        389235                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           404355                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        15120                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       389235                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          404355                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    621011997                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10975832000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11596843997                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2105000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      2105000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        40000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        40000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4797954496                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4797954496                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    621011997                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15773786496                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16394798493                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    621011997                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15773786496                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16394798493                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    809342530                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    809342530                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1103231500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1103231500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   1912574030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1912574030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248295                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.135802                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.588235                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.588235                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.250000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.382993                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.382993                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.277192                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.166456                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014751                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.277192                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.166456                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40078.405311                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40130.403929                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        42100                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        42100                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       115356                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        115356                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         15141                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        389248                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           404389                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        15141                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       389248                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          404389                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    621548498                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  10984970000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11606518498                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      2110000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      2110000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4799591496                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4799591496                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    621548498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15784561496                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16406109994                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    621548498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15784561496                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16406109994                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data   1332350000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1332350000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1882980500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1882980500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   3215330500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3215330500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.248614                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.136120                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.617284                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.617284                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.400000                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383479                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383479                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.277541                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.166814                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.014819                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.277541                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.166814                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40106.939962                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40156.378331                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data        42200                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total        42200                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41585.377340                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41585.377340                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40525.097938                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40545.556486                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41072.222024                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40525.097938                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40545.556486                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 41606.778113                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 41606.778113                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40551.426073                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40570.119350                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41050.690047                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40551.426073                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40570.119350                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -231,14 +231,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.287077                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.286638                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1711278506000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.287077                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.080442                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.080442                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1711308746000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.286638                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.080415                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.080415                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -249,12 +249,12 @@ system.iocache.overall_misses::tsunami.ide        41725                       #
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7639838806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7639838806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7660511804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7660511804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7660511804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7660511804                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7639193806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7639193806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7659866804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7659866804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7659866804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7659866804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -273,17 +273,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183862.119898                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183862.119898                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183595.249946                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183595.249946                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183595.249946                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183595.249946                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7420000                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183846.597179                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183846.597179                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183579.791588                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183579.791588                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183579.791588                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183579.791588                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7379000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7102                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7110                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1044.776119                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1037.834037                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -299,12 +299,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41725
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5478984000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5478984000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5490660000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5490660000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5490660000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5490660000                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5478339000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5478339000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5490015000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5490015000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5490015000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5490015000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -315,12 +315,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131858.490566                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131858.490566                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131591.611744                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131591.611744                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131591.611744                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131591.611744                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131842.967848                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131842.967848                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131576.153385                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131576.153385                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131576.153385                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131576.153385                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -338,22 +338,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9968108                       # DTB read hits
-system.cpu.dtb.read_misses                      43556                       # DTB read misses
-system.cpu.dtb.read_acv                           496                       # DTB read access violations
-system.cpu.dtb.read_accesses                   957960                       # DTB read accesses
-system.cpu.dtb.write_hits                     6640476                       # DTB write hits
-system.cpu.dtb.write_misses                     10042                       # DTB write misses
-system.cpu.dtb.write_acv                          402                       # DTB write access violations
-system.cpu.dtb.write_accesses                  340316                       # DTB write accesses
-system.cpu.dtb.data_hits                     16608584                       # DTB hits
-system.cpu.dtb.data_misses                      53598                       # DTB misses
-system.cpu.dtb.data_acv                           898                       # DTB access violations
-system.cpu.dtb.data_accesses                  1298276                       # DTB accesses
-system.cpu.itb.fetch_hits                     1341124                       # ITB hits
-system.cpu.itb.fetch_misses                     40235                       # ITB misses
-system.cpu.itb.fetch_acv                         1160                       # ITB acv
-system.cpu.itb.fetch_accesses                 1381359                       # ITB accesses
+system.cpu.dtb.read_hits                      9936242                       # DTB read hits
+system.cpu.dtb.read_misses                      43490                       # DTB read misses
+system.cpu.dtb.read_acv                           516                       # DTB read access violations
+system.cpu.dtb.read_accesses                   957786                       # DTB read accesses
+system.cpu.dtb.write_hits                     6625146                       # DTB write hits
+system.cpu.dtb.write_misses                     10048                       # DTB write misses
+system.cpu.dtb.write_acv                          376                       # DTB write access violations
+system.cpu.dtb.write_accesses                  340602                       # DTB write accesses
+system.cpu.dtb.data_hits                     16561388                       # DTB hits
+system.cpu.dtb.data_misses                      53538                       # DTB misses
+system.cpu.dtb.data_acv                           892                       # DTB access violations
+system.cpu.dtb.data_accesses                  1298388                       # DTB accesses
+system.cpu.itb.fetch_hits                     1339050                       # ITB hits
+system.cpu.itb.fetch_misses                     40176                       # ITB misses
+system.cpu.itb.fetch_acv                         1137                       # ITB acv
+system.cpu.itb.fetch_accesses                 1379226                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -366,142 +366,142 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                        122531860                       # number of cpu cycles simulated
+system.cpu.numCycles                        124718167                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 14045558                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           11719354                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             447776                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10129156                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  5920510                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 14016362                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           11699457                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             447467                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10098689                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  5905629                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                   939631                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               44501                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           31544288                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                       71453130                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    14045558                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            6860141                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      13465921                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 2135846                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               41803348                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                34171                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        276891                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       309124                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          186                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   8845261                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                302298                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples           88840406                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.804286                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.136255                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                   935083                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               44772                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           31431497                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                       71249565                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    14016362                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            6840712                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      13427140                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 2133623                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               43145521                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                33490                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        277896                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       300852                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          229                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   8810652                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                301668                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples           90022350                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.791465                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.121682                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 75374485     84.84%     84.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                   882693      0.99%     85.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1758870      1.98%     87.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   855110      0.96%     88.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2773745      3.12%     91.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                   603499      0.68%     92.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                   673337      0.76%     93.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1014466      1.14%     94.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  4904201      5.52%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 76595210     85.08%     85.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                   880275      0.98%     86.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1754034      1.95%     88.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   853758      0.95%     88.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2767447      3.07%     92.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                   598798      0.67%     92.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                   668363      0.74%     93.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1009728      1.12%     94.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  4894737      5.44%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total             88840406                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.114628                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.583139                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 32595578                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              41593167                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  12233698                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1054489                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                1363473                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved               614789                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                 43441                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts               70185288                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                133206                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                1363473                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 33740803                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                16340010                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       21029757                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  11532133                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               4834228                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts               66486071                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  7165                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                 750706                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               1800875                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands            44431145                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups              80611615                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups         80123142                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            488473                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              38259358                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                  6171779                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            1702958                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         251555                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  12743501                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             10564267                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores             6974375                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1310956                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores           921637                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                   58920823                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2093860                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                  57272597                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            128544                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined         7527772                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined      3875760                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved        1425872                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples      88840406                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.644668                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.291770                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total             90022350                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.112384                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.571285                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 32462663                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              42944944                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  12200929                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1050932                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                1362881                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved               612569                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                 43257                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts               69997551                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                131864                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                1362881                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 33604793                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                17288612                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       21444377                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  11497846                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               4823839                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts               66302391                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  7264                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                 752324                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               1793006                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands            44298032                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups              80385832                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups         79896368                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            489464                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              38124388                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                  6173636                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            1698063                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         251025                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  12720780                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             10525150                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores             6958577                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1307223                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores           920725                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                   58755274                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2090184                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                  57106230                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            126003                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined         7528195                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined      3871424                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved        1424917                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples      90022350                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.634356                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.284426                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            62934632     70.84%     70.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            12040664     13.55%     84.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             5383860      6.06%     90.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             3443587      3.88%     94.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4             2613267      2.94%     97.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             1328836      1.50%     98.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6              686879      0.77%     99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              354518      0.40%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               54163      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            64211383     71.33%     71.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            11984837     13.31%     84.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             5359973      5.95%     90.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             3439210      3.82%     94.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4             2607784      2.90%     97.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             1324300      1.47%     98.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6              687470      0.76%     99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              352783      0.39%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               54610      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total        88840406                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total        90022350                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   73519      9.73%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.73% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                 364094     48.19%     57.91% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                318003     42.09%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   75162      9.94%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      9.94% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 361865     47.84%     57.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                319378     42.22%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass              7291      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              39090989     68.25%     68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                61973      0.11%     68.38% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              38979239     68.26%     68.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                61855      0.11%     68.38% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.38% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd               25607      0.04%     68.42% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.42% # Type of FU issued
@@ -529,116 +529,116 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.43% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.43% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.43% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.43% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             10411715     18.18%     86.61% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             6718707     11.73%     98.34% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess             952679      1.66%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             10375615     18.17%     86.60% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             6703515     11.74%     98.34% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess             949472      1.66%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total               57272597                       # Type of FU issued
-system.cpu.iq.rate                           0.467410                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                      755616                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.013193                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          203573547                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes          68217667                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     55990659                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads              696212                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             338599                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses       327577                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses               57656594                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                  364328                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           594908                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total               57106230                       # Type of FU issued
+system.cpu.iq.rate                           0.457882                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      756405                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.013246                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          204420366                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes          68047675                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     55829438                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads              696851                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             339603                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses       327742                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses               57490896                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                  364448                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           598206                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      1450991                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses         2769                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        14176                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores       581838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      1442254                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses         2799                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        13958                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores       583775                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        18337                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked        105015                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads        17984                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked        104066                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                1363473                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                11404151                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                871964                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts            64586243                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            684405                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              10564267                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts              6974375                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1841535                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 624319                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 12765                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          14176                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         237440                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       422569                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               660009                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts              56745623                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              10040371                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts            526973                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                1362881                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                12351222                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                868923                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts            64407898                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            684720                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              10525150                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts              6958577                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1840963                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 621108                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 12330                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          13958                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         238471                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       421447                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               659918                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts              56579740                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              10008035                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts            526489                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                       3571560                       # number of nop insts executed
-system.cpu.iew.exec_refs                     16706164                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                  8999941                       # Number of branches executed
-system.cpu.iew.exec_stores                    6665793                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.463109                       # Inst execution rate
-system.cpu.iew.wb_sent                       56430087                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      56318236                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  27772479                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  37631426                       # num instructions consuming a value
+system.cpu.iew.exec_nop                       3562440                       # number of nop insts executed
+system.cpu.iew.exec_refs                     16658473                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                  8978804                       # Number of branches executed
+system.cpu.iew.exec_stores                    6650438                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.453661                       # Inst execution rate
+system.cpu.iew.wb_sent                       56268334                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      56157180                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  27683314                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  37519561                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.459621                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.738013                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.450273                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.737837                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       56285915                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         56285915                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts         8189376                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls          667988                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            616441                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples     87476933                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.643437                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.558745                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       56104643                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         56104643                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts         8193317                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls          665267                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            615735                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples     88659469                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.632811                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.547834                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     66214375     75.69%     75.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1      8956758     10.24%     85.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4831410      5.52%     91.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2600718      2.97%     94.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      1447358      1.65%     96.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5       605400      0.69%     96.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6       515608      0.59%     97.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       488345      0.56%     97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      1816961      2.08%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     67465140     76.09%     76.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1      8924230     10.07%     86.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4814714      5.43%     91.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2600553      2.93%     94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      1445109      1.63%     96.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5       596766      0.67%     96.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6       516883      0.58%     97.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       484830      0.55%     97.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      1811244      2.04%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total     87476933                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             56285915                       # Number of instructions committed
-system.cpu.commit.committedOps               56285915                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total     88659469                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             56104643                       # Number of instructions committed
+system.cpu.commit.committedOps               56104643                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       15505813                       # Number of memory references committed
-system.cpu.commit.loads                       9113276                       # Number of loads committed
-system.cpu.commit.membars                      227944                       # Number of memory barriers committed
-system.cpu.commit.branches                    8463135                       # Number of branches committed
+system.cpu.commit.refs                       15457698                       # Number of memory references committed
+system.cpu.commit.loads                       9082896                       # Number of loads committed
+system.cpu.commit.membars                      226441                       # Number of memory barriers committed
+system.cpu.commit.branches                    8439531                       # Number of branches committed
 system.cpu.commit.fp_insts                     324384                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  52124087                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               744545                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               1816961                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  51953528                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               739583                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               1811244                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    149884134                       # The number of ROB reads
-system.cpu.rob.rob_writes                   130314855                       # The number of ROB writes
-system.cpu.timesIdled                         1389359                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        33691454                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   3606309626                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    53091408                       # Number of Instructions Simulated
-system.cpu.committedOps                      53091408                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              53091408                       # Number of Instructions Simulated
-system.cpu.cpi                               2.307941                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.307941                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.433287                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.433287                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                 74386687                       # number of integer regfile reads
-system.cpu.int_regfile_writes                40627933                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                    166209                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                   166935                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                 1998011                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 950291                       # number of misc regfile writes
+system.cpu.rob.rob_reads                    150896568                       # The number of ROB reads
+system.cpu.rob.rob_writes                   129959625                       # The number of ROB writes
+system.cpu.timesIdled                         1384663                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        34695817                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   3604162300                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    52917560                       # Number of Instructions Simulated
+system.cpu.committedOps                      52917560                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              52917560                       # Number of Instructions Simulated
+system.cpu.cpi                               2.356839                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.356839                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.424297                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.424297                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                 74164887                       # number of integer regfile reads
+system.cpu.int_regfile_writes                40500361                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                    166351                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                   166958                       # number of floating regfile writes
+system.cpu.misc_regfile_reads                 1995249                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 947406                       # number of misc regfile writes
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -670,245 +670,245 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                1024388                       # number of replacements
-system.cpu.icache.tagsinuse                509.959478                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  7759501                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1024896                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.571013                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            23722278000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     509.959478                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996015                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996015                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      7759502                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         7759502                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       7759502                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          7759502                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      7759502                       # number of overall hits
-system.cpu.icache.overall_hits::total         7759502                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1085755                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1085755                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1085755                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1085755                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1085755                       # number of overall misses
-system.cpu.icache.overall_misses::total       1085755                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  17501015990                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  17501015990                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  17501015990                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  17501015990                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  17501015990                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  17501015990                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      8845257                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      8845257                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      8845257                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      8845257                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      8845257                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      8845257                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122750                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.122750                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.122750                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.122750                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.122750                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.122750                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16118.752380                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16118.752380                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16118.752380                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16118.752380                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16118.752380                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16118.752380                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      1777494                       # number of cycles access was blocked
+system.cpu.icache.replacements                1021086                       # number of replacements
+system.cpu.icache.tagsinuse                509.954176                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  7728678                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1021597                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.565290                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            23896761000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     509.954176                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996004                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996004                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      7728679                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         7728679                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       7728679                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          7728679                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      7728679                       # number of overall hits
+system.cpu.icache.overall_hits::total         7728679                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1081971                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1081971                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1081971                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1081971                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1081971                       # number of overall misses
+system.cpu.icache.overall_misses::total       1081971                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  17450602485                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  17450602485                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  17450602485                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  17450602485                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  17450602485                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  17450602485                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      8810650                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      8810650                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      8810650                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      8810650                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      8810650                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      8810650                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122803                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.122803                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.122803                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.122803                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.122803                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.122803                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16128.530695                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16128.530695                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16128.530695                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16128.530695                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16128.530695                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16128.530695                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      1774492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               208                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               205                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  8545.644231                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8656.058537                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60612                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        60612                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        60612                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        60612                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        60612                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        60612                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1025143                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1025143                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1025143                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1025143                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1025143                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1025143                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13492714994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  13492714994                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13492714994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  13492714994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13492714994                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  13492714994                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115897                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.115897                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115897                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.115897                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13161.788154                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13161.788154                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13161.788154                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13161.788154                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60133                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        60133                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        60133                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        60133                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        60133                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        60133                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1021838                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1021838                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1021838                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1021838                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1021838                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1021838                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  13459032492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  13459032492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  13459032492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  13459032492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  13459032492                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  13459032492                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.115978                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.115978                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.115978                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.115978                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13171.395556                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13171.395556                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13171.395556                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13171.395556                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1403592                       # number of replacements
-system.cpu.dcache.tagsinuse                511.995920                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 11877954                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1404104                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   8.459455                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               19693000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.995920                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7277634                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7277634                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      4189219                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        4189219                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       190679                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       190679                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       220144                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       220144                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      11466853                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         11466853                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     11466853                       # number of overall hits
-system.cpu.dcache.overall_hits::total        11466853                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1830581                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1830581                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1967996                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1967996                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        23423                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        23423                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data            4                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total            4                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3798577                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3798577                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3798577                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3798577                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  48883672000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  48883672000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  74930562797                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  74930562797                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    428682000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    428682000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        98000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total        98000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 123814234797                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 123814234797                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 123814234797                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 123814234797                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      9108215                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      9108215                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157215                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157215                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       214102                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       214102                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       220148                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       220148                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15265430                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15265430                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15265430                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15265430                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.200981                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.200981                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.319624                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.319624                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109401                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109401                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000018                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000018                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.248835                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.248835                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.248835                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.248835                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26703.910944                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 26703.910944                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38074.550353                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38074.550353                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18301.754686                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18301.754686                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        24500                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total        24500                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 32594.899300                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 32594.899300                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32594.899300                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32594.899300                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs    731758024                       # number of cycles access was blocked
+system.cpu.dcache.replacements                1401888                       # number of replacements
+system.cpu.dcache.tagsinuse                511.994858                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 11830963                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1402400                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                   8.436226                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               23765000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.994858                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999990                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7247947                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7247947                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4173007                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4173007                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       190139                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       190139                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       219622                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       219622                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      11420954                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         11420954                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     11420954                       # number of overall hits
+system.cpu.dcache.overall_hits::total        11420954                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1826719                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1826719                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1967450                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1967450                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        23276                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        23276                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3794169                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3794169                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3794169                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3794169                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  48828356500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  48828356500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  75021141961                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  75021141961                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    428009500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    428009500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       154000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       154000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 123849498461                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 123849498461                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 123849498461                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 123849498461                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9074666                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      9074666                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6140457                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6140457                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       213415                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       213415                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       219627                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       219627                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15215123                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15215123                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15215123                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15215123                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.201299                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.201299                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.320408                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.320408                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.109064                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.109064                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000023                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000023                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.249368                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.249368                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.249368                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.249368                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26730.086291                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 26730.086291                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38131.155537                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38131.155537                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18388.447328                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18388.447328                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        30800                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total        30800                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.061664                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 32642.061664                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.061664                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32642.061664                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs    733938028                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       178000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs             72544                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs             72096                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               7                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10087.092303                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10180.010375                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets 25428.571429                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       842689                       # number of writebacks
-system.cpu.dcache.writebacks::total            842689                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       745053                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       745053                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667452                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1667452                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5206                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         5206                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2412505                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2412505                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2412505                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2412505                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1085528                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1085528                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300544                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       300544                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18217                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        18217                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            4                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total            4                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1386072                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1386072                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1386072                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1386072                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28234901500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  28234901500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9648960448                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9648960448                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    269943500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    269943500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        85500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        85500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37883861948                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  37883861948                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37883861948                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  37883861948                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    904971500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    904971500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1224983998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1224983998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2129955498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   2129955498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119181                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119181                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048812                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085086                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.085086                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000018                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000018                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090798                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.090798                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090798                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.090798                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26010.293148                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26010.293148                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32104.984455                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32104.984455                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14818.219246                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14818.219246                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        21375                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        21375                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27331.813894                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27331.813894                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27331.813894                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27331.813894                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       840935                       # number of writebacks
+system.cpu.dcache.writebacks::total            840935                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       742319                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       742319                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1667295                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1667295                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5261                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5261                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2409614                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2409614                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2409614                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2409614                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1084400                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1084400                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       300155                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       300155                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        18015                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        18015                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1384555                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1384555                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1384555                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1384555                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  28231864000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  28231864000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9653593940                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9653593940                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    269637000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    269637000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       138000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       138000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  37885457940                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  37885457940                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  37885457940                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  37885457940                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1423534500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1423534500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2001030998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2001030998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3424565498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3424565498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.119498                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.119498                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.048882                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.084413                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.084413                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000023                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090999                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.090999                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090999                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.090999                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26034.548137                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26034.548137                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32162.029418                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32162.029418                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14967.360533                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14967.360533                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        27600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        27600                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27362.912950                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 27362.912950                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27362.912950                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 27362.912950                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -917,28 +917,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6430                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     211669                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74897     40.95%     40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21                     243      0.13%     41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1886      1.03%     42.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  105867     57.88%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               182893                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73530     49.29%     49.29% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      243      0.16%     49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1886      1.26%     50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73533     49.29%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149192                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1824783514500     97.87%     97.87% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                98568000      0.01%     97.88% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               384878500      0.02%     97.90% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             39156084500      2.10%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1864423045500                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981748                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.inst.quiesce                     6425                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     211112                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74681     40.96%     40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21                     133      0.07%     41.03% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22                    1886      1.03%     42.07% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  105636     57.93%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               182336                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73314     49.32%     49.32% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      133      0.09%     49.41% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1886      1.27%     50.68% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73315     49.32%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                148648                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1823792488500     97.82%     97.82% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21                71545000      0.00%     97.82% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               571672500      0.03%     97.85% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             40006830500      2.15%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1864442536500                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981695                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.694579                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.815734                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.694034                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.815242                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -974,32 +974,32 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4176      2.17%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4176      2.17%      2.18% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.20% # number of callpals executed
-system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                175546     91.19%     93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6791      3.53%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrkgp                      1      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::wrusp                      7      0.00%     96.92% # number of callpals executed
-system.cpu.kern.callpal::rdusp                      9      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::whami                      2      0.00%     96.93% # number of callpals executed
-system.cpu.kern.callpal::rti                     5220      2.71%     99.64% # number of callpals executed
+system.cpu.kern.callpal::wrent                      7      0.00%      2.21% # number of callpals executed
+system.cpu.kern.callpal::swpipl                175205     91.22%     93.43% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6791      3.54%     96.97% # number of callpals executed
+system.cpu.kern.callpal::wrkgp                      1      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::wrusp                      7      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::rdusp                      9      0.00%     96.97% # number of callpals executed
+system.cpu.kern.callpal::whami                      2      0.00%     96.98% # number of callpals executed
+system.cpu.kern.callpal::rti                     5112      2.66%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 192513                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5956                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1736                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2106                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1906                      
-system.cpu.kern.mode_good::user                  1736                      
+system.cpu.kern.callpal::total                 192064                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5850                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1735                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2104                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1905                      
+system.cpu.kern.mode_good::user                  1735                      
 system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.320013                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel     0.325641                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.080722                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.389059                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        29626491000      1.59%      1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           2782272500      0.15%      1.74% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1832014274000     98.26%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::idle       0.080798                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.393229                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        29922134000      1.60%      1.60% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           2785239500      0.15%      1.75% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1831735155000     98.25%    100.00% # number of ticks spent at the given mode
 system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
 
 ---------- End Simulation Statistics   ----------
index 0e9aa5888cb7db348a015946ee0789f14f000cc1..5540dd9479967306e2ac614027506733bd1d84af 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.503329                       # Number of seconds simulated
-sim_ticks                                2503329223500                       # Number of ticks simulated
-final_tick                               2503329223500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.538055                       # Number of seconds simulated
+sim_ticks                                2538055224500                       # Number of ticks simulated
+final_tick                               2538055224500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55645                       # Simulator instruction rate (inst/s)
-host_op_rate                                    71576                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2298862295                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 394936                       # Number of bytes of host memory used
-host_seconds                                  1088.94                       # Real time elapsed on the host
-sim_insts                                    60594713                       # Number of instructions simulated
-sim_ops                                      77942287                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
+host_inst_rate                                  74782                       # Simulator instruction rate (inst/s)
+host_op_rate                                    96192                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3131579061                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390232                       # Number of bytes of host memory used
+host_seconds                                   810.47                       # Real time elapsed on the host
+sim_insts                                    60608338                       # Number of instructions simulated
+sim_ops                                      77960937                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            799552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129435024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       799552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785216                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            799488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9090192                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131004176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       799488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          799488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3781888                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801288                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           6797960                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12493                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096888                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59144                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12492                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293438                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59092                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813162                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47751475                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3632775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51705154                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319395                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319395                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1512073                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1204824                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2716897                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1512073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47751475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4837599                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54422052                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total               813110                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47717846                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1538                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3581558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51615968                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315000                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315000                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1490073                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1188340                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2678413                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1490073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47717846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1538                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              315000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4769898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54294380                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64407                       # number of replacements
-system.l2c.tagsinuse                     51237.721374                       # Cycle average of tags in use
-system.l2c.total_refs                         1963815                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129804                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.129079                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2492699118000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36773.515896                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       46.128401                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8177.854263                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6240.222629                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.561119                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000704                       # Average percentage of cache occupancy
+system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         64349                       # number of replacements
+system.l2c.tagsinuse                     51370.291201                       # Cycle average of tags in use
+system.l2c.total_refs                         1966684                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129742                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         15.158422                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2527049892000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36909.964338                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       48.537302                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000243                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           8186.541319                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6225.247998                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.563201                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000741                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124784                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095218                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781826                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        123734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11927                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              976636                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              387128                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1499425                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          607519                       # number of Writeback hits
-system.l2c.Writeback_hits::total               607519                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               41                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  41                       # number of UpgradeReq hits
+system.l2c.occ_percent::cpu.inst             0.124917                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.094990                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.783848                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        122661                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         11547                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              978702                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              387818                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1500728                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          608398                       # number of Writeback hits
+system.l2c.Writeback_hits::total               608398                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               38                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  38                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112732                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112732                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         123734                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11927                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               976636                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               499860                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1612157                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        123734                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11927                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              976636                       # number of overall hits
-system.l2c.overall_hits::cpu.data              499860                       # number of overall hits
-system.l2c.overall_hits::total                1612157                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            112928                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112928                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         122661                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          11547                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               978702                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               500746                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1613656                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        122661                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         11547                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              978702                       # number of overall hits
+system.l2c.overall_hits::cpu.data              500746                       # number of overall hits
+system.l2c.overall_hits::total                1613656                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           61                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12374                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             12372                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23124                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133219                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133219                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::total                23125                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2903                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2903                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133164                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133164                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12374                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143910                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156343                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           58                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              12372                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143855                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156289                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           61                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12374                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143910                       # number of overall misses
-system.l2c.overall_misses::total               156343                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3035000                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.inst             12372                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143855                       # number of overall misses
+system.l2c.overall_misses::total               156289                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3190500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    659327498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    562370998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1224793496                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       994500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       994500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   7086596499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7086596499                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      3035000                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    658900997                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    562244999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1224396496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       996000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       996000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7068682495                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7068682495                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      3190500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    659327498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7648967497                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8311389995                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      3035000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu.inst    658900997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7630927494                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8293078991                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      3190500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    659327498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7648967497                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8311389995                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       123792                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11928                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          989010                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          397819                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1522549                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       607519                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           607519                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2950                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2950                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           18                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            18                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        245951                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           245951                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       123792                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11928                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           989010                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           643770                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1768500                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       123792                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11928                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          989010                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          643770                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1768500                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000084                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012512                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026874                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015188                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.986102                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.986102                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.111111                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.111111                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541649                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541649                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000084                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012512                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.223543                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088404                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000084                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012512                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.223543                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088404                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu.inst    658900997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7630927494                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8293078991                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       122722                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        11548                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          991074                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          398509                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1523853                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       608398                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           608398                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2941                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2941                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246092                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246092                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       122722                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        11548                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           991074                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           644601                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1769945                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       122722                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        11548                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          991074                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          644601                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1769945                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000087                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012483                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026827                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015175                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.987079                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.987079                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.541115                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541115                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000087                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012483                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.223169                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.088302                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000087                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012483                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.223169                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.088302                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53283.295458                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52602.282106                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52966.333506                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   341.870058                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   341.870058                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53195.088531                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53195.088531                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53257.435904                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52590.496586                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52946.875503                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   343.093352                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   343.093352                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53082.533530                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53082.533530                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53161.254389                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53257.435904                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 53045.966383                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53062.461152                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53161.254389                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53257.435904                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 53045.966383                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53062.461152                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -212,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59144                       # number of writebacks
-system.l2c.writebacks::total                    59144                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data             61                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                69                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data              61                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 69                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data             61                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                69                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               59092                       # number of writebacks
+system.l2c.writebacks::total                    59092                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             59                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                66                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              59                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 66                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             59                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                66                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12366                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10630                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23055                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133219                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133219                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12365                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10632                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23059                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2903                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2903                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133164                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133164                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12366                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143849                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156274                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12365                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143796                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156223                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12366                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143849                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156274                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu.inst        12365                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143796                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156223                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    507997999                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    430294500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    940666499                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    117136000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    117136000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5457467999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5457467999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    507604998                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    430224000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    940322998                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116314500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    116314500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5435229995                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5435229995                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    507997999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5887762499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6398134498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    507604998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5865453995                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6375552993                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    507997999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5887762499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6398134498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    507604998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5865453995                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6375552993                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131412946500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131418269500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31416947511                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31416947511                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745653500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166750976500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32068433085                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32068433085                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162835217011                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026721                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015142                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986102                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.986102                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541649                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541649                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088365                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088365                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 198814086585                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 198819409585                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026679                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015132                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.987079                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.987079                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541115                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541115                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.223078                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.088264                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.223078                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.088264                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40810.591225                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40810.591225                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -332,26 +332,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.checker.dtb.inst_hits                    0                       # ITB inst hits
 system.cpu.checker.dtb.inst_misses                  0                       # ITB inst misses
-system.cpu.checker.dtb.read_hits             15048154                       # DTB read hits
-system.cpu.checker.dtb.read_misses               7314                       # DTB read misses
-system.cpu.checker.dtb.write_hits            11293808                       # DTB write hits
-system.cpu.checker.dtb.write_misses              2189                       # DTB write misses
+system.cpu.checker.dtb.read_hits             15052335                       # DTB read hits
+system.cpu.checker.dtb.read_misses               7317                       # DTB read misses
+system.cpu.checker.dtb.write_hits            11295995                       # DTB write hits
+system.cpu.checker.dtb.write_misses              2195                       # DTB write misses
 system.cpu.checker.dtb.flush_tlb                    4                       # Number of times complete TLB was flushed
 system.cpu.checker.dtb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.dtb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.dtb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
 system.cpu.checker.dtb.flush_entries             6410                       # Number of entries that have been flushed from TLB
 system.cpu.checker.dtb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults            178                       # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults            181                       # Number of TLB faults due to prefetch
 system.cpu.checker.dtb.domain_faults                0                       # Number of TLB faults due to domain restrictions
 system.cpu.checker.dtb.perms_faults               452                       # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses         15055468                       # DTB read accesses
-system.cpu.checker.dtb.write_accesses        11295997                       # DTB write accesses
+system.cpu.checker.dtb.read_accesses         15059652                       # DTB read accesses
+system.cpu.checker.dtb.write_accesses        11298190                       # DTB write accesses
 system.cpu.checker.dtb.inst_accesses                0                       # ITB inst accesses
-system.cpu.checker.dtb.hits                  26341962                       # DTB hits
-system.cpu.checker.dtb.misses                    9503                       # DTB misses
-system.cpu.checker.dtb.accesses              26351465                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61773470                       # ITB inst hits
+system.cpu.checker.dtb.hits                  26348330                       # DTB hits
+system.cpu.checker.dtb.misses                    9512                       # DTB misses
+system.cpu.checker.dtb.accesses              26357842                       # DTB accesses
+system.cpu.checker.itb.inst_hits             61787107                       # ITB inst hits
 system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
@@ -368,36 +368,36 @@ system.cpu.checker.itb.domain_faults                0                       # Nu
 system.cpu.checker.itb.perms_faults                 0                       # Number of TLB faults due to permissions restrictions
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
-system.cpu.checker.itb.inst_accesses         61777941                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61773470                       # DTB hits
+system.cpu.checker.itb.inst_accesses         61791578                       # ITB inst accesses
+system.cpu.checker.itb.hits                  61787107                       # DTB hits
 system.cpu.checker.itb.misses                    4471                       # DTB misses
-system.cpu.checker.itb.accesses              61777941                       # DTB accesses
-system.cpu.checker.numCycles                 78232851                       # number of cpu cycles simulated
+system.cpu.checker.itb.accesses              61791578                       # DTB accesses
+system.cpu.checker.numCycles                 78251513                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
 system.cpu.checker.numWorkItemsCompleted            0                       # number of work items this cpu completed
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51771178                       # DTB read hits
-system.cpu.dtb.read_misses                      82022                       # DTB read misses
-system.cpu.dtb.write_hits                    11879780                       # DTB write hits
-system.cpu.dtb.write_misses                     18404                       # DTB write misses
+system.cpu.dtb.read_hits                     51779226                       # DTB read hits
+system.cpu.dtb.read_misses                      81574                       # DTB read misses
+system.cpu.dtb.write_hits                    11882622                       # DTB write hits
+system.cpu.dtb.write_misses                     18093                       # DTB write misses
 system.cpu.dtb.flush_tlb                            4                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     8063                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2874                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    631                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     8066                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      3293                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    606                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1260                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51853200                       # DTB read accesses
-system.cpu.dtb.write_accesses                11898184                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1237                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51860800                       # DTB read accesses
+system.cpu.dtb.write_accesses                11900715                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63650958                       # DTB hits
-system.cpu.dtb.misses                          100426                       # DTB misses
-system.cpu.dtb.accesses                      63751384                       # DTB accesses
-system.cpu.itb.inst_hits                     13147400                       # ITB inst hits
-system.cpu.itb.inst_misses                      12275                       # ITB inst misses
+system.cpu.dtb.hits                          63661848                       # DTB hits
+system.cpu.dtb.misses                           99667                       # DTB misses
+system.cpu.dtb.accesses                      63761515                       # DTB accesses
+system.cpu.itb.inst_hits                     13144692                       # ITB inst hits
+system.cpu.itb.inst_misses                      11967                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -406,121 +406,121 @@ system.cpu.itb.flush_tlb                            4                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                     126                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     5278                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     5259                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3416                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13159675                       # ITB inst accesses
-system.cpu.itb.hits                          13147400                       # DTB hits
-system.cpu.itb.misses                           12275                       # DTB misses
-system.cpu.itb.accesses                      13159675                       # DTB accesses
-system.cpu.numCycles                        415310668                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 13156659                       # ITB inst accesses
+system.cpu.itb.hits                          13144692                       # DTB hits
+system.cpu.itb.misses                           11967                       # DTB misses
+system.cpu.itb.accesses                      13156659                       # DTB accesses
+system.cpu.numCycles                        487285069                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 15527738                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           12466555                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             753811                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10646284                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  8367014                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 15533008                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12472748                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             753945                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10621013                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8369898                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1449693                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80905                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           33357472                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      101736318                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    15527738                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9816707                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22310929                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6078281                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     161634                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               94635812                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2484                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        132549                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208778                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          375                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13143214                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1025665                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6564                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154991090                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.809239                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.178893                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1450891                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               81082                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33390116                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      101781554                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15533008                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9820789                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22319812                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6080499                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     158808                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles              102222011                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2648                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        133571                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       207903                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          361                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13140422                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1021772                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6316                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          162617823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.771724                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.134680                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132697054     85.62%     85.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1371702      0.89%     86.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1758298      1.13%     87.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2653739      1.71%     89.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2357523      1.52%     90.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1143564      0.74%     91.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2918516      1.88%     93.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   809258      0.52%     94.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9281436      5.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                140314971     86.29%     86.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1367844      0.84%     87.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1761669      1.08%     88.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2653320      1.63%     89.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2361626      1.45%     91.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1142802      0.70%     92.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2916048      1.79%     93.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   808288      0.50%     94.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9291255      5.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154991090                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.037388                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.244964                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 35540110                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              94304374                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20024957                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1112327                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4009322                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2100739                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174603                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              118268322                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570412                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4009322                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37657945                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39869078                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       47822984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18880557                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6751204                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110681454                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 22988                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1160036                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4497834                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            31020                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           115504222                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             506609726                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        506516210                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             93516                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727449                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36776772                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             900485                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         799637                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13564830                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             21065339                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13879000                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1961867                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2663971                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  101316574                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2057711                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 126458108                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            199553                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        24657438                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65563204                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         513311                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154991090                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.815906                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.514046                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            162617823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.031877                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.208875                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35567426                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             101892214                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20037549                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1109983                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4010651                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2100654                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                174914                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              118316762                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                572114                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4010651                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37681511                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                40491658                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       54797467                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18895098                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6741438                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110776004                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 22866                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1160313                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4487001                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            30716                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           115615239                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             507028919                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        506935731                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             93188                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78747197                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 36868041                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             898954                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         797959                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13563069                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21067127                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13877132                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1956196                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2590406                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  101357427                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2059773                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 126494913                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            198538                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        24680718                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65543860                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         514575                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     162617823                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.777866                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.488052                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           108868078     70.24%     70.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14887887      9.61%     79.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7383585      4.76%     84.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6313472      4.07%     88.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12622401      8.14%     96.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2812506      1.81%     98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1537255      0.99%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              440277      0.28%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              125629      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           116473756     71.62%     71.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14895850      9.16%     80.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7383355      4.54%     85.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6325930      3.89%     89.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12628751      7.77%     96.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2810327      1.73%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1536412      0.94%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              438084      0.27%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125358      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154991090                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       162617823                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   54148      0.61%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   53829      0.61%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      4      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
@@ -549,397 +549,397 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8364176     94.75%     95.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                409089      4.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8366722     94.73%     95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                411335      4.66%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60068751     47.50%     47.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95236      0.08%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               7      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53417106     42.24%     90.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12511205      9.89%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60100692     47.51%     47.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95407      0.08%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  20      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  4      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              12      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           12      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53419362     42.23%     90.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12513627      9.89%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              126458108                       # Type of FU issued
-system.cpu.iq.rate                           0.304490                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8827417                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.069805                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          417011386                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128052835                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87416470                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               22950                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12920                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10331                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              134909754                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12105                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           645788                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              126494913                       # Type of FU issued
+system.cpu.iq.rate                           0.259591                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8831890                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.069820                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          424714403                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128119104                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87467949                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               22973                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12866                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10326                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              134951003                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12134                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           645792                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5350138                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11136                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        35101                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2080838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5347388                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11096                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        35111                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2076739                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107263                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1048290                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107215                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1052024                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4009322                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                29478613                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                536036                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           103628902                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            217385                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              21065339                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13879000                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1466402                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 126510                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 31155                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          35101                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         376939                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       332400                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               709339                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             123236608                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52461044                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3221500                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4010651                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30083339                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                540488                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           103672693                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            219471                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21067127                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13877132                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1468075                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 126042                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 41068                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          35111                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         376458                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       332668                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               709126                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             123289616                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52469824                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3205297                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        254617                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64851969                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11926568                       # Number of branches executed
-system.cpu.iew.exec_stores                   12390925                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.296734                       # Inst execution rate
-system.cpu.iew.wb_sent                      121860265                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87426801                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47494075                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  86379183                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        255493                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64863659                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11931891                       # Number of branches executed
+system.cpu.iew.exec_stores                   12393835                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253013                       # Inst execution rate
+system.cpu.iew.wb_sent                      121912605                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87478275                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47524907                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  86445005                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.210509                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.549832                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179522                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.549770                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       60745094                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         78092668                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24728606                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1544400                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            625654                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151064180                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.516950                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.491641                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       60758719                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         78111318                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        24740610                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1545198                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            625619                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158689613                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.492227                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.459221                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122872114     81.34%     81.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13991345      9.26%     90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3943128      2.61%     93.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2231050      1.48%     94.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2009345      1.33%     96.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1063949      0.70%     96.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1402638      0.93%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       655924      0.43%     98.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2894687      1.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    130476861     82.22%     82.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14004142      8.82%     91.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3942589      2.48%     93.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2238161      1.41%     94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2017118      1.27%     96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1061710      0.67%     96.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1402075      0.88%     97.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       657613      0.41%     98.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2889344      1.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151064180                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60745094                       # Number of instructions committed
-system.cpu.commit.committedOps               78092668                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    158689613                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60758719                       # Number of instructions committed
+system.cpu.commit.committedOps               78111318                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513363                       # Number of memory references committed
-system.cpu.commit.loads                      15715201                       # Number of loads committed
-system.cpu.commit.membars                      413054                       # Number of memory barriers committed
-system.cpu.commit.branches                   10161447                       # Number of branches committed
+system.cpu.commit.refs                       27520132                       # Number of memory references committed
+system.cpu.commit.loads                      15719739                       # Number of loads committed
+system.cpu.commit.membars                      413350                       # Number of memory barriers committed
+system.cpu.commit.branches                   10163894                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69131310                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995952                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2894687                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69148099                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               996264                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2889344                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    249075594                       # The number of ROB reads
-system.cpu.rob.rob_writes                   209750294                       # The number of ROB writes
-system.cpu.timesIdled                         1905944                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       260319578                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4591259733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60594713                       # Number of Instructions Simulated
-system.cpu.committedOps                      77942287                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60594713                       # Number of Instructions Simulated
-system.cpu.cpi                               6.853909                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.853909                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.145902                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.145902                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                557815351                       # number of integer regfile reads
-system.cpu.int_regfile_writes                90098493                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8218                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2870                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               134021846                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912706                       # number of misc regfile writes
-system.cpu.icache.replacements                 989908                       # number of replacements
-system.cpu.icache.tagsinuse                511.610984                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12068184                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 990420                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.184915                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6426400000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.610984                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999240                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999240                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12068184                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12068184                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12068184                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12068184                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12068184                       # number of overall hits
-system.cpu.icache.overall_hits::total        12068184                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1074896                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1074896                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1074896                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1074896                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1074896                       # number of overall misses
-system.cpu.icache.overall_misses::total       1074896                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16638687991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16638687991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16638687991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16638687991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16638687991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16638687991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13143080                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13143080                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13143080                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13143080                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13143080                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13143080                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081784                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.081784                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.081784                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.081784                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.081784                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.081784                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15479.346831                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15479.346831                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2960492                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                    256736769                       # The number of ROB reads
+system.cpu.rob.rob_writes                   209812510                       # The number of ROB writes
+system.cpu.timesIdled                         1906775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       324667246                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4588737338                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60608338                       # Number of Instructions Simulated
+system.cpu.committedOps                      77960937                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60608338                       # Number of Instructions Simulated
+system.cpu.cpi                               8.039902                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.039902                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.124380                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.124380                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                558055788                       # number of integer regfile reads
+system.cpu.int_regfile_writes                90157821                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8288                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2908                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               134082325                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 913357                       # number of misc regfile writes
+system.cpu.icache.replacements                 991945                       # number of replacements
+system.cpu.icache.tagsinuse                511.576100                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12062971                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 992457                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.154654                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             7225347000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.576100                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999172                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999172                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12062971                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12062971                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12062971                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12062971                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12062971                       # number of overall hits
+system.cpu.icache.overall_hits::total        12062971                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1077319                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1077319                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1077319                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1077319                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1077319                       # number of overall misses
+system.cpu.icache.overall_misses::total       1077319                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16672871489                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16672871489                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16672871489                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16672871489                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16672871489                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16672871489                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13140290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13140290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13140290                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13140290                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13140290                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13140290                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081986                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081986                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081986                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081986                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081986                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081986                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15476.262360                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15476.262360                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2904990                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               448                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               436                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  6608.241071                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6662.821101                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84437                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84437                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84437                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84437                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84437                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84437                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       990459                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       990459                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       990459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       990459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       990459                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       990459                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12623481992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12623481992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12623481992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12623481992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12623481992                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12623481992                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84824                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        84824                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        84824                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        84824                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        84824                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        84824                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       992495                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       992495                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       992495                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       992495                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       992495                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       992495                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12649346990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12649346990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12649346990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12649346990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12649346990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12649346990                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075360                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.075360                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.075360                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.075531                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.075531                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 643258                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991338                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21734239                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 643770                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.760876                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 644089                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991456                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 21738846                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 644601                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  33.724499                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991338                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.991456                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13902749                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13902749                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7257426                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7257426                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       285261                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       285261                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285646                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21160175                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21160175                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21160175                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21160175                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       765054                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        765054                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2992955                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2992955                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13791                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13791                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           18                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           18                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3758009                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3758009                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3758009                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3758009                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14856915000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14856915000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 130200810067                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 130200810067                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223590500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    223590500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       349500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       349500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145057725067                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145057725067                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145057725067                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145057725067                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14667803                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14667803                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10250381                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10250381                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299052                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       299052                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285664                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285664                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24918184                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24918184                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24918184                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24918184                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052159                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052159                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.291985                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.291985                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046116                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046116                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000063                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150814                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150814                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150814                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150814                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19419.433138                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19419.433138                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43502.428225                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43502.428225                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16212.783700                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16212.783700                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19416.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19416.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38599.621520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38599.621520                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     34077900                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7429000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7467                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             284                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4563.800723                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26158.450704                       # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data     13908205                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13908205                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7258424                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7258424                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       283313                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       283313                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285772                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285772                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21166629                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21166629                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21166629                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21166629                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       766922                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        766922                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2994004                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2994004                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13808                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13808                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3760926                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3760926                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3760926                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3760926                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14892290500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14892290500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129258725578                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129258725578                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223775000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    223775000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       402000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       402000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144151016078                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144151016078                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144151016078                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144151016078                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14675127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14675127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10252428                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10252428                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297121                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       297121                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285791                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285791                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24927555                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24927555                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24927555                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24927555                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052260                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052260                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.292029                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046473                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046473                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000066                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000066                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.150874                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.150874                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.150874                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.150874                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19418.259614                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19418.259614                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43172.529355                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43172.529355                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16206.184820                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16206.184820                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21157.894737                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21157.894737                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38328.596755                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38328.596755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38328.596755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38328.596755                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     33707409                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7420000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7431                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             286                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4536.052887                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25944.055944                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607519                       # number of writebacks
-system.cpu.dcache.writebacks::total            607519                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379422                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       379422                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744177                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2744177                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1481                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1481                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3123599                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3123599                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3123599                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3123599                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385632                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385632                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248778                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248778                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12310                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12310                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           18                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           18                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634410                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634410                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634410                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634410                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6262166095                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6262166095                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9286622435                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9286622435                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    163471000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    163471000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       289000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       289000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15548788530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15548788530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15548788530                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15548788530                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41268229410                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41268229410                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026291                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026291                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024270                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024270                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041163                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041163                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000063                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025460                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025460                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       608398                       # number of writebacks
+system.cpu.dcache.writebacks::total            608398                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       380638                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       380638                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2745107                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2745107                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1447                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1447                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3125745                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3125745                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3125745                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3125745                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386284                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       386284                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248897                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248897                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       635181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       635181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       635181                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       635181                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6271229149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6271229149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9237690949                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9237690949                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    163909000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    163909000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       338000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       338000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15508920098                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15508920098                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15508920098                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15508920098                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411312500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411312500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41911168414                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41911168414                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224322480914                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 224322480914                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026322                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026322                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041603                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041603                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000066                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025481                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025481                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025481                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025481                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16234.762892                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16234.762892                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37114.513027                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37114.513027                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13260.173125                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13260.173125                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17789.473684                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17789.473684                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24416.536543                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -961,16 +961,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1305424568773                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1323890643510                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88047                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    88043                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index 977ccc85a8110b693df2d439ff6e1c2a9b1d8ce9..6a50fad219e91321fc384aa11200780c748c150c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.582310                       # Number of seconds simulated
-sim_ticks                                2582310281500                       # Number of ticks simulated
-final_tick                               2582310281500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.617033                       # Number of seconds simulated
+sim_ticks                                2617033170500                       # Number of ticks simulated
+final_tick                               2617033170500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  62666                       # Simulator instruction rate (inst/s)
-host_op_rate                                    80652                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2566586582                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 395816                       # Number of bytes of host memory used
-host_seconds                                  1006.13                       # Real time elapsed on the host
-sim_insts                                    63050246                       # Number of instructions simulated
-sim_ops                                      81146063                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker          576                       # Number of bytes read from this memory
+host_inst_rate                                  88113                       # Simulator instruction rate (inst/s)
+host_op_rate                                   113402                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3655705591                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 391256                       # Number of bytes of host memory used
+host_seconds                                   715.88                       # Real time elapsed on the host
+sim_insts                                    63077791                       # Number of instructions simulated
+sim_ops                                      81181923                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker          640                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           396544                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4372212                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          704                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           425600                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          5220016                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129953444                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       396544                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       425600                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          822144                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4241024                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst           395840                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4357428                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker         1152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           425152                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          5244336                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131535204                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       395840                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       425152                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          820992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4255104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data       3012136                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7270160                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            9                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           7284240                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker           10                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst              6196                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             68388                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker           11                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              6650                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             81589                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15105053                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           66266                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst              6185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             68157                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker           18                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              6643                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             81969                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15301800                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           66486                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data           753034                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               823550                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        46290976                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker           223                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker            50                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              153562                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             1693140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           273                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              164814                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             2021452                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                50324488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         153562                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         164814                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             318375                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1642337                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data               6583                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            1166450                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2815370                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1642337                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       46290976                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker          223                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker           50                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             153562                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            1699723                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          273                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             164814                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            3187902                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53139859                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total               823770                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        46277796                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker           245                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker            49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              151255                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             1665026                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           440                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              162456                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             2003924                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50261191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         151255                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         162456                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             313711                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1625927                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data               6496                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            1150974                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2783396                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1625927                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       46277796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker          245                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker           49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             151255                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            1671522                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          440                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             162456                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            3154898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53044587                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          320                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           384                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          320                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst            5                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              6                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          124                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              149                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          124                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          149                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          124                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             149                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         72453                       # number of replacements
-system.l2c.tagsinuse                     52989.750711                       # Cycle average of tags in use
-system.l2c.total_refs                         1967154                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        137652                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         14.290777                       # Average number of references to valid blocks.
+system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           24                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          147                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              171                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           24                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          147                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          171                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           24                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          147                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             171                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         72594                       # number of replacements
+system.l2c.tagsinuse                     53100.305923                       # Cycle average of tags in use
+system.l2c.total_refs                         1970249                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        137794                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         14.298511                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        37689.434458                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker       3.667894                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.004429                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          4220.453796                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          2953.326384                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker       6.708393                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          4009.126872                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          4107.028485                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.575095                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker      0.000056                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        37791.704596                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       4.504480                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.004560                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4202.741800                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          2939.105076                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker      13.484693                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          4025.080355                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          4123.680364                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.576656                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000069                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.064399                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.045064                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker      0.000102                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.061174                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.062668                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.808559                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker        54491                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         6158                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             400629                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             165440                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker        78380                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         6682                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             615050                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             201442                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1528272                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          583270                       # number of Writeback hits
-system.l2c.Writeback_hits::total               583270                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1037                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             784                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1821                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           208                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data           159                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               367                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            48010                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            59262                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               107272                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker         54491                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          6158                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              400629                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              213450                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker         78380                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          6682                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              615050                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              260704                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1635544                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker        54491                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         6158                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             400629                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             213450                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker        78380                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         6682                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             615050                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             260704                       # number of overall hits
-system.l2c.overall_hits::total                1635544                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker            9                       # number of ReadReq misses
+system.l2c.occ_percent::cpu0.inst            0.064129                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.044847                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000206                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.061418                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.062922                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.810246                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        54561                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         5750                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             401038                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             165879                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        78192                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         6577                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             616294                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             201951                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1530242                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          584193                       # number of Writeback hits
+system.l2c.Writeback_hits::total               584193                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1046                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             814                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1860                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           204                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           171                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total               375                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            48310                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            58954                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               107264                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker         54561                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          5750                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              401038                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              214189                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         78192                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          6577                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              616294                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              260905                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1637506                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker        54561                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         5750                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             401038                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             214189                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        78192                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         6577                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             616294                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             260905                       # number of overall hits
+system.l2c.overall_hits::total                1637506                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker           10                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             6068                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             6301                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker           11                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             6610                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             6328                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                25329                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          5681                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          4309                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9990                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          780                       # number of SCUpgradeReq misses
+system.l2c.ReadReq_misses::cpu0.inst             6056                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             6316                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           18                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             6605                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             6313                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                25320                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          5689                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          4311                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             10000                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          783                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::cpu1.data          578                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1358                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          63459                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          76486                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139945                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker            9                       # number of demand (read+write) misses
+system.l2c.SCUpgradeReq_misses::total            1361                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          63204                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          76879                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             140083                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker           10                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              6068                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             69760                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker           11                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              6610                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             82814                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                165274                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker            9                       # number of overall misses
+system.l2c.demand_misses::cpu0.inst              6056                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             69520                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           18                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              6605                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             83192                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                165403                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker           10                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             6068                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            69760                       # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker           11                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             6610                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            82814                       # number of overall misses
-system.l2c.overall_misses::total               165274                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       470500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst             6056                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            69520                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           18                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             6605                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            83192                       # number of overall misses
+system.l2c.overall_misses::total               165403                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker       522500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       112500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    323600498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    331027497                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       573500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    351706500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    332606499                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1340097494                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     20411497                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     27614499                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     48025996                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1617000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6615500                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      8232500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3380389982                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   4066537489                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7446927471                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker       470500                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    322936498                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    331707998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       952500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    351349999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    331785500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1339367495                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     20090481                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27401499                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     47491980                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1617500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6565000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      8182500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3365710489                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   4075887489                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7441597978                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker       522500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       112500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    323600498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3711417479                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker       573500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    351706500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   4399143988                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8787024965                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker       470500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    322936498                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3697418487                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       952500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    351349999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   4407672989                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8780965473                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker       522500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       112500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    323600498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3711417479                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker       573500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    351706500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   4399143988                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8787024965                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker        54500                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         6160                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         406697                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         171741                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker        78391                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         6682                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         621660                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         207770                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1553601                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       583270                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           583270                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         6718                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         5093                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           11811                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          988                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          737                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1725                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       111469                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       135748                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247217                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker        54500                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         6160                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          406697                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          283210                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker        78391                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         6682                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          621660                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          343518                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1800818                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker        54500                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         6160                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         406697                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         283210                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker        78391                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         6682                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         621660                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         343518                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1800818                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014920                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036689                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.010633                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.030457                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016303                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.845639                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.846063                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.845822                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.789474                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.784261                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.787246                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.569297                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.563441                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.566082                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014920                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.246319                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.010633                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.241076                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.091777                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000165                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.000325                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014920                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.246319                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000140                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.010633                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.241076                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.091777                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst    322936498                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3697418487                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       952500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    351349999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   4407672989                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8780965473                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        54571                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         5752                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         407094                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         172195                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        78210                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         6577                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         622899                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         208264                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1555562                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       584193                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           584193                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         6735                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5125                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           11860                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          987                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          749                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1736                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       111514                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       135833                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247347                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker        54571                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         5752                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          407094                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          283709                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        78210                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         6577                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          622899                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          344097                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1802909                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        54571                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         5752                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         407094                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         283709                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        78210                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         6577                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         622899                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         344097                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1802909                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000183                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014876                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036679                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000230                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.010604                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.030312                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016277                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.844692                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.841171                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.843170                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.793313                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.771696                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.783986                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.566781                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.565982                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.566342                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000183                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014876                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.245040                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000230                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.010604                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.241769                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.091742                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000183                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000348                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014876                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.245040                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000230                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.010604                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.241769                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.091742                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52250                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        56250                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53329.020765                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52535.708142                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53208.245083                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52561.077592                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52907.635280                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3592.940855                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6408.563240                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  4807.407007                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2073.076923                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11445.501730                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  6062.223859                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.881987                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53167.082721                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53213.244282                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53325.049207                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52518.682394                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52916.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.549432                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52555.916363                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52897.610387                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3531.460889                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6356.181628                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  4749.198000                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2065.772669                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11358.131488                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  6012.123439                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53251.542450                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53016.916050                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53122.777054                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52250                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        56250                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53329.020765                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 53202.658816                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 53208.245083                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 53120.776535                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53166.408298                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52277.777778                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53325.049207                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 53184.960975                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52916.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 53194.549432                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52981.933227                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53088.308392                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52250                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        56250                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53329.020765                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 53202.658816                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52136.363636                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 53208.245083                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 53120.776535                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53166.408298                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53325.049207                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 53184.960975                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52916.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 53194.549432                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52981.933227                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53088.308392                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -323,168 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               66266                       # number of writebacks
-system.l2c.writebacks::total                    66266                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data            38                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst             5                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.data            23                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                71                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data             38                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst              5                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.data             23                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 71                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data            38                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst             5                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.data            23                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                71                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            9                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               66486                       # number of writebacks
+system.l2c.writebacks::total                    66486                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             4                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            40                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            25                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                76                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              4                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             40                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             25                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 76                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             4                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            40                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            25                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                76                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           10                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         6063                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         6263                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           11                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         6605                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         6305                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           25258                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         5681                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         4309                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         9990                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          780                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         6052                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         6276                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           18                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         6598                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         6288                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           25244                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         5689                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         4311                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        10000                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          783                       # number of SCUpgradeReq MSHR misses
 system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          578                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1358                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        63459                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        76486                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139945                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker            9                       # number of demand (read+write) MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1361                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        63204                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        76879                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140083                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           10                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         6063                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        69722                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker           11                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         6605                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        82791                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           165203                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker            9                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         6052                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        69480                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           18                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         6598                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        83167                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           165327                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           10                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         6063                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        69722                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker           11                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         6605                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        82791                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          165203                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst         6052                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        69480                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           18                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         6598                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        83167                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          165327                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        88000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    249380499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253173000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    270856500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    254736000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1029033999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    227403000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    172571500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    399974500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31217000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23131000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     54348000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2608915998                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3130662995                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5739578993                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    248870498                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    253621500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       733500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    270526499                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    254062500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1028302497                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    227738000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    172587000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    400325000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     31335500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     23126500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     54462000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2597363499                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   3131334993                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5728698492                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        88000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    249380499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   2862088998                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    270856500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3385398995                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6768612992                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       360000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    248870498                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   2850984999                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       733500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    270526499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3385397493                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6757000989                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       400000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        88000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    249380499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   2862088998                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       440000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    270856500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3385398995                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6768612992                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    248870498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   2850984999                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       733500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    270526499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3385397493                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6757000989                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9186576500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122396919500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131591208500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    704511999                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30785024883                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31489536882                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12326324000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      2170500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154700128500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167034202000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1153610999                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31143367304                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32296978303                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      5579000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   9891088499                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2133500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153181944383                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163080745382                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036468                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030346                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016258                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.845639                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.846063                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.845822                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.789474                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.784261                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.787246                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.569297                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.563441                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.566082                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.246185                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.241009                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.091738                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000165                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000325                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014908                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.246185                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000140                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010625                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.241009                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.091738                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13479934999                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      2170500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185843495804                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 199331180303                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000183                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000348                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014866                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036447                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000230                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.010592                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.030192                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016228                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.844692                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.841171                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.843170                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.793313                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.771696                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.783986                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.566781                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.565982                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.566342                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000183                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000348                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014866                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.244899                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000230                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.010592                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.241696                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.091700                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000183                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000348                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014866                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.244899                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000230                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.010592                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.241696                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.091700                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40423.598914                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41122.025446                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40411.328872                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41001.288118                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40404.341603                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40734.530859                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.288451                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.098817                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40032.500000                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40019.795658                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.245675                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40016.164585                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41094.922774                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40730.693596                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40895.030032                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40971.489573                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41122.025446                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41033.175000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41001.288118                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40706.019130                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40870.523199                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        44000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40971.489573                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41122.025446                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41033.175000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40750                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41001.288118                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40706.019130                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40870.523199                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -507,27 +507,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9083896                       # DTB read hits
-system.cpu0.dtb.read_misses                     37543                       # DTB read misses
-system.cpu0.dtb.write_hits                    5286239                       # DTB write hits
-system.cpu0.dtb.write_misses                     6882                       # DTB write misses
+system.cpu0.dtb.read_hits                     9087709                       # DTB read hits
+system.cpu0.dtb.read_misses                     37707                       # DTB read misses
+system.cpu0.dtb.write_hits                    5292852                       # DTB write hits
+system.cpu0.dtb.write_misses                     6797                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2244                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                     1393                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   382                       # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries                    2252                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults                     1465                       # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults                   402                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      574                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9121439                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5293121                       # DTB write accesses
+system.cpu0.dtb.perms_faults                      573                       # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses                 9125416                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5299649                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         14370135                       # DTB hits
-system.cpu0.dtb.misses                          44425                       # DTB misses
-system.cpu0.dtb.accesses                     14414560                       # DTB accesses
-system.cpu0.itb.inst_hits                     4418601                       # ITB inst hits
-system.cpu0.itb.inst_misses                      6114                       # ITB inst misses
+system.cpu0.dtb.hits                         14380561                       # DTB hits
+system.cpu0.dtb.misses                          44504                       # DTB misses
+system.cpu0.dtb.accesses                     14425065                       # DTB accesses
+system.cpu0.itb.inst_hits                     4426363                       # ITB inst hits
+system.cpu0.itb.inst_misses                      5791                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.write_hits                          0                       # DTB write hits
@@ -540,118 +540,118 @@ system.cpu0.itb.flush_entries                    1409                       # Nu
 system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                     1633                       # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults                     1661                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                 4424715                       # ITB inst accesses
-system.cpu0.itb.hits                          4418601                       # DTB hits
-system.cpu0.itb.misses                           6114                       # DTB misses
-system.cpu0.itb.accesses                      4424715                       # DTB accesses
-system.cpu0.numCycles                        66354055                       # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses                 4432154                       # ITB inst accesses
+system.cpu0.itb.hits                          4426363                       # DTB hits
+system.cpu0.itb.misses                           5791                       # DTB misses
+system.cpu0.itb.accesses                      4432154                       # DTB accesses
+system.cpu0.numCycles                        73540541                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                 6346252                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           4857071                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            316053                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              4075974                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 3037671                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                 6354280                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted           4863798                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect            316535                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups              4079773                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                 3047693                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  700378                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              30829                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles          12963003                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                      33274045                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                    6346252                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches           3738049                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                      7812188                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                1602844                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles                     89446                       # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles              22023764                       # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles                5932                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles        73578                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles        90886                       # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles          179                       # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines                  4416774                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes               175280                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes                   3223                       # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples          44209960                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             0.971808                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.352806                       # Number of instructions fetched each cycle (Total)
+system.cpu0.BPredUnit.usedRAS                  700511                       # Number of times the RAS was used to get a target.
+system.cpu0.BPredUnit.RASInCorrect              30883                       # Number of incorrect RAS predictions.
+system.cpu0.fetch.icacheStallCycles          12981968                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                      33339853                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                    6354280                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches           3748204                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                      7827899                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                1608255                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles                     88516                       # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles              23525864                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles                5853                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles        77679                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles        91798                       # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles          193                       # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines                  4424514                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes               175463                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes                   2818                       # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples          45755598                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             0.940589                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.320885                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                36406101     82.35%     82.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                  622907      1.41%     83.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                  820090      1.85%     85.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                  691511      1.56%     87.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                  794774      1.80%     88.97% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                  578673      1.31%     90.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                  721468      1.63%     91.91% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                  370773      0.84%     92.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                 3203663      7.25%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                37936221     82.91%     82.91% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                  625086      1.37%     84.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                  819758      1.79%     86.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                  695394      1.52%     87.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                  800497      1.75%     89.34% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                  578636      1.26%     90.60% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                  719119      1.57%     92.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                  370554      0.81%     92.98% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                 3210333      7.02%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total            44209960                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.095642                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       0.501462                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                13460475                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles             22052761                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                  7004876                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles               606078                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles               1085770                       # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved              992839                       # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred                66349                       # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts              41502146                       # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts               217622                       # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles               1085770                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                14072541                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                6178049                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles      13569314                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                  6948288                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles              2355998                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts              40249124                       # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents                 2572                       # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents                473537                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents              1335703                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents             188                       # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands           40597200                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups            181819083                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups       181783808                       # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups            35275                       # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps             31678350                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                 8918849                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts            463403                       # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts        418800                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                  5692374                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads             7927385                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores            5883720                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads          1132627                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores         1230816                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                  38008933                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded             947103                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                 38247071                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued            93468                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined        6756686                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined     14324325                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved        258267                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples     44209960                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        0.865123                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.479533                       # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total            45755598                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.086405                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       0.453353                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                13479181                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles             23559009                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                  7020718                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles               606128                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles               1090562                       # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved              996028                       # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred                66487                       # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts              41577642                       # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts               218603                       # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles               1090562                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                14092626                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                6784553                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles      14469405                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                  6963849                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles              2354603                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts              40318960                       # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents                 2633                       # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents                472928                       # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents              1334672                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents             351                       # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands           40667832                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups            182121697                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups       182086780                       # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups            34917                       # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps             31702592                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                 8965239                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts            463825                       # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts        419023                       # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts                  5696158                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads             7936117                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores            5894118                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads          1139492                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores         1233570                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                  38069002                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded             950684                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                 38295497                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued            94171                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined        6802670                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined     14391567                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved        261548                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples     45755598                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        0.836958                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.462966                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0           28324155     64.07%     64.07% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1            6346765     14.36%     78.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2            3236431      7.32%     85.74% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3            2507997      5.67%     91.42% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4            2107881      4.77%     96.18% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5             937016      2.12%     98.30% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6             515116      1.17%     99.47% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7             180639      0.41%     99.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8              53960      0.12%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0           29855724     65.25%     65.25% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1            6336412     13.85%     79.10% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2            3245721      7.09%     86.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3            2523061      5.51%     91.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4            2111675      4.62%     96.32% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5             936021      2.05%     98.37% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6             511535      1.12%     99.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7             181147      0.40%     99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8              54302      0.12%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total       44209960                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total       45755598                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                  27715      2.59%      2.59% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                   460      0.04%      2.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                  27761      2.59%      2.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                   464      0.04%      2.63% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IntDiv                      0      0.00%      2.63% # attempts to use FU when none available
 system.cpu0.iq.fu_full::FloatAdd                    0      0.00%      2.63% # attempts to use FU when none available
 system.cpu0.iq.fu_full::FloatCmp                    0      0.00%      2.63% # attempts to use FU when none available
@@ -679,401 +679,401 @@ system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%      2.63% # at
 system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%      2.63% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%      2.63% # attempts to use FU when none available
 system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%      2.63% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                839091     78.45%     81.09% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite               202283     18.91%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                835942     77.99%     80.62% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite               207752     19.38%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass            52344      0.14%      0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu             22968400     60.05%     60.19% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult               50115      0.13%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                 14      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 2      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc             11      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc           684      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc           11      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.32% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead             9563149     25.00%     85.33% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite            5612341     14.67%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu             23003680     60.07%     60.21% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult               50163      0.13%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                 14      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 3      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc             10      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc           682      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc           10      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     60.34% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead             9567598     24.98%     85.32% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite            5620993     14.68%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total              38247071                       # Type of FU issued
-system.cpu0.iq.rate                          0.576409                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                    1069549                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.027964                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads         121902835                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes         45721169                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses     35306324                       # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads               8427                       # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes              4840                       # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses         3930                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses              39259896                       # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses                   4380                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads          325721                       # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total              38295497                       # Type of FU issued
+system.cpu0.iq.rate                          0.520740                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                    1071919                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.027991                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads         123548516                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes         45830842                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses     35351164                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads               8368                       # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes              4748                       # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses         3893                       # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses              39310727                       # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses                   4345                       # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads          327037                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads      1504145                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses         3982                       # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation        13879                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores       608088                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads      1508258                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses         3980                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation        13847                       # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores       614652                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads      2149487                       # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked         5263                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads      2149655                       # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked         5288                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles               1085770                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                4069341                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles               129560                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts           39094255                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts            87678                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts              7927385                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts             5883720                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts            614122                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                 49261                       # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents                17662                       # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents         13879                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        160370                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect       144551                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              304921                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts             37828601                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts              9401576                       # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts           418470                       # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles               1090562                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                4675196                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles               127491                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts           39158193                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts            88903                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts              7936117                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts             5894118                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts            617815                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                 49276                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents                17780                       # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents         13847                       # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect        160769                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect       144529                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts              305298                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts             37872918                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts              9405503                       # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts           422579                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                       138219                       # number of nop insts executed
-system.cpu0.iew.exec_refs                    14960222                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                 5069889                       # Number of branches executed
-system.cpu0.iew.exec_stores                   5558646                       # Number of stores executed
-system.cpu0.iew.exec_rate                    0.570102                       # Inst execution rate
-system.cpu0.iew.wb_sent                      37608832                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                     35310254                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                 18670977                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                 35573590                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                       138507                       # number of nop insts executed
+system.cpu0.iew.exec_refs                    14971538                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                 5077620                       # Number of branches executed
+system.cpu0.iew.exec_stores                   5566035                       # Number of stores executed
+system.cpu0.iew.exec_rate                    0.514994                       # Inst execution rate
+system.cpu0.iew.wb_sent                      37653849                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                     35355057                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                 18700837                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                 35658328                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      0.532149                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.524855                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      0.480756                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.524445                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      24262280                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps        31997725                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts        6679991                       # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls         688836                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts           267429                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples     43160582                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     0.741365                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     1.695624                       # Number of insts commited each cycle
+system.cpu0.commit.commitCommittedInsts      24280608                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        32020757                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts        6703968                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls         689136                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts           267907                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples     44701440                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     0.716325                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     1.672707                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0     31020137     71.87%     71.87% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1      6071618     14.07%     85.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2      1950463      4.52%     90.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3      1036843      2.40%     92.86% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4       799662      1.85%     94.71% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5       507487      1.18%     95.89% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6       407135      0.94%     96.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7       202137      0.47%     97.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8      1165100      2.70%    100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0     32554343     72.83%     72.83% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1      6077315     13.60%     86.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2      1947893      4.36%     90.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3      1038743      2.32%     93.10% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4       803562      1.80%     94.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5       505193      1.13%     96.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6       401469      0.90%     96.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7       200976      0.45%     97.38% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8      1171946      2.62%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total     43160582                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts            24262280                       # Number of instructions committed
-system.cpu0.commit.committedOps              31997725                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total     44701440                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts            24280608                       # Number of instructions committed
+system.cpu0.commit.committedOps              32020757                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                      11698872                       # Number of memory references committed
-system.cpu0.commit.loads                      6423240                       # Number of loads committed
-system.cpu0.commit.membars                     234547                       # Number of memory barriers committed
-system.cpu0.commit.branches                   4415502                       # Number of branches committed
+system.cpu0.commit.refs                      11707325                       # Number of memory references committed
+system.cpu0.commit.loads                      6427859                       # Number of loads committed
+system.cpu0.commit.membars                     234599                       # Number of memory barriers committed
+system.cpu0.commit.branches                   4418672                       # Number of branches committed
 system.cpu0.commit.fp_insts                      3838                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                 28265931                       # Number of committed integer instructions.
-system.cpu0.commit.function_calls              499946                       # Number of function calls committed.
-system.cpu0.commit.bw_lim_events              1165100                       # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts                 28286546                       # Number of committed integer instructions.
+system.cpu0.commit.function_calls              500309                       # Number of function calls committed.
+system.cpu0.commit.bw_lim_events              1171946                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                    79788976                       # The number of ROB reads
-system.cpu0.rob.rob_writes                   78443760                       # The number of ROB writes
-system.cpu0.timesIdled                         426851                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                       22144095                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles                  5098222727                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   24181538                       # Number of Instructions Simulated
-system.cpu0.committedOps                     31916983                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total             24181538                       # Number of Instructions Simulated
-system.cpu0.cpi                              2.743996                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        2.743996                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.364432                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.364432                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads               176533858                       # number of integer regfile reads
-system.cpu0.int_regfile_writes               35079827                       # number of integer regfile writes
-system.cpu0.fp_regfile_reads                     3404                       # number of floating regfile reads
-system.cpu0.fp_regfile_writes                     942                       # number of floating regfile writes
-system.cpu0.misc_regfile_reads               47584444                       # number of misc regfile reads
-system.cpu0.misc_regfile_writes                527516                       # number of misc regfile writes
-system.cpu0.icache.replacements                406873                       # number of replacements
-system.cpu0.icache.tagsinuse               511.614484                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                 3975135                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                407385                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  9.757686                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle            6470209000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   511.614484                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.999247                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.999247                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst      3975135                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total        3975135                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst      3975135                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total         3975135                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst      3975135                       # number of overall hits
-system.cpu0.icache.overall_hits::total        3975135                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       441500                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       441500                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       441500                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        441500                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       441500                       # number of overall misses
-system.cpu0.icache.overall_misses::total       441500                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7129067996                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7129067996                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7129067996                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7129067996                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7129067996                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7129067996                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst      4416635                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total      4416635                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst      4416635                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total      4416635                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst      4416635                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total      4416635                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.099963                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.099963                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.099963                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.099963                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.099963                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.099963                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 16147.379379                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 16147.379379                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs      1348496                       # number of cycles access was blocked
+system.cpu0.rob.rob_reads                    81369547                       # The number of ROB reads
+system.cpu0.rob.rob_writes                   78542452                       # The number of ROB writes
+system.cpu0.timesIdled                         427204                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                       27784943                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles                  5160481977                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts                   24199866                       # Number of Instructions Simulated
+system.cpu0.committedOps                     31940015                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             24199866                       # Number of Instructions Simulated
+system.cpu0.cpi                              3.038882                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        3.038882                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.329068                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.329068                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads               176731885                       # number of integer regfile reads
+system.cpu0.int_regfile_writes               35129220                       # number of integer regfile writes
+system.cpu0.fp_regfile_reads                     3381                       # number of floating regfile reads
+system.cpu0.fp_regfile_writes                     940                       # number of floating regfile writes
+system.cpu0.misc_regfile_reads               47656068                       # number of misc regfile reads
+system.cpu0.misc_regfile_writes                527809                       # number of misc regfile writes
+system.cpu0.icache.replacements                407270                       # number of replacements
+system.cpu0.icache.tagsinuse               511.577657                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                 3982592                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                407782                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  9.766473                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle            7275068000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   511.577657                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.999175                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999175                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      3982592                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total        3982592                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst      3982592                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total         3982592                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst      3982592                       # number of overall hits
+system.cpu0.icache.overall_hits::total        3982592                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       441782                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       441782                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       441782                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        441782                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       441782                       # number of overall misses
+system.cpu0.icache.overall_misses::total       441782                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7132710997                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   7132710997                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   7132710997                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   7132710997                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   7132710997                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   7132710997                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      4424374                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total      4424374                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst      4424374                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total      4424374                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      4424374                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total      4424374                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.099852                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.099852                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.099852                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.099852                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.099852                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.099852                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16145.318272                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 16145.318272                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16145.318272                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 16145.318272                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16145.318272                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 16145.318272                       # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs      1383498                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs              167                       # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs              169                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs  8074.826347                       # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs  8186.378698                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        34106                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total        34106                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst        34106                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total        34106                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst        34106                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total        34106                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       407394                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       407394                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       407394                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       407394                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       407394                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       407394                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5468654996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5468654996                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5468654996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5468654996                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5468654996                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5468654996                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        33988                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        33988                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        33988                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        33988                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        33988                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        33988                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       407794                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       407794                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       407794                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       407794                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       407794                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       407794                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5471235499                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   5471235499                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5471235499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   5471235499                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5471235499                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   5471235499                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      8379000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      8379000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total      8379000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.092241                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.092241                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.092241                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.092241                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.092170                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.092170                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.092170                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.092170                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.092170                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.092170                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13416.665029                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13416.665029                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13416.665029                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 13416.665029                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13416.665029                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 13416.665029                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                275592                       # number of replacements
-system.cpu0.dcache.tagsinuse               476.837382                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 9554493                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                276104                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 34.604689                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                275687                       # number of replacements
+system.cpu0.dcache.tagsinuse               476.019935                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                 9558592                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                276199                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 34.607627                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              51448000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   476.837382                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.931323                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.931323                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5935954                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5935954                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3226635                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3226635                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174405                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       174405                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171548                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       171548                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      9162589                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         9162589                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      9162589                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        9162589                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       400527                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       400527                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data      1594104                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total      1594104                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         8985                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         8985                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7776                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7776                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data      1994631                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total       1994631                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data      1994631                       # number of overall misses
-system.cpu0.dcache.overall_misses::total      1994631                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7261400500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   7261400500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71837415855                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total  71837415855                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    113971500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    113971500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     93410500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     93410500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  79098816355                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  79098816355                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  79098816355                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  79098816355                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6336481                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6336481                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      4820739                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      4820739                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183390                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       183390                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179324                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       179324                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     11157220                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     11157220                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     11157220                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     11157220                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063210                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.063210                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330676                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.330676                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.048994                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.048994                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043363                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043363                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178775                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.178775                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178775                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.178775                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs      7527492                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets      1548500                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs             1462                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets             87                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  5148.763338                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575                       # average number of cycles each access was blocked
+system.cpu0.dcache.occ_blocks::cpu0.data   476.019935                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.929726                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.929726                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      5937166                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        5937166                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3229422                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       3229422                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       174299                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       174299                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       171559                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       171559                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data      9166588                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total         9166588                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data      9166588                       # number of overall hits
+system.cpu0.dcache.overall_hits::total        9166588                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       401556                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       401556                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1594295                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total      1594295                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9014                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9014                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7780                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7780                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1995851                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1995851                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1995851                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1995851                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   7292954000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   7292954000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  71657694355                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  71657694355                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    113831500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    113831500                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     90370500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     90370500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  78950648355                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  78950648355                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  78950648355                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  78950648355                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6338722                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6338722                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      4823717                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      4823717                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       183313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       183313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       179339                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       179339                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     11162439                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     11162439                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     11162439                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     11162439                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.063350                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.063350                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.330512                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.330512                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.049173                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.049173                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.043382                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.043382                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.178801                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.178801                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.178801                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.178801                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18161.735848                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 18161.735848                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44946.320697                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 44946.320697                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12628.300422                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12628.300422                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11615.745501                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11615.745501                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39557.385975                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 39557.385975                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39557.385975                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 39557.385975                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs      7317992                       # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets      1712000                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs             1467                       # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets             85                       # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  4988.406271                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 20141.176471                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       255542                       # number of writebacks
-system.cpu0.dcache.writebacks::total           255542                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       211236                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total       211236                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1463026                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total      1463026                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          516                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total          516                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data      1674262                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total      1674262                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data      1674262                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total      1674262                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189291                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       189291                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131078                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       131078                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8469                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8469                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks       255942                       # number of writebacks
+system.cpu0.dcache.writebacks::total           255942                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       212150                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       212150                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1463164                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1463164                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          530                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          530                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1675314                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1675314                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1675314                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1675314                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       189406                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       189406                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       131131                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       131131                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         8484                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         8484                       # number of LoadLockedReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7773                       # number of StoreCondReq MSHR misses
 system.cpu0.dcache.StoreCondReq_mshr_misses::total         7773                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       320369                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       320369                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       320369                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       320369                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2800937917                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2800937917                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4685815512                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4685815512                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     79569505                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     79569505                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     68924555                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     68924555                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       320537                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       320537                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       320537                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       320537                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2811014487                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2811014487                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4674099005                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4674099005                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     79244002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     79244002                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     65918035                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     65918035                       # number of StoreCondReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
 system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7486753429                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7486753429                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7486753429                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7486753429                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10315126500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10315126500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    849486399                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    849486399                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11164612899                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11164612899                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029873                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029873                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027190                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027190                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046180                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046180                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043346                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043346                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028714                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.028714                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028714                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.028714                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9395.383753                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9395.383753                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8867.175479                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8867.175479                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7485113492                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7485113492                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7485113492                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7485113492                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13455989500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13455989500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1298746899                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1298746899                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14754736399                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14754736399                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.029881                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.029881                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.027185                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.027185                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.046281                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.046281                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.043342                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.043342                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028716                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.028716                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028716                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.028716                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14841.211403                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14841.211403                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35644.500576                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35644.500576                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9340.405705                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9340.405705                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8480.385308                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8480.385308                       # average StoreCondReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
 system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23351.792436                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23351.792436                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23351.792436                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23351.792436                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                    43445270                       # DTB read hits
-system.cpu1.dtb.read_misses                     46285                       # DTB read misses
-system.cpu1.dtb.write_hits                    7088572                       # DTB write hits
-system.cpu1.dtb.write_misses                    12217                       # DTB write misses
+system.cpu1.dtb.read_hits                    43452334                       # DTB read hits
+system.cpu1.dtb.read_misses                     46277                       # DTB read misses
+system.cpu1.dtb.write_hits                    7091337                       # DTB write hits
+system.cpu1.dtb.write_misses                    12150                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    2504                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                     3688                       # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.flush_entries                    2524                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults                     3762                       # Number of TLB faults due to alignment restrictions
 system.cpu1.dtb.prefetch_faults                   371                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      674                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                43491555                       # DTB read accesses
-system.cpu1.dtb.write_accesses                7100789                       # DTB write accesses
+system.cpu1.dtb.perms_faults                      692                       # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses                43498611                       # DTB read accesses
+system.cpu1.dtb.write_accesses                7103487                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         50533842                       # DTB hits
-system.cpu1.dtb.misses                          58502                       # DTB misses
-system.cpu1.dtb.accesses                     50592344                       # DTB accesses
-system.cpu1.itb.inst_hits                     9223213                       # ITB inst hits
-system.cpu1.itb.inst_misses                      6180                       # ITB inst misses
+system.cpu1.dtb.hits                         50543671                       # DTB hits
+system.cpu1.dtb.misses                          58427                       # DTB misses
+system.cpu1.dtb.accesses                     50602098                       # DTB accesses
+system.cpu1.itb.inst_hits                     9232744                       # ITB inst hits
+system.cpu1.itb.inst_misses                      6115                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.write_hits                          0                       # DTB write hits
@@ -1112,122 +1112,122 @@ system.cpu1.itb.flush_tlb                           4                       # Nu
 system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1615                       # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries                    1606                       # Number of entries that have been flushed from TLB
 system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
 system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                     1780                       # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults                     1727                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                 9229393                       # ITB inst accesses
-system.cpu1.itb.hits                          9223213                       # DTB hits
-system.cpu1.itb.misses                           6180                       # DTB misses
-system.cpu1.itb.accesses                      9229393                       # DTB accesses
-system.cpu1.numCycles                       355232424                       # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses                 9238859                       # ITB inst accesses
+system.cpu1.itb.hits                          9232744                       # DTB hits
+system.cpu1.itb.misses                           6115                       # DTB misses
+system.cpu1.itb.accesses                      9238859                       # DTB accesses
+system.cpu1.numCycles                       420389270                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 9848764                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           8083275                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            447123                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              6868345                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 5662939                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                 9847995                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted           8081754                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect            448433                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups              6818773                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                 5657403                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  832004                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              49676                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles          22148379                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                      71952458                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                    9848764                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches           6494943                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                     15333431                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                4632908                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles                     88364                       # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles              74838070                       # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles                5775                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles        63991                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles       141562                       # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles          138                       # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines                  9221022                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes               859641                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes                   3677                       # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples         115781579                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             0.750934                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.109459                       # Number of instructions fetched each cycle (Total)
+system.cpu1.BPredUnit.usedRAS                  833939                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.RASInCorrect              50420                       # Number of incorrect RAS predictions.
+system.cpu1.fetch.icacheStallCycles          22177481                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                      71987538                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                    9847995                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches           6491342                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                     15338669                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                4640041                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles                     86616                       # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles              81067805                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles                5869                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles        63713                       # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles       142087                       # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles           99                       # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines                  9230611                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes               860735                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes                   3603                       # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples         122048207                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             0.712843                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.062128                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0               100456410     86.76%     86.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                  829573      0.72%     87.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                 1015846      0.88%     88.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                 2061622      1.78%     90.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                 1645380      1.42%     91.56% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                  616095      0.53%     92.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                 2274849      1.96%     94.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                  467300      0.40%     94.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                 6414504      5.54%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0               106717875     87.44%     87.44% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                  829211      0.68%     88.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                 1015415      0.83%     88.95% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                 2063306      1.69%     90.64% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                 1641471      1.34%     91.99% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                  615009      0.50%     92.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                 2274741      1.86%     94.35% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                  467540      0.38%     94.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                 6423639      5.26%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total           115781579                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.027725                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       0.202550                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                23776389                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles             74601447                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                 13781615                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles               561009                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles               3061119                       # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved             1241407                       # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred               102665                       # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts              81190791                       # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts               341149                       # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles               3061119                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                25333003                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles               33967991                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles      36116187                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                 12703540                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles              4599739                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts              74711209                       # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents                20422                       # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents                719883                       # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents              3284162                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents           33659                       # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands           79078972                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups            344223554                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups       344164086                       # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups            59468                       # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps             50180386                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                28898586                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts            486916                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts        421354                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                  8389500                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads            14026564                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores            8607423                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads          1068694                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores         1518812                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                  67421543                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded            1209489                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                 91958955                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued           109721                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined       18898752                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined     53543776                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved        290002                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples    115781579                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        0.794245                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.521941                       # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total           122048207                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.023426                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       0.171240                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                23807304                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles             80829213                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                 13786228                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles               560401                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles               3065061                       # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved             1241341                       # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred               102643                       # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts              81234919                       # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts               343119                       # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles               3065061                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                25364340                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles               34010393                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles      42304537                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                 12707018                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles              4596858                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts              74746383                       # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents                20429                       # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents                720817                       # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents              3279864                       # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents           33412                       # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands           79106997                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups            344419030                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups       344359691                       # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups            59339                       # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps             50193146                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                28913851                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts            487769                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts        421850                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                  8399849                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads            14034972                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores            8614706                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads          1072487                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores         1529720                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                  67446295                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded            1206628                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                 91979521                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued           109681                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined       18910261                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined     53596675                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved        286825                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples    122048207                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        0.753633                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.492572                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0           83973534     72.53%     72.53% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1            9124499      7.88%     80.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2            4576997      3.95%     84.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3            4009566      3.46%     87.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4           10699106      9.24%     97.07% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5            1974757      1.71%     98.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6            1060771      0.92%     99.69% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7             281863      0.24%     99.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8              80486      0.07%    100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0           90230410     73.93%     73.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1            9124502      7.48%     81.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2            4577298      3.75%     85.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3            4017634      3.29%     88.45% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4           10703333      8.77%     97.22% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5            1977632      1.62%     98.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6            1055737      0.87%     99.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7             281681      0.23%     99.93% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8              79980      0.07%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total      115781579                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total      122048207                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                  29310      0.37%      0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                   993      0.01%      0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                  28913      0.37%      0.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                   998      0.01%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IntDiv                      0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      0.38% # attempts to use FU when none available
@@ -1255,13 +1255,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      0.38% # at
 system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      0.38% # attempts to use FU when none available
 system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      0.38% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead               7573445     95.84%     96.23% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite               298199      3.77%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead               7574685     95.84%     96.22% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite               298874      3.78%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass           313737      0.34%      0.34% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu             39470238     42.92%     43.26% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult               61477      0.07%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu             39479578     42.92%     43.26% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult               61492      0.07%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     43.33% # Type of FU issued
@@ -1274,378 +1274,382 @@ system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     43.33% # Ty
 system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                 11      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                 12      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 2      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              8      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 6      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              7      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc          1690      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc          1697      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            8      0.00%     43.33% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     43.33% # Type of FU issued
 system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     43.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead            44643108     48.55%     91.88% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite            7468676      8.12%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead            44651207     48.54%     91.88% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite            7471778      8.12%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total              91958955                       # Type of FU issued
-system.cpu1.iq.rate                          0.258870                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                    7901947                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.085929                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads         307754751                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes         87542996                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses     55769663                       # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads              14772                       # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes              8137                       # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses         6817                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses              99539441                       # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses                   7724                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads          371642                       # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total              91979521                       # Type of FU issued
+system.cpu1.iq.rate                          0.218796                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                    7903470                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.085926                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads         314063875                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes         87576510                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses     55784562                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads              14814                       # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes              8109                       # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses         6801                       # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses              99561488                       # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses                   7766                       # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads          369403                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads      4037130                       # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses         6814                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation        21954                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores      1589436                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads      4042367                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses         6847                       # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation        22042                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores      1594624                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads     31965709                       # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked      1043610                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads     31965742                       # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked      1047944                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles               3061119                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles               25601852                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles               406330                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts           68756671                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts           131432                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts             14026564                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts             8607423                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts            899609                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                 81519                       # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents                 7124                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents         21954                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect        226065                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect       196785                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts              422850                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts             89098857                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts             43830249                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts          2860098                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles               3065061                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles               25634357                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles               409319                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts           68777683                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts           134755                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts             14034972                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts             8614706                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts            896270                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                 80399                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents                14951                       # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents         22042                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect        226446                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect       198201                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts              424647                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts             89117462                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts             43838045                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts          2862059                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                       125639                       # number of nop insts executed
-system.cpu1.iew.exec_refs                    51224079                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                 7396455                       # Number of branches executed
-system.cpu1.iew.exec_stores                   7393830                       # Number of stores executed
-system.cpu1.iew.exec_rate                    0.250818                       # Inst execution rate
-system.cpu1.iew.wb_sent                      87931251                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                     55776480                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                 30792122                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                 54566321                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                       124760                       # number of nop insts executed
+system.cpu1.iew.exec_refs                    51234744                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                 7395685                       # Number of branches executed
+system.cpu1.iew.exec_stores                   7396699                       # Number of stores executed
+system.cpu1.iew.exec_rate                    0.211988                       # Inst execution rate
+system.cpu1.iew.wb_sent                      87946957                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                     55791363                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                 30796912                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                 54575062                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      0.157014                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.564306                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      0.132714                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.564304                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      38938347                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps        49298719                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts       19014978                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls         919487                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts           376070                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples    112768879                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     0.437166                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.403258                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts      38947564                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        49311547                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts       19037243                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls         919803                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts           377326                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples    119031582                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     0.414273                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.369590                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0     95484340     84.67%     84.67% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1      8537208      7.57%     92.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2      2210726      1.96%     94.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3      1312266      1.16%     95.37% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4      1283048      1.14%     96.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5       588048      0.52%     97.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6      1003635      0.89%     97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7       487845      0.43%     98.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8      1861763      1.65%    100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0    101746657     85.48%     85.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1      8535054      7.17%     92.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2      2209116      1.86%     94.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3      1312161      1.10%     95.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4      1288209      1.08%     96.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5       590684      0.50%     97.19% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6       998098      0.84%     98.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7       485890      0.41%     98.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8      1865713      1.57%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total    112768879                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts            38938347                       # Number of instructions committed
-system.cpu1.commit.committedOps              49298719                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total    119031582                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts            38947564                       # Number of instructions committed
+system.cpu1.commit.committedOps              49311547                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                      17007421                       # Number of memory references committed
-system.cpu1.commit.loads                      9989434                       # Number of loads committed
-system.cpu1.commit.membars                     202281                       # Number of memory barriers committed
-system.cpu1.commit.branches                   6220621                       # Number of branches committed
+system.cpu1.commit.refs                      17012687                       # Number of memory references committed
+system.cpu1.commit.loads                      9992605                       # Number of loads committed
+system.cpu1.commit.membars                     202357                       # Number of memory barriers committed
+system.cpu1.commit.branches                   6222202                       # Number of branches committed
 system.cpu1.commit.fp_insts                      6758                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                 43690243                       # Number of committed integer instructions.
-system.cpu1.commit.function_calls              556165                       # Number of function calls committed.
-system.cpu1.commit.bw_lim_events              1861763                       # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts                 43701968                       # Number of committed integer instructions.
+system.cpu1.commit.function_calls              556417                       # Number of function calls committed.
+system.cpu1.commit.bw_lim_events              1865713                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                   178106600                       # The number of ROB reads
-system.cpu1.rob.rob_writes                  139781050                       # The number of ROB writes
-system.cpu1.timesIdled                        1519184                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                      239450845                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                  4808685831                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   38868708                       # Number of Instructions Simulated
-system.cpu1.committedOps                     49229080                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total             38868708                       # Number of Instructions Simulated
-system.cpu1.cpi                              9.139291                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        9.139291                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.109418                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.109418                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads               398713179                       # number of integer regfile reads
-system.cpu1.int_regfile_writes               58485097                       # number of integer regfile writes
-system.cpu1.fp_regfile_reads                     4918                       # number of floating regfile reads
-system.cpu1.fp_regfile_writes                    2338                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads               91819776                       # number of misc regfile reads
-system.cpu1.misc_regfile_writes                429481                       # number of misc regfile writes
-system.cpu1.icache.replacements                621812                       # number of replacements
-system.cpu1.icache.tagsinuse               498.762593                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                 8548797                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                622324                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 13.736891                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           74633258000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   498.762593                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.974146                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.974146                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst      8548797                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total        8548797                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst      8548797                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total         8548797                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst      8548797                       # number of overall hits
-system.cpu1.icache.overall_hits::total        8548797                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       672174                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       672174                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       672174                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        672174                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       672174                       # number of overall misses
-system.cpu1.icache.overall_misses::total       672174                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10613540997                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total  10613540997                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst  10613540997                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total  10613540997                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst  10613540997                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total  10613540997                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst      9220971                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total      9220971                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst      9220971                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total      9220971                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst      9220971                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total      9220971                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.072896                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.072896                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.072896                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.072896                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.072896                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.072896                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 15789.871368                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 15789.871368                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs      1180997                       # number of cycles access was blocked
+system.cpu1.rob.rob_reads                   184400014                       # The number of ROB reads
+system.cpu1.rob.rob_writes                  139856425                       # The number of ROB writes
+system.cpu1.timesIdled                        1519588                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles                      298341063                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                  4812976632                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                   38877925                       # Number of Instructions Simulated
+system.cpu1.committedOps                     49241908                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             38877925                       # Number of Instructions Simulated
+system.cpu1.cpi                             10.813058                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                       10.813058                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.092481                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.092481                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads               398800057                       # number of integer regfile reads
+system.cpu1.int_regfile_writes               58498146                       # number of integer regfile writes
+system.cpu1.fp_regfile_reads                     4943                       # number of floating regfile reads
+system.cpu1.fp_regfile_writes                    2344                       # number of floating regfile writes
+system.cpu1.misc_regfile_reads               91875872                       # number of misc regfile reads
+system.cpu1.misc_regfile_writes                429758                       # number of misc regfile writes
+system.cpu1.icache.replacements                623101                       # number of replacements
+system.cpu1.icache.tagsinuse               498.730815                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 8556871                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                623613                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 13.721444                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           75785780000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   498.730815                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.974084                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.974084                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      8556871                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        8556871                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      8556871                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         8556871                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      8556871                       # number of overall hits
+system.cpu1.icache.overall_hits::total        8556871                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       673686                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       673686                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       673686                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        673686                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       673686                       # number of overall misses
+system.cpu1.icache.overall_misses::total       673686                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  10642693998                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total  10642693998                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst  10642693998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total  10642693998                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst  10642693998                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total  10642693998                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      9230557                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      9230557                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      9230557                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      9230557                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      9230557                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      9230557                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.072984                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.072984                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.072984                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.072984                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.072984                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.072984                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15797.706941                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15797.706941                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15797.706941                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15797.706941                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15797.706941                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15797.706941                       # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs      1133998                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs              198                       # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs              174                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs  5964.631313                       # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs  6517.229885                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        49820                       # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total        49820                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst        49820                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total        49820                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst        49820                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total        49820                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       622354                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       622354                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       622354                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       622354                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       622354                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       622354                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8128418498                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   8128418498                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8128418498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   8128418498                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8128418498                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   8128418498                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3154000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3154000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total      3154000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067493                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.067493                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067493                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.067493                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        50044                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        50044                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        50044                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        50044                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        50044                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        50044                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       623642                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       623642                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       623642                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       623642                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       623642                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       623642                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   8149352498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   8149352498                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   8149352498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   8149352498                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   8149352498                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   8149352498                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      3211500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      3211500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      3211500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      3211500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.067563                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.067563                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.067563                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.067563                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.067563                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.067563                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13067.356750                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13067.356750                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13067.356750                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 13067.356750                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13067.356750                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 13067.356750                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                362958                       # number of replacements
-system.cpu1.dcache.tagsinuse               487.094495                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                13107479                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                363304                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 36.078543                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           70482639000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   487.094495                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.951356                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.951356                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      8608268                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        8608268                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4252418                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4252418                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       106100                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total       106100                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100714                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total       100714                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     12860686                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        12860686                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     12860686                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       12860686                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       410615                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       410615                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data      1595619                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total      1595619                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14222                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        14222                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10905                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10905                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data      2006234                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total       2006234                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data      2006234                       # number of overall misses
-system.cpu1.dcache.overall_misses::total      2006234                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8133768000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   8133768000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  66485489237                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total  66485489237                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    165213500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    165213500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     94467000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     94467000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data  74619257237                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total  74619257237                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data  74619257237                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total  74619257237                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      9018883                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      9018883                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      5848037                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      5848037                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       120322                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total       120322                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111619                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total       111619                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     14866920                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     14866920                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     14866920                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     14866920                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045528                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.045528                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272847                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.272847                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118199                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118199                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097698                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097698                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134946                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.134946                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134946                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.134946                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 41667.521656                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11616.755731                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11616.755731                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8662.723521                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8662.723521                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37193.695868                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 37193.695868                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37193.695868                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 37193.695868                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs     29476015                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets      5620000                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs             6671                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets            172                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4418.530205                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605                       # average number of cycles each access was blocked
+system.cpu1.dcache.replacements                363581                       # number of replacements
+system.cpu1.dcache.tagsinuse               487.223522                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                13117187                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                363929                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 36.043258                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           71474573000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   487.223522                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.951608                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.951608                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      8616147                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        8616147                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4254446                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4254446                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       105790                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total       105790                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       100736                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total       100736                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     12870593                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        12870593                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     12870593                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       12870593                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       410065                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       410065                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1595508                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total      1595508                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        14278                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        14278                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10912                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10912                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data      2005573                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total       2005573                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data      2005573                       # number of overall misses
+system.cpu1.dcache.overall_misses::total      2005573                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   8126055000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   8126055000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  66044305227                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  66044305227                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    166791500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    166791500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     95304000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     95304000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  74170360227                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  74170360227                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  74170360227                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  74170360227                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      9026212                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      9026212                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5849954                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      5849954                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       120068                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total       120068                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       111648                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total       111648                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     14876166                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     14876166                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     14876166                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     14876166                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.045430                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.045430                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.272739                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.272739                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118916                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118916                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.097736                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.097736                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.134818                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.134818                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.134818                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.134818                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19816.504700                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 19816.504700                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41393.904153                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 41393.904153                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11681.713125                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11681.713125                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8733.870968                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8733.870968                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36982.129410                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 36982.129410                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36982.129410                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 36982.129410                       # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs     29670016                       # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets      5568500                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs             6658                       # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets            173                       # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4456.295584                       # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 32187.861272                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       327729                       # number of writebacks
-system.cpu1.dcache.writebacks::total           327729                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       179332                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total       179332                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1432824                       # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total      1432824                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1447                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1447                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data      1612156                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total      1612156                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data      1612156                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total      1612156                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231283                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       231283                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162795                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       162795                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12775                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12775                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10900                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10900                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       394078                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       394078                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       394078                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       394078                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3556387454                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3556387454                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5557887685                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5557887685                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    103446504                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    103446504                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     60421505                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     60421505                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9114275139                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   9114275139                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9114275139                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   9114275139                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40580989302                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40580989302                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025644                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025644                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027838                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027838                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.106173                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.106173                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097654                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097654                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026507                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026507                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026507                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026507                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8097.573699                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8097.573699                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5543.257339                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5543.257339                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       328251                       # number of writebacks
+system.cpu1.dcache.writebacks::total           328251                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       178277                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       178277                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1432587                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1432587                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1464                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1464                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1610864                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1610864                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1610864                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1610864                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       231788                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       231788                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       162921                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       162921                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        12814                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        12814                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10909                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10909                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       394709                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       394709                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       394709                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       394709                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   3566201462                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   3566201462                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   5537603585                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   5537603585                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    104573506                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    104573506                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     61265506                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     61265506                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         2000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         2000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   9103805047                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   9103805047                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   9103805047                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   9103805047                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169309741500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169309741500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  40933880282                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  40933880282                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210243621782                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210243621782                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025679                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.025679                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.027850                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.027850                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.106723                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.106723                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.097709                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.097709                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026533                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026533                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026533                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026533                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15385.617297                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15385.617297                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33989.501568                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33989.501568                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8160.879195                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  8160.879195                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5616.051517                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5616.051517                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23064.599609                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23064.599609                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23064.599609                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23064.599609                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1667,18 +1671,18 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1305599683923                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323189312111                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1323189312111                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323189312111                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1323189312111                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   43782                       # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce                   43824                       # number of quiesce instructions executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   53899                       # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce                   53932                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index b903804f36748878fa61adbb2428fc320a2722a4..bc845639afb752c022abfa4987e73e584fbe6d4d 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.503329                       # Number of seconds simulated
-sim_ticks                                2503329223500                       # Number of ticks simulated
-final_tick                               2503329223500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.538055                       # Number of seconds simulated
+sim_ticks                                2538055224500                       # Number of ticks simulated
+final_tick                               2538055224500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  62297                       # Simulator instruction rate (inst/s)
-host_op_rate                                    80132                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2573650165                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 394796                       # Number of bytes of host memory used
-host_seconds                                   972.68                       # Real time elapsed on the host
-sim_insts                                    60594713                       # Number of instructions simulated
-sim_ops                                      77942287                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         3712                       # Number of bytes read from this memory
+host_inst_rate                                  88262                       # Simulator instruction rate (inst/s)
+host_op_rate                                   113532                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3696075323                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 390228                       # Number of bytes of host memory used
+host_seconds                                   686.69                       # Real time elapsed on the host
+sim_insts                                    60608338                       # Number of instructions simulated
+sim_ops                                      77960937                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::realview.clcd    121110528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         3904                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            799552                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9094032                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            129435024                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       799552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          799552                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3785216                       # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst            799488                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9090192                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            131004176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       799488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          799488                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3781888                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6801288                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      14942208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           58                       # Number of read requests responded to by this memory
+system.physmem.bytes_written::total           6797960                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15138816                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           61                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12493                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             142128                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15096888                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           59144                       # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst              12492                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15293438                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           59092                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               813162                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47751475                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker           1483                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             26                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               319395                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3632775                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51705154                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          319395                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             319395                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1512073                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1204824                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2716897                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1512073                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47751475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker          1483                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            26                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              319395                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4837599                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               54422052                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_writes::total               813110                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47717846                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker           1538                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             25                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               315000                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3581558                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                51615968                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          315000                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             315000                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1490073                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1188340                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2678413                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1490073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47717846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker          1538                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            25                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              315000                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4769898                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               54294380                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
 system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
 system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               26                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           26                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           26                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              26                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         64407                       # number of replacements
-system.l2c.tagsinuse                     51237.721374                       # Cycle average of tags in use
-system.l2c.total_refs                         1963815                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        129804                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         15.129079                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2492699118000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        36773.515896                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       46.128401                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000184                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           8177.854263                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6240.222629                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.561119                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000704                       # Average percentage of cache occupancy
+system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         64349                       # number of replacements
+system.l2c.tagsinuse                     51370.291201                       # Cycle average of tags in use
+system.l2c.total_refs                         1966684                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        129742                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         15.158422                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2527049892000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        36909.964338                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       48.537302                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000243                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           8186.541319                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6225.247998                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.563201                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000741                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.124784                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.095218                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.781826                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        123734                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker         11927                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              976636                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              387128                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1499425                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          607519                       # number of Writeback hits
-system.l2c.Writeback_hits::total               607519                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data               41                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                  41                       # number of UpgradeReq hits
+system.l2c.occ_percent::cpu.inst             0.124917                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.094990                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.783848                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        122661                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker         11547                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              978702                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              387818                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1500728                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          608398                       # number of Writeback hits
+system.l2c.Writeback_hits::total               608398                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data               38                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                  38                       # number of UpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu.data             16                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                16                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            112732                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               112732                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         123734                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker          11927                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               976636                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               499860                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1612157                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        123734                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker         11927                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              976636                       # number of overall hits
-system.l2c.overall_hits::cpu.data              499860                       # number of overall hits
-system.l2c.overall_hits::total                1612157                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           58                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            112928                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               112928                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         122661                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker          11547                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               978702                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               500746                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1613656                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        122661                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker         11547                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              978702                       # number of overall hits
+system.l2c.overall_hits::cpu.data              500746                       # number of overall hits
+system.l2c.overall_hits::total                1613656                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           61                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12374                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             12372                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.data             10691                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                23124                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2909                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2909                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total               2                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133219                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133219                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           58                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::total                23125                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2903                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2903                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total               3                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133164                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133164                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           61                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12374                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143910                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                156343                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           58                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              12372                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             143855                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                156289                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           61                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12374                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143910                       # number of overall misses
-system.l2c.overall_misses::total               156343                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3035000                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.inst             12372                       # number of overall misses
+system.l2c.overall_misses::cpu.data            143855                       # number of overall misses
+system.l2c.overall_misses::total               156289                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      3190500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker        60000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    659327498                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    562370998                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1224793496                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data       994500                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total       994500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   7086596499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7086596499                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      3035000                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    658900997                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    562244999                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1224396496                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       996000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       996000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7068682495                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7068682495                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      3190500                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker        60000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    659327498                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7648967497                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8311389995                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      3035000                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu.inst    658900997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7630927494                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8293078991                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      3190500                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker        60000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    659327498                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7648967497                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8311389995                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       123792                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker        11928                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          989010                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          397819                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1522549                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       607519                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           607519                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2950                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2950                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data           18                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total            18                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        245951                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           245951                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       123792                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker        11928                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           989010                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           643770                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1768500                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       123792                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker        11928                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          989010                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          643770                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1768500                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000084                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012512                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026874                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.015188                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.986102                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.986102                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.111111                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.111111                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.541649                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.541649                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000084                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012512                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.223543                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.088404                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000469                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000084                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012512                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.223543                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.088404                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu.inst    658900997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7630927494                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8293078991                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       122722                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker        11548                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          991074                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          398509                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1523853                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       608398                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           608398                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2941                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2941                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total            19                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246092                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           246092                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       122722                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker        11548                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           991074                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           644601                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1769945                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       122722                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker        11548                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          991074                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          644601                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1769945                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000087                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012483                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026827                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.015175                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.987079                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.987079                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.157895                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.541115                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.541115                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000087                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012483                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.223169                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.088302                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000497                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000087                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012483                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.223169                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.088302                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        60000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53283.295458                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52602.282106                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52966.333506                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   341.870058                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   341.870058                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 53195.088531                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 53195.088531                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53257.435904                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52590.496586                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52946.875503                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   343.093352                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   343.093352                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 53082.533530                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 53082.533530                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53161.254389                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52327.586207                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53257.435904                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 53045.966383                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53062.461152                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52303.278689                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        60000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53283.295458                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 53151.049246                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53161.254389                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53257.435904                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 53045.966383                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53062.461152                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -212,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               59144                       # number of writebacks
-system.l2c.writebacks::total                    59144                       # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu.inst              8                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu.data             61                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total                69                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu.inst               8                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu.data              61                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total                 69                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu.inst              8                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu.data             61                       # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total                69                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           58                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               59092                       # number of writebacks
+system.l2c.writebacks::total                    59092                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             59                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                66                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              59                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 66                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             59                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                66                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           61                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12366                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10630                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           23055                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2909                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2909                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133219                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133219                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           58                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12365                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10632                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           23059                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2903                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2903                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133164                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133164                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           61                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12366                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143849                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           156274                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           58                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12365                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        143796                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           156223                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           61                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12366                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143849                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          156274                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu.inst        12365                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       143796                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          156223                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        48000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    507997999                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    430294500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    940666499                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    117136000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    117136000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total        80000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5457467999                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5457467999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    507604998                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    430224000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    940322998                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    116314500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    116314500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       120000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5435229995                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5435229995                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker        48000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    507997999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5887762499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6398134498                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2326000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    507604998                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5865453995                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6375552993                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      2446000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker        48000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    507997999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5887762499                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6398134498                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    507604998                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5865453995                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6375552993                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      5323000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131412946500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131418269500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31416947511                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31416947511                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166745653500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166750976500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32068433085                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32068433085                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst      5323000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162835217011                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026721                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.015142                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.986102                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.986102                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.111111                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541649                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.541649                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.088365                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000469                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000084                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012503                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.223448                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.088365                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 198814086585                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 198819409585                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026679                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.015132                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.987079                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.987079                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.157895                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.541115                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.541115                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.223078                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.088264                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000497                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000087                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012476                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.223078                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.088264                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336                       # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40465.011287                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40779.001605                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40066.999656                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40066.999656                       # average UpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40816.061360                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40816.061360                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40790.105392                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40810.591225                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        48000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40941.772131                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41051.758835                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40790.105392                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40810.591225                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -332,27 +332,27 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     51771178                       # DTB read hits
-system.cpu.dtb.read_misses                      82022                       # DTB read misses
-system.cpu.dtb.write_hits                    11879780                       # DTB write hits
-system.cpu.dtb.write_misses                     18404                       # DTB write misses
+system.cpu.dtb.read_hits                     51779226                       # DTB read hits
+system.cpu.dtb.read_misses                      81574                       # DTB read misses
+system.cpu.dtb.write_hits                    11882622                       # DTB write hits
+system.cpu.dtb.write_misses                     18093                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     4476                       # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults                      2874                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    631                       # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries                     4488                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults                      3293                       # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults                    606                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults                      1260                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 51853200                       # DTB read accesses
-system.cpu.dtb.write_accesses                11898184                       # DTB write accesses
+system.cpu.dtb.perms_faults                      1237                       # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses                 51860800                       # DTB read accesses
+system.cpu.dtb.write_accesses                11900715                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          63650958                       # DTB hits
-system.cpu.dtb.misses                          100426                       # DTB misses
-system.cpu.dtb.accesses                      63751384                       # DTB accesses
-system.cpu.itb.inst_hits                     13147400                       # ITB inst hits
-system.cpu.itb.inst_misses                      12275                       # ITB inst misses
+system.cpu.dtb.hits                          63661848                       # DTB hits
+system.cpu.dtb.misses                           99667                       # DTB misses
+system.cpu.dtb.accesses                      63761515                       # DTB accesses
+system.cpu.itb.inst_hits                     13144692                       # ITB inst hits
+system.cpu.itb.inst_misses                      11967                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.write_hits                           0                       # DTB write hits
@@ -361,121 +361,121 @@ system.cpu.itb.flush_tlb                            2                       # Nu
 system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries                     2641                       # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries                     2632                       # Number of entries that have been flushed from TLB
 system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
 system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
 system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults                      3416                       # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults                      3496                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 13159675                       # ITB inst accesses
-system.cpu.itb.hits                          13147400                       # DTB hits
-system.cpu.itb.misses                           12275                       # DTB misses
-system.cpu.itb.accesses                      13159675                       # DTB accesses
-system.cpu.numCycles                        415310668                       # number of cpu cycles simulated
+system.cpu.itb.inst_accesses                 13156659                       # ITB inst accesses
+system.cpu.itb.hits                          13144692                       # DTB hits
+system.cpu.itb.misses                           11967                       # DTB misses
+system.cpu.itb.accesses                      13156659                       # DTB accesses
+system.cpu.numCycles                        487285069                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 15527738                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           12466555                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect             753811                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              10646284                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                  8367014                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 15533008                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           12472748                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect             753945                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              10621013                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                  8369898                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                  1449693                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect               80905                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           33357472                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      101736318                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    15527738                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches            9816707                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      22310929                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 6078281                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     161634                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles               94635812                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                 2484                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        132549                       # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles       208778                       # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles          375                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                  13143214                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               1025665                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    6564                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          154991090                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.809239                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.178893                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                  1450891                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect               81082                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles           33390116                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      101781554                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    15533008                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches            9820789                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      22319812                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 6080499                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     158808                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles              102222011                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                 2648                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        133571                       # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles       207903                       # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles          361                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                  13140422                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               1021772                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    6316                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          162617823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.771724                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.134680                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                132697054     85.62%     85.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1371702      0.89%     86.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  1758298      1.13%     87.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  2653739      1.71%     89.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  2357523      1.52%     90.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  1143564      0.74%     91.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2918516      1.88%     93.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                   809258      0.52%     94.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                  9281436      5.99%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                140314971     86.29%     86.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1367844      0.84%     87.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  1761669      1.08%     88.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  2653320      1.63%     89.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  2361626      1.45%     91.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  1142802      0.70%     92.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2916048      1.79%     93.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                   808288      0.50%     94.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                  9291255      5.71%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            154991090                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.037388                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.244964                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 35540110                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              94304374                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  20024957                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               1112327                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4009322                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved              2100739                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                174603                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts              118268322                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                570412                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4009322                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 37657945                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                39869078                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       47822984                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  18880557                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles               6751204                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              110681454                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 22988                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                1160036                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               4497834                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            31020                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           115504222                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups             506609726                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups        506516210                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups             93516                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps              78727449                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 36776772                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             900485                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         799637                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  13564830                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             21065339                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            13879000                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1961867                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          2663971                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  101316574                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2057711                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 126458108                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            199553                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        24657438                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     65563204                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         513311                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     154991090                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.815906                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.514046                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            162617823                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.031877                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.208875                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35567426                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             101892214                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  20037549                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               1109983                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4010651                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved              2100654                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                174914                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts              118316762                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                572114                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4010651                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 37681511                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                40491658                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       54797467                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  18895098                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles               6741438                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              110776004                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 22866                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                1160313                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               4487001                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            30716                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           115615239                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups             507028919                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups        506935731                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups             93188                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps              78747197                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 36868041                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             898954                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         797959                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  13563069                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             21067127                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            13877132                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1956196                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          2590406                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  101357427                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2059773                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 126494913                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            198538                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        24680718                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     65543860                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         514575                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     162617823                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.777866                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.488052                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           108868078     70.24%     70.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            14887887      9.61%     79.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2             7383585      4.76%     84.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             6313472      4.07%     88.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12622401      8.14%     96.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             2812506      1.81%     98.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             1537255      0.99%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              440277      0.28%     99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              125629      0.08%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           116473756     71.62%     71.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            14895850      9.16%     80.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2             7383355      4.54%     85.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             6325930      3.89%     89.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12628751      7.77%     96.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             2810327      1.73%     98.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             1536412      0.94%     99.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              438084      0.27%     99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              125358      0.08%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       154991090                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       162617823                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   54148      0.61%      0.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   53829      0.61%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      4      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      0.61% # attempts to use FU when none available
@@ -504,397 +504,397 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      0.61% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      0.61% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      0.61% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8364176     94.75%     95.37% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                409089      4.63%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8366722     94.73%     95.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                411335      4.66%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass            363666      0.29%      0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu              60068751     47.50%     47.79% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                95236      0.08%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                  14      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  5      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               7      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.86% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            7      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             53417106     42.24%     90.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            12511205      9.89%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu              60100692     47.51%     47.80% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                95407      0.08%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                  20      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  4      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc              12      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc           2111      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc           12      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     47.88% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             53419362     42.23%     90.11% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            12513627      9.89%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              126458108                       # Type of FU issued
-system.cpu.iq.rate                           0.304490                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     8827417                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.069805                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          417011386                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         128052835                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses     87416470                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads               22950                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes              12920                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses        10331                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              134909754                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                   12105                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads           645788                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              126494913                       # Type of FU issued
+system.cpu.iq.rate                           0.259591                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     8831890                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.069820                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          424714403                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         128119104                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses     87467949                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads               22973                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes              12866                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses        10326                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              134951003                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                   12134                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads           645792                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      5350138                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        11136                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        35101                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2080838                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      5347388                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        11096                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        35111                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2076739                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads     34107263                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked       1048290                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads     34107215                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked       1052024                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4009322                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                29478613                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                536036                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           103628902                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            217385                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              21065339                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             13879000                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            1466402                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 126510                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 31155                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          35101                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         376939                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       332400                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts               709339                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             123236608                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              52461044                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3221500                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4010651                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                30083339                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                540488                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           103672693                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            219471                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              21067127                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             13877132                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            1468075                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 126042                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 41068                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          35111                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         376458                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       332668                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts               709126                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             123289616                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              52469824                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3205297                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                        254617                       # number of nop insts executed
-system.cpu.iew.exec_refs                     64851969                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 11926568                       # Number of branches executed
-system.cpu.iew.exec_stores                   12390925                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.296734                       # Inst execution rate
-system.cpu.iew.wb_sent                      121860265                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                      87426801                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                  47494075                       # num instructions producing a value
-system.cpu.iew.wb_consumers                  86379183                       # num instructions consuming a value
+system.cpu.iew.exec_nop                        255493                       # number of nop insts executed
+system.cpu.iew.exec_refs                     64863659                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 11931891                       # Number of branches executed
+system.cpu.iew.exec_stores                   12393835                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.253013                       # Inst execution rate
+system.cpu.iew.wb_sent                      121912605                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                      87478275                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                  47524907                       # num instructions producing a value
+system.cpu.iew.wb_consumers                  86445005                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.210509                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.549832                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.179522                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.549770                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       60745094                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps         78092668                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        24728606                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1544400                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts            625654                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    151064180                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.516950                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.491641                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts       60758719                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         78111318                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        24740610                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1545198                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts            625619                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158689613                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.492227                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.459221                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    122872114     81.34%     81.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     13991345      9.26%     90.60% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      3943128      2.61%     93.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3      2231050      1.48%     94.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      2009345      1.33%     96.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1063949      0.70%     96.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1402638      0.93%     97.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7       655924      0.43%     98.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      2894687      1.92%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    130476861     82.22%     82.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     14004142      8.82%     91.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      3942589      2.48%     93.53% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3      2238161      1.41%     94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2017118      1.27%     96.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1061710      0.67%     96.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1402075      0.88%     97.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7       657613      0.41%     98.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      2889344      1.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    151064180                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts             60745094                       # Number of instructions committed
-system.cpu.commit.committedOps               78092668                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    158689613                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts             60758719                       # Number of instructions committed
+system.cpu.commit.committedOps               78111318                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       27513363                       # Number of memory references committed
-system.cpu.commit.loads                      15715201                       # Number of loads committed
-system.cpu.commit.membars                      413054                       # Number of memory barriers committed
-system.cpu.commit.branches                   10161447                       # Number of branches committed
+system.cpu.commit.refs                       27520132                       # Number of memory references committed
+system.cpu.commit.loads                      15719739                       # Number of loads committed
+system.cpu.commit.membars                      413350                       # Number of memory barriers committed
+system.cpu.commit.branches                   10163894                       # Number of branches committed
 system.cpu.commit.fp_insts                      10212                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                  69131310                       # Number of committed integer instructions.
-system.cpu.commit.function_calls               995952                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               2894687                       # number cycles where commit BW limit reached
+system.cpu.commit.int_insts                  69148099                       # Number of committed integer instructions.
+system.cpu.commit.function_calls               996264                       # Number of function calls committed.
+system.cpu.commit.bw_lim_events               2889344                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    249075594                       # The number of ROB reads
-system.cpu.rob.rob_writes                   209750294                       # The number of ROB writes
-system.cpu.timesIdled                         1905944                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       260319578                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   4591259733                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    60594713                       # Number of Instructions Simulated
-system.cpu.committedOps                      77942287                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total              60594713                       # Number of Instructions Simulated
-system.cpu.cpi                               6.853909                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         6.853909                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.145902                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.145902                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                557815348                       # number of integer regfile reads
-system.cpu.int_regfile_writes                90098492                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                      8218                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                     2870                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               134021846                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 912706                       # number of misc regfile writes
-system.cpu.icache.replacements                 989908                       # number of replacements
-system.cpu.icache.tagsinuse                511.610984                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 12068184                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 990420                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  12.184915                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle             6426400000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     511.610984                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.999240                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.999240                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     12068184                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        12068184                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      12068184                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         12068184                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     12068184                       # number of overall hits
-system.cpu.icache.overall_hits::total        12068184                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1074896                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1074896                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1074896                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1074896                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1074896                       # number of overall misses
-system.cpu.icache.overall_misses::total       1074896                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  16638687991                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  16638687991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  16638687991                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  16638687991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  16638687991                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  16638687991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     13143080                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     13143080                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     13143080                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     13143080                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     13143080                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     13143080                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081784                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.081784                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.081784                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.081784                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.081784                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.081784                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15479.346831                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15479.346831                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      2960492                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                    256736769                       # The number of ROB reads
+system.cpu.rob.rob_writes                   209812510                       # The number of ROB writes
+system.cpu.timesIdled                         1906775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       324667246                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   4588737338                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                    60608338                       # Number of Instructions Simulated
+system.cpu.committedOps                      77960937                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              60608338                       # Number of Instructions Simulated
+system.cpu.cpi                               8.039902                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         8.039902                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.124380                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.124380                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                558055785                       # number of integer regfile reads
+system.cpu.int_regfile_writes                90157820                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                      8288                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                     2908                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               134082325                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 913357                       # number of misc regfile writes
+system.cpu.icache.replacements                 991945                       # number of replacements
+system.cpu.icache.tagsinuse                511.576100                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 12062971                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 992457                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  12.154654                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle             7225347000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     511.576100                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999172                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999172                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12062971                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12062971                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12062971                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12062971                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12062971                       # number of overall hits
+system.cpu.icache.overall_hits::total        12062971                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1077319                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1077319                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1077319                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1077319                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1077319                       # number of overall misses
+system.cpu.icache.overall_misses::total       1077319                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16672871489                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16672871489                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16672871489                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16672871489                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16672871489                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16672871489                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13140290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13140290                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13140290                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13140290                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13140290                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13140290                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.081986                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.081986                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.081986                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.081986                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.081986                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.081986                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15476.262360                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15476.262360                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15476.262360                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15476.262360                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15476.262360                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15476.262360                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      2904990                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               448                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               436                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  6608.241071                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  6662.821101                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84437                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        84437                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        84437                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        84437                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        84437                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        84437                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       990459                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       990459                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       990459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       990459                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       990459                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       990459                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12623481992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  12623481992                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12623481992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  12623481992                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12623481992                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  12623481992                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        84824                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        84824                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        84824                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        84824                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        84824                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        84824                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       992495                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       992495                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       992495                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       992495                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       992495                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       992495                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12649346990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12649346990                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12649346990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12649346990                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12649346990                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12649346990                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      7992500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      7992500                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total      7992500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075360                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.075360                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075360                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.075360                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.075531                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.075531                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.075531                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.075531                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12744.998202                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12744.998202                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 12744.998202                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 643258                       # number of replacements
-system.cpu.dcache.tagsinuse                511.991338                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 21734239                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 643770                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  33.760876                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 644089                       # number of replacements
+system.cpu.dcache.tagsinuse                511.991456                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 21738846                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 644601                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  33.724499                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               50933000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.991338                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.991456                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999983                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999983                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13902749                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13902749                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      7257426                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        7257426                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       285261                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       285261                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       285646                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       285646                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      21160175                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         21160175                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     21160175                       # number of overall hits
-system.cpu.dcache.overall_hits::total        21160175                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       765054                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        765054                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      2992955                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      2992955                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        13791                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        13791                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data           18                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total           18                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      3758009                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3758009                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3758009                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3758009                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  14856915000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  14856915000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 130200810067                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 130200810067                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223590500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    223590500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       349500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total       349500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145057725067                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145057725067                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145057725067                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145057725067                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     14667803                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     14667803                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10250381                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10250381                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       299052                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       299052                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       285664                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       285664                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     24918184                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     24918184                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     24918184                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     24918184                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052159                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052159                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.291985                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.291985                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046116                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046116                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000063                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total     0.000063                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.150814                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.150814                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.150814                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.150814                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19419.433138                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19419.433138                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43502.428225                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 43502.428225                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16212.783700                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16212.783700                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 19416.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 19416.666667                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 38599.621520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 38599.621520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 38599.621520                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     34077900                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets      7429000                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              7467                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets             284                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  4563.800723                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 26158.450704                       # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data     13908205                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13908205                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7258424                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        7258424                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       283313                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       283313                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285772                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       285772                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      21166629                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         21166629                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     21166629                       # number of overall hits
+system.cpu.dcache.overall_hits::total        21166629                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       766922                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        766922                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2994004                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2994004                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13808                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        13808                       # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           19                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total           19                       # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data      3760926                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3760926                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3760926                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3760926                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14892290500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14892290500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 129258725578                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 129258725578                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    223775000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    223775000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       402000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       402000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 144151016078                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 144151016078                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 144151016078                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 144151016078                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     14675127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     14675127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10252428                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10252428                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       297121                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       297121                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285791                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       285791                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     24927555                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     24927555                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     24927555                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     24927555                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052260                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052260                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.292029                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.292029                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046473                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046473                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000066                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total     0.000066                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.150874                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.150874                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.150874                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.150874                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19418.259614                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19418.259614                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43172.529355                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 43172.529355                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16206.184820                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16206.184820                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21157.894737                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21157.894737                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 38328.596755                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 38328.596755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 38328.596755                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 38328.596755                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     33707409                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets      7420000                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              7431                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets             286                       # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  4536.052887                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 25944.055944                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       607519                       # number of writebacks
-system.cpu.dcache.writebacks::total            607519                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       379422                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       379422                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2744177                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      2744177                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1481                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total         1481                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      3123599                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      3123599                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      3123599                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      3123599                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385632                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       385632                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248778                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       248778                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12310                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        12310                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           18                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total           18                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       634410                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       634410                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       634410                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       634410                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6262166095                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6262166095                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9286622435                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9286622435                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    163471000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    163471000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       289000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       289000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15548788530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  15548788530                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15548788530                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  15548788530                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41268229410                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41268229410                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026291                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026291                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024270                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024270                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041163                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041163                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000063                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000063                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.025460                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025460                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.025460                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       608398                       # number of writebacks
+system.cpu.dcache.writebacks::total            608398                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       380638                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       380638                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2745107                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2745107                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1447                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1447                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3125745                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3125745                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3125745                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3125745                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       386284                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       386284                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       248897                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       248897                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12361                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           19                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       635181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       635181                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       635181                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       635181                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6271229149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6271229149                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9237690949                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9237690949                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    163909000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    163909000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       338000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       338000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  15508920098                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  15508920098                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  15508920098                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  15508920098                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411312500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411312500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41911168414                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41911168414                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224322480914                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 224322480914                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.026322                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.026322                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024277                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.041603                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.041603                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000066                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000066                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025481                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.025481                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025481                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.025481                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16234.762892                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16234.762892                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37114.513027                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37114.513027                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13260.173125                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13260.173125                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17789.473684                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17789.473684                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24416.536543                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24416.536543                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -916,16 +916,16 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1305424568773                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323890643510                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1323890643510                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323890643510                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1323890643510                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    88047                       # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce                    88043                       # number of quiesce instructions executed
 
 ---------- End Simulation Statistics   ----------
index d3e4451ad3b17c7a554077801da40332e97e941a..2d55f3c333c568cfb1aa6739f04bd07634cfdc6a 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.172910                       # Number of seconds simulated
-sim_ticks                                5172910256500                       # Number of ticks simulated
-final_tick                               5172910256500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.172174                       # Number of seconds simulated
+sim_ticks                                5172174196500                       # Number of ticks simulated
+final_tick                               5172174196500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 136129                       # Simulator instruction rate (inst/s)
-host_op_rate                                   268264                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1651021148                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 373420                       # Number of bytes of host memory used
-host_seconds                                  3133.16                       # Real time elapsed on the host
-sim_insts                                   426513995                       # Number of instructions simulated
-sim_ops                                     840512563                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2464064                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker         2944                       # Number of bytes read from this memory
+host_inst_rate                                 197854                       # Simulator instruction rate (inst/s)
+host_op_rate                                   391125                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2509698416                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 367744                       # Number of bytes of host memory used
+host_seconds                                  2060.87                       # Real time elapsed on the host
+sim_insts                                   407751921                       # Number of instructions simulated
+sim_ops                                     806059216                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2469504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker         2816                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          448                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst           1067584                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          10442240                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             13977280                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst      1067584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total         1067584                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      9176384                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           9176384                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        38501                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker           46                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst           1070336                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          10446016                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             13989120                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst      1070336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total         1070336                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      9206912                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           9206912                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        38586                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker           44                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            7                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              16681                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             163160                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                218395                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          143381                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               143381                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       476340                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            569                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              16724                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             163219                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                218580                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          143858                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               143858                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       477460                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker            544                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             87                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               206380                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2018639                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2702015                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          206380                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             206380                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1773931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1773931                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1773931                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       476340                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           569                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               206941                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2019657                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2704688                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          206941                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             206941                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1780085                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1780085                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1780085                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       477460                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker           544                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            87                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              206380                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2018639                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4475945                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        106892                       # number of replacements
-system.l2c.tagsinuse                     64846.239814                       # Cycle average of tags in use
-system.l2c.total_refs                         3994467                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        171328                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         23.314735                       # Average number of references to valid blocks.
+system.physmem.bw_total::cpu.inst              206941                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2019657                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4484774                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        107330                       # number of replacements
+system.l2c.tagsinuse                     64831.864344                       # Cycle average of tags in use
+system.l2c.total_refs                         3982185                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        171532                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         23.215406                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50145.406461                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker       11.508776                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.169764                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           3382.865025                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data          11306.289787                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.765158                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000176                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        50277.913573                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        9.980895                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.169682                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3388.636576                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data          11155.163618                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.767180                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000152                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000003                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.051618                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.172520                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.989475                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker        113294                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          9300                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst             1056563                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1345318                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2524475                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1607595                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1607595                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              334                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 334                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            163366                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               163366                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker         113294                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           9300                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst              1056563                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1508684                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2687841                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker        113294                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          9300                       # number of overall hits
-system.l2c.overall_hits::cpu.inst             1056563                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1508684                       # number of overall hits
-system.l2c.overall_hits::total                2687841                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker           46                       # number of ReadReq misses
+system.l2c.occ_percent::cpu.inst             0.051706                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.170214                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.989256                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        111938                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          8555                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1051956                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1345107                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2517556                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1612922                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1612922                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              325                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 325                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            163659                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               163659                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker         111938                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           8555                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1051956                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1508766                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2681215                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker        111938                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          8555                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1051956                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1508766                       # number of overall hits
+system.l2c.overall_hits::total                2681215                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker           44                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             16683                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             35188                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                51924                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2935                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2935                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          128896                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             128896                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker           46                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu.inst             16726                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             35201                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                51978                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1498                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1498                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          128962                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             128962                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker           44                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            7                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              16683                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             164084                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                180820                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker           46                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              16726                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             164163                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                180940                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker           44                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            7                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             16683                       # number of overall misses
-system.l2c.overall_misses::cpu.data            164084                       # number of overall misses
-system.l2c.overall_misses::total               180820                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2412500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.inst             16726                       # number of overall misses
+system.l2c.overall_misses::cpu.data            164163                       # number of overall misses
+system.l2c.overall_misses::total               180940                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      2308000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker       364000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    885747500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   1875717995                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2764241995                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     38348000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     38348000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6718316497                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6718316497                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker      2412500                       # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    887926997                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1876685493                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2767284490                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     37648500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     37648500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6721908000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6721908000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      2308000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker       364000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    885747500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   8594034492                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      9482558492                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker      2412500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu.inst    887926997                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8598593493                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9489192490                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      2308000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker       364000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    885747500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   8594034492                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     9482558492                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker       113340                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         9307                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst         1073246                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1380506                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2576399                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1607595                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1607595                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         3269                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3269                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        292262                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           292262                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker       113340                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         9307                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst          1073246                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1672768                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2868661                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker       113340                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         9307                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst         1073246                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1672768                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2868661                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000752                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.015544                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.025489                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.020154                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.897828                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.897828                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.441029                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.441029                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000752                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.015544                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.098091                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.063033                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000406                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000752                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.015544                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.098091                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.063033                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu.inst    887926997                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8598593493                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9489192490                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       111982                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         8562                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1068682                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1380308                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2569534                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1612922                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1612922                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1823                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1823                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        292621                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           292621                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker       111982                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         8562                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1068682                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1672929                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2862155                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       111982                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         8562                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1068682                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1672929                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2862155                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000393                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000818                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.015651                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.025502                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.020229                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.821722                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.821722                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.440713                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.440713                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000393                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000818                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.015651                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.098129                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.063218                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000393                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000818                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.015651                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.098129                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.063218                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52454.545455                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 53092.819037                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 53305.615409                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 53236.306814                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13065.758092                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 13065.758092                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52121.993677                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52121.993677                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 53086.631412                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 53313.414193                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53239.533841                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 25132.510013                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 25132.510013                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52123.168065                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52123.168065                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52454.545455                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 53092.819037                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52375.822701                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52441.978166                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52445.652174                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 53086.631412                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52378.389119                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52443.862551                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52454.545455                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 53092.819037                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52375.822701                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52441.978166                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 53086.631412                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52378.389119                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52443.862551                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -189,8 +189,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               96714                       # number of writebacks
-system.l2c.writebacks::total                    96714                       # number of writebacks
+system.l2c.writebacks::writebacks               97191                       # number of writebacks
+system.l2c.writebacks::total                    97191                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu.inst              2                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 3                       # number of ReadReq MSHR hits
@@ -200,88 +200,88 @@ system.l2c.demand_mshr_hits::total                  3                       # nu
 system.l2c.overall_mshr_hits::cpu.inst              2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 3                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           46                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           44                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            7                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        16681                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        35187                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           51921                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2935                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2935                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       128896                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        128896                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker           46                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        16724                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        35200                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           51975                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         1498                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1498                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       128962                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        128962                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           44                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            7                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         16681                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        164083                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           180817                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker           46                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         16724                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        164162                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           180937                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           44                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            7                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        16681                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       164083                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          180817                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu.inst        16724                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       164162                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          180937                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      1774500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       280000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    682272500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1445683499                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   2130086999                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    117833500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    117833500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5165552500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5165552500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    683968997                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1446479000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2132502497                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     60328500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     60328500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5168491500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5168491500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      1774500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker       280000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    682272500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   6611235999                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   7295639499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      1851000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    683968997                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6614970500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7300993997                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      1774500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker       280000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    682272500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   6611235999                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   7295639499                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59192780564                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  59192780564                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1212414000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1212414000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  60405194564                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  60405194564                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025488                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.020153                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.897828                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.897828                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.441029                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.441029                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.098091                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.063032                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000406                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000752                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.015543                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.098091                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.063032                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_latency::cpu.inst    683968997                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6614970500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7300993997                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  88673683000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  88673683000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   2309054000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2309054000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  90982737000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  90982737000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000393                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000818                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015649                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.025502                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.020227                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.821722                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.821722                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.440713                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.440713                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000393                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000818                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.015649                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.098128                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063217                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000393                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000818                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.015649                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.098128                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063217                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41085.727655                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 41025.538780                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40147.700170                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40147.700170                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40075.351446                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40075.351446                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40897.452583                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41093.153409                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 41029.389072                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40272.696929                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40272.696929                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40077.631395                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40077.631395                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40292.022934                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40348.194578                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40239.130435                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40897.452583                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.382001                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40351.028242                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40329.545455                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40901.174990                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40292.022934                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40348.194578                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40897.452583                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.382001                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40351.028242                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47569                       # number of replacements
-system.iocache.tagsinuse                     0.199376                       # Cycle average of tags in use
+system.iocache.replacements                     47572                       # number of replacements
+system.iocache.tagsinuse                     0.197153                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47585                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47588                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              5000598404000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.199376                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.012461                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.012461                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          904                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              904                       # number of ReadReq misses
+system.iocache.warmup_cycle              5000849406000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.197153                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.012322                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.012322                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          907                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              907                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47624                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47624                       # number of overall misses
-system.iocache.overall_misses::total            47624                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    135906932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    135906932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6908833160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   6908833160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   7044740092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7044740092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   7044740092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7044740092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          904                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            904                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47627                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47627                       # number of overall misses
+system.iocache.overall_misses::total            47627                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    136172932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    136172932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6920648160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6920648160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   7056821092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7056821092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   7056821092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7056821092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          907                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            907                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47624                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47624                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47624                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47624                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47627                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47627                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47627                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47627                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150339.526549                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 150339.526549                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147877.422089                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 147877.422089                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147924.157820                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 147924.157820                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147924.157820                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 147924.157820                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150135.536935                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 150135.536935                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148130.311644                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 148130.311644                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148168.498793                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 148168.498793                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148168.498793                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 148168.498793                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs        269004                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   25                       # number of cycles access was blocked
@@ -348,22 +348,22 @@ system.iocache.fast_writes                          0                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          904                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          904                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          907                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          907                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47624                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47624                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47624                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47624                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88867000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     88867000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4479079912                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4479079912                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4567946912                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4567946912                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4567946912                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4567946912                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47627                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47627                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47627                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47627                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     88977000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     88977000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4490887946                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4490887946                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4579864946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4579864946                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4579864946                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4579864946                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98304.203540                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 98304.203540                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95870.717295                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 95870.717295                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 95916.909793                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95916.909793                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 95916.909793                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98100.330761                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 98100.330761                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96123.457748                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 96123.457748                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 96161.104961                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96161.104961                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 96161.104961                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -393,411 +393,411 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                        473223088                       # number of cpu cycles simulated
+system.cpu.numCycles                        475031565                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 90016360                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           90016360                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1178248                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              84343978                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 81707122                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 86684856                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           86684856                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1176632                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              82122133                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 79543196                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           31356562                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      446929489                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    90016360                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           81707122                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     169790434                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 5330018                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles                     171751                       # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles              104797996                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                37968                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles         45006                       # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles          453                       # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines                   9363044                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                536807                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes                    5287                       # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples          310312997                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.834177                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.376352                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           31269539                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      428184771                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    86684856                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           79543196                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     164289785                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 5325147                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles                     164614                       # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles               76824227                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                37234                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles         45914                       # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles          429                       # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines                   9378048                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                536886                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes                    4957                       # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples          276741596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              3.053538                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.401990                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                140957479     45.42%     45.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  1776597      0.57%     46.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 72781994     23.45%     69.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                   982988      0.32%     69.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  1642902      0.53%     70.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3674853      1.18%     71.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  1139478      0.37%     71.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1444103      0.47%     72.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 85912603     27.69%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                112886536     40.79%     40.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  1619655      0.59%     41.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 71962795     26.00%     67.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                   983886      0.36%     67.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  1644119      0.59%     68.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  2486257      0.90%     69.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  1139995      0.41%     69.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1450599      0.52%     70.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 82567754     29.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            310312997                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.190220                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.944437                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 36508708                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             100881020                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 164105770                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               4704672                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                4112827                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              876214899                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   957                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                4112827                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 40925858                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                44314017                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       11153757                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 163784094                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              46022444                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              872421528                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                 10519                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               35242822                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents               3962452                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents         32001317                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1394162179                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2488413918                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2488413062                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups               856                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1347546247                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 46615925                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts             471039                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts         478955                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  48145791                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             18923985                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            10455746                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads           1291287                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          1021115                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  865765672                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             1722965                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 864313181                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            123185                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        26037339                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     53671952                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         207307                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     310312997                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.785295                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        2.396376                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            276741596                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.182482                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.901382                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 35010017                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              74311956                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 159865423                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               3444346                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                4109854                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              841785392                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   993                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                4109854                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 38173067                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                41532647                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       11823127                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 159691932                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              21410969                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              837988743                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                 10561                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               14331873                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents               3961467                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents          8380256                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1328629800                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2380702001                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2380701417                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups               584                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1282020322                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 46609471                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts             469457                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts         477289                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  33840968                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             17569417                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            10446486                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads           1246814                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          1007946                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  831743249                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             1259421                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 823989117                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            123035                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        26027822                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     53490149                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         209479                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     276741596                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.977468                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        2.409448                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           102585339     33.06%     33.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            23772488      7.66%     40.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            19036495      6.13%     46.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3             7825788      2.52%     49.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            80603332     25.97%     75.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             3104423      1.00%     76.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            72752969     23.45%     99.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              520222      0.17%     99.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              111941      0.04%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            86092872     31.11%     31.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            17946523      6.48%     37.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            12957239      4.68%     42.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3             7826219      2.83%     45.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            76249367     27.55%     72.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             3109383      1.12%     73.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            71927366     25.99%     99.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              520136      0.19%     99.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              112491      0.04%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       310312997                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       276741596                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  164594      7.88%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1764434     84.50%     92.38% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                159044      7.62%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  163103     18.01%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.01% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                 583729     64.45%     82.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                158924     17.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass            296261      0.03%      0.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             829427794     95.96%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.00% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             25158656      2.91%     98.91% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite             9430470      1.09%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass            296041      0.04%      0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             796340985     96.64%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     96.68% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             17916922      2.17%     98.85% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite             9435169      1.15%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              864313181                       # Type of FU issued
-system.cpu.iq.rate                           1.826439                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2088072                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.002416                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         2041288204                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         893536846                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    853917717                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 372                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes                410                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           96                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              866104816                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     176                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads          1579729                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              823989117                       # Type of FU issued
+system.cpu.iq.rate                           1.734599                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                      905756                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001099                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         1925886604                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         859041376                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    819484767                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 193                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes                234                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           50                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              824598744                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                      88                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads          1578458                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads      3631905                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        20141                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        12168                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      2053612                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads      3618337                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        20593                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        12016                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      2047079                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads      7821470                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked          4399                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads      1917340                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked          4451                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                4112827                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                27932530                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1927286                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           867488637                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            301587                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              18923985                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             10455746                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts             885039                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 975379                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 15665                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          12168                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         701708                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       624080                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1325788                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             862427395                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              24732275                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1885785                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                4109854                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                27168187                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1772103                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           833002670                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            300864                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              17569417                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             10446486                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts             728436                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 974858                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 15486                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          12016                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         697910                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       625387                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1323297                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             822095189                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              17489841                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1893927                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     33921373                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 86494176                       # Number of branches executed
-system.cpu.iew.exec_stores                    9189098                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.822454                       # Inst execution rate
-system.cpu.iew.wb_sent                      861944484                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     853917813                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 669630870                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1918703675                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     26681633                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 83151598                       # Number of branches executed
+system.cpu.iew.exec_stores                    9191792                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.730612                       # Inst execution rate
+system.cpu.iew.wb_sent                      821608460                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     819484817                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 640296111                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1828731330                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.804472                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.349002                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.725117                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.350131                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      426513995                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        840512563                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        26872606                       # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls         1515656                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1183314                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    306215725                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.744838                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.861126                       # Number of insts commited each cycle
+system.cpu.commit.commitCommittedInsts      407751921                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        806059216                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        26839677                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls         1049940                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts           1181775                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    272647181                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.956419                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.843352                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    125266635     40.91%     40.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     14734551      4.81%     45.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2      4258737      1.39%     47.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     76646765     25.03%     72.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3892941      1.27%     73.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      1792387      0.59%     74.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      1104205      0.36%     74.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     71994718     23.51%     97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      6524786      2.13%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     98573076     36.15%     36.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     13223290      4.85%     41.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2      4246957      1.56%     42.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     75817327     27.81%     70.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      2710299      0.99%     71.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      1789124      0.66%     72.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      1087866      0.40%     72.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     71017917     26.05%     98.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4181325      1.53%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    306215725                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            426513995                       # Number of instructions committed
-system.cpu.commit.committedOps              840512563                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    272647181                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            407751921                       # Number of instructions committed
+system.cpu.commit.committedOps              806059216                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       23694211                       # Number of memory references committed
-system.cpu.commit.loads                      15292077                       # Number of loads committed
-system.cpu.commit.membars                      781571                       # Number of memory barriers committed
-system.cpu.commit.branches                   85505598                       # Number of branches committed
+system.cpu.commit.refs                       22350484                       # Number of memory references committed
+system.cpu.commit.loads                      13951077                       # Number of loads committed
+system.cpu.commit.membars                      471695                       # Number of memory barriers committed
+system.cpu.commit.branches                   82163258                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 768332766                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 735013406                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               6524786                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4181325                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   1166996622                       # The number of ROB reads
-system.cpu.rob.rob_writes                  1738897212                       # The number of ROB writes
-system.cpu.timesIdled                         2997983                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                       162910091                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles                   9872594876                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   426513995                       # Number of Instructions Simulated
-system.cpu.committedOps                     840512563                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             426513995                       # Number of Instructions Simulated
-system.cpu.cpi                               1.109514                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.109514                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.901296                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.901296                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               2163164515                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1362660599                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        96                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               281055752                       # number of misc regfile reads
-system.cpu.misc_regfile_writes                 403699                       # number of misc regfile writes
-system.cpu.icache.replacements                1072786                       # number of replacements
-system.cpu.icache.tagsinuse                510.225454                       # Cycle average of tags in use
-system.cpu.icache.total_refs                  8218240                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                1073298                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   7.656997                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            56932893000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.225454                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996534                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996534                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst      8218240                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total         8218240                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst       8218240                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total          8218240                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst      8218240                       # number of overall hits
-system.cpu.icache.overall_hits::total         8218240                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst      1144801                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total       1144801                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst      1144801                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total        1144801                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst      1144801                       # number of overall misses
-system.cpu.icache.overall_misses::total       1144801                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  18871083485                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  18871083485                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  18871083485                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  18871083485                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  18871083485                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  18871083485                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst      9363041                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total      9363041                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst      9363041                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total      9363041                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst      9363041                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total      9363041                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.122268                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.122268                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.122268                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.122268                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.122268                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.122268                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16484.160553                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16484.160553                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16484.160553                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16484.160553                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16484.160553                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16484.160553                       # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs      3261491                       # number of cycles access was blocked
+system.cpu.rob.rob_reads                   1101286190                       # The number of ROB reads
+system.cpu.rob.rob_writes                  1669922447                       # The number of ROB writes
+system.cpu.timesIdled                         1659907                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                       198289969                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles                   9869314281                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts                   407751921                       # Number of Instructions Simulated
+system.cpu.committedOps                     806059216                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             407751921                       # Number of Instructions Simulated
+system.cpu.cpi                               1.165001                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.165001                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.858368                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.858368                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               2053713870                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1297159076                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        50                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               265135377                       # number of misc regfile reads
+system.cpu.misc_regfile_writes                 402339                       # number of misc regfile writes
+system.cpu.icache.replacements                1068223                       # number of replacements
+system.cpu.icache.tagsinuse                510.418027                       # Cycle average of tags in use
+system.cpu.icache.total_refs                  8239400                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                1068735                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   7.709488                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            57281567000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.418027                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996910                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996910                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      8239400                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         8239400                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       8239400                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          8239400                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      8239400                       # number of overall hits
+system.cpu.icache.overall_hits::total         8239400                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst      1138645                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total       1138645                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst      1138645                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total        1138645                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst      1138645                       # number of overall misses
+system.cpu.icache.overall_misses::total       1138645                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  18814976480                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  18814976480                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  18814976480                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  18814976480                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  18814976480                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  18814976480                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9378045                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9378045                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9378045                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9378045                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9378045                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9378045                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.121416                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.121416                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.121416                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.121416                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.121416                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.121416                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16524.005709                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16524.005709                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16524.005709                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16524.005709                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16524.005709                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16524.005709                       # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs      3200487                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs               378                       # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs               386                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs  8628.283069                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs  8291.417098                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69972                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total        69972                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst        69972                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total        69972                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst        69972                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total        69972                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1074829                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total      1074829                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst      1074829                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total      1074829                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst      1074829                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total      1074829                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14733142991                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  14733142991                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14733142991                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  14733142991                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14733142991                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  14733142991                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.114795                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.114795                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.114795                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.114795                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13707.429732                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 13707.429732                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13707.429732                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 13707.429732                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        69787                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        69787                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        69787                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        69787                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        69787                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        69787                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1068858                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1068858                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1068858                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1068858                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1068858                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1068858                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  14704003987                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  14704003987                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  14704003987                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  14704003987                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  14704003987                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  14704003987                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.113975                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.113975                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.113975                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.113975                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.113975                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.113975                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13756.742230                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13756.742230                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13756.742230                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 13756.742230                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13756.742230                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 13756.742230                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements        11223                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        6.037503                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs          31260                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs        11237                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.781881                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5131387386000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.037503                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.377344                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.377344                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        31468                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total        31468                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements        10021                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        6.028958                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs          32291                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs        10034                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         3.218158                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5136098133000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.028958                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.376810                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.376810                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        32310                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total        32310                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        31471                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total        31471                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        31471                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total        31471                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        12107                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total        12107                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        12107                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total        12107                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        12107                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total        12107                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    196957000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total    196957000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    196957000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total    196957000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    196957000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total    196957000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43575                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        43575                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        32313                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total        32313                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        32313                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total        32313                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker        10911                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total        10911                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker        10911                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total        10911                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker        10911                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total        10911                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    183901500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    183901500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    183901500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    183901500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    183901500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    183901500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        43221                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        43221                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43578                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        43578                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43578                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        43578                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.277843                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.277843                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.277824                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.277824                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.277824                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.277824                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16268.026761                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16268.026761                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16268.026761                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16268.026761                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16268.026761                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16268.026761                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        43224                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        43224                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        43224                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        43224                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.252447                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.252447                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.252429                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.252429                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.252429                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.252429                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16854.687930                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16854.687930                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16854.687930                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16854.687930                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16854.687930                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16854.687930                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -806,78 +806,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks         1700                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total         1700                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        12107                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        12107                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        12107                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total        12107                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        12107                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total        12107                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    159950045                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    159950045                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    159950045                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    159950045                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    159950045                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    159950045                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.277843                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.277843                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.277824                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.277824                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.277824                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.277824                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13211.369043                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13211.369043                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13211.369043                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13211.369043                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks         1563                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1563                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker        10911                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total        10911                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker        10911                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total        10911                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker        10911                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total        10911                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker    150559535                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total    150559535                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker    150559535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total    150559535                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker    150559535                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total    150559535                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.252447                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.252447                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.252429                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.252429                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.252429                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.252429                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13798.875905                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13798.875905                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13798.875905                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13798.875905                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13798.875905                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13798.875905                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements       118986                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse       13.873264                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs         132191                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs       119002                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.110830                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5112880781000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.873264                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.867079                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.867079                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       132191                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total       132191                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       132191                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total       132191                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       132191                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total       132191                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       120057                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total       120057                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       120057                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total       120057                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       120057                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total       120057                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2156991000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2156991000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2156991000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total   2156991000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2156991000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total   2156991000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       252248                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total       252248                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       252248                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total       252248                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       252248                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total       252248                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.475948                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.475948                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.475948                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.475948                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17966.390964                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17966.390964                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17966.390964                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17966.390964                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements       116564                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse       12.971477                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs         137576                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs       116580                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.180100                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5113123336000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    12.971477                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.810717                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.810717                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       137576                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total       137576                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       137576                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total       137576                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       137576                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total       137576                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       117614                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total       117614                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       117614                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total       117614                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       117614                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total       117614                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   2140596500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   2140596500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   2140596500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   2140596500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   2140596500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   2140596500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       255190                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total       255190                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       255190                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total       255190                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       255190                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total       255190                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.460888                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.460888                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.460888                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.460888                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.460888                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.460888                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18200.184502                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18200.184502                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18200.184502                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18200.184502                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18200.184502                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18200.184502                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -886,146 +886,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks        34205                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total        34205                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       120057                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       120057                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       120057                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total       120057                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       120057                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total       120057                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1794187508                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1794187508                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1794187508                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1794187508                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.475948                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.475948                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.475948                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.475948                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14944.463946                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14944.463946                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14944.463946                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14944.463946                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks        39184                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        39184                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       117614                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       117614                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       117614                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       117614                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       117614                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       117614                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1785080011                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1785080011                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1785080011                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1785080011                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1785080011                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1785080011                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.460888                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.460888                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.460888                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.460888                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.460888                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.460888                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15177.444956                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15177.444956                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15177.444956                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15177.444956                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1672900                       # number of replacements
-system.cpu.dcache.tagsinuse                511.996980                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 19011613                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1673412                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.360988                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1673020                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997654                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 19008279                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1673532                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.358181                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               36854000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.996980                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     10933058                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        10933058                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8074504                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8074504                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      19007562                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         19007562                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     19007562                       # number of overall hits
-system.cpu.dcache.overall_hits::total        19007562                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2431156                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2431156                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       318255                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       318255                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2749411                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2749411                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2749411                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2749411                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  45213675500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  45213675500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  10676522982                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  10676522982                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55890198482                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55890198482                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55890198482                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55890198482                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13364214                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13364214                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8392759                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8392759                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21756973                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21756973                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21756973                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21756973                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181915                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.181915                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037920                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037920                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.126369                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.126369                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.126369                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.126369                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18597.603568                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 18597.603568                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33547.070689                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33547.070689                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20328.062440                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20328.062440                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20328.062440                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20328.062440                       # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs     26730982                       # number of cycles access was blocked
+system.cpu.dcache.occ_blocks::cpu.data     511.997654                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     10932679                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        10932679                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8073031                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8073031                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      19005710                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         19005710                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     19005710                       # number of overall hits
+system.cpu.dcache.overall_hits::total        19005710                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2430444                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2430444                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       317095                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       317095                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2747539                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2747539                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2747539                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2747539                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  45216991000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  45216991000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10602716492                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10602716492                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55819707492                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55819707492                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55819707492                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55819707492                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13363123                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13363123                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8390126                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8390126                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21753249                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21753249                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21753249                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21753249                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.181877                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.181877                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037794                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037794                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.126305                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.126305                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.126305                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.126305                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18604.415901                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 18604.415901                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33437.034617                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33437.034617                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.256654                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20316.256654                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.256654                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20316.256654                       # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs     27551492                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs              4911                       # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs              4916                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs  5443.083282                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs  5604.453214                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1571690                       # number of writebacks
-system.cpu.dcache.writebacks::total           1571690                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1049439                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total      1049439                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22786                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total        22786                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      1072225                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      1072225                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      1072225                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      1072225                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381717                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1381717                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       295469                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       295469                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1677186                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1677186                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1677186                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1677186                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23302977034                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23302977034                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9408800483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   9408800483                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32711777517                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  32711777517                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32711777517                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  32711777517                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85208357000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85208357000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1386111000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1386111000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86594468000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  86594468000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103389                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103389                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035205                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035205                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077087                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.077087                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077087                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.077087                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16865.231472                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16865.231472                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31843.612978                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31843.612978                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19503.965283                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19503.965283                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19503.965283                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19503.965283                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1572175                       # number of writebacks
+system.cpu.dcache.writebacks::total           1572175                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1048961                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1048961                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22710                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        22710                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1071671                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1071671                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1071671                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1071671                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1381483                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1381483                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       294385                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       294385                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1675868                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1675868                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1675868                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1675868                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23305790513                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23305790513                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9339566493                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9339566493                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32645357006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  32645357006                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32645357006                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  32645357006                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  96733569500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  96733569500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2477085000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2477085000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  99210654500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  99210654500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.103380                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.103380                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035087                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.035087                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.077040                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.077040                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.077040                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.077040                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16870.124723                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16870.124723                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31725.687426                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31725.687426                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19479.670837                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19479.670837                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19479.670837                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19479.670837                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
index 90df3051e29de87e6d2ba69551ea86b5073c6129..fd6a73c63c53522cf3fbaa154ae19653cc3fcb49 100644 (file)
@@ -1,77 +1,77 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.305568                       # Number of seconds simulated
-sim_ticks                                5305568377500                       # Number of ticks simulated
-final_tick                               5305568377500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.309130                       # Number of seconds simulated
+sim_ticks                                5309130431000                       # Number of ticks simulated
+final_tick                               5309130431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 148548                       # Simulator instruction rate (inst/s)
-host_op_rate                                   304739                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             5673062484                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 518516                       # Number of bytes of host memory used
-host_seconds                                   935.22                       # Real time elapsed on the host
-sim_insts                                   138925597                       # Number of instructions simulated
-sim_ops                                     284998538                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 252383                       # Simulator instruction rate (inst/s)
+host_op_rate                                   484244                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            12393223655                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 461792                       # Number of bytes of host memory used
+host_seconds                                   428.39                       # Real time elapsed on the host
+sim_insts                                   108118332                       # Number of instructions simulated
+sim_ops                                     207445228                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide        35160                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker       131880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker        65368                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        843619360                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         40106316                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker        91872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker        42696                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst        468873856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data         53484588                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1406451096                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    843619360                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst    468873856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1312493216                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker       107024                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker        51696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        833139344                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         64776128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker       119080                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker        55640                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst        193794504                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data         32074945                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1124153521                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    833139344                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst    193794504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1026933848                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      32433610                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data      35512400                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          70937130                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data      44442078                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data      25482673                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          72915871                       # Number of bytes written to this memory
 system.physmem.num_reads::pc.south_bridge.ide          811                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker        16485                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker         8171                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst         105452420                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data           6721793                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker        11484                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker         5337                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst          58609232                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data           8980167                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             179805900                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker        13378                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker         6462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         104142418                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data          11379014                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker        14885                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker         6955                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst          24224313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data           4791752                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             144579988                       # Number of read requests responded to by this memory
 system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          4872539                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data          4951932                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total              9871209                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide         6627                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker         24857                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker         12321                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           159006406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             7559287                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker         17316                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker          8047                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            88373916                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            10080840                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               265089618                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      159006406                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       88373916                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          247380322                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide       563767                       # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data          6585171                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data          3512759                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             10144668                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide         6623                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker         20158                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker          9737                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           156925763                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12200892                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker         22429                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker         10480                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            36502118                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             6041469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               211739669                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      156925763                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       36502118                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          193427881                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide       563389                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            6113126                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            6693420                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               13370317                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       570394                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker        24857                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker        12324                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          159006406                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           13672414                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker        17316                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker         8047                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           88373916                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           16774261                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              278459935                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            8370877                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            4799783                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               13734052                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       570011                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker        20158                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker         9740                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          156925763                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           20571769                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker        22429                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker        10480                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           36502118                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           10841251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              225473721                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -114,52 +114,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu0.numCycles                     10611136755                       # number of cpu cycles simulated
+system.cpu0.numCycles                     10617406972                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   90467113                       # Number of instructions committed
-system.cpu0.committedOps                    191744891                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            172320091                       # Number of integer alu accesses
+system.cpu0.committedInsts                   89456821                       # Number of instructions committed
+system.cpu0.committedOps                    172956710                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            163049245                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts     18433408                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   172320091                       # number of integer instructions
+system.cpu0.num_conditional_control_insts     15979073                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                   163049245                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          529438037                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         286410601                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          506406726                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         269974282                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     19683230                       # number of memory refs
-system.cpu0.num_load_insts                   14799913                       # Number of load instructions
-system.cpu0.num_store_insts                   4883317                       # Number of store instructions
-system.cpu0.num_idle_cycles              10087385086.886099                       # Number of idle cycles
-system.cpu0.num_busy_cycles              523751668.113901                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.049359                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.950641                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     18821806                       # number of memory refs
+system.cpu0.num_load_insts                   12224477                       # Number of load instructions
+system.cpu0.num_store_insts                   6597329                       # Number of store instructions
+system.cpu0.num_idle_cycles              9900769036.140667                       # Number of idle cycles
+system.cpu0.num_busy_cycles              716637935.859333                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.067497                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.932503                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                       0                       # number of quiesce instructions executed
-system.cpu1.numCycles                     10608184676                       # number of cpu cycles simulated
+system.cpu1.numCycles                     10618260862                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   48458484                       # Number of instructions committed
-system.cpu1.committedOps                     93253647                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             88897203                       # Number of integer alu accesses
+system.cpu1.committedInsts                   18661511                       # Number of instructions committed
+system.cpu1.committedOps                     34488518                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             33823915                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                          0                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      8156142                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    88897203                       # number of integer instructions
+system.cpu1.num_conditional_control_insts      2426468                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    33823915                       # number of integer instructions
 system.cpu1.num_fp_insts                            0                       # number of float instructions
-system.cpu1.num_int_register_reads          272264147                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes         138280138                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          103356389                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          49288010                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14383325                       # number of memory refs
-system.cpu1.num_load_insts                    9129593                       # Number of load instructions
-system.cpu1.num_store_insts                   5253732                       # Number of store instructions
-system.cpu1.num_idle_cycles              10274264583.773684                       # Number of idle cycles
-system.cpu1.num_busy_cycles              333920092.226317                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.031478                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.968522                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                      8339462                       # number of memory refs
+system.cpu1.num_load_insts                    4801557                       # Number of load instructions
+system.cpu1.num_store_insts                   3537905                       # Number of store instructions
+system.cpu1.num_idle_cycles              10461852949.262030                       # Number of idle cycles
+system.cpu1.num_busy_cycles              156407912.737971                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.014730                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.985270                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                       0                       # number of quiesce instructions executed
 
index 19b49bfc43d3d2c3c6d6b073287f21c20aeb9ad2..de241166d4904ba421bfb5476b971e936b998a0c 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.954210                       # Number of seconds simulated
-sim_ticks                                1954209529000                       # Number of ticks simulated
-final_tick                               1954209529000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.962054                       # Number of seconds simulated
+sim_ticks                                1962054431000                       # Number of ticks simulated
+final_tick                               1962054431000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1320479                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1320478                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            43430338961                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 301360                       # Number of bytes of host memory used
-host_seconds                                    45.00                       # Real time elapsed on the host
-sim_insts                                    59416773                       # Number of instructions simulated
-sim_ops                                      59416773                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst           717056                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         23797184                       # Number of bytes read from this memory
-system.physmem.bytes_read::tsunami.ide        2649344                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           145856                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          1424768                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28734208                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       717056                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       145856                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          862912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7745216                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7745216                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst             11204                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data            371831                       # Number of read requests responded to by this memory
-system.physmem.num_reads::tsunami.ide           41396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              2279                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             22262                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                448972                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          121019                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               121019                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst              366929                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            12177396                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1355711                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst               74637                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data              729076                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14703750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         366929                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst          74637                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             441566                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3963350                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3963350                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3963350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             366929                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           12177396                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1355711                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst              74637                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data             729076                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18667100                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        342059                       # number of replacements
-system.l2c.tagsinuse                     65268.160318                       # Cycle average of tags in use
-system.l2c.total_refs                         2559182                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        407064                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.286928                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    7752825000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55637.634903                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          3742.497316                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4175.530834                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          1176.828105                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data           535.669160                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.848963                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.057106                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.063714                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.017957                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.008174                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.995913                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst             478624                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             342590                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             511938                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             491329                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1824481                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          858650                       # number of Writeback hits
-system.l2c.Writeback_hits::total               858650                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data             133                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data              95                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 228                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data            22                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data            24                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total                46                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data           101497                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            99318                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               200815                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.inst              478624                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              444087                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              511938                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              590647                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2025296                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst             478624                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             444087                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             511938                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             590647                       # number of overall hits
-system.l2c.overall_hits::total                2025296                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst            11204                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data           270589                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             2290                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             1211                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285294                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          2582                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data           476                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              3058                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data           85                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data           88                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total             173                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data         101602                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          21093                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             122695                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst             11204                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data            372191                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              2290                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             22304                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                407989                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst            11204                       # number of overall misses
-system.l2c.overall_misses::cpu0.data           372191                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             2290                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            22304                       # number of overall misses
-system.l2c.overall_misses::total               407989                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst    582910000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data  14075669000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    119002000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data     63420000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    14841001000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data      1144000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data      1924000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total      3068000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data       695000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data       156000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total       851000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   5283582000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   1096874000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6380456000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    582910000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data  19359251000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    119002000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   1160294000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     21221457000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    582910000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data  19359251000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    119002000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   1160294000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    21221457000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst         489828                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         613179                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         514228                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         492540                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2109775                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       858650                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           858650                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         2715                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data          571                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            3286                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          107                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          112                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total           219                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       203099                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       120411                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           323510                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst          489828                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          816278                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          514228                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          612951                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2433285                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         489828                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         816278                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         514228                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         612951                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2433285                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.022873                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.441289                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.004453                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.002459                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.135225                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.951013                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.833625                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.930615                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.794393                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.785714                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.789954                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.500258                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.175175                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.379262                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.022873                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.455961                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.004453                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.036388                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.167670                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.022873                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.455961                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.004453                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.036388                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.167670                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52026.954659                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52018.629730                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51965.938865                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52369.942197                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52020.024957                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   443.067390                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4042.016807                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  1003.270111                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  8176.470588                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  1772.727273                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  4919.075145                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.736167                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52001.801546                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52002.575492                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52014.291049                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52014.777359                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52026.954659                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52014.291049                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 51965.938865                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52021.789813                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52014.777359                       # average overall miss latency
+host_inst_rate                                2014980                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2014979                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            66592137800                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 297124                       # Number of bytes of host memory used
+host_seconds                                    29.46                       # Real time elapsed on the host
+sim_insts                                    59368818                       # Number of instructions simulated
+sim_ops                                      59368818                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst           834816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         24594240                       # Number of bytes read from this memory
+system.physmem.bytes_read::tsunami.ide        2650816                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst            29056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data           572928                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             28681856                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       834816                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst        29056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          863872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7716416                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7716416                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst             13044                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data            384285                       # Number of read requests responded to by this memory
+system.physmem.num_reads::tsunami.ide           41419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst               454                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data              8952                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                448154                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          120569                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               120569                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst              425481                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            12534943                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1351041                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst               14809                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data              292004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14618277                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         425481                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst          14809                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             440290                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3932825                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3932825                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3932825                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             425481                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           12534943                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1351041                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst              14809                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data             292004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18551102                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        341254                       # number of replacements
+system.l2c.tagsinuse                     65290.172220                       # Cycle average of tags in use
+system.l2c.total_refs                         2492312                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        406269                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.134635                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    7854344000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        55481.040218                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4824.761707                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4855.330442                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           116.015324                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data            13.024529                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.846573                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.073620                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.074086                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.001770                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000199                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.996249                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             902302                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             773944                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst              86739                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              31910                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1794895                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          820354                       # number of Writeback hits
+system.l2c.Writeback_hits::total               820354                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data             162                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              57                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 219                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            23                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            21                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total                44                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data           172408                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            12341                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               184749                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.inst              902302                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              946352                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               86739                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               44251                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1979644                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst             902302                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             946352                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              86739                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              44251                       # number of overall hits
+system.l2c.overall_hits::total                1979644                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst            13044                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           271462                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst              465                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              325                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285296                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2436                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           489                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2925                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           35                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           73                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total             108                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113191                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           8669                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             121860                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst             13044                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            384653                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               465                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              8994                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                407156                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst            13044                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           384653                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              465                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             8994                       # number of overall misses
+system.l2c.overall_misses::total               407156                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst    678900500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  14120860000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     24120000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     17316000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    14841196500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      1412000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      1560000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      2972000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       156000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       208000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       364000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5886266000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    450808000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6337074000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    678900500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  20007126000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     24120000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    468124000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21178270500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    678900500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  20007126000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     24120000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    468124000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21178270500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         915346                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1045406                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst          87204                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          32235                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2080191                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       820354                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           820354                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2598                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          546                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            3144                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           58                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data           94                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total           152                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       285599                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        21010                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           306609                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst          915346                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1331005                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           87204                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           53245                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2386800                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         915346                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1331005                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          87204                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          53245                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2386800                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014250                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.259671                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.005332                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.010082                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.137149                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.937644                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.895604                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.930344                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.603448                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.776596                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.710526                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.396328                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.412613                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.397444                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014250                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.288994                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.005332                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.168917                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.170587                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014250                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.288994                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.005332                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.168917                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.170587                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52046.956455                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.814648                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51870.967742                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data        53280                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52020.345536                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   579.638752                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  3190.184049                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  1016.068376                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  4457.142857                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2849.315068                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  3370.370370                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.950765                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52002.307071                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52002.904973                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52046.956455                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52013.440686                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 51870.967742                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52048.476762                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52015.125652                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52046.956455                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52013.440686                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 51870.967742                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52048.476762                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52015.125652                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -221,119 +221,119 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79488                       # number of writebacks
-system.l2c.writebacks::total                    79488                       # number of writebacks
+system.l2c.writebacks::writebacks               79049                       # number of writebacks
+system.l2c.writebacks::total                    79049                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
 system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
 system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst        11204                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data       270589                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         2279                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         1211                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285283                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         2582                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data          476                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         3058                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           85                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           88                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total          173                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data       101602                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        21093                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        122695                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst        11204                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data       372191                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         2279                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        22304                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           407978                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst        11204                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data       372191                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         2279                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        22304                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          407978                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    448459000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10828601000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     91164000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data     48888000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11417112000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    103374000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19058000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    122432000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      3419000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3520000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total      6939000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4064358000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    843758000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4908116000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    448459000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data  14892959000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst     91164000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data    892646000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16325228000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    448459000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data  14892959000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst     91164000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data    892646000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16325228000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    538312030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data    264188000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    802500030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    914384000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    465175000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1379559000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1452696030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data    729363000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   2182059030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.441289                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.002459                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.135220                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.951013                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.833625                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.930615                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.794393                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.789954                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.500258                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.175175                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.379262                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.455961                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.036388                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.167666                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.022873                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.455961                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.004432                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.036388                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.167666                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.405887                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40037.815126                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40036.625245                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadReq_mshr_misses::cpu0.inst        13044                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       271462                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst          454                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data          325                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285285                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2436                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          489                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2925                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           35                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           73                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          108                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       113191                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         8669                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        121860                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        13044                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       384653                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          454                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         8994                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           407145                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        13044                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       384653                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          454                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         8994                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          407145                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    522369000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  10863316000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     18183000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     13416000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11417284000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     97500000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19560000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    117060000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1400000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2920000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      4320000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4527974000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    346780000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4874754000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    522369000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  15391290000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     18183000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    360196000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16292038000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    522369000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  15391290000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     18183000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    360196000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16292038000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   1370658000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     19250000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1389908000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1967340000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    505194000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2472534000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   3337998000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    524444000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3862442000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014250                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.259671                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.005206                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.010082                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.137144                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.937644                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.895604                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.930344                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.603448                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.776596                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.710526                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.396328                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.412613                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.397444                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014250                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.288994                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.005206                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.168917                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.170582                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014250                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.288994                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.005206                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.168917                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.170582                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40046.688132                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.814648                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40050.660793                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        41280                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.624989                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.630542                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40020.512821                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
 system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736167                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575492                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291049                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40014.971396                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291049                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40014.971396                       # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.950765                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40002.307071                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.904973                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40046.688132                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.440686                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40050.660793                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40048.476762                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40015.321323                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40046.688132                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.440686                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40050.660793                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40048.476762                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40015.321323                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -344,39 +344,39 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     41707                       # number of replacements
-system.iocache.tagsinuse                     1.261563                       # Cycle average of tags in use
+system.iocache.replacements                     41698                       # number of replacements
+system.iocache.tagsinuse                     0.566768                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     41723                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     41714                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1747651126000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.261563                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.078848                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.078848                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::tsunami.ide          176                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              176                       # number of ReadReq misses
+system.iocache.warmup_cycle              1754521474000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       0.566768                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.035423                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.035423                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          178                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              178                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::tsunami.ide        41728                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             41728                       # number of demand (read+write) misses
-system.iocache.overall_misses::tsunami.ide        41728                       # number of overall misses
-system.iocache.overall_misses::total            41728                       # number of overall misses
-system.iocache.ReadReq_miss_latency::tsunami.ide     21013998                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total     21013998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7626285806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7626285806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7647299804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7647299804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7647299804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7647299804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::tsunami.ide          176                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            176                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::tsunami.ide        41730                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             41730                       # number of demand (read+write) misses
+system.iocache.overall_misses::tsunami.ide        41730                       # number of overall misses
+system.iocache.overall_misses::total            41730                       # number of overall misses
+system.iocache.ReadReq_miss_latency::tsunami.ide     21239998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     21239998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7628774806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7628774806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7650014804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7650014804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7650014804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7650014804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          178                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            178                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::tsunami.ide        41728                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           41728                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::tsunami.ide        41728                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          41728                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41730                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           41730                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41730                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          41730                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
@@ -385,40 +385,40 @@ system.iocache.demand_miss_rate::tsunami.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119397.715909                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183535.950279                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183265.428585                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183265.428585                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7316000                       # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119325.831461                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119325.831461                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183595.851126                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183595.851126                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183321.706302                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183321.706302                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183321.706302                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183321.706302                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7551000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7050                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7072                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1037.730496                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1067.731900                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks::writebacks           41531                       # number of writebacks
-system.iocache.writebacks::total                41531                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::tsunami.ide          176                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          176                       # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          178                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          178                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::tsunami.ide        41728                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        41728                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::tsunami.ide        41728                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        41728                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11861000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     11861000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5465428000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5465428000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5477289000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5477289000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5477289000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5477289000                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::tsunami.ide        41730                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41730                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41730                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41730                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11983000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11983000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5467915000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5467915000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5479898000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5479898000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5479898000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5479898000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -427,14 +427,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131261.718750                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131261.718750                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67320.224719                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67320.224719                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131592.101463                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131592.101463                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131317.948718                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131317.948718                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131317.948718                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131317.948718                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits                          0                       # IT
 system.cpu0.dtb.fetch_misses                        0                       # ITB misses
 system.cpu0.dtb.fetch_acv                           0                       # ITB acv
 system.cpu0.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu0.dtb.read_hits                     5733461                       # DTB read hits
+system.cpu0.dtb.read_hits                     8658373                       # DTB read hits
 system.cpu0.dtb.read_misses                      7687                       # DTB read misses
 system.cpu0.dtb.read_acv                          174                       # DTB read access violations
 system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
-system.cpu0.dtb.write_hits                    3961949                       # DTB write hits
+system.cpu0.dtb.write_hits                    6036768                       # DTB write hits
 system.cpu0.dtb.write_misses                      798                       # DTB write misses
 system.cpu0.dtb.write_acv                         115                       # DTB write access violations
 system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
-system.cpu0.dtb.data_hits                     9695410                       # DTB hits
+system.cpu0.dtb.data_hits                    14695141                       # DTB hits
 system.cpu0.dtb.data_misses                      8485                       # DTB misses
 system.cpu0.dtb.data_acv                          289                       # DTB access violations
 system.cpu0.dtb.data_accesses                  719860                       # DTB accesses
-system.cpu0.itb.fetch_hits                    3214179                       # ITB hits
+system.cpu0.itb.fetch_hits                    3948342                       # ITB hits
 system.cpu0.itb.fetch_misses                     3841                       # ITB misses
 system.cpu0.itb.fetch_acv                         143                       # ITB acv
-system.cpu0.itb.fetch_accesses                3218020                       # ITB accesses
+system.cpu0.itb.fetch_accesses                3952183                       # ITB accesses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
 system.cpu0.itb.read_acv                            0                       # DTB read access violations
@@ -480,55 +480,55 @@ system.cpu0.itb.data_hits                           0                       # DT
 system.cpu0.itb.data_misses                         0                       # DTB misses
 system.cpu0.itb.data_acv                            0                       # DTB access violations
 system.cpu0.itb.data_accesses                       0                       # DTB accesses
-system.cpu0.numCycles                      3908419058                       # number of cpu cycles simulated
+system.cpu0.numCycles                      3924108862                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   36160769                       # Number of instructions committed
-system.cpu0.committedOps                     36160769                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33648309                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                143029                       # Number of float alu accesses
-system.cpu0.num_func_calls                     874750                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4239273                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33648309                       # number of integer instructions
-system.cpu0.num_fp_insts                       143029                       # number of float instructions
-system.cpu0.num_int_register_reads           46246517                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          25142738                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads               70823                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes              71471                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                      9725994                       # number of memory refs
-system.cpu0.num_load_insts                    5755174                       # Number of load instructions
-system.cpu0.num_store_insts                   3970820                       # Number of store instructions
-system.cpu0.num_idle_cycles              3741414636.998085                       # Number of idle cycles
-system.cpu0.num_busy_cycles              167004421.001915                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.042729                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.957271                       # Percentage of idle cycles
+system.cpu0.committedInsts                   54115388                       # Number of instructions committed
+system.cpu0.committedOps                     54115388                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             50086021                       # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses                302769                       # Number of float alu accesses
+system.cpu0.num_func_calls                    1426994                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      6243543                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    50086021                       # number of integer instructions
+system.cpu0.num_fp_insts                       302769                       # number of float instructions
+system.cpu0.num_int_register_reads           68608752                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          37121526                       # number of times the integer registers were written
+system.cpu0.num_fp_register_reads              149232                       # number of times the floating registers were read
+system.cpu0.num_fp_register_writes             152287                       # number of times the floating registers were written
+system.cpu0.num_mem_refs                     14741011                       # number of memory refs
+system.cpu0.num_load_insts                    8689642                       # Number of load instructions
+system.cpu0.num_store_insts                   6051369                       # Number of store instructions
+system.cpu0.num_idle_cycles              3676810844.998126                       # Number of idle cycles
+system.cpu0.num_busy_cycles              247298017.001874                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.063020                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.936980                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                    4839                       # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei                    129053                       # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0                   41012     38.31%     38.31% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21                    131      0.12%     38.43% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22                   1971      1.84%     40.27% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30                     17      0.02%     40.29% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31                  63919     59.71%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total              107050                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0                    40581     48.74%     48.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21                     131      0.16%     48.90% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22                    1971      2.37%     51.26% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30                      17      0.02%     51.28% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31                   40564     48.72%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total                83264                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0            1905788612000     97.52%     97.52% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21               88224500      0.00%     97.53% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22              590412500      0.03%     97.56% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30               12827000      0.00%     97.56% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31            47728597000      2.44%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total        1954208673000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0                 0.989491                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.quiesce                    6365                       # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei                    202758                       # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0                   72603     40.61%     40.61% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21                    134      0.07%     40.69% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22                   1979      1.11%     41.79% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30                      6      0.00%     41.80% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31                 104051     58.20%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total              178773                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0                    71234     49.27%     49.27% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21                     134      0.09%     49.36% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22                    1979      1.37%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30                       6      0.00%     50.73% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31                   71230     49.27%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total               144583                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0            1900684456500     96.87%     96.87% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21              103099000      0.01%     96.88% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22              795217500      0.04%     96.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30                5572000      0.00%     96.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31            60465248000      3.08%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total        1962053593000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0                 0.981144                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::21                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31                0.634616                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total             0.777805                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31                0.684568                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total             0.808752                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.syscall::2                         6      2.68%      2.68% # number of syscalls executed
 system.cpu0.kern.syscall::3                        19      8.48%     11.16% # number of syscalls executed
 system.cpu0.kern.syscall::4                         3      1.34%     12.50% # number of syscalls executed
@@ -561,37 +561,37 @@ system.cpu0.kern.syscall::144                       1      0.45%     99.11% # nu
 system.cpu0.kern.syscall::147                       2      0.89%    100.00% # number of syscalls executed
 system.cpu0.kern.syscall::total                   224                       # number of syscalls executed
 system.cpu0.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir                   91      0.08%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrmces                    1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrfen                     1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.08% # number of callpals executed
-system.cpu0.kern.callpal::swpctx                 1959      1.72%      1.80% # number of callpals executed
-system.cpu0.kern.callpal::tbi                      44      0.04%      1.84% # number of callpals executed
-system.cpu0.kern.callpal::wrent                     7      0.01%      1.84% # number of callpals executed
-system.cpu0.kern.callpal::swpipl               101152     88.59%     90.44% # number of callpals executed
-system.cpu0.kern.callpal::rdps                   6620      5.80%     96.24% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp                     1      0.00%     96.24% # number of callpals executed
-system.cpu0.kern.callpal::wrusp                     4      0.00%     96.24% # number of callpals executed
-system.cpu0.kern.callpal::rdusp                     7      0.01%     96.25% # number of callpals executed
-system.cpu0.kern.callpal::whami                     2      0.00%     96.25% # number of callpals executed
-system.cpu0.kern.callpal::rti                    3778      3.31%     99.56% # number of callpals executed
-system.cpu0.kern.callpal::callsys                 356      0.31%     99.87% # number of callpals executed
-system.cpu0.kern.callpal::imb                     149      0.13%    100.00% # number of callpals executed
-system.cpu0.kern.callpal::total                114174                       # number of callpals executed
-system.cpu0.kern.mode_switch::kernel             5323                       # number of protection mode switches
-system.cpu0.kern.mode_switch::user               1231                       # number of protection mode switches
+system.cpu0.kern.callpal::wripir                   91      0.05%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrmces                    1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrfen                     1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr                  1      0.00%      0.05% # number of callpals executed
+system.cpu0.kern.callpal::swpctx                 3870      2.06%      2.11% # number of callpals executed
+system.cpu0.kern.callpal::tbi                      44      0.02%      2.13% # number of callpals executed
+system.cpu0.kern.callpal::wrent                     7      0.00%      2.14% # number of callpals executed
+system.cpu0.kern.callpal::swpipl               171949     91.52%     93.66% # number of callpals executed
+system.cpu0.kern.callpal::rdps                   6691      3.56%     97.22% # number of callpals executed
+system.cpu0.kern.callpal::wrkgp                     1      0.00%     97.22% # number of callpals executed
+system.cpu0.kern.callpal::wrusp                     4      0.00%     97.22% # number of callpals executed
+system.cpu0.kern.callpal::rdusp                     7      0.00%     97.23% # number of callpals executed
+system.cpu0.kern.callpal::whami                     2      0.00%     97.23% # number of callpals executed
+system.cpu0.kern.callpal::rti                    4706      2.50%     99.73% # number of callpals executed
+system.cpu0.kern.callpal::callsys                 356      0.19%     99.92% # number of callpals executed
+system.cpu0.kern.callpal::imb                     149      0.08%    100.00% # number of callpals executed
+system.cpu0.kern.callpal::total                187881                       # number of callpals executed
+system.cpu0.kern.mode_switch::kernel             7232                       # number of protection mode switches
+system.cpu0.kern.mode_switch::user               1230                       # number of protection mode switches
 system.cpu0.kern.mode_switch::idle                  0                       # number of protection mode switches
-system.cpu0.kern.mode_good::kernel               1230                      
-system.cpu0.kern.mode_good::user                 1231                      
+system.cpu0.kern.mode_good::kernel               1229                      
+system.cpu0.kern.mode_good::user                 1230                      
 system.cpu0.kern.mode_good::idle                    0                      
-system.cpu0.kern.mode_switch_good::kernel     0.231073                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel     0.169939                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good::idle           nan                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total     0.375496                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel      1950522760000     99.81%     99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user          3685906000      0.19%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total     0.290593                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel      1958392751000     99.81%     99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user          3660835000      0.19%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks::idle                   0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    1960                       # number of times the context was actually changed
+system.cpu0.kern.swap_context                    3871                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu0.icache.replacements                489206                       # number of replacements
-system.cpu0.icache.tagsinuse               508.795620                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                35679696                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                489718                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 72.857636                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           36113258000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   508.795620                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.993741                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.993741                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     35679696                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       35679696                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     35679696                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        35679696                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     35679696                       # number of overall hits
-system.cpu0.icache.overall_hits::total       35679696                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       489848                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       489848                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       489848                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        489848                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       489848                       # number of overall misses
-system.cpu0.icache.overall_misses::total       489848                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   7462315000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   7462315000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   7462315000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   7462315000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   7462315000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   7462315000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     36169544                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     36169544                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     36169544                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     36169544                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     36169544                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     36169544                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013543                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013543                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013543                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013543                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013543                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013543                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 15233.939916                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 15233.939916                       # average overall miss latency
+system.cpu0.icache.replacements                914730                       # number of replacements
+system.cpu0.icache.tagsinuse               508.781983                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                53208794                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                915241                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 58.136375                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           36528993000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   508.781983                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.993715                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.993715                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     53208794                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       53208794                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     53208794                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        53208794                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     53208794                       # number of overall hits
+system.cpu0.icache.overall_hits::total       53208794                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       915369                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       915369                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       915369                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        915369                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       915369                       # number of overall misses
+system.cpu0.icache.overall_misses::total       915369                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13645389000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13645389000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13645389000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13645389000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13645389000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13645389000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     54124163                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     54124163                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     54124163                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     54124163                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     54124163                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     54124163                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016912                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.016912                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016912                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.016912                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016912                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.016912                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14906.981775                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14906.981775                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14906.981775                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14906.981775                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14906.981775                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14906.981775                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -676,112 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       489848                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       489848                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       489848                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       489848                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       489848                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       489848                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   5992109500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   5992109500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   5992109500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   5992109500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   5992109500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   5992109500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013543                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013543                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013543                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013543                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915369                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       915369                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       915369                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       915369                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       915369                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       915369                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10898588000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10898588000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10898588000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10898588000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10898588000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10898588000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016912                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.016912                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016912                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.016912                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016912                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.016912                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11906.223610                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11906.223610                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11906.223610                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11906.223610                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11906.223610                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11906.223610                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                817819                       # number of replacements
-system.cpu0.dcache.tagsinuse               479.881496                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                 8879648                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                818331                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 10.850925                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              85697000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   479.881496                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.937269                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.937269                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      5008276                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        5008276                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      3627744                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       3627744                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       117045                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       117045                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       122538                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       122538                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data      8636020                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total         8636020                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data      8636020                       # number of overall hits
-system.cpu0.dcache.overall_hits::total        8636020                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       610602                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       610602                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       207036                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       207036                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6562                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         6562                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data          580                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total          580                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       817638                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        817638                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       817638                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       817638                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  19940652000                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total  19940652000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   7284412000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   7284412000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data     92857000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total     92857000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      8303000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total      8303000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data  27225064000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total  27225064000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data  27225064000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total  27225064000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      5618878                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      5618878                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      3834780                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      3834780                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       123607                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       123607                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       123118                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       123118                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data      9453658                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total      9453658                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data      9453658                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total      9453658                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.108670                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.108670                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.053989                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.053989                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.053088                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.053088                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.004711                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.004711                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.086489                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.086489                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.086489                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.086489                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768                       # average overall miss latency
+system.cpu0.dcache.replacements               1337806                       # number of replacements
+system.cpu0.dcache.tagsinuse               506.531092                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                13370025                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs               1338318                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                  9.990170                       # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle             101834000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   506.531092                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.989319                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.989319                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7444474                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        7444474                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5554839                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5554839                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       175825                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       175825                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191178                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       191178                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     12999313                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        12999313                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     12999313                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       12999313                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1037616                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total      1037616                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       289306                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       289306                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16762                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total        16762                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          448                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total          448                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data      1326922                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total       1326922                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data      1326922                       # number of overall misses
+system.cpu0.dcache.overall_misses::total      1326922                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  26113316000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  26113316000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   8963970000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   8963970000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    238512000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    238512000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      4951000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      4951000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  35077286000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  35077286000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  35077286000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  35077286000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8482090                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      8482090                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5844145                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5844145                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       192587                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       192587                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       191626                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       191626                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     14326235                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     14326235                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14326235                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     14326235                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122330                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.122330                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049504                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.049504                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.087036                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.087036                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002338                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.002338                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092622                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.092622                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092622                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.092622                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25166.647392                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25166.647392                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30984.390230                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 30984.390230                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14229.328242                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14229.328242                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11051.339286                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11051.339286                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26435.077570                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 26435.077570                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26435.077570                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 26435.077570                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -790,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       359687                       # number of writebacks
-system.cpu0.dcache.writebacks::total           359687                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       610602                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       610602                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       207036                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       207036                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         6562                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         6562                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          580                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total          580                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       817638                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       817638                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       817638                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       817638                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  18108780524                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total  18108780524                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6663302002                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6663302002                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     73171000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     73171000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      6563000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      6563000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  24772082526                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total  24772082526                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  24772082526                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total  24772082526                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    601210500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    601210500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1014423500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1014423500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   1615634000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total   1615634000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.108670                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.108670                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.053989                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.053989                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.053088                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.053088                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.004711                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.004711                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.086489                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.086489                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.086489                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.086489                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       785164                       # number of writebacks
+system.cpu0.dcache.writebacks::total           785164                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1037616                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1037616                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       289306                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       289306                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16762                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16762                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          448                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          448                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1326922                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1326922                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1326922                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1326922                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23000405022                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23000405022                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8096051001                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8096051001                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    188226000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    188226000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      3606001                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      3606001                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  31096456023                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  31096456023                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  31096456023                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  31096456023                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   1463096000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   1463096000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   2089087000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   2089087000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3552183000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3552183000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122330                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.122330                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049504                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.049504                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.087036                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.087036                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002338                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.002338                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092622                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.092622                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092622                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.092622                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22166.586697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 22166.586697                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27984.386777                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27984.386777                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11229.328242                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11229.328242                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8049.109375                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  8049.109375                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23435.029356                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23435.029356                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23435.029356                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23435.029356                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -857,22 +857,22 @@ system.cpu1.dtb.fetch_hits                          0                       # IT
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
 system.cpu1.dtb.fetch_acv                           0                       # ITB acv
 system.cpu1.dtb.fetch_accesses                      0                       # ITB accesses
-system.cpu1.dtb.read_hits                     3958078                       # DTB read hits
+system.cpu1.dtb.read_hits                     1027490                       # DTB read hits
 system.cpu1.dtb.read_misses                      2750                       # DTB read misses
 system.cpu1.dtb.read_acv                           36                       # DTB read access violations
 system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
-system.cpu1.dtb.write_hits                    2742847                       # DTB write hits
+system.cpu1.dtb.write_hits                     663174                       # DTB write hits
 system.cpu1.dtb.write_misses                      356                       # DTB write misses
 system.cpu1.dtb.write_acv                          48                       # DTB write access violations
 system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
-system.cpu1.dtb.data_hits                     6700925                       # DTB hits
+system.cpu1.dtb.data_hits                     1690664                       # DTB hits
 system.cpu1.dtb.data_misses                      3106                       # DTB misses
 system.cpu1.dtb.data_acv                           84                       # DTB access violations
 system.cpu1.dtb.data_accesses                  302878                       # DTB accesses
-system.cpu1.itb.fetch_hits                    2128502                       # ITB hits
+system.cpu1.itb.fetch_hits                    1394882                       # ITB hits
 system.cpu1.itb.fetch_misses                     1246                       # ITB misses
 system.cpu1.itb.fetch_acv                          41                       # ITB acv
-system.cpu1.itb.fetch_accesses                2129748                       # ITB accesses
+system.cpu1.itb.fetch_accesses                1396128                       # ITB accesses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
 system.cpu1.itb.read_acv                            0                       # DTB read access violations
@@ -885,51 +885,51 @@ system.cpu1.itb.data_hits                           0                       # DT
 system.cpu1.itb.data_misses                         0                       # DTB misses
 system.cpu1.itb.data_acv                            0                       # DTB access violations
 system.cpu1.itb.data_accesses                       0                       # DTB accesses
-system.cpu1.numCycles                      3908222400                       # number of cpu cycles simulated
+system.cpu1.numCycles                      3923836450                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   23256004                       # Number of instructions committed
-system.cpu1.committedOps                     23256004                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             21401422                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                186242                       # Number of float alu accesses
-system.cpu1.num_func_calls                     709842                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      2519926                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    21401422                       # number of integer instructions
-system.cpu1.num_fp_insts                       186242                       # number of float instructions
-system.cpu1.num_int_register_reads           29248159                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          15707401                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads               95219                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes              97489                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                      6725970                       # number of memory refs
-system.cpu1.num_load_insts                    3973767                       # Number of load instructions
-system.cpu1.num_store_insts                   2752203                       # Number of store instructions
-system.cpu1.num_idle_cycles              3808683702.691761                       # Number of idle cycles
-system.cpu1.num_busy_cycles              99538697.308239                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.025469                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.974531                       # Percentage of idle cycles
+system.cpu1.committedInsts                    5253430                       # Number of instructions committed
+system.cpu1.committedOps                      5253430                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses              4920456                       # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses                 25430                       # Number of float alu accesses
+system.cpu1.num_func_calls                     157592                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts       506756                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                     4920456                       # number of integer instructions
+system.cpu1.num_fp_insts                        25430                       # number of float instructions
+system.cpu1.num_int_register_reads            6826440                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes           3699681                       # number of times the integer registers were written
+system.cpu1.num_fp_register_reads               16282                       # number of times the floating registers were read
+system.cpu1.num_fp_register_writes              16129                       # number of times the floating registers were written
+system.cpu1.num_mem_refs                      1700289                       # number of memory refs
+system.cpu1.num_load_insts                    1033544                       # Number of load instructions
+system.cpu1.num_store_insts                    666745                       # Number of store instructions
+system.cpu1.num_idle_cycles              3903109824.944130                       # Number of idle cycles
+system.cpu1.num_busy_cycles              20726625.055870                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.005282                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.994718                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                    3849                       # number of quiesce instructions executed
-system.cpu1.kern.inst.hwrei                    109556                       # number of hwrei instructions executed
-system.cpu1.kern.ipl_count::0                   40729     40.60%     40.60% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22                   1966      1.96%     42.56% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30                     91      0.09%     42.65% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31                  57540     57.35%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total              100326                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0                    39783     48.79%     48.79% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22                    1966      2.41%     51.21% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30                      91      0.11%     51.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31                   39692     48.68%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total                81532                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0            1901560916500     97.31%     97.31% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22              537337500      0.03%     97.34% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30               59036000      0.00%     97.34% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31            51953880000      2.66%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total        1954111170000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0                 0.976773                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.quiesce                    2331                       # number of quiesce instructions executed
+system.cpu1.kern.inst.hwrei                     35943                       # number of hwrei instructions executed
+system.cpu1.kern.ipl_count::0                    9143     31.85%     31.85% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22                   1973      6.87%     38.72% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30                     91      0.32%     39.04% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31                  17500     60.96%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total               28707                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0                     9135     45.13%     45.13% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22                    1973      9.75%     54.87% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30                      91      0.45%     55.32% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31                    9044     44.68%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total                20243                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0            1920768070500     97.90%     97.90% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22              725778000      0.04%     97.94% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30               67189500      0.00%     97.94% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31            40357157000      2.06%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total        1961918195000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0                 0.999125                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::22                       1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used::30                       1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31                0.689816                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::total             0.812671                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::31                0.516800                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.ipl_used::total             0.705159                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.syscall::2                         2      1.96%      1.96% # number of syscalls executed
 system.cpu1.kern.syscall::3                        11     10.78%     12.75% # number of syscalls executed
 system.cpu1.kern.syscall::4                         1      0.98%     13.73% # number of syscalls executed
@@ -953,82 +953,82 @@ system.cpu1.kern.syscall::132                       2      1.96%     99.02% # nu
 system.cpu1.kern.syscall::144                       1      0.98%    100.00% # number of syscalls executed
 system.cpu1.kern.syscall::total                   102                       # number of syscalls executed
 system.cpu1.kern.callpal::cserve                    1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir                   17      0.02%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrmces                    1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::wrfen                     1      0.00%      0.02% # number of callpals executed
-system.cpu1.kern.callpal::swpctx                 2292      2.22%      2.24% # number of callpals executed
-system.cpu1.kern.callpal::tbi                      10      0.01%      2.25% # number of callpals executed
-system.cpu1.kern.callpal::wrent                     7      0.01%      2.26% # number of callpals executed
-system.cpu1.kern.callpal::swpipl                94758     91.98%     94.24% # number of callpals executed
-system.cpu1.kern.callpal::rdps                   2221      2.16%     96.40% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp                     1      0.00%     96.40% # number of callpals executed
-system.cpu1.kern.callpal::wrusp                     3      0.00%     96.40% # number of callpals executed
-system.cpu1.kern.callpal::rdusp                     2      0.00%     96.40% # number of callpals executed
-system.cpu1.kern.callpal::whami                     3      0.00%     96.41% # number of callpals executed
-system.cpu1.kern.callpal::rti                    3510      3.41%     99.81% # number of callpals executed
-system.cpu1.kern.callpal::callsys                 161      0.16%     99.97% # number of callpals executed
-system.cpu1.kern.callpal::imb                      31      0.03%    100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir                    6      0.02%      0.02% # number of callpals executed
+system.cpu1.kern.callpal::wrmces                    1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::wrfen                     1      0.00%      0.03% # number of callpals executed
+system.cpu1.kern.callpal::swpctx                  365      1.24%      1.27% # number of callpals executed
+system.cpu1.kern.callpal::tbi                      10      0.03%      1.31% # number of callpals executed
+system.cpu1.kern.callpal::wrent                     7      0.02%      1.33% # number of callpals executed
+system.cpu1.kern.callpal::swpipl                24055     81.82%     83.15% # number of callpals executed
+system.cpu1.kern.callpal::rdps                   2165      7.36%     90.51% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp                     1      0.00%     90.52% # number of callpals executed
+system.cpu1.kern.callpal::wrusp                     3      0.01%     90.53% # number of callpals executed
+system.cpu1.kern.callpal::rdusp                     2      0.01%     90.53% # number of callpals executed
+system.cpu1.kern.callpal::whami                     3      0.01%     90.54% # number of callpals executed
+system.cpu1.kern.callpal::rti                    2587      8.80%     99.34% # number of callpals executed
+system.cpu1.kern.callpal::callsys                 161      0.55%     99.89% # number of callpals executed
+system.cpu1.kern.callpal::imb                      31      0.11%    100.00% # number of callpals executed
 system.cpu1.kern.callpal::rdunique                  1      0.00%    100.00% # number of callpals executed
-system.cpu1.kern.callpal::total                103020                       # number of callpals executed
-system.cpu1.kern.mode_switch::kernel             2836                       # number of protection mode switches
-system.cpu1.kern.mode_switch::user                515                       # number of protection mode switches
-system.cpu1.kern.mode_switch::idle               2038                       # number of protection mode switches
-system.cpu1.kern.mode_good::kernel                568                      
-system.cpu1.kern.mode_good::user                  515                      
-system.cpu1.kern.mode_good::idle                   53                      
-system.cpu1.kern.mode_switch_good::kernel     0.200282                       # fraction of useful protection mode switches
+system.cpu1.kern.callpal::total                 29400                       # number of callpals executed
+system.cpu1.kern.mode_switch::kernel              879                       # number of protection mode switches
+system.cpu1.kern.mode_switch::user                516                       # number of protection mode switches
+system.cpu1.kern.mode_switch::idle               2075                       # number of protection mode switches
+system.cpu1.kern.mode_good::kernel                532                      
+system.cpu1.kern.mode_good::user                  516                      
+system.cpu1.kern.mode_good::idle                   16                      
+system.cpu1.kern.mode_switch_good::kernel     0.605233                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good::user             1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle      0.026006                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total     0.210800                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel       72317077000      3.70%      3.70% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user          1608073000      0.08%      3.78% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle        1879348652000     96.22%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2293                       # number of times the context was actually changed
-system.cpu1.icache.replacements                513692                       # number of replacements
-system.cpu1.icache.tagsinuse               501.294138                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                22744965                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                514204                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 44.233349                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           96225204000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   501.294138                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.979090                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.979090                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     22744965                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       22744965                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     22744965                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        22744965                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     22744965                       # number of overall hits
-system.cpu1.icache.overall_hits::total       22744965                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       514229                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       514229                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       514229                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        514229                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       514229                       # number of overall misses
-system.cpu1.icache.overall_misses::total       514229                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7551928500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   7551928500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   7551928500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   7551928500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   7551928500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   7551928500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     23259194                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     23259194                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     23259194                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     23259194                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     23259194                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     23259194                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.022109                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.022109                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.022109                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.022109                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.022109                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.022109                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14685.924948                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14685.924948                       # average overall miss latency
+system.cpu1.kern.mode_switch_good::idle      0.007711                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total     0.306628                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel        4074736000      0.21%      0.21% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user          1594048000      0.08%      0.29% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle        1955463610000     99.71%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                     366                       # number of times the context was actually changed
+system.cpu1.icache.replacements                 86665                       # number of replacements
+system.cpu1.icache.tagsinuse               419.761966                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                 5169415                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                 87177                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 59.297923                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1958459766000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   419.761966                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.819848                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.819848                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      5169415                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total        5169415                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst      5169415                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total         5169415                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst      5169415                       # number of overall hits
+system.cpu1.icache.overall_hits::total        5169415                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst        87205                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total        87205                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst        87205                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total         87205                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst        87205                       # number of overall misses
+system.cpu1.icache.overall_misses::total        87205                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1314538500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   1314538500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   1314538500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   1314538500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   1314538500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   1314538500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      5256620                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total      5256620                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst      5256620                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total      5256620                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      5256620                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total      5256620                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016590                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.016590                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016590                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.016590                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016590                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.016590                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15074.118457                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 15074.118457                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15074.118457                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 15074.118457                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15074.118457                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15074.118457                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1037,112 +1037,112 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       514229                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       514229                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       514229                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       514229                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       514229                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       514229                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   6009175500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   6009175500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   6009175500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   6009175500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   6009175500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   6009175500                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.022109                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.022109                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.022109                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.022109                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        87205                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total        87205                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst        87205                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total        87205                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst        87205                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total        87205                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1052891500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   1052891500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1052891500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   1052891500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1052891500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   1052891500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.016590                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.016590                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016590                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.016590                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12073.751505                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12073.751505                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12073.751505                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 12073.751505                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12073.751505                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 12073.751505                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                642542                       # number of replacements
-system.cpu1.dcache.tagsinuse               493.349728                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 6059289                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                642979                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                  9.423774                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           54205321000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   493.349728                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.963574                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.963574                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      3370941                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        3370941                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      2541028                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       2541028                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        71125                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        71125                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        80221                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        80221                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data      5911969                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         5911969                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data      5911969                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        5911969                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       513441                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       513441                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       122213                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       122213                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        13103                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        13103                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data          640                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total          640                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       635654                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        635654                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       635654                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       635654                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   7202554500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   7202554500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   2665634000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   2665634000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    183727000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    183727000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8466000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total      8466000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   9868188500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   9868188500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   9868188500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   9868188500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      3884382                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      3884382                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      2663241                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      2663241                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        84228                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        84228                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        80861                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        80861                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data      6547623                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total      6547623                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data      6547623                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total      6547623                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.132181                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.132181                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.045889                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.045889                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.155566                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.155566                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.007915                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.007915                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.097082                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.097082                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.097082                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.097082                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.465354                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15524.465354                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.465354                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15524.465354                       # average overall miss latency
+system.cpu1.dcache.replacements                 53525                       # number of replacements
+system.cpu1.dcache.tagsinuse               416.811918                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 1627176                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                 53933                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 30.170322                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1941569697000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   416.811918                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.814086                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.814086                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data       982724                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total         982724                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       626457                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total        626457                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11310                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        11310                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11708                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        11708                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data      1609181                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total         1609181                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data      1609181                       # number of overall hits
+system.cpu1.dcache.overall_hits::total        1609181                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data        35620                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total        35620                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        22610                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total        22610                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1003                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total         1003                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          543                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total          543                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data        58230                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total         58230                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data        58230                       # number of overall misses
+system.cpu1.dcache.overall_misses::total        58230                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    484449000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total    484449000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    694363000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total    694363000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     12193000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     12193000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      7082000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      7082000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   1178812000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   1178812000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   1178812000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   1178812000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1018344                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      1018344                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       649067                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total       649067                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        12313                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12251                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        12251                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data      1667411                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total      1667411                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      1667411                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total      1667411                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.034978                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.034978                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.034835                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.034835                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081459                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.081459                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044323                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.044323                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034922                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.034922                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034922                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.034922                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13600.477260                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13600.477260                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30710.437859                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 30710.437859                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12156.530409                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12156.530409                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13042.357274                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13042.357274                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20244.066632                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 20244.066632                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20244.066632                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 20244.066632                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1151,66 +1151,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       498963                       # number of writebacks
-system.cpu1.dcache.writebacks::total           498963                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       513441                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       513441                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       122213                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       122213                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        13103                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        13103                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          640                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total          640                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       635654                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       635654                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       635654                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       635654                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   5662217009                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   5662217009                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   2298995000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   2298995000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data    144418000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total    144418000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6549000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6549000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data         5000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total         5000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   7961212009                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   7961212009                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   7961212009                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   7961212009                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data    295035500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total    295035500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    516366500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    516366500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    811402000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total    811402000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.132181                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.132181                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.155566                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.155566                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.007915                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.007915                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.097082                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.097082                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.097082                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.097082                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks        35190                       # number of writebacks
+system.cpu1.dcache.writebacks::total            35190                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        35620                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        35620                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        22610                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        22610                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1003                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1003                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          543                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          543                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data        58230                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total        58230                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data        58230                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total        58230                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    377581004                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    377581004                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    626529004                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    626529004                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data      9184000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total      9184000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      5453000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      5453000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1004110008                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1004110008                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1004110008                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1004110008                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     20565000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     20565000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    534607500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    534607500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    555172500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    555172500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.034978                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.034978                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.034835                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.034835                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.081459                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.081459                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.044323                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.044323                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034922                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.034922                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034922                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.034922                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10600.252779                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10600.252779                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27710.261123                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27710.261123                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9156.530409                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  9156.530409                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10042.357274                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10042.357274                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17243.860690                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17243.860690                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17243.860690                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17243.860690                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
index c7cd1312f3e427ef7191556cbc0fce69d87643cd..9ccbe5ddb95384ddb179b4b408214be760c5f3c3 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.920853                       # Number of seconds simulated
-sim_ticks                                1920853042000                       # Number of ticks simulated
-final_tick                               1920853042000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.921792                       # Number of seconds simulated
+sim_ticks                                1921792488000                       # Number of ticks simulated
+final_tick                               1921792488000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1381815                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1381815                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            47239093914                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 299308                       # Number of bytes of host memory used
-host_seconds                                    40.66                       # Real time elapsed on the host
-sim_insts                                    56187824                       # Number of instructions simulated
-sim_ops                                      56187824                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            850688                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          24847552                       # Number of bytes read from this memory
+host_inst_rate                                1964765                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1964764                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            67191639126                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 295072                       # Number of bytes of host memory used
+host_seconds                                    28.60                       # Real time elapsed on the host
+sim_insts                                    56195476                       # Number of instructions simulated
+sim_ops                                      56195476                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            850624                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          24858752                       # Number of bytes read from this memory
 system.physmem.bytes_read::tsunami.ide        2652352                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             28350592                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          850688                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      7389056                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7389056                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              13292                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             388243                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total             28361728                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       850624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          850624                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      7403520                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7403520                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst              13291                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             388418                       # Number of read requests responded to by this memory
 system.physmem.num_reads::tsunami.ide           41443                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                442978                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          115454                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               115454                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               442870                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             12935686                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::tsunami.ide           1380820                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                14759376                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          442870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             442870                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3846758                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                3846758                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3846758                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              442870                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            12935686                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::tsunami.ide          1380820                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               18606133                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        336066                       # number of replacements
-system.l2c.tagsinuse                     65311.806529                       # Cycle average of tags in use
-system.l2c.total_refs                         2448197                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        401228                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          6.101760                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                    5946056000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        55675.727094                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           4768.395922                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           4867.683513                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.849544                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.072760                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.074275                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.996579                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.inst              916208                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              814933                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1731141                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          835149                       # number of Writeback hits
-system.l2c.Writeback_hits::total               835149                       # number of Writeback hits
+system.physmem.num_reads::total                443152                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          115680                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               115680                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               442620                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             12935191                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::tsunami.ide           1380145                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                14757955                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          442620                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             442620                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3852403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                3852403                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3852403                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              442620                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            12935191                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::tsunami.ide          1380145                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               18610359                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                        336240                       # number of replacements
+system.l2c.tagsinuse                     65308.066862                       # Cycle average of tags in use
+system.l2c.total_refs                         2448422                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        401402                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          6.099676                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                    6040304000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        55651.693971                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           4767.859045                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           4888.513847                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.849177                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.072752                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.074593                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.996522                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst              916493                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              814973                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1731466                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          835196                       # number of Writeback hits
+system.l2c.Writeback_hits::total               835196                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data                4                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   4                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            187605                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               187605                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.inst               916208                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1002538                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1918746                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.inst              916208                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1002538                       # number of overall hits
-system.l2c.overall_hits::total                1918746                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.inst             13292                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data            271915                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total               285207                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            187534                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               187534                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.inst               916493                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1002507                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1919000                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.inst              916493                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1002507                       # number of overall hits
+system.l2c.overall_hits::total                1919000                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.inst             13291                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            271963                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total               285254                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu.data             14                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                14                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          116718                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             116718                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.inst              13292                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             388633                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                401925                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.inst             13292                       # number of overall misses
-system.l2c.overall_misses::cpu.data            388633                       # number of overall misses
-system.l2c.overall_misses::total               401925                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.inst    691773000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data  14144855000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total    14836628000                       # number of ReadReq miss cycles
+system.l2c.ReadExReq_misses::cpu.data          116845                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             116845                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.inst              13291                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             388808                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                402099                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.inst             13291                       # number of overall misses
+system.l2c.overall_misses::cpu.data            388808                       # number of overall misses
+system.l2c.overall_misses::total               402099                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.inst    691744000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  14147302000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    14839046000                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu.data       320000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total       320000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6070015000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6070015000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.inst    691773000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data  20214870000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total     20906643000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.inst    691773000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data  20214870000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total    20906643000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.inst          929500                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1086848                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2016348                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       835149                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           835149                       # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_miss_latency::cpu.data   6076563000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6076563000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    691744000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  20223865000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     20915609000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    691744000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  20223865000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    20915609000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst          929784                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1086936                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2016720                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       835196                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           835196                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu.data           18                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        304323                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           304323                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.inst           929500                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1391171                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2320671                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          929500                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1391171                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2320671                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.014300                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.250187                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.141447                       # miss rate for ReadReq accesses
+system.l2c.ReadExReq_accesses::cpu.data        304379                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           304379                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.inst           929784                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1391315                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2321099                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          929784                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1391315                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2321099                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.014295                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.250211                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.141445                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu.data     0.777778                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::total       0.777778                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.383533                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.383533                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.inst        0.014300                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.279357                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.173193                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.inst       0.014300                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.279357                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.173193                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52020.560505                       # average ReadReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383880                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.383880                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.014295                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.279454                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.173236                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.014295                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.279454                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.173236                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52046.046197                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.215849                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52020.465971                       # average ReadReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857                       # average UpgradeReq miss latency
 system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52005.817440                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52015.320367                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52016.279157                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52015.320367                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52016.279157                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.331850                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52005.331850                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52046.046197                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52015.043415                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52016.068182                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52046.046197                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52015.043415                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52016.068182                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -141,66 +141,66 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               73942                       # number of writebacks
-system.l2c.writebacks::total                    73942                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu.inst        13292                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data       271915                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total          285207                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               74168                       # number of writebacks
+system.l2c.writebacks::total                    74168                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.inst        13291                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       271963                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          285254                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu.data           14                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::total           14                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       116718                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        116718                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         13292                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        388633                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           401925                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        13292                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       388633                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          401925                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    532266000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data  10881875000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total  11414141000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_misses::cpu.data       116845                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        116845                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         13291                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        388808                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           402099                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        13291                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       388808                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          402099                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    532249000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  10883746000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  11415995000                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       620000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::total       620000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4669399000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4669399000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    532266000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data  15551274000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total  16083540000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    532266000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data  15551274000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total  16083540000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    772639030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total    772639030                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1072677000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1072677000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data   1845316030                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total   1845316030                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250187                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.141447                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4674423000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4674423000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    532249000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  15558169000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16090418000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    532249000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  15558169000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16090418000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data   1331550000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   1331550000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1893145000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1893145000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   3224695000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   3224695000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.014295                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.250211                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.141445                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.777778                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::total     0.777778                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383533                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.383533                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.279357                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.173193                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.014300                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.279357                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.173193                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383880                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.383880                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.014295                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.279454                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.173236                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.014295                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.279454                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.173236                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.820480                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.215849                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.455454                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40016.271692                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40016.271692                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.331850                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.331850                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.820480                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.043415                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40016.060721                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.820480                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.043415                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40016.060721                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
-system.iocache.tagsinuse                     1.356968                       # Cycle average of tags in use
+system.iocache.tagsinuse                     1.355427                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              1753491316000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide       1.356968                       # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide      0.084811                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.084811                       # Average percentage of cache occupancy
+system.iocache.warmup_cycle              1754498131000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide       1.355427                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.084714                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.084714                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -227,12 +227,12 @@ system.iocache.overall_misses::tsunami.ide        41725                       #
 system.iocache.overall_misses::total            41725                       # number of overall misses
 system.iocache.ReadReq_miss_latency::tsunami.ide     20672998                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total     20672998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide   7638105806                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7638105806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide   7658778804                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7658778804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide   7658778804                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7658778804                       # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   7634106806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7634106806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   7654779804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7654779804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   7654779804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7654779804                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
@@ -251,17 +251,17 @@ system.iocache.overall_miss_rate::tsunami.ide            1
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
 system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119497.098266                       # average ReadReq miss latency
 system.iocache.ReadReq_avg_miss_latency::total 119497.098266                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183820.413121                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 183820.413121                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 183553.716093                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183553.716093                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 183553.716093                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183553.716093                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs       7453000                       # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183724.172266                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 183724.172266                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 183457.874272                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 183457.874272                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 183457.874272                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 183457.874272                       # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs       7454000                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                 7118                       # number of cycles access was blocked
+system.iocache.blocked::no_mshrs                 7097                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs  1047.063782                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs  1050.302945                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
@@ -277,12 +277,12 @@ system.iocache.overall_mshr_misses::tsunami.ide        41725
 system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11676000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total     11676000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5477251000                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   5477251000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide   5488927000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   5488927000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide   5488927000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   5488927000                       # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   5473252000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   5473252000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   5484928000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   5484928000                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   5484928000                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   5484928000                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
@@ -293,12 +293,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide            1
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
 system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67491.329480                       # average ReadReq mshr miss latency
 system.iocache.ReadReq_avg_mshr_miss_latency::total 67491.329480                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131816.783789                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 131816.783789                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131550.077891                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 131550.077891                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131550.077891                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 131550.077891                       # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131720.542934                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 131720.542934                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131454.236070                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131454.236070                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131454.236070                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131454.236070                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -316,22 +316,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                      9065773                       # DTB read hits
+system.cpu.dtb.read_hits                      9066933                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
-system.cpu.dtb.write_hits                     6357048                       # DTB write hits
+system.cpu.dtb.write_hits                     6357519                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
-system.cpu.dtb.data_hits                     15422821                       # DTB hits
+system.cpu.dtb.data_hits                     15424452                       # DTB hits
 system.cpu.dtb.data_misses                      11471                       # DTB misses
 system.cpu.dtb.data_acv                           367                       # DTB access violations
 system.cpu.dtb.data_accesses                  1020787                       # DTB accesses
-system.cpu.itb.fetch_hits                     4975760                       # ITB hits
+system.cpu.itb.fetch_hits                     4975863                       # ITB hits
 system.cpu.itb.fetch_misses                      5006                       # ITB misses
 system.cpu.itb.fetch_acv                          184                       # ITB acv
-system.cpu.itb.fetch_accesses                 4980766                       # ITB accesses
+system.cpu.itb.fetch_accesses                 4980869                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -344,51 +344,51 @@ system.cpu.itb.data_hits                            0                       # DT
 system.cpu.itb.data_misses                          0                       # DTB misses
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
-system.cpu.numCycles                       3841706084                       # number of cpu cycles simulated
+system.cpu.numCycles                       3843584976                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    56187824                       # Number of instructions committed
-system.cpu.committedOps                      56187824                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              52059470                       # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
-system.cpu.num_func_calls                     1483670                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      6469221                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     52059470                       # number of integer instructions
-system.cpu.num_fp_insts                        324460                       # number of float instructions
-system.cpu.num_int_register_reads            71329755                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           38524240                       # number of times the integer registers were written
-system.cpu.num_fp_register_reads               163642                       # number of times the floating registers were read
-system.cpu.num_fp_register_writes              166520                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      15475451                       # number of memory refs
-system.cpu.num_load_insts                     9102635                       # Number of load instructions
-system.cpu.num_store_insts                    6372816                       # Number of store instructions
-system.cpu.num_idle_cycles               3589579952.998131                       # Number of idle cycles
-system.cpu.num_busy_cycles               252126131.001869                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.065629                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.934371                       # Percentage of idle cycles
+system.cpu.committedInsts                    56195476                       # Number of instructions committed
+system.cpu.committedOps                      56195476                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              52066692                       # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses                 324259                       # Number of float alu accesses
+system.cpu.num_func_calls                     1483822                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      6469666                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     52066692                       # number of integer instructions
+system.cpu.num_fp_insts                        324259                       # number of float instructions
+system.cpu.num_int_register_reads            71339619                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           38530592                       # number of times the integer registers were written
+system.cpu.num_fp_register_reads               163543                       # number of times the floating registers were read
+system.cpu.num_fp_register_writes              166418                       # number of times the floating registers were written
+system.cpu.num_mem_refs                      15477059                       # number of memory refs
+system.cpu.num_load_insts                     9103780                       # Number of load instructions
+system.cpu.num_store_insts                    6373279                       # Number of store instructions
+system.cpu.num_idle_cycles               3588655153.998133                       # Number of idle cycles
+system.cpu.num_busy_cycles               254929822.001867                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.066326                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.933674                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                     6379                       # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei                     212104                       # number of hwrei instructions executed
-system.cpu.kern.ipl_count::0                    74929     40.88%     40.88% # number of times we switched to this ipl
+system.cpu.kern.inst.quiesce                     6374                       # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei                     212119                       # number of hwrei instructions executed
+system.cpu.kern.ipl_count::0                    74932     40.88%     40.88% # number of times we switched to this ipl
 system.cpu.kern.ipl_count::21                     131      0.07%     40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22                    1936      1.06%     42.01% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31                  106285     57.99%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total               183281                       # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0                     73562     49.31%     49.31% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::21                      131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22                     1936      1.30%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31                    73562     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total                149191                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0             1861395652500     96.90%     96.90% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21                90398000      0.00%     96.91% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22               587366500      0.03%     96.94% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31             58778792000      3.06%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total         1920852209000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0                  0.981756                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_count::22                    1937      1.06%     42.01% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31                  106298     57.99%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total               183298                       # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0                     73565     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::21                      131      0.09%     49.39% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::22                     1937      1.30%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31                    73565     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total                149198                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0             1861046523500     96.84%     96.84% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21               104284500      0.01%     96.84% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22               779455000      0.04%     96.89% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31             59861392000      3.11%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total         1921791655000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0                  0.981757                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used::22                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31                 0.692120                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total              0.814001                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31                 0.692064                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total              0.813964                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.syscall::2                          8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall::3                         30      9.20%     11.66% # number of syscalls executed
 system.cpu.kern.syscall::4                          4      1.23%     12.88% # number of syscalls executed
@@ -424,33 +424,33 @@ system.cpu.kern.callpal::cserve                     1      0.00%      0.00% # nu
 system.cpu.kern.callpal::wrmces                     1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrfen                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal::wrvptptr                   1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx                  4177      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx                  4174      2.16%      2.16% # number of callpals executed
 system.cpu.kern.callpal::tbi                       54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal::wrent                      7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl                176052     91.22%     93.41% # number of callpals executed
-system.cpu.kern.callpal::rdps                    6837      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal::swpipl                176067     91.22%     93.41% # number of callpals executed
+system.cpu.kern.callpal::rdps                    6838      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrkgp                      1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::wrusp                      7      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::rdusp                      9      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal::whami                      2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal::rti                     5161      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal::rti                     5162      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal::callsys                  515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal::imb                      181      0.09%    100.00% # number of callpals executed
-system.cpu.kern.callpal::total                 193007                       # number of callpals executed
-system.cpu.kern.mode_switch::kernel              5906                       # number of protection mode switches
-system.cpu.kern.mode_switch::user                1738                       # number of protection mode switches
-system.cpu.kern.mode_switch::idle                2098                       # number of protection mode switches
-system.cpu.kern.mode_good::kernel                1908                      
-system.cpu.kern.mode_good::user                  1738                      
-system.cpu.kern.mode_good::idle                   170                      
-system.cpu.kern.mode_switch_good::kernel     0.323061                       # fraction of useful protection mode switches
+system.cpu.kern.callpal::total                 193021                       # number of callpals executed
+system.cpu.kern.mode_switch::kernel              5905                       # number of protection mode switches
+system.cpu.kern.mode_switch::user                1740                       # number of protection mode switches
+system.cpu.kern.mode_switch::idle                2097                       # number of protection mode switches
+system.cpu.kern.mode_good::kernel                1909                      
+system.cpu.kern.mode_good::user                  1740                      
+system.cpu.kern.mode_good::idle                   169                      
+system.cpu.kern.mode_switch_good::kernel     0.323285                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good::user              1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle       0.081030                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total      0.391706                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel        46234707000      2.41%      2.41% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user           5259387000      0.27%      2.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle         1869358108000     97.32%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4178                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle       0.080591                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total      0.391911                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel        46687559000      2.43%      2.43% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user           5260775000      0.27%      2.70% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle         1869843314000     97.30%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4175                       # number of times the context was actually changed
 system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
 system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
 system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
@@ -482,51 +482,51 @@ system.tsunami.ethernet.totalRxOrn                  0                       # to
 system.tsunami.ethernet.coalescedTotal            nan                       # average number of interrupts coalesced into each post
 system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
-system.cpu.icache.replacements                 928849                       # number of replacements
-system.cpu.icache.tagsinuse                508.732123                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 55270143                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 929360                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  59.471188                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            35877190000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     508.732123                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.993617                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.993617                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     55270143                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        55270143                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      55270143                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         55270143                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     55270143                       # number of overall hits
-system.cpu.icache.overall_hits::total        55270143                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       929520                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        929520                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       929520                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         929520                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       929520                       # number of overall misses
-system.cpu.icache.overall_misses::total        929520                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  13854449500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  13854449500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  13854449500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  13854449500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  13854449500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  13854449500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     56199663                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     56199663                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     56199663                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     56199663                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     56199663                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     56199663                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016540                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.016540                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.016540                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.016540                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.016540                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.016540                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14904.950405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14904.950405                       # average overall miss latency
+system.cpu.icache.replacements                 929133                       # number of replacements
+system.cpu.icache.tagsinuse                508.706285                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 55277511                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 929644                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  59.460945                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            36213864000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     508.706285                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.993567                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.993567                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     55277511                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        55277511                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      55277511                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         55277511                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     55277511                       # number of overall hits
+system.cpu.icache.overall_hits::total        55277511                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       929804                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        929804                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       929804                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         929804                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       929804                       # number of overall misses
+system.cpu.icache.overall_misses::total        929804                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13857748000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13857748000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13857748000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13857748000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13857748000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13857748000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56207315                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     56207315                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     56207315                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     56207315                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56207315                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     56207315                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016542                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.016542                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016542                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.016542                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016542                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.016542                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14903.945348                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14903.945348                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14903.945348                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14903.945348                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14903.945348                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14903.945348                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -535,104 +535,104 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929520                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       929520                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       929520                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       929520                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       929520                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       929520                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11065203000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total  11065203000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11065203000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total  11065203000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11065203000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total  11065203000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016540                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.016540                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.016540                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       929804                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       929804                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       929804                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       929804                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       929804                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       929804                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11067649000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11067649000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11067649000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11067649000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11067649000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11067649000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.016542                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.016542                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016542                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.016542                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.206482                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.206482                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.206482                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.206482                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.206482                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.206482                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1390657                       # number of replacements
-system.cpu.dcache.tagsinuse                511.983813                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14050696                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1391169                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.099920                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               85768000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.983813                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999968                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999968                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data      7815339                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total         7815339                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      5853076                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        5853076                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       182979                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       182979                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       199284                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       199284                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      13668415                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         13668415                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     13668415                       # number of overall hits
-system.cpu.dcache.overall_hits::total        13668415                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1069522                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1069522                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       304341                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       304341                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        17326                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        17326                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data      1373863                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1373863                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1373863                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1373863                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  26656014000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  26656014000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9232792000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9232792000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    248493000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    248493000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  35888806000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  35888806000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  35888806000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  35888806000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data      8884861                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total      8884861                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      6157417                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      6157417                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200305                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       200305                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       199284                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       199284                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     15042278                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     15042278                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     15042278                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     15042278                       # number of overall (read+write) accesses
+system.cpu.dcache.replacements                1390802                       # number of replacements
+system.cpu.dcache.tagsinuse                511.979761                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14052158                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1391314                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.099918                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              101905000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data     511.979761                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999960                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999960                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7816348                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total         7816348                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5853489                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        5853489                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183027                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       183027                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199276                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       199276                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      13669837                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         13669837                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     13669837                       # number of overall hits
+system.cpu.dcache.overall_hits::total        13669837                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1069663                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1069663                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304397                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       304397                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17273                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        17273                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1374060                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1374060                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1374060                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1374060                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  26660030000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  26660030000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9238691000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9238691000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    247715000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    247715000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  35898721000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  35898721000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  35898721000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  35898721000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8886011                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total      8886011                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6157886                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6157886                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200300                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       200300                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       199276                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     15043897                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     15043897                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15043897                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     15043897                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120376                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.120376                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049427                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.049427                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086498                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086498                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.091333                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.091333                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.091333                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.091333                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26122.550793                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26122.550793                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049432                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.049432                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.086236                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.086236                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091337                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.091337                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091337                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.091337                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.765709                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.765709                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30350.795179                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30350.795179                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14341.168297                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14341.168297                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26126.021426                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26126.021426                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26126.021426                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26126.021426                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -641,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       835149                       # number of writebacks
-system.cpu.dcache.writebacks::total            835149                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069522                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1069522                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304341                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       304341                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17326                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        17326                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1373863                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1373863                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1373863                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1373863                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23447403000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  23447403000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8319769000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8319769000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    196515000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    196515000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31767172000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  31767172000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31767172000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  31767172000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    862831000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    862831000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1190523500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1190523500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2053354500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total   2053354500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.writebacks::writebacks       835196                       # number of writebacks
+system.cpu.dcache.writebacks::total            835196                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069663                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069663                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304397                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304397                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17273                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17273                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1374060                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1374060                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1374060                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1374060                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23450996000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23450996000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8325500000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8325500000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    195896000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    195896000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  31776496000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  31776496000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  31776496000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  31776496000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   1421708000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   1421708000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2011005000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2011005000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   3432713000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   3432713000                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120376                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.120376                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049427                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086498                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086498                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.091333                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091333                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.091333                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039                       # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049432                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.049432                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.086236                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.086236                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.091337                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091337                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.091337                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.723640                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.723640                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27350.795179                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27350.795179                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11341.168297                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11341.168297                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23125.988676                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23125.988676                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23125.988676                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23125.988676                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
index 2693ffabedb5b445317608ca10491d79e0bde627..a84f458bf8dbebb9e813d3737a41031a6c61d31d 100644 (file)
@@ -1,71 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  1.172545                       # Number of seconds simulated
-sim_ticks                                1172544977000                       # Number of ticks simulated
-final_tick                               1172544977000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  1.207291                       # Number of seconds simulated
+sim_ticks                                1207290627000                       # Number of ticks simulated
+final_tick                               1207290627000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 706392                       # Simulator instruction rate (inst/s)
-host_op_rate                                   900233                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            13469238975                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 389548                       # Number of bytes of host memory used
-host_seconds                                    87.05                       # Real time elapsed on the host
-sim_insts                                    61493926                       # Number of instructions simulated
-sim_ops                                      78368454                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd     50331648                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst           394788                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data          4717236                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst           322588                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data          4794736                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             60561444                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst       394788                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst       322588                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          717376                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      4107264                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           7134608                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd       6291456                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst             12387                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data             73779                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst              5122                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data             74944                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total               6457695                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           64176                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               821012                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        42925132                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker            55                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker           109                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst              336693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data             4023075                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker           218                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst              275118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             4089170                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51649570                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst         336693                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst         275118                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             611811                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           3502863                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data              14498                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data            2567359                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                6084720                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           3502863                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       42925132                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker           55                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker          109                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst             336693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data            4037573                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker          218                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst             275118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            6656529                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               57734290                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                1000042                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1274494                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            19638848032                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383956                       # Number of bytes of host memory used
+host_seconds                                    61.47                       # Real time elapsed on the host
+sim_insts                                    61477134                       # Number of instructions simulated
+sim_ops                                      78349023                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
@@ -76,245 +21,318 @@ system.realview.nvmem.num_reads::cpu0.inst            5                       #
 system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
 system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
 system.realview.nvmem.bw_read::cpu0.inst           17                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst           41                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               58                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst           40                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               56                       # Total read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_inst_read::cpu0.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst           41                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           58                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst           40                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           56                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu0.inst           17                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst           41                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              58                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         69301                       # number of replacements
-system.l2c.tagsinuse                     52667.431766                       # Cycle average of tags in use
-system.l2c.total_refs                         1645571                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        134500                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         12.234729                       # Average number of references to valid blocks.
+system.realview.nvmem.bw_total::cpu1.inst           40                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              56                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::realview.clcd     52642784                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst           394084                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data          4718772                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker           64                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst           323100                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data          4791152                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             62870404                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst       394084                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst       323100                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          717184                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      4105920                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data         17000                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data       3010344                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           7133264                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd       6580348                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst             12376                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data             73803                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker            1                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst              5130                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data             74888                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total               6746553                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           64155                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data             4250                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data           752586                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               820991                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        43604069                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker            53                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker           106                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst              326420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data             3908563                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker           212                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker            53                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst              267624                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             3968516                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                52075617                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst         326420                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst         267624                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             594044                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           3400938                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data              14081                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data            2493471                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                5908490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           3400938                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       43604069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker          106                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst             326420                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data            3922645                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker          212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker           53                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst             267624                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            6461987                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               57984106                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         69267                       # number of replacements
+system.l2c.tagsinuse                     52917.687187                       # Cycle average of tags in use
+system.l2c.total_refs                         1645693                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        134464                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         12.238912                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        39900.139395                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker       0.000282                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker       0.001242                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst          3730.644795                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data          4216.663550                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker       2.734150                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst          2763.076938                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data          2054.171414                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.608828                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        40124.661939                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       0.000403                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.001466                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3720.854168                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          4213.259552                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       2.746626                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.itb.walker       0.001732                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2800.295642                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2055.865658                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.612254                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.056925                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data            0.064341                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.056776                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.064289                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.dtb.walker      0.000042                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.042161                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data            0.031344                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.803641                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker         4102                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker         1845                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst             402958                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data             205810                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker         5738                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker         1962                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst             449307                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data             144268                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1215990                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          572486                       # number of Writeback hits
-system.l2c.Writeback_hits::total               572486                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data            1132                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data             588                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1720                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data           206                       # number of SCUpgradeReq hits
+system.l2c.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.042729                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.031370                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.807460                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4114                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1841                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             402307                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             205875                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         5723                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1959                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             449970                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             144091                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1215880                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          572580                       # number of Writeback hits
+system.l2c.Writeback_hits::total               572580                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data            1130                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             572                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                1702                       # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           212                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::cpu1.data           104                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               310                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data            56781                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data            53046                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               109827                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker          4102                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker          1845                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst              402958                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data              262591                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker          5738                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker          1962                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst              449307                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data              197314                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1325817                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker         4102                       # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker         1845                       # number of overall hits
-system.l2c.overall_hits::cpu0.inst             402958                       # number of overall hits
-system.l2c.overall_hits::cpu0.data             262591                       # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker         5738                       # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker         1962                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst             449307                       # number of overall hits
-system.l2c.overall_hits::cpu1.data             197314                       # number of overall hits
-system.l2c.overall_hits::total                1325817                       # number of overall hits
+system.l2c.SCUpgradeReq_hits::total               316                       # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data            56723                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            53017                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               109740                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker          4114                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1841                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              402307                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              262598                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          5723                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1959                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              449970                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              197108                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1325620                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker         4114                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1841                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             402307                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             262598                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         5723                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1959                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             449970                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             197108                       # number of overall hits
+system.l2c.overall_hits::total                1325620                       # number of overall hits
 system.l2c.ReadReq_misses::cpu0.dtb.walker            1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst             5755                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data             7866                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             5744                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             7874                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.dtb.walker            4                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst             5035                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data             3646                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                22309                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data          4696                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data          3601                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              8297                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data          568                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data          498                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1066                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data          67165                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data          72394                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             139559                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker            1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             5043                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             3639                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                22308                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          4704                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          3584                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              8288                       # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          569                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          485                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total            1054                       # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data          67193                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          72340                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             139533                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu0.dtb.walker            1                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst              5755                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data             75031                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              5744                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data             75067                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.dtb.walker            4                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst              5035                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data             76040                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                161868                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            1                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              5043                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             75979                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                161841                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu0.dtb.walker            1                       # number of overall misses
 system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu0.inst             5755                       # number of overall misses
-system.l2c.overall_misses::cpu0.data            75031                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             5744                       # number of overall misses
+system.l2c.overall_misses::cpu0.data            75067                       # number of overall misses
 system.l2c.overall_misses::cpu1.dtb.walker            4                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst             5035                       # number of overall misses
-system.l2c.overall_misses::cpu1.data            76040                       # number of overall misses
-system.l2c.overall_misses::total               161868                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            1                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             5043                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            75979                       # number of overall misses
+system.l2c.overall_misses::total               161841                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu0.dtb.walker        52000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu0.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst    299823500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data    409333998                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    298918500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    409688500                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       208500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst    262768000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data    190087500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1162377498                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data     29968997                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data     27317000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     57285997                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3654000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6100000                       # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total      9754000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data   3493697466                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data   3769025494                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   7262722960                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker        52500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    263122000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    189491500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1161637500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     30055000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     27347000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     57402000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      3692000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      6038000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      9730000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   3494564965                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   3764669994                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7259234959                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu0.dtb.walker        52000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu0.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst    299823500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data   3903031464                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    298918500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   3904253465                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.dtb.walker       208500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst    262768000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data   3959112994                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8425100458                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker        52500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    263122000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   3954161494                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8420872459                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu0.dtb.walker        52000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu0.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst    299823500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data   3903031464                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    298918500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   3904253465                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.dtb.walker       208500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst    262768000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data   3959112994                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8425100458                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker         4103                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker         1847                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst         408713                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data         213676                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker         5742                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker         1962                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst         454342                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data         147914                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1238299                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       572486                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           572486                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data         5828                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data         4189                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           10017                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data          774                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data          602                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1376                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data       123946                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data       125440                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           249386                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker         4103                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker         1847                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst          408713                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data          337622                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker         5742                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker         1962                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst          454342                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data          273354                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1487685                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker         4103                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker         1847                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst         408713                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data         337622                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker         5742                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker         1962                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst         454342                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data         273354                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1487685                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.014081                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.036813                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.011082                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.024649                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.018016                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.805765                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data     0.859632                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.828292                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.733850                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.827243                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total     0.774709                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data     0.541889                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data     0.577121                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.559610                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.014081                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.222234                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.011082                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.278174                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.108805                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000244                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker     0.001083                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.014081                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.222234                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000697                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.011082                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.278174                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.108805                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu1.itb.walker        52500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    263122000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   3954161494                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8420872459                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4115                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1843                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         408051                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         213749                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         5727                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1960                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         455013                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         147730                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1238188                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       572580                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           572580                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         5834                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4156                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            9990                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          781                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          589                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total          1370                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       123916                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       125357                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           249273                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker         4115                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1843                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          408051                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          337665                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         5727                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1960                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          455013                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          273087                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1487461                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4115                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1843                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         408051                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         337665                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         5727                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1960                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         455013                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         273087                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1487461                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.014077                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.036838                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.011083                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.024633                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.018017                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.806308                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.862368                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.829630                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.728553                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.823430                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total     0.769343                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.542246                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.577072                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.559760                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.014077                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.222312                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.011083                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.278223                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.108804                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000243                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.001085                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.014077                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.222312                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.000698                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.000510                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.011083                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.278223                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.108804                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52097.914857                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 52038.392830                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52040.128830                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52030.543561                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52125                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52188.282026                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 52135.902359                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52103.523152                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6381.813671                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7585.948348                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total  6904.422924                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6433.098592                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12248.995984                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total  9150.093809                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52016.637624                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52062.677763                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52040.520210                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52175.689074                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52072.410003                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52072.686928                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6389.243197                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  7630.301339                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total  6925.916988                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6488.576450                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12449.484536                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total  9231.499051                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52007.872323                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52041.332513                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52025.219547                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 52097.914857                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52018.918367                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52040.128830                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52010.250376                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52188.282026                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 52066.188769                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52049.203413                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52175.689074                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52042.820964                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52031.762403                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 52097.914857                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52018.918367                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52040.128830                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52010.250376                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52125                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52188.282026                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 52066.188769                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52049.203413                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52175.689074                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52042.820964                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52031.762403                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -323,8 +341,8 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               64176                       # number of writebacks
-system.l2c.writebacks::total                    64176                       # number of writebacks
+system.l2c.writebacks::writebacks               64155                       # number of writebacks
+system.l2c.writebacks::total                    64155                       # number of writebacks
 system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
 system.l2c.ReadReq_mshr_hits::total                 1                       # number of ReadReq MSHR hits
 system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
@@ -333,149 +351,161 @@ system.l2c.overall_mshr_hits::cpu0.inst             1                       # nu
 system.l2c.overall_mshr_hits::total                 1                       # number of overall MSHR hits
 system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst         5754                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data         7866                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         5743                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         7874                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            4                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst         5035                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data         3646                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           22308                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data         4696                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data         3601                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         8297                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          568                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          498                       # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total         1066                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data        67165                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data        72394                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        139559                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         5043                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         3639                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           22307                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         4704                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3584                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8288                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          569                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          485                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1054                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        67193                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        72340                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        139533                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu0.dtb.walker            1                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst         5754                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data        75031                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         5743                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data        75067                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.dtb.walker            4                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst         5035                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data        76040                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           161867                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         5043                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        75979                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           161840                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu0.dtb.walker            1                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst         5754                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data        75031                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         5743                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data        75067                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.dtb.walker            4                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst         5035                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data        76040                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          161867                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         5043                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        75979                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          161840                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    230747000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data    314937000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    229974000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    315198000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    202344000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data    146333000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    894641000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    187986000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    144285000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    332271000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22750000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19953000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total     42703000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2687673000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2900282000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5587955000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    202602000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    145821000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    893915000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    188555000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    143675000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    332230000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     22768000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19442000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     42210000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   2688204000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2896575000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5584779000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu0.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst    230747000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data   3002610000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    229974000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   3003402000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst    202344000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data   3046615000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6482596000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker        40000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    202602000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   3042396000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6478694000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker        40000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu0.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst    230747000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data   3002610000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    229974000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   3003402000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       160000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst    202344000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data   3046615000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6482596000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker        40000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    202602000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   3042396000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6478694000                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   9314941499                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data  12448668498                       # number of ReadReq MSHR uncacheable cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122157234000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131741656499                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    694839000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30621237500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31316076500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154365734497                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167083883995                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1128303000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  30843793500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31972096500                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data  10009780499                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  13576971498                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 163057732999                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036813                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024649                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.018015                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.805765                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.859632                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.828292                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.733850                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.827243                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.774709                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.541889                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577121                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.559610                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data     0.222234                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data     0.278174                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.108805                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000244                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001083                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014078                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data     0.222234                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000697                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011082                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data     0.278174                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.108805                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185209527997                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 199055980495                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.036838                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.024633                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.018016                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.806308                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.862368                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.829630                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.728553                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.823430                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.769343                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.542246                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.577072                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.559760                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.222312                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.278223                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.108803                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000243                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.001085                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.014074                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.222312                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.000698                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.000510                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.011083                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.278223                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.108803                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40044.227756                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40030.226060                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060                       # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40174.895895                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40071.723001                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.295378                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40083.971088                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40087.890625                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40085.666023                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40014.059754                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40086.597938                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.438330                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40007.203131                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40041.125242                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40024.789835                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40044.227756                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40009.618075                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40048.904347                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40174.895895                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40042.590716                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40031.475531                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40044.227756                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40009.618075                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40048.904347                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40174.895895                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40042.590716                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40031.475531                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
@@ -498,26 +528,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     7082876                       # DTB read hits
-system.cpu0.dtb.read_misses                      3736                       # DTB read misses
-system.cpu0.dtb.write_hits                    5665319                       # DTB write hits
+system.cpu0.dtb.read_hits                     7076084                       # DTB read hits
+system.cpu0.dtb.read_misses                      3743                       # DTB read misses
+system.cpu0.dtb.write_hits                    5660386                       # DTB write hits
 system.cpu0.dtb.write_misses                      804                       # DTB write misses
 system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    1790                       # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries                    1791                       # Number of entries that have been flushed from TLB
 system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
 system.cpu0.dtb.prefetch_faults                   141                       # Number of TLB faults due to prefetch
 system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu0.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 7086612                       # DTB read accesses
-system.cpu0.dtb.write_accesses                5666123                       # DTB write accesses
+system.cpu0.dtb.read_accesses                 7079827                       # DTB read accesses
+system.cpu0.dtb.write_accesses                5661190                       # DTB write accesses
 system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         12748195                       # DTB hits
-system.cpu0.dtb.misses                           4540                       # DTB misses
-system.cpu0.dtb.accesses                     12752735                       # DTB accesses
-system.cpu0.itb.inst_hits                    29606138                       # ITB inst hits
+system.cpu0.dtb.hits                         12736470                       # DTB hits
+system.cpu0.dtb.misses                           4547                       # DTB misses
+system.cpu0.dtb.accesses                     12741017                       # DTB accesses
+system.cpu0.itb.inst_hits                    29574655                       # ITB inst hits
 system.cpu0.itb.inst_misses                      2205                       # ITB inst misses
 system.cpu0.itb.read_hits                           0                       # DTB read hits
 system.cpu0.itb.read_misses                         0                       # DTB read misses
@@ -534,79 +564,79 @@ system.cpu0.itb.domain_faults                       0                       # Nu
 system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu0.itb.read_accesses                       0                       # DTB read accesses
 system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                29608343                       # ITB inst accesses
-system.cpu0.itb.hits                         29606138                       # DTB hits
+system.cpu0.itb.inst_accesses                29576860                       # ITB inst accesses
+system.cpu0.itb.hits                         29574655                       # DTB hits
 system.cpu0.itb.misses                           2205                       # DTB misses
-system.cpu0.itb.accesses                     29608343                       # DTB accesses
-system.cpu0.numCycles                      2345089954                       # number of cpu cycles simulated
+system.cpu0.itb.accesses                     29576860                       # DTB accesses
+system.cpu0.numCycles                      2414581254                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   28907917                       # Number of instructions committed
-system.cpu0.committedOps                     37265600                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses             33149705                       # Number of integer alu accesses
+system.cpu0.committedInsts                   28876799                       # Number of instructions committed
+system.cpu0.committedOps                     37228975                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses             33114839                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  3860                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1243107                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4358822                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    33149705                       # number of integer instructions
+system.cpu0.num_func_calls                    1241592                       # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts      4354316                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                    33114839                       # number of integer instructions
 system.cpu0.num_fp_insts                         3860                       # number of float instructions
-system.cpu0.num_int_register_reads          190344582                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          36275228                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          190147140                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes          36238708                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3022                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                840                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     13418689                       # number of memory refs
-system.cpu0.num_load_insts                    7420825                       # Number of load instructions
-system.cpu0.num_store_insts                   5997864                       # Number of store instructions
-system.cpu0.num_idle_cycles              2204555139.350120                       # Number of idle cycles
-system.cpu0.num_busy_cycles              140534814.649880                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.059927                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.940073                       # Percentage of idle cycles
+system.cpu0.num_mem_refs                     13404188                       # number of memory refs
+system.cpu0.num_load_insts                    7413537                       # Number of load instructions
+system.cpu0.num_store_insts                   5990651                       # Number of store instructions
+system.cpu0.num_idle_cycles              2267023722.330122                       # Number of idle cycles
+system.cpu0.num_busy_cycles              147557531.669878                       # Number of busy cycles
+system.cpu0.not_idle_fraction                0.061111                       # Percentage of non-idle cycles
+system.cpu0.idle_fraction                    0.938889                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   46687                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                408797                       # number of replacements
-system.cpu0.icache.tagsinuse               509.495989                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                29196812                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                409309                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 71.331957                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           75128897000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   509.495989                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.995109                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.995109                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst     29196812                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       29196812                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst     29196812                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        29196812                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst     29196812                       # number of overall hits
-system.cpu0.icache.overall_hits::total       29196812                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst       409309                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       409309                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst       409309                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        409309                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst       409309                       # number of overall misses
-system.cpu0.icache.overall_misses::total       409309                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6108172000                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total   6108172000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst   6108172000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total   6108172000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst   6108172000                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total   6108172000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst     29606121                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     29606121                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst     29606121                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     29606121                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst     29606121                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     29606121                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013825                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.013825                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013825                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.013825                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013825                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.013825                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14923.131424                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14923.131424                       # average overall miss latency
+system.cpu0.kern.inst.quiesce                   46683                       # number of quiesce instructions executed
+system.cpu0.icache.replacements                408135                       # number of replacements
+system.cpu0.icache.tagsinuse               509.469782                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                29165991                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                408647                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                 71.372091                       # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle           75845657000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst   509.469782                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.995058                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.995058                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     29165991                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total       29165991                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst     29165991                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total        29165991                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst     29165991                       # number of overall hits
+system.cpu0.icache.overall_hits::total       29165991                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst       408647                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total       408647                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst       408647                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total        408647                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst       408647                       # number of overall misses
+system.cpu0.icache.overall_misses::total       408647                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   6096214000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   6096214000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   6096214000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   6096214000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   6096214000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   6096214000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     29574638                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total     29574638                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst     29574638                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total     29574638                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     29574638                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total     29574638                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.013817                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.013817                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.013817                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.013817                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.013817                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.013817                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14918.044180                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14918.044180                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14918.044180                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14918.044180                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14918.044180                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14918.044180                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -615,120 +645,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       409309                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total       409309                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst       409309                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total       409309                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst       409309                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total       409309                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4879387500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total   4879387500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4879387500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total   4879387500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4879387500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total   4879387500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       408647                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       408647                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       408647                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       408647                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       408647                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       408647                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4869428500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4869428500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4869428500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4869428500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4869428500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4869428500                       # number of overall MSHR miss cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_latency::total    351814000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013825                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.013825                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013825                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.013825                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.013817                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.013817                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.013817                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.013817                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11915.977604                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11915.977604                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11915.977604                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11915.977604                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11915.977604                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11915.977604                       # average overall mshr miss latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                330813                       # number of replacements
-system.cpu0.dcache.tagsinuse               457.939353                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                12292528                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                331325                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 37.101118                       # Average number of references to valid blocks.
+system.cpu0.dcache.replacements                330734                       # number of replacements
+system.cpu0.dcache.tagsinuse               459.649704                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                12280871                       # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs                331246                       # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs                 37.074775                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle             664264000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   457.939353                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.894413                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.894413                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data      6612408                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        6612408                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data      5360091                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       5360091                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147992                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       147992                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149726                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       149726                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data     11972499                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        11972499                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data     11972499                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       11972499                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data       228125                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       228125                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data       141749                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       141749                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9279                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9279                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7492                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7492                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data       369874                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        369874                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data       369874                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       369874                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3443081500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total   3443081500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4917870500                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total   4917870500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100339500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total    100339500                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74628000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total     74628000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data   8360952000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total   8360952000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data   8360952000                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total   8360952000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data      6840533                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      6840533                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data      5501840                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      5501840                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157271                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       157271                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157218                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       157218                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data     12342373                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     12342373                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data     12342373                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     12342373                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033349                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.033349                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025764                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.025764                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059000                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059000                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047654                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047654                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029968                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.029968                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029968                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.029968                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9961.025093                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9961.025093                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441                       # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data   459.649704                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.897753                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.897753                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6605687                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total        6605687                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5355220                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total       5355220                       # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       147939                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total       147939                       # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       149683                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total       149683                       # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data     11960907                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total        11960907                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data     11960907                       # number of overall hits
+system.cpu0.dcache.overall_hits::total       11960907                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data       228053                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total       228053                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       141722                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total       141722                       # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9325                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total         9325                       # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7497                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total         7497                       # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data       369775                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total        369775                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data       369775                       # number of overall misses
+system.cpu0.dcache.overall_misses::total       369775                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3443053000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3443053000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   4918745500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   4918745500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100903000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    100903000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     74598000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     74598000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   8361798500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   8361798500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   8361798500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   8361798500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      6833740                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total      6833740                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5496942                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total      5496942                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       157264                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total       157264                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       157180                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total       157180                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data     12330682                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total     12330682                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12330682                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total     12330682                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.033372                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.033372                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.025782                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.025782                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.059295                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.059295                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.047697                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total     0.047697                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.029988                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.029988                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.029988                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.029988                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15097.600119                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15097.600119                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34707.000325                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 34707.000325                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10820.697051                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10820.697051                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9950.380152                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total  9950.380152                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22613.206680                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 22613.206680                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22613.206680                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 22613.206680                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -737,62 +767,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks       306322                       # number of writebacks
-system.cpu0.dcache.writebacks::total           306322                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228125                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total       228125                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141749                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total       141749                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9279                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9279                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7485                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total         7485                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data       369874                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total       369874                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data       369874                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total       369874                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2758091164                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2758091164                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4492431566                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4492431566                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72483506                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72483506                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     52154019                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     52154019                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7250522730                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total   7250522730                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7250522730                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total   7250522730                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  10425846000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  10425846000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data    819721500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total    819721500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  11245567500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total  11245567500                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033349                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033349                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025764                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025764                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059000                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047609                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047609                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029968                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.029968                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029968                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.029968                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7811.564393                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7811.564393                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6967.804810                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6967.804810                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887                       # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks       306480                       # number of writebacks
+system.cpu0.dcache.writebacks::total           306480                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       228053                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       228053                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       141722                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       141722                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9325                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9325                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7489                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7489                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       369775                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       369775                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       369775                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       369775                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2758299641                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2758299641                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   4493384071                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   4493384071                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     72902006                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     72902006                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     52119015                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     52119015                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1001                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1001                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   7251683712                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   7251683712                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   7251683712                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   7251683712                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data  13559859000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total  13559859000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1253198500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1253198500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  14813057500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  14813057500                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.033372                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.033372                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.025782                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.025782                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.059295                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.059295                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.047646                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.047646                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.029988                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.029988                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.029988                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.029988                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12094.993887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12094.993887                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31705.621364                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31705.621364                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7817.909491                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total  7817.909491                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6959.409133                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total  6959.409133                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19611.070819                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19611.070819                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19611.070819                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19611.070819                       # average overall mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
@@ -802,26 +836,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     8314117                       # DTB read hits
-system.cpu1.dtb.read_misses                      3669                       # DTB read misses
-system.cpu1.dtb.write_hits                    5830380                       # DTB write hits
-system.cpu1.dtb.write_misses                     1436                       # DTB write misses
+system.cpu1.dtb.read_hits                     8318170                       # DTB read hits
+system.cpu1.dtb.read_misses                      3663                       # DTB read misses
+system.cpu1.dtb.write_hits                    5832653                       # DTB write hits
+system.cpu1.dtb.write_misses                     1435                       # DTB write misses
 system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
 system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
 system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1967                       # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries                    1968                       # Number of entries that have been flushed from TLB
 system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                   140                       # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults                   142                       # Number of TLB faults due to prefetch
 system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
 system.cpu1.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 8317786                       # DTB read accesses
-system.cpu1.dtb.write_accesses                5831816                       # DTB write accesses
+system.cpu1.dtb.read_accesses                 8321833                       # DTB read accesses
+system.cpu1.dtb.write_accesses                5834088                       # DTB write accesses
 system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         14144497                       # DTB hits
-system.cpu1.dtb.misses                           5105                       # DTB misses
-system.cpu1.dtb.accesses                     14149602                       # DTB accesses
-system.cpu1.itb.inst_hits                    33196626                       # ITB inst hits
+system.cpu1.dtb.hits                         14150823                       # DTB hits
+system.cpu1.dtb.misses                           5098                       # DTB misses
+system.cpu1.dtb.accesses                     14155921                       # DTB accesses
+system.cpu1.itb.inst_hits                    33211066                       # ITB inst hits
 system.cpu1.itb.inst_misses                      2171                       # ITB inst misses
 system.cpu1.itb.read_hits                           0                       # DTB read hits
 system.cpu1.itb.read_misses                         0                       # DTB read misses
@@ -838,79 +872,79 @@ system.cpu1.itb.domain_faults                       0                       # Nu
 system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
 system.cpu1.itb.read_accesses                       0                       # DTB read accesses
 system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                33198797                       # ITB inst accesses
-system.cpu1.itb.hits                         33196626                       # DTB hits
+system.cpu1.itb.inst_accesses                33213237                       # ITB inst accesses
+system.cpu1.itb.hits                         33211066                       # DTB hits
 system.cpu1.itb.misses                           2171                       # DTB misses
-system.cpu1.itb.accesses                     33198797                       # DTB accesses
-system.cpu1.numCycles                      2343593518                       # number of cpu cycles simulated
+system.cpu1.itb.accesses                     33213237                       # DTB accesses
+system.cpu1.numCycles                      2413083038                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.committedInsts                   32586009                       # Number of instructions committed
-system.cpu1.committedOps                     41102854                       # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses             37326288                       # Number of integer alu accesses
+system.cpu1.committedInsts                   32600335                       # Number of instructions committed
+system.cpu1.committedOps                     41120048                       # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses             37342001                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  6793                       # Number of float alu accesses
-system.cpu1.num_func_calls                     962171                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3714570                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    37326288                       # number of integer instructions
+system.cpu1.num_func_calls                     963082                       # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts      3716244                       # number of instructions that are conditional controls
+system.cpu1.num_int_insts                    37342001                       # number of integer instructions
 system.cpu1.num_fp_insts                         6793                       # number of float instructions
-system.cpu1.num_int_register_reads          213739964                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          39466250                       # number of times the integer registers were written
+system.cpu1.num_int_register_reads          213831809                       # number of times the integer registers were read
+system.cpu1.num_int_register_writes          39482622                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                4535                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes               2260                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     14682267                       # number of memory refs
-system.cpu1.num_load_insts                    8636040                       # Number of load instructions
-system.cpu1.num_store_insts                   6046227                       # Number of store instructions
-system.cpu1.num_idle_cycles              1858750530.714142                       # Number of idle cycles
-system.cpu1.num_busy_cycles              484842987.285858                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.206880                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.793120                       # Percentage of idle cycles
+system.cpu1.num_mem_refs                     14689113                       # number of memory refs
+system.cpu1.num_load_insts                    8640454                       # Number of load instructions
+system.cpu1.num_store_insts                   6048659                       # Number of store instructions
+system.cpu1.num_idle_cycles              1863361909.381196                       # Number of idle cycles
+system.cpu1.num_busy_cycles              549721128.618804                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.227809                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.772191                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   43921                       # number of quiesce instructions executed
-system.cpu1.icache.replacements                454393                       # number of replacements
-system.cpu1.icache.tagsinuse               478.384673                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                32741717                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                454905                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 71.974845                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           92994898000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst   478.384673                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.934345                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.934345                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst     32741717                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       32741717                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst     32741717                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        32741717                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst     32741717                       # number of overall hits
-system.cpu1.icache.overall_hits::total       32741717                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst       454905                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       454905                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst       454905                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        454905                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst       454905                       # number of overall misses
-system.cpu1.icache.overall_misses::total       454905                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6718353500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total   6718353500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst   6718353500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total   6718353500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst   6718353500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total   6718353500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst     33196622                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     33196622                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst     33196622                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     33196622                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst     33196622                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     33196622                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013703                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.013703                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013703                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.013703                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013703                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.013703                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 14768.695662                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 14768.695662                       # average overall miss latency
+system.cpu1.kern.inst.quiesce                   43948                       # number of quiesce instructions executed
+system.cpu1.icache.replacements                455071                       # number of replacements
+system.cpu1.icache.tagsinuse               479.019014                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                32755479                       # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs                455583                       # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs                 71.897940                       # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle           94151388000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst   479.019014                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.935584                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.935584                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     32755479                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total       32755479                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst     32755479                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total        32755479                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst     32755479                       # number of overall hits
+system.cpu1.icache.overall_hits::total       32755479                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst       455583                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total       455583                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst       455583                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total        455583                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst       455583                       # number of overall misses
+system.cpu1.icache.overall_misses::total       455583                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   6728267000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   6728267000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   6728267000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   6728267000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   6728267000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   6728267000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     33211062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total     33211062                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst     33211062                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total     33211062                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     33211062                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total     33211062                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.013718                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.013718                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.013718                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.013718                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.013718                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.013718                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.476875                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.476875                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.476875                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 14768.476875                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.476875                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 14768.476875                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -919,120 +953,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       454905                       # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total       454905                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst       454905                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total       454905                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst       454905                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total       454905                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5352734000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total   5352734000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5352734000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total   5352734000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5352734000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total   5352734000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       455583                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       455583                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       455583                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       455583                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       455583                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       455583                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5360614000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5360614000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5360614000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5360614000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5360614000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5360614000                       # number of overall MSHR miss cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013703                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.013703                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013703                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.013703                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.707334                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.707334                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.707334                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.707334                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.013718                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.013718                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.013718                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.013718                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11766.492604                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11766.492604                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11766.492604                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11766.492604                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11766.492604                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11766.492604                       # average overall mshr miss latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                292476                       # number of replacements
-system.cpu1.dcache.tagsinuse               472.237187                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                11966907                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                292816                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 40.868351                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           84138671000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data   472.237187                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.922338                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.922338                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data      6949314                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        6949314                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data      4829723                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       4829723                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81817                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        81817                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82772                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        82772                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data     11779037                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total        11779037                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data     11779037                       # number of overall hits
-system.cpu1.dcache.overall_hits::total       11779037                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data       170766                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       170766                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data       150259                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       150259                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11112                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        11112                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10077                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10077                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data       321025                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        321025                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data       321025                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       321025                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2375372000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total   2375372000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5143695000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total   5143695000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106521500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total    106521500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     88394000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total     88394000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data   7519067000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total   7519067000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data   7519067000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total   7519067000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data      7120080                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      7120080                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data      4979982                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      4979982                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        92929                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        92929                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92849                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        92849                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data     12100062                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     12100062                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data     12100062                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     12100062                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.023984                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.023984                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030173                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.030173                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119575                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119575                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108531                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108531                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026531                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.026531                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026531                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.026531                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13910.099200                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13910.099200                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34232.192414                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 34232.192414                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9586.168107                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9586.168107                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8771.856703                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8771.856703                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587                       # average overall miss latency
+system.cpu1.dcache.replacements                292605                       # number of replacements
+system.cpu1.dcache.tagsinuse               473.034253                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                11973075                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                292945                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs                 40.871409                       # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle           85130110000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data   473.034253                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.923895                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.923895                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6952995                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total        6952995                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      4831955                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total       4831955                       # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        81928                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total        81928                       # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        82891                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total        82891                       # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data     11784950                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total        11784950                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data     11784950                       # number of overall hits
+system.cpu1.dcache.overall_hits::total       11784950                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data       170988                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total       170988                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       150171                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total       150171                       # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11121                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total        11121                       # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        10078                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total        10078                       # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data       321159                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total        321159                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data       321159                       # number of overall misses
+system.cpu1.dcache.overall_misses::total       321159                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2374183000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2374183000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5137653000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   5137653000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    106350500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    106350500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     87844000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     87844000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   7511836000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   7511836000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   7511836000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   7511836000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7123983                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total      7123983                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4982126                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total      4982126                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        93049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total        93049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        92969                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total        92969                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data     12106109                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total     12106109                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     12106109                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total     12106109                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.024002                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.024002                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.030142                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.030142                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.119518                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.119518                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.108402                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total     0.108402                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.026529                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.026529                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.026529                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.026529                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13885.085503                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 13885.085503                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34212.018299                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 34212.018299                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data  9563.033900                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total  9563.033900                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8716.411987                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total  8716.411987                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23389.772667                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 23389.772667                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23389.772667                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 23389.772667                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1041,62 +1075,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks       266164                       # number of writebacks
-system.cpu1.dcache.writebacks::total           266164                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170766                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total       170766                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150259                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total       150259                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11112                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11112                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10067                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total        10067                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data       321025                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total       321025                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data       321025                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total       321025                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1862452631                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1862452631                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4692688176                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4692688176                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     73165002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     73165002                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     58182011                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     58182011                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6555140807                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total   6555140807                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6555140807                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total   6555140807                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39709759000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39709759000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.023984                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.023984                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030173                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030173                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119575                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119575                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108423                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108423                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026531                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.026531                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026531                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.026531                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6584.323434                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6584.323434                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5779.478593                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5779.478593                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102                       # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks       266100                       # number of writebacks
+system.cpu1.dcache.writebacks::total           266100                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       170988                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       170988                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       150171                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       150171                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11121                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11121                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        10070                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        10070                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       321159                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       321159                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       321159                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       321159                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   1860610613                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   1860610613                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   4686894192                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   4686894192                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     72963005                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     72963005                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     57623011                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     57623011                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   6547504805                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   6547504805                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   6547504805                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   6547504805                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168686172000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168686172000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  39932194000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  39932194000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 208618366000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 208618366000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.024002                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.024002                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.030142                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.030142                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.119518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.119518                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.108316                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.108316                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.026529                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.026529                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.026529                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.026529                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10881.527435                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10881.527435                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31210.381445                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31210.381445                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  6560.831310                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total  6560.831310                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5722.245382                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total  5722.245382                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20387.112941                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20387.112941                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20387.112941                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20387.112941                       # average overall mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
@@ -1118,10 +1152,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 550791407487                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 574301885796                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 574301885796                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 574301885796                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 574301885796                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index 724af20422352b92533b2ed368f73095c5299727..9441865716141061475bdc963ece01d68e4f442c 100644 (file)
@@ -1,54 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  2.594328                       # Number of seconds simulated
-sim_ticks                                2594327510000                       # Number of ticks simulated
-final_tick                               2594327510000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  2.629150                       # Number of seconds simulated
+sim_ticks                                2629149747000                       # Number of ticks simulated
+final_tick                               2629149747000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 600896                       # Simulator instruction rate (inst/s)
-host_op_rate                                   764626                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            25897323777                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 390576                       # Number of bytes of host memory used
-host_seconds                                   100.18                       # Real time elapsed on the host
-sim_insts                                    60196191                       # Number of instructions simulated
-sim_ops                                      76598245                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd    122683392                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            704288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           9067216                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            132455344                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       704288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          704288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      3695616                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           6711688                       # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd      15335424                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              17207                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             141709                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total              15494347                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks           57744                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               811762                       # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd        47289092                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker            123                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               271472                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              3495016                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                51055753                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          271472                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             271472                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1424499                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data             1162564                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                2587063                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1424499                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd       47289092                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker           123                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              271472                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4657580                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               53642816                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 820445                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1044003                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            35827378651                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 386004                       # Number of bytes of host memory used
+host_seconds                                    73.38                       # Real time elapsed on the host
+sim_insts                                    60207390                       # Number of instructions simulated
+sim_ops                                      76612873                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
 system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
@@ -61,141 +23,179 @@ system.realview.nvmem.bw_inst_read::cpu.inst            8
 system.realview.nvmem.bw_inst_read::total            8                       # Instruction read bandwidth from this memory (bytes/s)
 system.realview.nvmem.bw_total::cpu.inst            8                       # Total bandwidth to/from this memory (bytes/s)
 system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         62159                       # number of replacements
-system.l2c.tagsinuse                     51417.185894                       # Cycle average of tags in use
-system.l2c.total_refs                         1682923                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        127542                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         13.195049                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                  2544924960000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        38023.288706                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker        3.884784                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.000558                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           7004.395748                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data           6385.616098                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.580189                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker       0.000059                       # Average percentage of cache occupancy
+system.physmem.bytes_read::realview.clcd    124256256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker          256                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst            705696                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9115408                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            134077744                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       705696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          705696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      3736256                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data        3016072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           6752328                       # Number of bytes written to this memory
+system.physmem.num_reads::realview.clcd      15532032                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker            4                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker            2                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              17229                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             142462                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total              15691729                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks           58379                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data            754018                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               812397                       # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd        47261004                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker             97                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker             49                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               268412                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3467055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                50996618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          268412                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             268412                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1421089                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data             1147166                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                2568255                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1421089                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd       47261004                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker            97                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker            49                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              268412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4614222                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               53564873                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         62933                       # number of replacements
+system.l2c.tagsinuse                     51862.510726                       # Cycle average of tags in use
+system.l2c.total_refs                         1683379                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        128318                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         13.118806                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                  2576532162000                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks        38450.903251                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        2.914018                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.000670                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           7005.048584                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6403.644203                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.586714                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000044                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.106879                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.097437                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.784564                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          8754                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          3544                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              843519                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data              370124                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1225941                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks          596001                       # number of Writeback hits
-system.l2c.Writeback_hits::total               596001                       # number of Writeback hits
+system.l2c.occ_percent::cpu.inst             0.106889                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.097712                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.791359                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          8836                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3549                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              844195                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              370308                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                1226888                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks          596416                       # number of Writeback hits
+system.l2c.Writeback_hits::total               596416                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            114391                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               114391                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           8754                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           3544                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               843519                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data               484515                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1340332                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          8754                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          3544                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              843519                       # number of overall hits
-system.l2c.overall_hits::cpu.data              484515                       # number of overall hits
-system.l2c.overall_hits::total                1340332                       # number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker            5                       # number of ReadReq misses
+system.l2c.ReadExReq_hits::cpu.data            113846                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               113846                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           8836                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3549                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               844195                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               484154                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 1340734                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          8836                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3549                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              844195                       # number of overall hits
+system.l2c.overall_hits::cpu.data              484154                       # number of overall hits
+system.l2c.overall_hits::total                1340734                       # number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker            4                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu.itb.walker            2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             10591                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             10247                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                20845                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           2879                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              2879                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          133059                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             133059                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker            5                       # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu.inst             10613                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             10261                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                20880                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2845                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              2845                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          133824                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             133824                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker            4                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu.itb.walker            2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              10591                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             143306                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153904                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker            5                       # number of overall misses
+system.l2c.demand_misses::cpu.inst              10613                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             144085                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                154704                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker            4                       # number of overall misses
 system.l2c.overall_misses::cpu.itb.walker            2                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             10591                       # number of overall misses
-system.l2c.overall_misses::cpu.data            143306                       # number of overall misses
-system.l2c.overall_misses::total               153904                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker       260500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu.inst             10613                       # number of overall misses
+system.l2c.overall_misses::cpu.data            144085                       # number of overall misses
+system.l2c.overall_misses::total               154704                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker       208000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu.itb.walker       104000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    552260500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data    533540500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     1086165500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    553137500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    534185000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1087634500                       # number of ReadReq miss cycles
 system.l2c.UpgradeReq_miss_latency::cpu.data      1040000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_latency::total      1040000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   6923957000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   6923957000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker       260500                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6961477000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6961477000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker       208000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker       104000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    552260500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7457497500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      8010122500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker       260500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu.inst    553137500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7495662000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8049111500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker       208000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker       104000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    552260500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7457497500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     8010122500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker         8759                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         3546                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          854110                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data          380371                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1246786                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks       596001                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           596001                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         2905                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            2905                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        247450                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           247450                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         8759                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         3546                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           854110                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data           627821                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1494236                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         8759                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         3546                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          854110                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data          627821                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1494236                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000564                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.012400                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.026939                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.016719                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.991050                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.991050                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.537721                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.537721                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.000564                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.012400                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.228259                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.102998                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker     0.000571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.000564                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.012400                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.228259                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.102998                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52100                       # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu.inst    553137500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7495662000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8049111500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         8840                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3551                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          854808                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          380569                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            1247768                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       596416                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total           596416                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2871                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            2871                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        247670                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           247670                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         8840                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3551                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           854808                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           628239                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             1495438                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         8840                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3551                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          854808                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          628239                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            1495438                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000452                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.000563                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.012416                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.026962                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.016734                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.990944                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.990944                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.540332                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.540332                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000452                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.000563                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.012416                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.229347                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.103451                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000452                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.000563                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.012416                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.229347                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.103451                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52144.320650                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52067.971113                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52106.764212                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data   361.236540                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total   361.236540                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52036.743099                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52036.743099                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52118.863658                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52059.740766                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52089.774904                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   365.553603                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total   365.553603                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52019.645206                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52019.645206                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52046.226869                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52100                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52118.863658                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52022.500607                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52029.110430                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52144.320650                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52038.976037                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52046.226869                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52118.863658                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52022.500607                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52029.110430                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -204,92 +204,92 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               57744                       # number of writebacks
-system.l2c.writebacks::total                    57744                       # number of writebacks
-system.l2c.ReadReq_mshr_misses::cpu.dtb.walker            5                       # number of ReadReq MSHR misses
+system.l2c.writebacks::writebacks               58379                       # number of writebacks
+system.l2c.writebacks::total                    58379                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker            4                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            2                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        10591                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        10247                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           20845                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         2879                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         2879                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       133059                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        133059                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu.dtb.walker            5                       # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        10613                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        10261                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           20880                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2845                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2845                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       133824                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        133824                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker            4                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            2                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         10591                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        143306                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153904                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu.dtb.walker            5                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         10613                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        144085                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           154704                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker            4                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            2                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        10591                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       143306                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153904                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       200000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu.inst        10613                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       144085                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          154704                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       160000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker        80000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425162000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data    410573000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total    836015000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115365000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total    115365000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5327229000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   5327229000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       200000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    425775500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    411049000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total    837064500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    114083000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    114083000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5355569000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5355569000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       160000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker        80000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    425162000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5737802000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6163244000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       200000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    425775500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5766618000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6192633500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       160000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker        80000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    425162000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5737802000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6163244000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    425775500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5766618000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6192633500                       # number of overall MSHR miss cycles
 system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst    264840000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131435179000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 131700019000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31197392500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total  31197392500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 166753837500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167018677500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31852864000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31852864000                       # number of WriteReq MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_latency::cpu.inst    264840000                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data 162632571500                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 162897411500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026939                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.016719                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991050                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.991050                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.537721                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.537721                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.102998                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000571                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000564                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.012400                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.228259                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.102998                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 198606701500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 198871541500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000452                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.012416                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.026962                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.016734                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.990944                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.990944                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.540332                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.540332                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000452                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.012416                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.229347                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.103451                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000452                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.000563                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.012416                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.229347                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.103451                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.298313                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40059.350940                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40089.295977                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.472759                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.472759                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40019.495756                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40019.495756                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40118.298313                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40022.334039                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40028.916512                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40046.028693                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40118.298313                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40022.334039                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40028.916512                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
@@ -307,26 +307,26 @@ system.cf0.dma_write_bytes                          0                       # Nu
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     14995137                       # DTB read hits
-system.cpu.dtb.read_misses                       7357                       # DTB read misses
-system.cpu.dtb.write_hits                    11229787                       # DTB write hits
-system.cpu.dtb.write_misses                      2205                       # DTB write misses
+system.cpu.dtb.read_hits                     14998169                       # DTB read hits
+system.cpu.dtb.read_misses                       7372                       # DTB read misses
+system.cpu.dtb.write_hits                    11231565                       # DTB write hits
+system.cpu.dtb.write_misses                      2270                       # DTB write misses
 system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
 system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries                     3485                       # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries                     3524                       # Number of entries that have been flushed from TLB
 system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults                    182                       # Number of TLB faults due to prefetch
+system.cpu.dtb.prefetch_faults                    231                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 15002494                       # DTB read accesses
-system.cpu.dtb.write_accesses                11231992                       # DTB write accesses
+system.cpu.dtb.read_accesses                 15005541                       # DTB read accesses
+system.cpu.dtb.write_accesses                11233835                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          26224924                       # DTB hits
-system.cpu.dtb.misses                            9562                       # DTB misses
-system.cpu.dtb.accesses                      26234486                       # DTB accesses
-system.cpu.itb.inst_hits                     61490084                       # ITB inst hits
+system.cpu.dtb.hits                          26229734                       # DTB hits
+system.cpu.dtb.misses                            9642                       # DTB misses
+system.cpu.dtb.accesses                      26239376                       # DTB accesses
+system.cpu.itb.inst_hits                     61501359                       # ITB inst hits
 system.cpu.itb.inst_misses                       4471                       # ITB inst misses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
@@ -343,79 +343,79 @@ system.cpu.itb.domain_faults                        0                       # Nu
 system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
 system.cpu.itb.read_accesses                        0                       # DTB read accesses
 system.cpu.itb.write_accesses                       0                       # DTB write accesses
-system.cpu.itb.inst_accesses                 61494555                       # ITB inst accesses
-system.cpu.itb.hits                          61490084                       # DTB hits
+system.cpu.itb.inst_accesses                 61505830                       # ITB inst accesses
+system.cpu.itb.hits                          61501359                       # DTB hits
 system.cpu.itb.misses                            4471                       # DTB misses
-system.cpu.itb.accesses                      61494555                       # DTB accesses
-system.cpu.numCycles                       5188655020                       # number of cpu cycles simulated
+system.cpu.itb.accesses                      61505830                       # DTB accesses
+system.cpu.numCycles                       5258299494                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                    60196191                       # Number of instructions committed
-system.cpu.committedOps                      76598245                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses              68865648                       # Number of integer alu accesses
+system.cpu.committedInsts                    60207390                       # Number of instructions committed
+system.cpu.committedOps                      76612873                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses              68878830                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
-system.cpu.num_func_calls                     2139540                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      7910583                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                     68865648                       # number of integer instructions
+system.cpu.num_func_calls                     2140176                       # number of times a function call or return occured
+system.cpu.num_conditional_control_insts      7911775                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                     68878830                       # number of integer instructions
 system.cpu.num_fp_insts                         10269                       # number of float instructions
-system.cpu.num_int_register_reads           394743471                       # number of times the integer registers were read
-system.cpu.num_int_register_writes           74177139                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           394820534                       # number of times the integer registers were read
+system.cpu.num_int_register_writes           74191435                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      27392126                       # number of memory refs
-system.cpu.num_load_insts                    15659006                       # Number of load instructions
-system.cpu.num_store_insts                   11733120                       # Number of store instructions
-system.cpu.num_idle_cycles               4570211154.554238                       # Number of idle cycles
-system.cpu.num_busy_cycles               618443865.445762                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.119192                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.880808                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      27397151                       # number of memory refs
+system.cpu.num_load_insts                    15662227                       # Number of load instructions
+system.cpu.num_store_insts                   11734924                       # Number of store instructions
+system.cpu.num_idle_cycles               4567780450.602262                       # Number of idle cycles
+system.cpu.num_busy_cycles               690519043.397737                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.131320                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.868680                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.quiesce                    82989                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 855220                       # number of replacements
-system.cpu.icache.tagsinuse                510.929118                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 60634352                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 855732                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  70.856707                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle            18856022000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.929118                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.997908                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.997908                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     60634352                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        60634352                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      60634352                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         60634352                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     60634352                       # number of overall hits
-system.cpu.icache.overall_hits::total        60634352                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       855732                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        855732                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       855732                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         855732                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       855732                       # number of overall misses
-system.cpu.icache.overall_misses::total        855732                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  12556184500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  12556184500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  12556184500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  12556184500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  12556184500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  12556184500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     61490084                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     61490084                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     61490084                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     61490084                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     61490084                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     61490084                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013917                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.013917                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.013917                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.013917                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14673.033730                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14673.033730                       # average overall miss latency
+system.cpu.kern.inst.quiesce                    83013                       # number of quiesce instructions executed
+system.cpu.icache.replacements                 855930                       # number of replacements
+system.cpu.icache.tagsinuse                510.898307                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 60644917                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 856442                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                  70.810302                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle            19819985000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.898307                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.997848                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.997848                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     60644917                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        60644917                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      60644917                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         60644917                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     60644917                       # number of overall hits
+system.cpu.icache.overall_hits::total        60644917                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       856442                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        856442                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       856442                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         856442                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       856442                       # number of overall misses
+system.cpu.icache.overall_misses::total        856442                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12566277500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12566277500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12566277500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12566277500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12566277500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12566277500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     61501359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     61501359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     61501359                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     61501359                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     61501359                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     61501359                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.013926                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.013926                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.013926                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.013926                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.013926                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.013926                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14672.654424                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14672.654424                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14672.654424                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14672.654424                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14672.654424                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14672.654424                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -424,112 +424,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       855732                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       855732                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       855732                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       855732                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       855732                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       855732                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9987081500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9987081500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9987081500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9987081500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9987081500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9987081500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       856442                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       856442                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       856442                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       856442                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       856442                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       856442                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9995044500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9995044500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9995044500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9995044500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9995044500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9995044500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013917                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013917                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.013926                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.013926                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.013926                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.013926                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.013926                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.013926                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.427770                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.427770                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.427770                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.427770                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.427770                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.427770                       # average overall mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 627309                       # number of replacements
-system.cpu.dcache.tagsinuse                511.875626                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 23653426                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 627821                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  37.675430                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 627727                       # number of replacements
+system.cpu.dcache.tagsinuse                511.877273                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 23657788                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 628239                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  37.657306                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              661351000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.875626                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     13194612                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        13194612                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      9972158                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        9972158                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data       236094                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total       236094                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data       247657                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total       247657                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      23166770                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         23166770                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     23166770                       # number of overall hits
-system.cpu.dcache.overall_hits::total        23166770                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       368807                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        368807                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       250355                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       250355                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data        11564                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total        11564                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data       619162                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         619162                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       619162                       # number of overall misses
-system.cpu.dcache.overall_misses::total        619162                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   5738700500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   5738700500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9229453000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9229453000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    171857500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total    171857500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  14968153500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  14968153500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  14968153500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  14968153500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13563419                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13563419                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     10222513                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     10222513                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247658                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total       247658                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data       247657                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total       247657                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     23785932                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     23785932                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     23785932                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     23785932                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027191                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.027191                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024491                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.024491                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046693                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046693                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.026031                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.026031                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.026031                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.026031                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 24174.858115                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 24174.858115                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data     511.877273                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999760                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999760                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     13196825                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        13196825                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9973191                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        9973191                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236701                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total       236701                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       248200                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total       248200                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      23170016                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         23170016                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     23170016                       # number of overall hits
+system.cpu.dcache.overall_hits::total        23170016                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       369069                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        369069                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250541                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       250541                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11500                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total        11500                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data       619610                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         619610                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       619610                       # number of overall misses
+system.cpu.dcache.overall_misses::total        619610                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5742174000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5742174000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9260838000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9260838000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    170995500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    170995500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15003012000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15003012000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15003012000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15003012000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13565894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13565894                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10223732                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     10223732                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       248201                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total       248201                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       248200                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total       248200                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     23789626                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     23789626                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23789626                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     23789626                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027206                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.027206                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024506                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.024506                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total     0.046333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026045                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.026045                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026045                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.026045                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15558.537834                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15558.537834                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36963.363282                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 36963.363282                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14869.173913                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14869.173913                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24213.637611                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 24213.637611                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24213.637611                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 24213.637611                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -538,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       596001                       # number of writebacks
-system.cpu.dcache.writebacks::total            596001                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368807                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       368807                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250355                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       250355                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11564                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total        11564                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       619162                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       619162                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       619162                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       619162                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4631124500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   4631124500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8478310000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8478310000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    137164000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    137164000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13109434500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  13109434500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13109434500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  13109434500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40357680500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40357680500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027191                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027191                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024491                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024491                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046693                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046693                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026031                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026031                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks       596416                       # number of writebacks
+system.cpu.dcache.writebacks::total            596416                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       369069                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       369069                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250541                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250541                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11500                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11500                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       619610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       619610                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       619610                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       619610                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4633803000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4633803000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8509109000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8509109000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    136482000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    136482000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13142912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13142912000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13142912000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13142912000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182150932500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182150932500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  41013343500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  41013343500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 223164276000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 223164276000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027206                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.027206                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024506                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.024506                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.046333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026045                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026045                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026045                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026045                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12555.383953                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12555.383953                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33962.940197                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33962.940197                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        11868                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total        11868                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21211.587934                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 21211.587934                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21211.587934                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 21211.587934                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -607,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs          nan                       #
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750                       # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1342178832750                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1358668189629                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1358668189629                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1358668189629                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1358668189629                       # number of overall MSHR uncacheable cycles
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
index a4ae62a223b87a25a21ca4a38e5416b6533102d5..2aa8a86ab0ace259433373448ed9fdb04e270ea4 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  5.191766                       # Number of seconds simulated
-sim_ticks                                5191766314000                       # Number of ticks simulated
-final_tick                               5191766314000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  5.196043                       # Number of seconds simulated
+sim_ticks                                5196043137000                       # Number of ticks simulated
+final_tick                               5196043137000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 787684                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1511929                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            29598304712                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 358992                       # Number of bytes of host memory used
-host_seconds                                   175.41                       # Real time elapsed on the host
-sim_insts                                   138165780                       # Number of instructions simulated
-sim_ops                                     265203824                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide      2891072                       # Number of bytes read from this memory
+host_inst_rate                                1241473                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2393258                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            50303585789                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354304                       # Number of bytes of host memory used
+host_seconds                                   103.29                       # Real time elapsed on the host
+sim_insts                                   128236332                       # Number of instructions simulated
+sim_ops                                     247208442                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide      2881344                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst            821248                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           8939328                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             12651968                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       821248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          821248                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks      8080768                       # Number of bytes written to this memory
-system.physmem.bytes_written::total           8080768                       # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide        45173                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst            824320                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           8950528                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             12656512                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       824320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          824320                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks      8081152                       # Number of bytes written to this memory
+system.physmem.bytes_written::total           8081152                       # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide        45021                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst              12832                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             139677                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                197687                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          126262                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               126262                       # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide       556857                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst              12880                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             139852                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                197758                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          126268                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               126268                       # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide       554527                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             62                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst               158183                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1721828                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2436929                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          158183                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             158183                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks           1556458                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                1556458                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks           1556458                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide       556857                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               158644                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1722566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2435798                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          158644                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             158644                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks           1555251                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                1555251                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks           1555251                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide       554527                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            62                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              158183                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1721828                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3993388                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                         86221                       # number of replacements
-system.l2c.tagsinuse                     64766.656127                       # Cycle average of tags in use
-system.l2c.total_refs                         3490237                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        150947                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                         23.122268                       # Average number of references to valid blocks.
+system.physmem.bw_total::cpu.inst              158644                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1722566                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3991049                       # Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements                         86291                       # number of replacements
+system.l2c.tagsinuse                     64759.780052                       # Cycle average of tags in use
+system.l2c.total_refs                         3494113                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                        150981                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                         23.142733                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks        50170.355166                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker        0.141198                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst           3484.481205                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data          11111.678558                       # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks           0.765539                       # Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks        50071.847750                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.141309                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3396.359734                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data          11291.431260                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.764036                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu.itb.walker       0.000002                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst             0.053169                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data             0.169551                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.988261                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker          6306                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker          2757                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst              777565                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data             1279351                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                2065979                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks         1541329                       # number of Writeback hits
-system.l2c.Writeback_hits::total              1541329                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data              319                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                 319                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data            200451                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               200451                       # number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker           6306                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker           2757                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst               777565                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data              1479802                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 2266430                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker          6306                       # number of overall hits
-system.l2c.overall_hits::cpu.itb.walker          2757                       # number of overall hits
-system.l2c.overall_hits::cpu.inst              777565                       # number of overall hits
-system.l2c.overall_hits::cpu.data             1479802                       # number of overall hits
-system.l2c.overall_hits::total                2266430                       # number of overall hits
+system.l2c.occ_percent::cpu.inst             0.051824                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.172294                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.988156                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          6458                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          2811                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              779608                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1280721                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                2069598                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks         1543757                       # number of Writeback hits
+system.l2c.Writeback_hits::total              1543757                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data              305                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                 305                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data            200867                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total               200867                       # number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker           6458                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           2811                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               779608                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1481588                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                 2270465                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker          6458                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          2811                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              779608                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1481588                       # number of overall hits
+system.l2c.overall_hits::total                2270465                       # number of overall hits
 system.l2c.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst             12833                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data             28373                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                41211                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data           1346                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              1346                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data          112235                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             112235                       # number of ReadExReq misses
+system.l2c.ReadReq_misses::cpu.inst             12881                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             28319                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                41205                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1371                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total              1371                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data          112462                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total             112462                       # number of ReadExReq misses
 system.l2c.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst              12833                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data             140608                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                153446                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              12881                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             140781                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                153667                       # number of demand (read+write) misses
 system.l2c.overall_misses::cpu.itb.walker            5                       # number of overall misses
-system.l2c.overall_misses::cpu.inst             12833                       # number of overall misses
-system.l2c.overall_misses::cpu.data            140608                       # number of overall misses
-system.l2c.overall_misses::total               153446                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             12881                       # number of overall misses
+system.l2c.overall_misses::cpu.data            140781                       # number of overall misses
+system.l2c.overall_misses::total               153667                       # number of overall misses
 system.l2c.ReadReq_miss_latency::cpu.itb.walker       260000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst    667948500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data   1489806000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total     2158014500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data     32975000                       # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total     32975000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data   5839097000                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total   5839097000                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    670242000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1486972500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2157474500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     34071000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     34071000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   5850445000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   5850445000                       # number of ReadExReq miss cycles
 system.l2c.demand_miss_latency::cpu.itb.walker       260000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst    667948500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data   7328903000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total      7997111500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    670242000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   7337417500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8007919500                       # number of demand (read+write) miss cycles
 system.l2c.overall_miss_latency::cpu.itb.walker       260000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst    667948500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data   7328903000                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total     7997111500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker         6306                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker         2762                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst          790398                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data         1307724                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            2107190                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks      1541329                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total          1541329                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data         1665                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total            1665                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data        312686                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           312686                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker         6306                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker         2762                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst           790398                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data          1620410                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             2419876                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker         6306                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker         2762                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst          790398                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data         1620410                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            2419876                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001810                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst       0.016236                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data       0.021696                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.019557                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data     0.808408                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.808408                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data     0.358938                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        0.358938                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.itb.walker     0.001810                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst        0.016236                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data        0.086773                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.063411                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.itb.walker     0.001810                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst       0.016236                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data       0.086773                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.063411                       # miss rate for overall accesses
+system.l2c.overall_miss_latency::cpu.inst    670242000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   7337417500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8007919500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         6458                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         2816                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          792489                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1309040                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total            2110803                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1543757                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total          1543757                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1676                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total            1676                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        313329                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total           313329                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu.dtb.walker         6458                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         2816                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           792489                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1622369                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total             2424132                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         6458                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         2816                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          792489                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1622369                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total            2424132                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001776                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016254                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.021633                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.019521                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.818019                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.818019                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.358926                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        0.358926                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001776                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016254                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.086775                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.063391                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001776                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016254                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.086775                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.063391                       # miss rate for overall accesses
 system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52049.286994                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.877207                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 52365.011769                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24498.514116                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 24498.514116                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52025.633715                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 52025.633715                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52033.382501                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52507.945196                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 52359.531610                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24851.203501                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 24851.203501                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52021.527271                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 52021.527271                       # average ReadExReq miss latency
 system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52049.286994                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52122.944640                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52116.780496                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52033.382501                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52119.373353                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52112.161362                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52049.286994                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52122.944640                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52116.780496                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52033.382501                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52119.373353                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52112.161362                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -171,78 +171,78 @@ system.l2c.avg_blocked_cycles::no_mshrs           nan                       # av
 system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks::writebacks               79595                       # number of writebacks
-system.l2c.writebacks::total                    79595                       # number of writebacks
+system.l2c.writebacks::writebacks               79601                       # number of writebacks
+system.l2c.writebacks::total                    79601                       # number of writebacks
 system.l2c.ReadReq_mshr_misses::cpu.itb.walker            5                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.inst        12833                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu.data        28373                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total           41211                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu.data         1346                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total         1346                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu.data       112235                       # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total        112235                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        12881                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        28319                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           41205                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         1371                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1371                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       112462                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        112462                       # number of ReadExReq MSHR misses
 system.l2c.demand_mshr_misses::cpu.itb.walker            5                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.inst         12833                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu.data        140608                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total           153446                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         12881                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        140781                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           153667                       # number of demand (read+write) MSHR misses
 system.l2c.overall_mshr_misses::cpu.itb.walker            5                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.inst        12833                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu.data       140608                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total          153446                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        12881                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       140781                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          153667                       # number of overall MSHR misses
 system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       200000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.inst    513944000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu.data   1149325000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total   1663469000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     54216000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total     54216000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4492274000                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total   4492274000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    515661000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1147140000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1663001000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     55229000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     55229000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4500898000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4500898000                       # number of ReadExReq MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu.itb.walker       200000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.inst    513944000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu.data   5641599000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total   6155743000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    515661000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   5648038000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6163899000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu.itb.walker       200000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.inst    513944000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu.data   5641599000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total   6155743000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  56050191064                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total  56050191064                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1204378000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total   1204378000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu.data  57254569064                       # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total  57254569064                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.021696                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.019557                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.808408                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.808408                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.358938                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total     0.358938                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu.data     0.086773                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.063411                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001810                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.inst     0.016236                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu.data     0.086773                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.063411                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency::cpu.inst    515661000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   5648038000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6163899000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  86117450000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  86117450000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   2306140000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   2306140000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  88423590000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  88423590000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001776                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016254                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.021633                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.019521                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.818019                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.818019                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.358926                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total     0.358926                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001776                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.016254                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.086775                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total      0.063391                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001776                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.016254                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.086775                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total     0.063391                       # mshr miss rate for overall accesses
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.700983                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 40364.684186                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40279.346211                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40279.346211                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40025.606985                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 40025.606985                       # average ReadExReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40032.683798                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40507.786292                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40359.203980                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40283.734500                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40283.734500                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40021.500596                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 40021.500596                       # average ReadExReq mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu.data 40122.887745                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40116.672966                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40032.683798                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40119.320079                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40112.053987                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40048.624640                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu.data 40122.887745                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40116.672966                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40032.683798                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40119.320079                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40112.053987                       # average overall mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
@@ -250,39 +250,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.replacements                     47504                       # number of replacements
-system.iocache.tagsinuse                     0.108710                       # Cycle average of tags in use
+system.iocache.replacements                     47503                       # number of replacements
+system.iocache.tagsinuse                     0.108785                       # Cycle average of tags in use
 system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                     47520                       # Sample count of references to valid blocks.
+system.iocache.sampled_refs                     47519                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle              5048944307000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide     0.108710                       # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide     0.006794                       # Average percentage of cache occupancy
-system.iocache.occ_percent::total            0.006794                       # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide          839                       # number of ReadReq misses
-system.iocache.ReadReq_misses::total              839                       # number of ReadReq misses
+system.iocache.warmup_cycle              5053216388000                       # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide     0.108785                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.006799                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.006799                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          838                       # number of ReadReq misses
+system.iocache.ReadReq_misses::total              838                       # number of ReadReq misses
 system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide        47559                       # number of demand (read+write) misses
-system.iocache.demand_misses::total             47559                       # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide        47559                       # number of overall misses
-system.iocache.overall_misses::total            47559                       # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128944932                       # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total    128944932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   7159405160                       # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total   7159405160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide   7288350092                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   7288350092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide   7288350092                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   7288350092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide          839                       # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total            839                       # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide        47558                       # number of demand (read+write) misses
+system.iocache.demand_misses::total             47558                       # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide        47558                       # number of overall misses
+system.iocache.overall_misses::total            47558                       # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    128838932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    128838932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   7147789160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   7147789160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   7276628092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   7276628092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   7276628092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   7276628092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          838                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total            838                       # number of ReadReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide        47559                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total           47559                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide        47559                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total          47559                       # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47558                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total           47558                       # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47558                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total          47558                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
 system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
@@ -291,14 +291,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
 system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153688.834327                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 153688.834327                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 153240.692637                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 153240.692637                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153248.598415                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 153248.598415                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153248.598415                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 153248.598415                       # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 153745.742243                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 153745.742243                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 152992.062500                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 152992.062500                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 153005.342781                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 153005.342781                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 153005.342781                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 153005.342781                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs        372008                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                   38                       # number of cycles access was blocked
@@ -309,22 +309,22 @@ system.iocache.fast_writes                          0                       # nu
 system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks           46667                       # number of writebacks
 system.iocache.writebacks::total                46667                       # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          839                       # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total          839                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          838                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          838                       # number of ReadReq MSHR misses
 system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
 system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide        47559                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total        47559                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide        47559                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total        47559                       # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     85286000                       # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total     85286000                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4729709976                       # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total   4729709976                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4814995976                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   4814995976                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4814995976                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   4814995976                       # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47558                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47558                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47558                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47558                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     85232000                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     85232000                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   4718093984                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   4718093984                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4803325984                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4803325984                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4803325984                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4803325984                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
 system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
@@ -333,14 +333,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1
 system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
 system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
 system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101651.966627                       # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 101651.966627                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 101235.230651                       # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 101235.230651                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 101242.582392                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 101242.582392                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 101242.582392                       # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 101708.830549                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 101708.830549                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 100986.600685                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 100986.600685                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 100999.326801                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 100999.326801                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 100999.326801                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -354,75 +354,75 @@ system.pc.south_bridge.ide.disks1.dma_read_txs            0
 system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
 system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.
-system.cpu.numCycles                      10383532628                       # number of cpu cycles simulated
+system.cpu.numCycles                      10392086274                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   138165780                       # Number of instructions committed
-system.cpu.committedOps                     265203824                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             249613019                       # Number of integer alu accesses
+system.cpu.committedInsts                   128236332                       # Number of instructions committed
+system.cpu.committedOps                     247208442                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             231946757                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     24887741                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    249613019                       # number of integer instructions
+system.cpu.num_conditional_control_insts     23151326                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    231946757                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads           778264795                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          423017346                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           720715933                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          387556667                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      23180616                       # number of memory refs
-system.cpu.num_load_insts                    14822216                       # Number of load instructions
-system.cpu.num_store_insts                    8358400                       # Number of store instructions
-system.cpu.num_idle_cycles               9771874926.286118                       # Number of idle cycles
-system.cpu.num_busy_cycles               611657701.713882                       # Number of busy cycles
-system.cpu.not_idle_fraction                 0.058907                       # Percentage of non-idle cycles
-system.cpu.idle_fraction                     0.941093                       # Percentage of idle cycles
+system.cpu.num_mem_refs                      22230275                       # number of memory refs
+system.cpu.num_load_insts                    13869948                       # Number of load instructions
+system.cpu.num_store_insts                    8360327                       # Number of store instructions
+system.cpu.num_idle_cycles               9776409858.670118                       # Number of idle cycles
+system.cpu.num_busy_cycles               615676415.329882                       # Number of busy cycles
+system.cpu.not_idle_fraction                 0.059245                       # Percentage of non-idle cycles
+system.cpu.idle_fraction                     0.940755                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
-system.cpu.icache.replacements                 789892                       # number of replacements
-system.cpu.icache.tagsinuse                510.351457                       # Cycle average of tags in use
-system.cpu.icache.total_refs                158472876                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                 790404                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 200.496045                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           160421909000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     510.351457                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.996780                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.996780                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    158472876                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       158472876                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     158472876                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        158472876                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    158472876                       # number of overall hits
-system.cpu.icache.overall_hits::total       158472876                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       790411                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        790411                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       790411                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         790411                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       790411                       # number of overall misses
-system.cpu.icache.overall_misses::total        790411                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst  11780909500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total  11780909500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst  11780909500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total  11780909500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst  11780909500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total  11780909500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    159263287                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    159263287                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    159263287                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    159263287                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    159263287                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    159263287                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004963                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.004963                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.004963                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.004963                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.004963                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.004963                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 14904.789407                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 14904.789407                       # average overall miss latency
+system.cpu.icache.replacements                 791983                       # number of replacements
+system.cpu.icache.tagsinuse                510.339207                       # Cycle average of tags in use
+system.cpu.icache.total_refs                144447737                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                 792495                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                 182.269588                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           160970951000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst     510.339207                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996756                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996756                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    144447737                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       144447737                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     144447737                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        144447737                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    144447737                       # number of overall hits
+system.cpu.icache.overall_hits::total       144447737                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       792502                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        792502                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       792502                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         792502                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       792502                       # number of overall misses
+system.cpu.icache.overall_misses::total        792502                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11813272500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11813272500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11813272500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11813272500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11813272500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11813272500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    145240239                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    145240239                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    145240239                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    145240239                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    145240239                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    145240239                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.005456                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.005456                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.005456                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.005456                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.005456                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.005456                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14906.299921                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 14906.299921                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14906.299921                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 14906.299921                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14906.299921                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 14906.299921                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -431,80 +431,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       790411                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       790411                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       790411                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       790411                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       790411                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       790411                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9408658500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   9408658500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9408658500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   9408658500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9408658500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   9408658500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.004963                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.004963                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004963                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.004963                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       792502                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       792502                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       792502                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       792502                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       792502                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       792502                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9434751000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9434751000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9434751000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9434751000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9434751000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9434751000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.005456                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.005456                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.005456                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.005456                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.005456                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.005456                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11905.018536                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11905.018536                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11905.018536                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11905.018536                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11905.018536                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11905.018536                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements         3403                       # number of replacements
-system.cpu.itb_walker_cache.tagsinuse        3.070913                       # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs           8040                       # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs         3415                       # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs         2.354319                       # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5164836918000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.070913                       # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191932                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total     0.191932                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         8060                       # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total         8060                       # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements         3538                       # number of replacements
+system.cpu.itb_walker_cache.tagsinuse        3.068811                       # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs           7893                       # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs         3550                       # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs         2.223380                       # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5169410055000                       # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.068811                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191801                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.191801                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7916                       # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total         7916                       # number of ReadReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         8062                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total         8062                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         8062                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total         8062                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4266                       # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total         4266                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4266                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total         4266                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4266                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total         4266                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     50418000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total     50418000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     50418000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total     50418000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     50418000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total     50418000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12326                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total        12326                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7918                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total         7918                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7918                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total         7918                       # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4398                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total         4398                       # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4398                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total         4398                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4398                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total         4398                       # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     51351000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     51351000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     51351000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     51351000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     51351000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     51351000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12314                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total        12314                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12328                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total        12328                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12328                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total        12328                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.346098                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.346098                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.346042                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     0.346042                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.346042                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     0.346042                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11818.565401                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11818.565401                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11818.565401                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11818.565401                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11818.565401                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11818.565401                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12316                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total        12316                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12316                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total        12316                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.357154                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.357154                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.357096                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total     0.357096                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.357096                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total     0.357096                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11675.989086                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11675.989086                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11675.989086                       # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11675.989086                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11675.989086                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11675.989086                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -513,78 +513,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks          726                       # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total          726                       # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4266                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4266                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4266                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total         4266                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4266                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total         4266                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     37620000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     37620000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     37620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37620000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37620000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.346098                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.346098                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.346042                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.346042                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.346042                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.346042                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8818.565401                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8818.565401                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8818.565401                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8818.565401                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks          656                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          656                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4398                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4398                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4398                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4398                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4398                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4398                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     38157000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     38157000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     38157000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     38157000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     38157000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     38157000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.357154                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total     0.357154                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.357096                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     0.357096                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.357096                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     0.357096                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8675.989086                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total  8675.989086                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8675.989086                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total  8675.989086                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8675.989086                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total  8675.989086                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements         7529                       # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse        5.053120                       # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs          13331                       # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs         7543                       # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs         1.767334                       # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5161009077000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.053120                       # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315820                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total     0.315820                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13332                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total        13332                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13332                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total        13332                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13332                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total        13332                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8729                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total         8729                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8729                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total         8729                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8729                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total         8729                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    112265000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    112265000                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    112265000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total    112265000                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    112265000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total    112265000                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22061                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total        22061                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22061                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total        22061                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22061                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total        22061                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.395676                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     0.395676                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.395676                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     0.395676                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12861.152480                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12861.152480                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12861.152480                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12861.152480                       # average overall miss latency
+system.cpu.dtb_walker_cache.replacements         7615                       # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse        5.050606                       # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs          13416                       # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs         7630                       # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs         1.758322                       # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5165509990000                       # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.050606                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315663                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.315663                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13416                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total        13416                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13416                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total        13416                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13416                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total        13416                       # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8830                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total         8830                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8830                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total         8830                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8830                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total         8830                       # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    114790500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    114790500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    114790500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    114790500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    114790500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    114790500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        22246                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total        22246                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        22246                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total        22246                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        22246                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total        22246                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.396925                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.396925                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.396925                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total     0.396925                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.396925                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total     0.396925                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13000.056625                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 13000.056625                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13000.056625                       # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 13000.056625                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13000.056625                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 13000.056625                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -593,90 +593,90 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks         2916                       # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total         2916                       # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8729                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8729                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8729                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total         8729                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8729                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total         8729                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     86078000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     86078000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     86078000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     86078000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.395676                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.395676                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.395676                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.395676                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total  9861.152480                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total  9861.152480                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  9861.152480                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total  9861.152480                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks         3005                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         3005                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8830                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8830                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8830                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8830                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8830                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8830                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     88300000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     88300000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     88300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     88300000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     88300000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     88300000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.396925                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total     0.396925                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.396925                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     0.396925                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.396925                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     0.396925                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        10000                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total        10000                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker        10000                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total        10000                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker        10000                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total        10000                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                1620698                       # number of replacements
-system.cpu.dcache.tagsinuse                511.997463                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 20024816                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                1621210                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.351772                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                1622589                       # number of replacements
+system.cpu.dcache.tagsinuse                511.997330                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 20023565                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                1623101                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.336611                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               45838000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     511.997463                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data     511.997330                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     11989143                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        11989143                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data      8033492                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total        8033492                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      20022635                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         20022635                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     20022635                       # number of overall hits
-system.cpu.dcache.overall_hits::total        20022635                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      1308550                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       1308550                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       314872                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       314872                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      1623422                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        1623422                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      1623422                       # number of overall misses
-system.cpu.dcache.overall_misses::total       1623422                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  19872663500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  19872663500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   9327755500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   9327755500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  29200419000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  29200419000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  29200419000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  29200419000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     13297693                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     13297693                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data      8348364                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total      8348364                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     21646057                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     21646057                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     21646057                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     21646057                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098404                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.098404                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037717                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.037717                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074999                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074999                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074999                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074999                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 17986.955333                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17986.955333                       # average overall miss latency
+system.cpu.dcache.ReadReq_hits::cpu.data     11986605                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        11986605                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8034775                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        8034775                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      20021380                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         20021380                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     20021380                       # number of overall hits
+system.cpu.dcache.overall_hits::total        20021380                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1309816                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1309816                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       315519                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       315519                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1625335                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1625335                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1625335                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1625335                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  19889195500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  19889195500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9348149500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9348149500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  29237345000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29237345000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  29237345000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29237345000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13296421                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     13296421                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8350294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      8350294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     21646715                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     21646715                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21646715                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     21646715                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098509                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.098509                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037785                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.037785                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.075085                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.075085                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075085                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.075085                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15184.724801                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15184.724801                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29627.849670                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 29627.849670                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17988.503908                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 17988.503908                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17988.503908                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 17988.503908                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -685,46 +685,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      1537687                       # number of writebacks
-system.cpu.dcache.writebacks::total           1537687                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1308550                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1308550                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       314872                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       314872                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      1623422                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      1623422                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      1623422                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      1623422                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15946963002                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  15946963002                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8383136001                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   8383136001                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24330099003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  24330099003                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24330099003                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  24330099003                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  75924400500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  75924400500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1366040500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1366040500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77290441000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  77290441000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098404                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098404                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037717                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037717                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.074999                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.074999                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.074999                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.074999                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      1540096                       # number of writebacks
+system.cpu.dcache.writebacks::total           1540096                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1309816                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1309816                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315519                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315519                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1625335                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1625335                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1625335                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1625335                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15959698500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15959698500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8401590001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8401590001                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24361288501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24361288501                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24361288501                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24361288501                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  93628676500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  93628676500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   2467826500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   2467826500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  96096503000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  96096503000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098509                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.098509                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037785                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.037785                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075085                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.075085                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075085                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.075085                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12184.687391                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12184.687391                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26627.841750                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26627.841750                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14988.472223                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14988.472223                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14988.472223                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14988.472223                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency