ARM: Adds dummy support for a L2 latency miscreg.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 6a734a5822bbceba7f95c9c7403bf31d2bdf5d47..3bcb5c97d020e7a60e8af00023d5b453dc2c7899 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -143,6 +143,9 @@ let {{
           case MISCREG_BPIALL:
             return new WarnUnimplemented(
                     isRead ? "mrc bpiall" : "mcr bpiall", machInst);
+          case MISCREG_L2LATENCY:
+            return new WarnUnimplemented(
+                    isRead ? "mrc l2latency" : "mcr l2latency", machInst);
 
             // Write only.
           case MISCREG_TLBIALLIS:

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 13dec0add62d1417c8b5851d4bf3b361911756ca..fc04ce87dec45b47fd0221cd22b541bf28ceb20e 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -381,6 +381,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
                     return MISCREG_PMINTENCLR;
                 }
             }
+        } else if (opc1 == 1) {
+            return MISCREG_L2LATENCY;
         }
         //Reserved for Branch Predictor, Cache and TCM operations
         break;

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index cf9da428afeb7638b20444005d78f65eda69054e..90b4fd99914c83a33441c705e3a10f554e26d4de 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -191,6 +191,7 @@ namespace ArmISA
         MISCREG_MVBAR,
         MISCREG_ISR,
         MISCREG_FCEIDR,
+        MISCREG_L2LATENCY,
 
 
         MISCREG_CP15_END,