i965: Use ctx->Texture._MaxEnabledTexImageUnit for upper bound

Avoid looping over 32/48/96 (!!) tex image units every draw, most of
which we don't care about.

Improves performance on everyone's favorite not-a-benchmark by 2.9% on
Haswell.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index 583c7d66b209655da7acbb0eb353094520c39fb1..34afc26ccbdb6d75e8cda951f468556ae9c8dab1 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -315,7 +315,8 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
       intel_renderbuffer_resolve_hiz(brw, depth_irb);
 
    /* Resolve depth buffer and render cache of each enabled texture. */
-   for (int i = 0; i < ctx->Const.MaxCombinedTextureImageUnits; i++) {
+   int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
+   for (int i = 0; i <= maxEnabledUnit; i++) {
       if (!ctx->Texture.Unit[i]._ReallyEnabled)
         continue;
       tex_obj = intel_texture_object(ctx->Texture.Unit[i]._Current);

diff --git a/src/mesa/drivers/dri/i965/brw_tex.c b/src/mesa/drivers/dri/i965/brw_tex.c
index b1f4de071490886c42ca137fedf1c5ccc75d309d..305d83d09da666c26a4f4992f2065b1e3ba58345 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -46,8 +46,9 @@ void brw_validate_textures( struct brw_context *brw )
 {
    struct gl_context *ctx = &brw->ctx;
    int i;
+   int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
 
-   for (i = 0; i < ctx->Const.MaxCombinedTextureImageUnits; i++) {
+   for (i = 0; i <= maxEnabledUnit; i++) {
       struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 
       if (texUnit->_ReallyEnabled) {