reduce line width
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 3 May 2023 10:59:13 +0000 (11:59 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 3 May 2023 10:59:13 +0000 (11:59 +0100)
conferences/siliconsalon2023/siliconsalon2023.tex

index 2a9956bcba45d6b6b7ca8f322c31b784150fa15d..39ba81932246cc35ca6c4ff1dfd5a35bbe1c3f8b 100644 (file)
    \item Shift by 64-bit is just "pick a register"
    \item Add a 2nd input register with what needs to be shifted IN\\
          (64-bit carry in)
-   \item Add a 2nd output register saving what normally gets thrown away\\
+   \item Add 2nd output saving what normally gets thrown away\\
                (64-bit carry-out)
    \item Again: a chain of these performs Vector-by-Scalar shift
   \end{itemize}