* interp.c (sim_resume): Handle 0xff as a single byte insn.

        * simops.c: Fix overflow computation for "add" and "inc"
        instructions.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index db9a6d2c1f2efa7fc5d598dcf6d39e34a534f832..634b5f9da675cfa04917803c5aa16f005ad940b3 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,10 @@
+Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
+
+       * interp.c (sim_resume): Handle 0xff as a single byte insn.
+
+       * simops.c: Fix overflow computation for "add" and "inc"
+       instructions.
+
 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
 
        * simops.c: Handle "break" instruction.

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index b406c41c6e37243aa3da39921dba96896504edeb..719aaf573279e21b0d95f3d1e1e7574b0915dc0d 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -998,7 +998,7 @@ void OP_E0 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1021,7 +1021,7 @@ void OP_F160 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1044,7 +1044,7 @@ void OP_F150 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1067,7 +1067,7 @@ void OP_F170 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1090,7 +1090,7 @@ void OP_2800 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1113,7 +1113,7 @@ void OP_FAC00000 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1136,7 +1136,7 @@ void OP_FCC00000 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1159,7 +1159,7 @@ void OP_2000 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1182,7 +1182,7 @@ void OP_FAD00000 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1205,7 +1205,7 @@ void OP_FCD00000 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1264,7 +1264,7 @@ void OP_F140 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < reg2);
-  v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
+  v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
        && (reg2 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
@@ -1522,7 +1522,7 @@ void OP_40 (insn, extension)
   z = (value == 0);
   n = (value & 0x80000000);
   c = (reg1 < imm);
-  v = ((reg1 & 0x80000000) != (imm & 0x80000000)
+  v = ((reg1 & 0x80000000) == (imm & 0x80000000)
        && (reg1 & 0x80000000) != (value & 0x80000000));
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);