base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 2bff11b5c532aa2c812e41a0c1f013c285b16229..6c71320b6129f6854d383f27e8618ee1b72a0b7d 100644 (file)
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -48,7 +48,6 @@ const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 // control register file contents

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index d2095d84d1842ab4e0fcc4370f09ba75f5bfed2e..6f7097b084ab5806e8da449f223acf34500d7f5d 100644 (file)
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -282,7 +282,6 @@ typedef RegVal IntReg;
 
 // floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 
 // cop-0/cop-1 system control register
 typedef RegVal MiscReg;

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 527193cc436ac36170d074434ca077848c2d0ac9..fb815af4ad6953372ad3e2373b143460afb078c8 100644 (file)
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -48,7 +48,6 @@ namespace NullISA {
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg;
 typedef RegVal MiscReg;
 const RegIndex ZeroReg = 0;

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 39f7d34f80fe8ed71cf0c8428154878df67e4b85..989b4c52a3f6308394224e66aa45b3ecd3d11bbd 100644 (file)
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -49,7 +49,6 @@ typedef RegVal IntReg;
 
 // Floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 75f74ef2d2dedea45c0d81848e164e233b6a77ff..2de154e228472f58c5065a6628a3957751bf474e 100644 (file)
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -65,7 +65,6 @@ const int MaxMiscDestRegs = 1;
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
 typedef RegVal MiscReg;
 

diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a2a74cc4ab40fe7c3deb7ae11a39067b28dc0841..509f7a1117fe5658d80a9adb0d1337a1e9beb2ad 100644 (file)
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -105,7 +105,6 @@ constexpr unsigned NumVecRegs = 1;
 
 //These floating point types are correct for mmx, but not
 //technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 } // namespace X86ISA

diff --git a/src/base/types.hh b/src/base/types.hh
index c02a606cfefa349b11f602b884cdb58cc94dce84..d99384529b9a8824db4b083f05eab266b917a33a 100644 (file)
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -166,7 +166,6 @@ isRomMicroPC(MicroPC upc)
 const Addr MaxAddr = (Addr)-1;
 
 typedef uint64_t RegVal;
-typedef double FloatRegVal;
 
 static inline uint32_t
 floatToBits32(float val)