* Link Options:: Specifying libraries and so on.
* Directory Options:: Where to find header files and libraries.
Where to find the compiler executable files.
-* Submodel Options:: Specifying minor hardware or convention variations,
- such as 68010 vs 68020.
* Code Gen Options:: Specifying conventions for function calls, data layout
and register usage.
+* Submodel Options:: Specifying minor hardware or convention variations,
+ such as 68010 vs 68020.
* Spec Files:: How to pass switches to sub-processes.
* Environment Variables:: Env vars that affect GCC.
* Precompiled Headers:: Compiling a header once, and using it many times.
-iquote@var{dir} -L@var{dir} -no-canonical-prefixes -I- @gol
--sysroot=@var{dir} --no-sysroot-suffix}
+@item Code Generation Options
+@xref{Code Gen Options,,Options for Code Generation Conventions}.
+@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol
+-ffixed-@var{reg} -fexceptions @gol
+-fnon-call-exceptions -fdelete-dead-exceptions -funwind-tables @gol
+-fasynchronous-unwind-tables @gol
+-fno-gnu-unique @gol
+-finhibit-size-directive -finstrument-functions @gol
+-finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{} @gol
+-finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{} @gol
+-fno-common -fno-ident @gol
+-fpcc-struct-return -fpic -fPIC -fpie -fPIE -fno-plt @gol
+-fno-jump-tables @gol
+-frecord-gcc-switches @gol
+-freg-struct-return -fshort-enums @gol
+-fshort-double -fshort-wchar @gol
+-fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol
+-fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol
+-fno-stack-limit -fsplit-stack @gol
+-fleading-underscore -ftls-model=@var{model} @gol
+-fstack-reuse=@var{reuse_level} @gol
+-ftrapv -fwrapv -fbounds-check @gol
+-fvisibility=@r{[}default@r{|}internal@r{|}hidden@r{|}protected@r{]} @gol
+-fstrict-volatile-bitfields -fsync-libcalls}
+
@item Machine Dependent Options
@xref{Submodel Options,,Hardware Models and Configurations}.
@c This list is ordered alphanumerically by subsection name.
@emph{zSeries Options}
See S/390 and zSeries Options.
-
-@item Code Generation Options
-@xref{Code Gen Options,,Options for Code Generation Conventions}.
-@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol
--ffixed-@var{reg} -fexceptions @gol
--fnon-call-exceptions -fdelete-dead-exceptions -funwind-tables @gol
--fasynchronous-unwind-tables @gol
--fno-gnu-unique @gol
--finhibit-size-directive -finstrument-functions @gol
--finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{} @gol
--finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{} @gol
--fno-common -fno-ident @gol
--fpcc-struct-return -fpic -fPIC -fpie -fPIE -fno-plt @gol
--fno-jump-tables @gol
--frecord-gcc-switches @gol
--freg-struct-return -fshort-enums @gol
--fshort-double -fshort-wchar @gol
--fverbose-asm -fpack-struct[=@var{n}] -fstack-check @gol
--fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol
--fno-stack-limit -fsplit-stack @gol
--fleading-underscore -ftls-model=@var{model} @gol
--fstack-reuse=@var{reuse_level} @gol
--ftrapv -fwrapv -fbounds-check @gol
--fvisibility=@r{[}default@r{|}internal@r{|}hidden@r{|}protected@r{]} @gol
--fstrict-volatile-bitfields -fsync-libcalls}
@end table
independent.
@end table
-@node Submodel Options
-@section Hardware Models and Configurations
-@cindex submodel options
-@cindex specifying hardware config
-@cindex hardware models and configurations, specifying
-@cindex machine dependent options
+@node Code Gen Options
+@section Options for Code Generation Conventions
+@cindex code generation conventions
+@cindex options, code generation
+@cindex run-time options
-Each target machine types can have its own
-special options, starting with @samp{-m}, to choose among various
-hardware models or configurations---for example, 68010 vs 68020,
-floating coprocessor or none. A single installed version of the
-compiler can compile for any model or configuration, according to the
-options specified.
+These machine-independent options control the interface conventions
+used in code generation.
-Some configurations of the compiler also support additional special
-options, usually for compatibility with other compilers on the same
-platform.
+Most of them have both positive and negative forms; the negative form
+of @option{-ffoo} is @option{-fno-foo}. In the table below, only
+one of the forms is listed---the one that is not the default. You
+can figure out the other form by either removing @samp{no-} or adding
+it.
-@c This list is ordered alphanumerically by subsection name.
-@c It should be the same order and spelling as these options are listed
-@c in Machine Dependent Options
+@table @gcctabopt
+@item -fbounds-check
+@opindex fbounds-check
+For front ends that support it, generate additional code to check that
+indices used to access arrays are within the declared range. This is
+currently only supported by the Java and Fortran front ends, where
+this option defaults to true and false respectively.
-@menu
-* AArch64 Options::
-* Adapteva Epiphany Options::
-* ARC Options::
-* ARM Options::
-* AVR Options::
-* Blackfin Options::
-* C6X Options::
-* CRIS Options::
-* CR16 Options::
-* Darwin Options::
-* DEC Alpha Options::
-* FR30 Options::
-* FT32 Options::
-* FRV Options::
-* GNU/Linux Options::
-* H8/300 Options::
-* HPPA Options::
-* IA-64 Options::
-* LM32 Options::
-* M32C Options::
-* M32R/D Options::
-* M680x0 Options::
-* MCore Options::
-* MeP Options::
-* MicroBlaze Options::
-* MIPS Options::
-* MMIX Options::
-* MN10300 Options::
-* Moxie Options::
-* MSP430 Options::
-* NDS32 Options::
-* Nios II Options::
-* Nvidia PTX Options::
-* PDP-11 Options::
-* picoChip Options::
-* PowerPC Options::
-* RL78 Options::
-* RS/6000 and PowerPC Options::
-* RX Options::
-* S/390 and zSeries Options::
-* Score Options::
-* SH Options::
-* Solaris 2 Options::
-* SPARC Options::
-* SPU Options::
-* System V Options::
-* TILE-Gx Options::
-* TILEPro Options::
-* V850 Options::
-* VAX Options::
-* Visium Options::
-* VMS Options::
-* VxWorks Options::
-* x86 Options::
-* x86 Windows Options::
-* Xstormy16 Options::
-* Xtensa Options::
-* zSeries Options::
-@end menu
+@item -fstack-reuse=@var{reuse-level}
+@opindex fstack_reuse
+This option controls stack space reuse for user declared local/auto variables
+and compiler generated temporaries. @var{reuse_level} can be @samp{all},
+@samp{named_vars}, or @samp{none}. @samp{all} enables stack reuse for all
+local variables and temporaries, @samp{named_vars} enables the reuse only for
+user defined local variables with names, and @samp{none} disables stack reuse
+completely. The default value is @samp{all}. The option is needed when the
+program extends the lifetime of a scoped local variable or a compiler generated
+temporary beyond the end point defined by the language. When a lifetime of
+a variable ends, and if the variable lives in memory, the optimizing compiler
+has the freedom to reuse its stack space with other temporaries or scoped
+local variables whose live range does not overlap with it. Legacy code extending
+local lifetime is likely to break with the stack reuse optimization.
-@node AArch64 Options
-@subsection AArch64 Options
-@cindex AArch64 Options
+For example,
-These options are defined for AArch64 implementations:
+@smallexample
+ int *p;
+ @{
+ int local1;
-@table @gcctabopt
+ p = &local1;
+ local1 = 10;
+ ....
+ @}
+ @{
+ int local2;
+ local2 = 20;
+ ...
+ @}
-@item -mabi=@var{name}
-@opindex mabi
-Generate code for the specified data model. Permissible values
-are @samp{ilp32} for SysV-like data model where int, long int and pointer
-are 32-bit, and @samp{lp64} for SysV-like data model where int is 32-bit,
-but long int and pointer are 64-bit.
+ if (*p == 10) // out of scope use of local1
+ @{
-The default depends on the specific target configuration. Note that
-the LP64 and ILP32 ABIs are not link-compatible; you must compile your
-entire program with the same ABI, and link with a compatible set of libraries.
+ @}
+@end smallexample
-@item -mbig-endian
-@opindex mbig-endian
-Generate big-endian code. This is the default when GCC is configured for an
-@samp{aarch64_be-*-*} target.
+Another example:
+@smallexample
-@item -mgeneral-regs-only
-@opindex mgeneral-regs-only
-Generate code which uses only the general-purpose registers. This will prevent
-the compiler from using floating-point and Advanced SIMD registers but will not
-impose any restrictions on the assembler.
+ struct A
+ @{
+ A(int k) : i(k), j(k) @{ @}
+ int i;
+ int j;
+ @};
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate little-endian code. This is the default when GCC is configured for an
-@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target.
+ A *ap;
-@item -mcmodel=tiny
-@opindex mcmodel=tiny
-Generate code for the tiny code model. The program and its statically defined
-symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
-be statically or dynamically linked. This model is not fully implemented and
-mostly treated as @samp{small}.
+ void foo(const A& ar)
+ @{
+ ap = &ar;
+ @}
-@item -mcmodel=small
-@opindex mcmodel=small
-Generate code for the small code model. The program and its statically defined
-symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
-be statically or dynamically linked. This is the default code model.
+ void bar()
+ @{
+ foo(A(10)); // temp object's lifetime ends when foo returns
-@item -mcmodel=large
-@opindex mcmodel=large
-Generate code for the large code model. This makes no assumptions about
-addresses and sizes of sections. Pointers are 64 bits. Programs can be
-statically linked only.
+ @{
+ A a(20);
+ ....
+ @}
+ ap->i+= 10; // ap references out of scope temp whose space
+ // is reused with a. What is the value of ap->i?
+ @}
-@item -mstrict-align
-@opindex mstrict-align
-Do not assume that unaligned memory references are handled by the system.
+@end smallexample
-@item -momit-leaf-frame-pointer
-@itemx -mno-omit-leaf-frame-pointer
-@opindex momit-leaf-frame-pointer
-@opindex mno-omit-leaf-frame-pointer
-Omit or keep the frame pointer in leaf functions. The former behaviour is the
-default.
-
-@item -mtls-dialect=desc
-@opindex mtls-dialect=desc
-Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
-of TLS variables. This is the default.
-
-@item -mtls-dialect=traditional
-@opindex mtls-dialect=traditional
-Use traditional TLS as the thread-local storage mechanism for dynamic accesses
-of TLS variables.
-
-@item -mtls-size=@var{size}
-@opindex mtls-size
-Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
-This option depends on binutils higher than 2.25.
+The lifetime of a compiler generated temporary is well defined by the C++
+standard. When a lifetime of a temporary ends, and if the temporary lives
+in memory, the optimizing compiler has the freedom to reuse its stack
+space with other temporaries or scoped local variables whose live range
+does not overlap with it. However some of the legacy code relies on
+the behavior of older compilers in which temporaries' stack space is
+not reused, the aggressive stack reuse can lead to runtime errors. This
+option is used to control the temporary stack reuse optimization.
-@item -mfix-cortex-a53-835769
-@itemx -mno-fix-cortex-a53-835769
-@opindex mfix-cortex-a53-835769
-@opindex mno-fix-cortex-a53-835769
-Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
-This involves inserting a NOP instruction between memory instructions and
-64-bit integer multiply-accumulate instructions.
+@item -ftrapv
+@opindex ftrapv
+This option generates traps for signed overflow on addition, subtraction,
+multiplication operations.
+The options @option{-ftrapv} and @option{-fwrapv} override each other, so using
+@option{-ftrapv} @option{-fwrapv} on the command-line results in
+@option{-fwrapv} being effective. Note that only active options override, so
+using @option{-ftrapv} @option{-fwrapv} @option{-fno-wrapv} on the command-line
+results in @option{-ftrapv} being effective.
-@item -mfix-cortex-a53-843419
-@itemx -mno-fix-cortex-a53-843419
-@opindex mfix-cortex-a53-843419
-@opindex mno-fix-cortex-a53-843419
-Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
-This erratum workaround is made at link time and this will only pass the
-corresponding flag to the linker.
+@item -fwrapv
+@opindex fwrapv
+This option instructs the compiler to assume that signed arithmetic
+overflow of addition, subtraction and multiplication wraps around
+using twos-complement representation. This flag enables some optimizations
+and disables others. This option is enabled by default for the Java
+front end, as required by the Java language specification.
+The options @option{-ftrapv} and @option{-fwrapv} override each other, so using
+@option{-ftrapv} @option{-fwrapv} on the command-line results in
+@option{-fwrapv} being effective. Note that only active options override, so
+using @option{-ftrapv} @option{-fwrapv} @option{-fno-wrapv} on the command-line
+results in @option{-ftrapv} being effective.
-@item -mlow-precision-recip-sqrt
-@item -mno-low-precision-recip-sqrt
-@opindex -mlow-precision-recip-sqrt
-@opindex -mno-low-precision-recip-sqrt
-The square root estimate uses two steps instead of three for double-precision,
-and one step instead of two for single-precision.
-Thus reducing latency and precision.
-This is only relevant if @option{-ffast-math} activates
-reciprocal square root estimate instructions.
-Which in turn depends on the target processor.
+@item -fexceptions
+@opindex fexceptions
+Enable exception handling. Generates extra code needed to propagate
+exceptions. For some targets, this implies GCC generates frame
+unwind information for all functions, which can produce significant data
+size overhead, although it does not affect execution. If you do not
+specify this option, GCC enables it by default for languages like
+C++ that normally require exception handling, and disables it for
+languages like C that do not normally require it. However, you may need
+to enable this option when compiling C code that needs to interoperate
+properly with exception handlers written in C++. You may also wish to
+disable this option if you are compiling older C++ programs that don't
+use exception handling.
-@item -march=@var{name}
-@opindex march
-Specify the name of the target architecture and, optionally, one or
-more feature modifiers. This option has the form
-@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
+@item -fnon-call-exceptions
+@opindex fnon-call-exceptions
+Generate code that allows trapping instructions to throw exceptions.
+Note that this requires platform-specific runtime support that does
+not exist everywhere. Moreover, it only allows @emph{trapping}
+instructions to throw exceptions, i.e.@: memory references or floating-point
+instructions. It does not allow exceptions to be thrown from
+arbitrary signal handlers such as @code{SIGALRM}.
-The permissible values for @var{arch} are @samp{armv8-a},
-@samp{armv8.1-a} or @var{native}.
+@item -fdelete-dead-exceptions
+@opindex fdelete-dead-exceptions
+Consider that instructions that may throw exceptions but don't otherwise
+contribute to the execution of the program can be optimized away.
+This option is enabled by default for the Ada front end, as permitted by
+the Ada language specification.
+Optimization passes that cause dead exceptions to be removed are enabled independently at different optimization levels.
-The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
-support for the ARMv8.1 architecture extension. In particular, it
-enables the @samp{+crc} and @samp{+lse} features.
+@item -funwind-tables
+@opindex funwind-tables
+Similar to @option{-fexceptions}, except that it just generates any needed
+static data, but does not affect the generated code in any other way.
+You normally do not need to enable this option; instead, a language processor
+that needs this handling enables it on your behalf.
-The value @samp{native} is available on native AArch64 GNU/Linux and
-causes the compiler to pick the architecture of the host system. This
-option has no effect if the compiler is unable to recognize the
-architecture of the host system,
+@item -fasynchronous-unwind-tables
+@opindex fasynchronous-unwind-tables
+Generate unwind table in DWARF 2 format, if supported by target machine. The
+table is exact at each instruction boundary, so it can be used for stack
+unwinding from asynchronous events (such as debugger or garbage collector).
-The permissible values for @var{feature} are listed in the sub-section
-on @ref{aarch64-feature-modifiers,,@option{-march} and @option{-mcpu}
-Feature Modifiers}. Where conflicting feature modifiers are
-specified, the right-most feature is used.
+@item -fno-gnu-unique
+@opindex fno-gnu-unique
+On systems with recent GNU assembler and C library, the C++ compiler
+uses the @code{STB_GNU_UNIQUE} binding to make sure that definitions
+of template static data members and static local variables in inline
+functions are unique even in the presence of @code{RTLD_LOCAL}; this
+is necessary to avoid problems with a library used by two different
+@code{RTLD_LOCAL} plugins depending on a definition in one of them and
+therefore disagreeing with the other one about the binding of the
+symbol. But this causes @code{dlclose} to be ignored for affected
+DSOs; if your program relies on reinitialization of a DSO via
+@code{dlclose} and @code{dlopen}, you can use
+@option{-fno-gnu-unique}.
-GCC uses @var{name} to determine what kind of instructions it can emit
-when generating assembly code. If @option{-march} is specified
-without either of @option{-mtune} or @option{-mcpu} also being
-specified, the code is tuned to perform well across a range of target
-processors implementing the target architecture.
+@item -fpcc-struct-return
+@opindex fpcc-struct-return
+Return ``short'' @code{struct} and @code{union} values in memory like
+longer ones, rather than in registers. This convention is less
+efficient, but it has the advantage of allowing intercallability between
+GCC-compiled files and files compiled with other compilers, particularly
+the Portable C Compiler (pcc).
-@item -mtune=@var{name}
-@opindex mtune
-Specify the name of the target processor for which GCC should tune the
-performance of the code. Permissible values for this option are:
-@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
-@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
-@samp{xgene1}.
+The precise convention for returning structures in memory depends
+on the target configuration macros.
-Additionally, this option can specify that GCC should tune the performance
-of the code for a big.LITTLE system. Permissible values for this
-option are: @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
+Short structures and unions are those whose size and alignment match
+that of some integer type.
-Additionally on native AArch64 GNU/Linux systems the value
-@samp{native} is available. This option causes the compiler to pick
-the architecture of and tune the performance of the code for the
-processor of the host system. This option has no effect if the
-compiler is unable to recognize the architecture of the host system.
+@strong{Warning:} code compiled with the @option{-fpcc-struct-return}
+switch is not binary compatible with code compiled with the
+@option{-freg-struct-return} switch.
+Use it to conform to a non-default application binary interface.
-Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=}
-are specified, the code is tuned to perform well across a range
-of target processors.
+@item -freg-struct-return
+@opindex freg-struct-return
+Return @code{struct} and @code{union} values in registers when possible.
+This is more efficient for small structures than
+@option{-fpcc-struct-return}.
-This option cannot be suffixed by feature modifiers.
+If you specify neither @option{-fpcc-struct-return} nor
+@option{-freg-struct-return}, GCC defaults to whichever convention is
+standard for the target. If there is no standard convention, GCC
+defaults to @option{-fpcc-struct-return}, except on targets where GCC is
+the principal compiler. In those cases, we can choose the standard, and
+we chose the more efficient register return alternative.
-@item -mcpu=@var{name}
-@opindex mcpu
-Specify the name of the target processor, optionally suffixed by one
-or more feature modifiers. This option has the form
-@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where
-the permissible values for @var{cpu} are the same as those available
-for @option{-mtune}. The permissible values for @var{feature} are
-documented in the sub-section on
-@ref{aarch64-feature-modifiers,,@option{-march} and @option{-mcpu}
-Feature Modifiers}. Where conflicting feature modifiers are
-specified, the right-most feature is used.
+@strong{Warning:} code compiled with the @option{-freg-struct-return}
+switch is not binary compatible with code compiled with the
+@option{-fpcc-struct-return} switch.
+Use it to conform to a non-default application binary interface.
-Additionally on native AArch64 GNU/Linux systems the value
-@samp{native} is available. This option causes the compiler to tune
-the performance of the code for the processor of the host system.
-This option has no effect if the compiler is unable to recognize the
-architecture of the host system.
+@item -fshort-enums
+@opindex fshort-enums
+Allocate to an @code{enum} type only as many bytes as it needs for the
+declared range of possible values. Specifically, the @code{enum} type
+is equivalent to the smallest integer type that has enough room.
-GCC uses @var{name} to determine what kind of instructions it can emit when
-generating assembly code (as if by @option{-march}) and to determine
-the target processor for which to tune for performance (as if
-by @option{-mtune}). Where this option is used in conjunction
-with @option{-march} or @option{-mtune}, those options take precedence
-over the appropriate part of this option.
+@strong{Warning:} the @option{-fshort-enums} switch causes GCC to generate
+code that is not binary compatible with code generated without that switch.
+Use it to conform to a non-default application binary interface.
-@item -moverride=@var{string}
-@opindex moverride
-Override tuning decisions made by the back-end in response to a
-@option{-mtune=} switch. The syntax, semantics, and accepted values
-for @var{string} in this option are not guaranteed to be consistent
-across releases.
+@item -fshort-double
+@opindex fshort-double
+Use the same size for @code{double} as for @code{float}.
-This option is only intended to be useful when developing GCC.
+@strong{Warning:} the @option{-fshort-double} switch causes GCC to generate
+code that is not binary compatible with code generated without that switch.
+Use it to conform to a non-default application binary interface.
-@item -mpc-relative-literal-loads
-@opindex mpcrelativeliteralloads
-Enable PC relative literal loads. If this option is used, literal
-pools are assumed to have a range of up to 1MiB and an appropriate
-instruction sequence is used. This option has no impact when used
-with @option{-mcmodel=tiny}.
+@item -fshort-wchar
+@opindex fshort-wchar
+Override the underlying type for @code{wchar_t} to be @code{short
+unsigned int} instead of the default for the target. This option is
+useful for building programs to run under WINE@.
-@end table
+@strong{Warning:} the @option{-fshort-wchar} switch causes GCC to generate
+code that is not binary compatible with code generated without that switch.
+Use it to conform to a non-default application binary interface.
-@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
-@anchor{aarch64-feature-modifiers}
-@cindex @option{-march} feature modifiers
-@cindex @option{-mcpu} feature modifiers
-Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
-the following and their inverses @option{no@var{feature}}:
+@item -fno-common
+@opindex fno-common
+In C code, controls the placement of uninitialized global variables.
+Unix C compilers have traditionally permitted multiple definitions of
+such variables in different compilation units by placing the variables
+in a common block.
+This is the behavior specified by @option{-fcommon}, and is the default
+for GCC on most targets.
+On the other hand, this behavior is not required by ISO C, and on some
+targets may carry a speed or code size penalty on variable references.
+The @option{-fno-common} option specifies that the compiler should place
+uninitialized global variables in the data section of the object file,
+rather than generating them as common blocks.
+This has the effect that if the same variable is declared
+(without @code{extern}) in two different compilations,
+you get a multiple-definition error when you link them.
+In this case, you must compile with @option{-fcommon} instead.
+Compiling with @option{-fno-common} is useful on targets for which
+it provides better performance, or if you wish to verify that the
+program will work on other systems that always treat uninitialized
+variable declarations this way.
-@table @samp
-@item crc
-Enable CRC extension. This is on by default for
-@option{-march=armv8.1-a}.
-@item crypto
-Enable Crypto extension. This also enables Advanced SIMD and floating-point
-instructions.
-@item fp
-Enable floating-point instructions. This is on by default for all possible
-values for options @option{-march} and @option{-mcpu}.
-@item simd
-Enable Advanced SIMD instructions. This also enables floating-point
-instructions. This is on by default for all possible values for options
-@option{-march} and @option{-mcpu}.
-@item lse
-Enable Large System Extension instructions. This is on by default for
-@option{-march=armv8.1-a}.
+@item -fno-ident
+@opindex fno-ident
+Ignore the @code{#ident} directive.
-@end table
+@item -finhibit-size-directive
+@opindex finhibit-size-directive
+Don't output a @code{.size} assembler directive, or anything else that
+would cause trouble if the function is split in the middle, and the
+two halves are placed at locations far apart in memory. This option is
+used when compiling @file{crtstuff.c}; you should not need to use it
+for anything else.
-That is, @option{crypto} implies @option{simd} implies @option{fp}.
-Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
-implies @option{nosimd} implies @option{nocrypto}.
+@item -fverbose-asm
+@opindex fverbose-asm
+Put extra commentary information in the generated assembly code to
+make it more readable. This option is generally only of use to those
+who actually need to read the generated assembly code (perhaps while
+debugging the compiler itself).
-@node Adapteva Epiphany Options
-@subsection Adapteva Epiphany Options
+@option{-fno-verbose-asm}, the default, causes the
+extra information to be omitted and is useful when comparing two assembler
+files.
-These @samp{-m} options are defined for Adapteva Epiphany:
+@item -frecord-gcc-switches
+@opindex frecord-gcc-switches
+This switch causes the command line used to invoke the
+compiler to be recorded into the object file that is being created.
+This switch is only implemented on some targets and the exact format
+of the recording is target and binary file format dependent, but it
+usually takes the form of a section containing ASCII text. This
+switch is related to the @option{-fverbose-asm} switch, but that
+switch only records information in the assembler output file as
+comments, so it never reaches the object file.
+See also @option{-grecord-gcc-switches} for another
+way of storing compiler options into the object file.
-@table @gcctabopt
-@item -mhalf-reg-file
-@opindex mhalf-reg-file
-Don't allocate any register in the range @code{r32}@dots{}@code{r63}.
-That allows code to run on hardware variants that lack these registers.
+@item -fpic
+@opindex fpic
+@cindex global offset table
+@cindex PIC
+Generate position-independent code (PIC) suitable for use in a shared
+library, if supported for the target machine. Such code accesses all
+constant addresses through a global offset table (GOT)@. The dynamic
+loader resolves the GOT entries when the program starts (the dynamic
+loader is not part of GCC; it is part of the operating system). If
+the GOT size for the linked executable exceeds a machine-specific
+maximum size, you get an error message from the linker indicating that
+@option{-fpic} does not work; in that case, recompile with @option{-fPIC}
+instead. (These maximums are 8k on the SPARC, 28k on AArch64 and 32k
+on the m68k and RS/6000. The x86 has no such limit.)
-@item -mprefer-short-insn-regs
-@opindex mprefer-short-insn-regs
-Preferrentially allocate registers that allow short instruction generation.
-This can result in increased instruction count, so this may either reduce or
-increase overall code size.
+Position-independent code requires special support, and therefore works
+only on certain machines. For the x86, GCC supports PIC for System V
+but not for the Sun 386i. Code generated for the IBM RS/6000 is always
+position-independent.
-@item -mbranch-cost=@var{num}
-@opindex mbranch-cost
-Set the cost of branches to roughly @var{num} ``simple'' instructions.
-This cost is only a heuristic and is not guaranteed to produce
-consistent results across releases.
+When this flag is set, the macros @code{__pic__} and @code{__PIC__}
+are defined to 1.
-@item -mcmove
-@opindex mcmove
-Enable the generation of conditional moves.
+@item -fPIC
+@opindex fPIC
+If supported for the target machine, emit position-independent code,
+suitable for dynamic linking and avoiding any limit on the size of the
+global offset table. This option makes a difference on AArch64, m68k,
+PowerPC and SPARC@.
-@item -mnops=@var{num}
-@opindex mnops
-Emit @var{num} NOPs before every other generated instruction.
+Position-independent code requires special support, and therefore works
+only on certain machines.
-@item -mno-soft-cmpsf
-@opindex mno-soft-cmpsf
-For single-precision floating-point comparisons, emit an @code{fsub} instruction
-and test the flags. This is faster than a software comparison, but can
-get incorrect results in the presence of NaNs, or when two different small
-numbers are compared such that their difference is calculated as zero.
-The default is @option{-msoft-cmpsf}, which uses slower, but IEEE-compliant,
-software comparisons.
+When this flag is set, the macros @code{__pic__} and @code{__PIC__}
+are defined to 2.
-@item -mstack-offset=@var{num}
-@opindex mstack-offset
-Set the offset between the top of the stack and the stack pointer.
-E.g., a value of 8 means that the eight bytes in the range @code{sp+0@dots{}sp+7}
-can be used by leaf functions without stack allocation.
-Values other than @samp{8} or @samp{16} are untested and unlikely to work.
-Note also that this option changes the ABI; compiling a program with a
-different stack offset than the libraries have been compiled with
-generally does not work.
-This option can be useful if you want to evaluate if a different stack
-offset would give you better code, but to actually use a different stack
-offset to build working programs, it is recommended to configure the
-toolchain with the appropriate @option{--with-stack-offset=@var{num}} option.
+@item -fpie
+@itemx -fPIE
+@opindex fpie
+@opindex fPIE
+These options are similar to @option{-fpic} and @option{-fPIC}, but
+generated position independent code can be only linked into executables.
+Usually these options are used when @option{-pie} GCC option is
+used during linking.
-@item -mno-round-nearest
-@opindex mno-round-nearest
-Make the scheduler assume that the rounding mode has been set to
-truncating. The default is @option{-mround-nearest}.
+@option{-fpie} and @option{-fPIE} both define the macros
+@code{__pie__} and @code{__PIE__}. The macros have the value 1
+for @option{-fpie} and 2 for @option{-fPIE}.
-@item -mlong-calls
-@opindex mlong-calls
-If not otherwise specified by an attribute, assume all calls might be beyond
-the offset range of the @code{b} / @code{bl} instructions, and therefore load the
-function address into a register before performing a (otherwise direct) call.
-This is the default.
+@item -fno-plt
+@opindex fno-plt
+Do not use the PLT for external function calls in position-independent code.
+Instead, load the callee address at call sites from the GOT and branch to it.
+This leads to more efficient code by eliminating PLT stubs and exposing
+GOT loads to optimizations. On architectures such as 32-bit x86 where
+PLT stubs expect the GOT pointer in a specific register, this gives more
+register allocation freedom to the compiler.
+Lazy binding requires use of the PLT;
+with @option{-fno-plt} all external symbols are resolved at load time.
-@item -mshort-calls
-@opindex short-calls
-If not otherwise specified by an attribute, assume all direct calls are
-in the range of the @code{b} / @code{bl} instructions, so use these instructions
-for direct calls. The default is @option{-mlong-calls}.
+Alternatively, the function attribute @code{noplt} can be used to avoid calls
+through the PLT for specific external functions.
-@item -msmall16
-@opindex msmall16
-Assume addresses can be loaded as 16-bit unsigned values. This does not
-apply to function addresses for which @option{-mlong-calls} semantics
-are in effect.
+In position-dependent code, a few targets also convert calls to
+functions that are marked to not use the PLT to use the GOT instead.
-@item -mfp-mode=@var{mode}
-@opindex mfp-mode
-Set the prevailing mode of the floating-point unit.
-This determines the floating-point mode that is provided and expected
-at function call and return time. Making this mode match the mode you
-predominantly need at function start can make your programs smaller and
-faster by avoiding unnecessary mode switches.
+@item -fno-jump-tables
+@opindex fno-jump-tables
+Do not use jump tables for switch statements even where it would be
+more efficient than other code generation strategies. This option is
+of use in conjunction with @option{-fpic} or @option{-fPIC} for
+building code that forms part of a dynamic linker and cannot
+reference the address of a jump table. On some targets, jump tables
+do not require a GOT and this option is not needed.
-@var{mode} can be set to one the following values:
+@item -ffixed-@var{reg}
+@opindex ffixed
+Treat the register named @var{reg} as a fixed register; generated code
+should never refer to it (except perhaps as a stack pointer, frame
+pointer or in some other fixed role).
-@table @samp
-@item caller
-Any mode at function entry is valid, and retained or restored when
-the function returns, and when it calls other functions.
-This mode is useful for compiling libraries or other compilation units
-you might want to incorporate into different programs with different
-prevailing FPU modes, and the convenience of being able to use a single
-object file outweighs the size and speed overhead for any extra
-mode switching that might be needed, compared with what would be needed
-with a more specific choice of prevailing FPU mode.
+@var{reg} must be the name of a register. The register names accepted
+are machine-specific and are defined in the @code{REGISTER_NAMES}
+macro in the machine description macro file.
-@item truncate
-This is the mode used for floating-point calculations with
-truncating (i.e.@: round towards zero) rounding mode. That includes
-conversion from floating point to integer.
+This flag does not have a negative form, because it specifies a
+three-way choice.
-@item round-nearest
-This is the mode used for floating-point calculations with
-round-to-nearest-or-even rounding mode.
+@item -fcall-used-@var{reg}
+@opindex fcall-used
+Treat the register named @var{reg} as an allocable register that is
+clobbered by function calls. It may be allocated for temporaries or
+variables that do not live across a call. Functions compiled this way
+do not save and restore the register @var{reg}.
-@item int
-This is the mode used to perform integer calculations in the FPU, e.g.@:
-integer multiply, or integer multiply-and-accumulate.
-@end table
+It is an error to use this flag with the frame pointer or stack pointer.
+Use of this flag for other registers that have fixed pervasive roles in
+the machine's execution model produces disastrous results.
-The default is @option{-mfp-mode=caller}
+This flag does not have a negative form, because it specifies a
+three-way choice.
-@item -mnosplit-lohi
-@itemx -mno-postinc
-@itemx -mno-postmodify
-@opindex mnosplit-lohi
-@opindex mno-postinc
-@opindex mno-postmodify
-Code generation tweaks that disable, respectively, splitting of 32-bit
-loads, generation of post-increment addresses, and generation of
-post-modify addresses. The defaults are @option{msplit-lohi},
-@option{-mpost-inc}, and @option{-mpost-modify}.
+@item -fcall-saved-@var{reg}
+@opindex fcall-saved
+Treat the register named @var{reg} as an allocable register saved by
+functions. It may be allocated even for temporaries or variables that
+live across a call. Functions compiled this way save and restore
+the register @var{reg} if they use it.
-@item -mnovect-double
-@opindex mno-vect-double
-Change the preferred SIMD mode to SImode. The default is
-@option{-mvect-double}, which uses DImode as preferred SIMD mode.
+It is an error to use this flag with the frame pointer or stack pointer.
+Use of this flag for other registers that have fixed pervasive roles in
+the machine's execution model produces disastrous results.
-@item -max-vect-align=@var{num}
-@opindex max-vect-align
-The maximum alignment for SIMD vector mode types.
-@var{num} may be 4 or 8. The default is 8.
-Note that this is an ABI change, even though many library function
-interfaces are unaffected if they don't use SIMD vector modes
-in places that affect size and/or alignment of relevant types.
+A different sort of disaster results from the use of this flag for
+a register in which function values may be returned.
-@item -msplit-vecmove-early
-@opindex msplit-vecmove-early
-Split vector moves into single word moves before reload. In theory this
-can give better register allocation, but so far the reverse seems to be
-generally the case.
+This flag does not have a negative form, because it specifies a
+three-way choice.
-@item -m1reg-@var{reg}
-@opindex m1reg-
-Specify a register to hold the constant @minus{}1, which makes loading small negative
-constants and certain bitmasks faster.
-Allowable values for @var{reg} are @samp{r43} and @samp{r63},
-which specify use of that register as a fixed register,
-and @samp{none}, which means that no register is used for this
-purpose. The default is @option{-m1reg-none}.
+@item -fpack-struct[=@var{n}]
+@opindex fpack-struct
+Without a value specified, pack all structure members together without
+holes. When a value is specified (which must be a small power of two), pack
+structure members according to this value, representing the maximum
+alignment (that is, objects with default alignment requirements larger than
+this are output potentially unaligned at the next fitting location.
-@end table
+@strong{Warning:} the @option{-fpack-struct} switch causes GCC to generate
+code that is not binary compatible with code generated without that switch.
+Additionally, it makes the code suboptimal.
+Use it to conform to a non-default application binary interface.
-@node ARC Options
-@subsection ARC Options
-@cindex ARC options
+@item -finstrument-functions
+@opindex finstrument-functions
+Generate instrumentation calls for entry and exit to functions. Just
+after function entry and just before function exit, the following
+profiling functions are called with the address of the current
+function and its call site. (On some platforms,
+@code{__builtin_return_address} does not work beyond the current
+function, so the call site information may not be available to the
+profiling functions otherwise.)
-The following options control the architecture variant for which code
-is being compiled:
+@smallexample
+void __cyg_profile_func_enter (void *this_fn,
+ void *call_site);
+void __cyg_profile_func_exit (void *this_fn,
+ void *call_site);
+@end smallexample
-@c architecture variants
-@table @gcctabopt
+The first argument is the address of the start of the current function,
+which may be looked up exactly in the symbol table.
-@item -mbarrel-shifter
-@opindex mbarrel-shifter
-Generate instructions supported by barrel shifter. This is the default
-unless @option{-mcpu=ARC601} or @samp{-mcpu=ARCEM} is in effect.
+This instrumentation is also done for functions expanded inline in other
+functions. The profiling calls indicate where, conceptually, the
+inline function is entered and exited. This means that addressable
+versions of such functions must be available. If all your uses of a
+function are expanded inline, this may mean an additional expansion of
+code size. If you use @code{extern inline} in your C code, an
+addressable version of such functions must be provided. (This is
+normally the case anyway, but if you get lucky and the optimizer always
+expands the functions inline, you might have gotten away without
+providing static copies.)
-@item -mcpu=@var{cpu}
-@opindex mcpu
-Set architecture type, register usage, and instruction scheduling
-parameters for @var{cpu}. There are also shortcut alias options
-available for backward compatibility and convenience. Supported
-values for @var{cpu} are
+A function may be given the attribute @code{no_instrument_function}, in
+which case this instrumentation is not done. This can be used, for
+example, for the profiling functions listed above, high-priority
+interrupt routines, and any functions from which the profiling functions
+cannot safely be called (perhaps signal handlers, if the profiling
+routines generate output or allocate memory).
-@table @samp
-@opindex mA6
-@opindex mARC600
-@item ARC600
-@item arc600
-Compile for ARC600. Aliases: @option{-mA6}, @option{-mARC600}.
+@item -finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{}
+@opindex finstrument-functions-exclude-file-list
-@item ARC601
-@item arc601
-@opindex mARC601
-Compile for ARC601. Alias: @option{-mARC601}.
+Set the list of functions that are excluded from instrumentation (see
+the description of @option{-finstrument-functions}). If the file that
+contains a function definition matches with one of @var{file}, then
+that function is not instrumented. The match is done on substrings:
+if the @var{file} parameter is a substring of the file name, it is
+considered to be a match.
-@item ARC700
-@item arc700
-@opindex mA7
-@opindex mARC700
-Compile for ARC700. Aliases: @option{-mA7}, @option{-mARC700}.
-This is the default when configured with @option{--with-cpu=arc700}@.
+For example:
-@item ARCEM
-@item arcem
-Compile for ARC EM.
+@smallexample
+-finstrument-functions-exclude-file-list=/bits/stl,include/sys
+@end smallexample
-@item ARCHS
-@item archs
-Compile for ARC HS.
-@end table
+@noindent
+excludes any inline function defined in files whose pathnames
+contain @file{/bits/stl} or @file{include/sys}.
-@item -mdpfp
-@opindex mdpfp
-@itemx -mdpfp-compact
-@opindex mdpfp-compact
-FPX: Generate Double Precision FPX instructions, tuned for the compact
-implementation.
+If, for some reason, you want to include letter @samp{,} in one of
+@var{sym}, write @samp{\,}. For example,
+@option{-finstrument-functions-exclude-file-list='\,\,tmp'}
+(note the single quote surrounding the option).
-@item -mdpfp-fast
-@opindex mdpfp-fast
-FPX: Generate Double Precision FPX instructions, tuned for the fast
-implementation.
+@item -finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{}
+@opindex finstrument-functions-exclude-function-list
-@item -mno-dpfp-lrsr
-@opindex mno-dpfp-lrsr
-Disable LR and SR instructions from using FPX extension aux registers.
+This is similar to @option{-finstrument-functions-exclude-file-list},
+but this option sets the list of function names to be excluded from
+instrumentation. The function name to be matched is its user-visible
+name, such as @code{vector<int> blah(const vector<int> &)}, not the
+internal mangled name (e.g., @code{_Z4blahRSt6vectorIiSaIiEE}). The
+match is done on substrings: if the @var{sym} parameter is a substring
+of the function name, it is considered to be a match. For C99 and C++
+extended identifiers, the function name must be given in UTF-8, not
+using universal character names.
-@item -mea
-@opindex mea
-Generate Extended arithmetic instructions. Currently only
-@code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are
-supported. This is always enabled for @option{-mcpu=ARC700}.
+@item -fstack-check
+@opindex fstack-check
+Generate code to verify that you do not go beyond the boundary of the
+stack. You should specify this flag if you are running in an
+environment with multiple threads, but you only rarely need to specify it in
+a single-threaded environment since stack overflow is automatically
+detected on nearly all systems if there is only one stack.
-@item -mno-mpy
-@opindex mno-mpy
-Do not generate mpy instructions for ARC700.
+Note that this switch does not actually cause checking to be done; the
+operating system or the language runtime must do that. The switch causes
+generation of code to ensure that they see the stack being extended.
-@item -mmul32x16
-@opindex mmul32x16
-Generate 32x16 bit multiply and mac instructions.
+You can additionally specify a string parameter: @samp{no} means no
+checking, @samp{generic} means force the use of old-style checking,
+@samp{specific} means use the best checking method and is equivalent
+to bare @option{-fstack-check}.
-@item -mmul64
-@opindex mmul64
-Generate mul64 and mulu64 instructions. Only valid for @option{-mcpu=ARC600}.
+Old-style checking is a generic mechanism that requires no specific
+target support in the compiler but comes with the following drawbacks:
-@item -mnorm
-@opindex mnorm
-Generate norm instruction. This is the default if @option{-mcpu=ARC700}
-is in effect.
+@enumerate
+@item
+Modified allocation strategy for large objects: they are always
+allocated dynamically if their size exceeds a fixed threshold.
-@item -mspfp
-@opindex mspfp
-@itemx -mspfp-compact
-@opindex mspfp-compact
-FPX: Generate Single Precision FPX instructions, tuned for the compact
-implementation.
+@item
+Fixed limit on the size of the static frame of functions: when it is
+topped by a particular function, stack checking is not reliable and
+a warning is issued by the compiler.
-@item -mspfp-fast
-@opindex mspfp-fast
-FPX: Generate Single Precision FPX instructions, tuned for the fast
-implementation.
+@item
+Inefficiency: because of both the modified allocation strategy and the
+generic implementation, code performance is hampered.
+@end enumerate
-@item -msimd
-@opindex msimd
-Enable generation of ARC SIMD instructions via target-specific
-builtins. Only valid for @option{-mcpu=ARC700}.
+Note that old-style stack checking is also the fallback method for
+@samp{specific} if no target support has been added in the compiler.
-@item -msoft-float
-@opindex msoft-float
-This option ignored; it is provided for compatibility purposes only.
-Software floating point code is emitted by default, and this default
-can overridden by FPX options; @samp{mspfp}, @samp{mspfp-compact}, or
-@samp{mspfp-fast} for single precision, and @samp{mdpfp},
-@samp{mdpfp-compact}, or @samp{mdpfp-fast} for double precision.
+@item -fstack-limit-register=@var{reg}
+@itemx -fstack-limit-symbol=@var{sym}
+@itemx -fno-stack-limit
+@opindex fstack-limit-register
+@opindex fstack-limit-symbol
+@opindex fno-stack-limit
+Generate code to ensure that the stack does not grow beyond a certain value,
+either the value of a register or the address of a symbol. If a larger
+stack is required, a signal is raised at run time. For most targets,
+the signal is raised before the stack overruns the boundary, so
+it is possible to catch the signal without taking special precautions.
-@item -mswap
-@opindex mswap
-Generate swap instructions.
-
-@item -matomic
-@opindex matomic
-This enables Locked Load/Store Conditional extension to implement
-atomic memopry built-in functions. Not available for ARC 6xx or ARC
-EM cores.
-
-@item -mdiv-rem
-@opindex mdiv-rem
-Enable DIV/REM instructions for ARCv2 cores.
+For instance, if the stack starts at absolute address @samp{0x80000000}
+and grows downwards, you can use the flags
+@option{-fstack-limit-symbol=__stack_limit} and
+@option{-Wl,--defsym,__stack_limit=0x7ffe0000} to enforce a stack limit
+of 128KB@. Note that this may only work with the GNU linker.
-@item -mcode-density
-@opindex mcode-density
-Enable code density instructions for ARC EM, default on for ARC HS.
+You can locally override stack limit checking by using the
+@code{no_stack_limit} function attribute (@pxref{Function Attributes}).
-@item -mmpy-option=@var{multo}
-@opindex mmpy-option
-Compile ARCv2 code with a multiplier design option. @samp{wlh1} is
-the default value. The recognized values for @var{multo} are:
+@item -fsplit-stack
+@opindex fsplit-stack
+Generate code to automatically split the stack before it overflows.
+The resulting program has a discontiguous stack which can only
+overflow if the program is unable to allocate any more memory. This
+is most useful when running threaded programs, as it is no longer
+necessary to calculate a good stack size to use for each thread. This
+is currently only implemented for the x86 targets running
+GNU/Linux.
-@table @samp
-@item 0
-No multiplier available.
+When code compiled with @option{-fsplit-stack} calls code compiled
+without @option{-fsplit-stack}, there may not be much stack space
+available for the latter code to run. If compiling all code,
+including library code, with @option{-fsplit-stack} is not an option,
+then the linker can fix up these calls so that the code compiled
+without @option{-fsplit-stack} always has a large stack. Support for
+this is implemented in the gold linker in GNU binutils release 2.21
+and later.
-@item 1
-@opindex w
-The multiply option is set to w: 16x16 multiplier, fully pipelined.
-The following instructions are enabled: MPYW, and MPYUW.
+@item -fleading-underscore
+@opindex fleading-underscore
+This option and its counterpart, @option{-fno-leading-underscore}, forcibly
+change the way C symbols are represented in the object file. One use
+is to help link with legacy assembly code.
-@item 2
-@opindex wlh1
-The multiply option is set to wlh1: 32x32 multiplier, fully
-pipelined (1 stage). The following instructions are additionaly
-enabled: MPY, MPYU, MPYM, MPYMU, and MPY_S.
+@strong{Warning:} the @option{-fleading-underscore} switch causes GCC to
+generate code that is not binary compatible with code generated without that
+switch. Use it to conform to a non-default application binary interface.
+Not all targets provide complete support for this switch.
-@item 3
-@opindex wlh2
-The multiply option is set to wlh2: 32x32 multiplier, fully pipelined
-(2 stages). The following instructions are additionaly enabled: MPY,
-MPYU, MPYM, MPYMU, and MPY_S.
+@item -ftls-model=@var{model}
+@opindex ftls-model
+Alter the thread-local storage model to be used (@pxref{Thread-Local}).
+The @var{model} argument should be one of @samp{global-dynamic},
+@samp{local-dynamic}, @samp{initial-exec} or @samp{local-exec}.
+Note that the choice is subject to optimization: the compiler may use
+a more efficient model for symbols not visible outside of the translation
+unit, or if @option{-fpic} is not given on the command line.
-@item 4
-@opindex wlh3
-The multiply option is set to wlh3: Two 16x16 multiplier, blocking,
-sequential. The following instructions are additionaly enabled: MPY,
-MPYU, MPYM, MPYMU, and MPY_S.
+The default without @option{-fpic} is @samp{initial-exec}; with
+@option{-fpic} the default is @samp{global-dynamic}.
-@item 5
-@opindex wlh4
-The multiply option is set to wlh4: One 16x16 multiplier, blocking,
-sequential. The following instructions are additionaly enabled: MPY,
-MPYU, MPYM, MPYMU, and MPY_S.
+@item -fvisibility=@r{[}default@r{|}internal@r{|}hidden@r{|}protected@r{]}
+@opindex fvisibility
+Set the default ELF image symbol visibility to the specified option---all
+symbols are marked with this unless overridden within the code.
+Using this feature can very substantially improve linking and
+load times of shared object libraries, produce more optimized
+code, provide near-perfect API export and prevent symbol clashes.
+It is @strong{strongly} recommended that you use this in any shared objects
+you distribute.
-@item 6
-@opindex wlh5
-The multiply option is set to wlh5: One 32x4 multiplier, blocking,
-sequential. The following instructions are additionaly enabled: MPY,
-MPYU, MPYM, MPYMU, and MPY_S.
+Despite the nomenclature, @samp{default} always means public; i.e.,
+available to be linked against from outside the shared object.
+@samp{protected} and @samp{internal} are pretty useless in real-world
+usage so the only other commonly used option is @samp{hidden}.
+The default if @option{-fvisibility} isn't specified is
+@samp{default}, i.e., make every symbol public.
-@end table
+A good explanation of the benefits offered by ensuring ELF
+symbols have the correct visibility is given by ``How To Write
+Shared Libraries'' by Ulrich Drepper (which can be found at
+@w{@uref{http://www.akkadia.org/drepper/}})---however a superior
+solution made possible by this option to marking things hidden when
+the default is public is to make the default hidden and mark things
+public. This is the norm with DLLs on Windows and with @option{-fvisibility=hidden}
+and @code{__attribute__ ((visibility("default")))} instead of
+@code{__declspec(dllexport)} you get almost identical semantics with
+identical syntax. This is a great boon to those working with
+cross-platform projects.
-This option is only available for ARCv2 cores@.
+For those adding visibility support to existing code, you may find
+@code{#pragma GCC visibility} of use. This works by you enclosing
+the declarations you wish to set visibility for with (for example)
+@code{#pragma GCC visibility push(hidden)} and
+@code{#pragma GCC visibility pop}.
+Bear in mind that symbol visibility should be viewed @strong{as
+part of the API interface contract} and thus all new code should
+always specify visibility when it is not the default; i.e., declarations
+only for use within the local DSO should @strong{always} be marked explicitly
+as hidden as so to avoid PLT indirection overheads---making this
+abundantly clear also aids readability and self-documentation of the code.
+Note that due to ISO C++ specification requirements, @code{operator new} and
+@code{operator delete} must always be of default visibility.
-@end table
+Be aware that headers from outside your project, in particular system
+headers and headers from any other library you use, may not be
+expecting to be compiled with visibility other than the default. You
+may need to explicitly say @code{#pragma GCC visibility push(default)}
+before including any such headers.
-The following options are passed through to the assembler, and also
-define preprocessor macro symbols.
+@code{extern} declarations are not affected by @option{-fvisibility}, so
+a lot of code can be recompiled with @option{-fvisibility=hidden} with
+no modifications. However, this means that calls to @code{extern}
+functions with no explicit visibility use the PLT, so it is more
+effective to use @code{__attribute ((visibility))} and/or
+@code{#pragma GCC visibility} to tell the compiler which @code{extern}
+declarations should be treated as hidden.
-@c Flags used by the assembler, but for which we define preprocessor
-@c macro symbols as well.
-@table @gcctabopt
-@item -mdsp-packa
-@opindex mdsp-packa
-Passed down to the assembler to enable the DSP Pack A extensions.
-Also sets the preprocessor symbol @code{__Xdsp_packa}.
+Note that @option{-fvisibility} does affect C++ vague linkage
+entities. This means that, for instance, an exception class that is
+be thrown between DSOs must be explicitly marked with default
+visibility so that the @samp{type_info} nodes are unified between
+the DSOs.
-@item -mdvbf
-@opindex mdvbf
-Passed down to the assembler to enable the dual viterbi butterfly
-extension. Also sets the preprocessor symbol @code{__Xdvbf}.
+An overview of these techniques, their benefits and how to use them
+is at @uref{http://gcc.gnu.org/@/wiki/@/Visibility}.
-@c ARC700 4.10 extension instruction
-@item -mlock
-@opindex mlock
-Passed down to the assembler to enable the Locked Load/Store
-Conditional extension. Also sets the preprocessor symbol
-@code{__Xlock}.
+@item -fstrict-volatile-bitfields
+@opindex fstrict-volatile-bitfields
+This option should be used if accesses to volatile bit-fields (or other
+structure fields, although the compiler usually honors those types
+anyway) should use a single access of the width of the
+field's type, aligned to a natural alignment if possible. For
+example, targets with memory-mapped peripheral registers might require
+all such accesses to be 16 bits wide; with this flag you can
+declare all peripheral bit-fields as @code{unsigned short} (assuming short
+is 16 bits on these targets) to force GCC to use 16-bit accesses
+instead of, perhaps, a more efficient 32-bit access.
-@item -mmac-d16
-@opindex mmac-d16
-Passed down to the assembler. Also sets the preprocessor symbol
-@code{__Xxmac_d16}.
+If this option is disabled, the compiler uses the most efficient
+instruction. In the previous example, that might be a 32-bit load
+instruction, even though that accesses bytes that do not contain
+any portion of the bit-field, or memory-mapped registers unrelated to
+the one being updated.
-@item -mmac-24
-@opindex mmac-24
-Passed down to the assembler. Also sets the preprocessor symbol
-@code{__Xxmac_24}.
+In some cases, such as when the @code{packed} attribute is applied to a
+structure field, it may not be possible to access the field with a single
+read or write that is correctly aligned for the target machine. In this
+case GCC falls back to generating multiple accesses rather than code that
+will fault or truncate the result at run time.
-@c ARC700 4.10 extension instruction
-@item -mrtsc
-@opindex mrtsc
-Passed down to the assembler to enable the 64-bit Time-Stamp Counter
-extension instruction. Also sets the preprocessor symbol
-@code{__Xrtsc}.
+Note: Due to restrictions of the C/C++11 memory model, write accesses are
+not allowed to touch non bit-field members. It is therefore recommended
+to define all bits of the field's type as bit-field members.
-@c ARC700 4.10 extension instruction
-@item -mswape
-@opindex mswape
-Passed down to the assembler to enable the swap byte ordering
-extension instruction. Also sets the preprocessor symbol
-@code{__Xswape}.
+The default value of this option is determined by the application binary
+interface for the target processor.
-@item -mtelephony
-@opindex mtelephony
-Passed down to the assembler to enable dual and single operand
-instructions for telephony. Also sets the preprocessor symbol
-@code{__Xtelephony}.
+@item -fsync-libcalls
+@opindex fsync-libcalls
+This option controls whether any out-of-line instance of the @code{__sync}
+family of functions may be used to implement the C++11 @code{__atomic}
+family of functions.
-@item -mxy
-@opindex mxy
-Passed down to the assembler to enable the XY Memory extension. Also
-sets the preprocessor symbol @code{__Xxy}.
+The default value of this option is enabled, thus the only useful form
+of the option is @option{-fno-sync-libcalls}. This option is used in
+the implementation of the @file{libatomic} runtime library.
@end table
-The following options control how the assembly code is annotated:
+@node Submodel Options
+@section Hardware Models and Configurations
+@cindex submodel options
+@cindex specifying hardware config
+@cindex hardware models and configurations, specifying
+@cindex machine dependent options
-@c Assembly annotation options
-@table @gcctabopt
-@item -misize
-@opindex misize
-Annotate assembler instructions with estimated addresses.
+Each target machine types can have its own
+special options, starting with @samp{-m}, to choose among various
+hardware models or configurations---for example, 68010 vs 68020,
+floating coprocessor or none. A single installed version of the
+compiler can compile for any model or configuration, according to the
+options specified.
-@item -mannotate-align
-@opindex mannotate-align
-Explain what alignment considerations lead to the decision to make an
-instruction short or long.
+Some configurations of the compiler also support additional special
+options, usually for compatibility with other compilers on the same
+platform.
-@end table
+@c This list is ordered alphanumerically by subsection name.
+@c It should be the same order and spelling as these options are listed
+@c in Machine Dependent Options
-The following options are passed through to the linker:
+@menu
+* AArch64 Options::
+* Adapteva Epiphany Options::
+* ARC Options::
+* ARM Options::
+* AVR Options::
+* Blackfin Options::
+* C6X Options::
+* CRIS Options::
+* CR16 Options::
+* Darwin Options::
+* DEC Alpha Options::
+* FR30 Options::
+* FT32 Options::
+* FRV Options::
+* GNU/Linux Options::
+* H8/300 Options::
+* HPPA Options::
+* IA-64 Options::
+* LM32 Options::
+* M32C Options::
+* M32R/D Options::
+* M680x0 Options::
+* MCore Options::
+* MeP Options::
+* MicroBlaze Options::
+* MIPS Options::
+* MMIX Options::
+* MN10300 Options::
+* Moxie Options::
+* MSP430 Options::
+* NDS32 Options::
+* Nios II Options::
+* Nvidia PTX Options::
+* PDP-11 Options::
+* picoChip Options::
+* PowerPC Options::
+* RL78 Options::
+* RS/6000 and PowerPC Options::
+* RX Options::
+* S/390 and zSeries Options::
+* Score Options::
+* SH Options::
+* Solaris 2 Options::
+* SPARC Options::
+* SPU Options::
+* System V Options::
+* TILE-Gx Options::
+* TILEPro Options::
+* V850 Options::
+* VAX Options::
+* Visium Options::
+* VMS Options::
+* VxWorks Options::
+* x86 Options::
+* x86 Windows Options::
+* Xstormy16 Options::
+* Xtensa Options::
+* zSeries Options::
+@end menu
+
+@node AArch64 Options
+@subsection AArch64 Options
+@cindex AArch64 Options
+
+These options are defined for AArch64 implementations:
-@c options passed through to the linker
@table @gcctabopt
-@item -marclinux
-@opindex marclinux
-Passed through to the linker, to specify use of the @code{arclinux} emulation.
-This option is enabled by default in tool chains built for
-@w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets
-when profiling is not requested.
-@item -marclinux_prof
-@opindex marclinux_prof
-Passed through to the linker, to specify use of the
-@code{arclinux_prof} emulation. This option is enabled by default in
-tool chains built for @w{@code{arc-linux-uclibc}} and
-@w{@code{arceb-linux-uclibc}} targets when profiling is requested.
+@item -mabi=@var{name}
+@opindex mabi
+Generate code for the specified data model. Permissible values
+are @samp{ilp32} for SysV-like data model where int, long int and pointer
+are 32-bit, and @samp{lp64} for SysV-like data model where int is 32-bit,
+but long int and pointer are 64-bit.
-@end table
+The default depends on the specific target configuration. Note that
+the LP64 and ILP32 ABIs are not link-compatible; you must compile your
+entire program with the same ABI, and link with a compatible set of libraries.
-The following options control the semantics of generated code:
+@item -mbig-endian
+@opindex mbig-endian
+Generate big-endian code. This is the default when GCC is configured for an
+@samp{aarch64_be-*-*} target.
-@c semantically relevant code generation options
-@table @gcctabopt
-@item -mlong-calls
-@opindex mlong-calls
-Generate call insns as register indirect calls, thus providing access
-to the full 32-bit address range.
+@item -mgeneral-regs-only
+@opindex mgeneral-regs-only
+Generate code which uses only the general-purpose registers. This will prevent
+the compiler from using floating-point and Advanced SIMD registers but will not
+impose any restrictions on the assembler.
-@item -mmedium-calls
-@opindex mmedium-calls
-Don't use less than 25 bit addressing range for calls, which is the
-offset available for an unconditional branch-and-link
-instruction. Conditional execution of function calls is suppressed, to
-allow use of the 25-bit range, rather than the 21-bit range with
-conditional branch-and-link. This is the default for tool chains built
-for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate little-endian code. This is the default when GCC is configured for an
+@samp{aarch64-*-*} but not an @samp{aarch64_be-*-*} target.
-@item -mno-sdata
-@opindex mno-sdata
-Do not generate sdata references. This is the default for tool chains
-built for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}}
-targets.
+@item -mcmodel=tiny
+@opindex mcmodel=tiny
+Generate code for the tiny code model. The program and its statically defined
+symbols must be within 1GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This model is not fully implemented and
+mostly treated as @samp{small}.
-@item -mucb-mcount
-@opindex mucb-mcount
-Instrument with mcount calls as used in UCB code. I.e. do the
-counting in the callee, not the caller. By default ARC instrumentation
-counts in the caller.
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small code model. The program and its statically defined
+symbols must be within 4GB of each other. Pointers are 64 bits. Programs can
+be statically or dynamically linked. This is the default code model.
-@item -mvolatile-cache
-@opindex mvolatile-cache
-Use ordinarily cached memory accesses for volatile references. This is the
-default.
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large code model. This makes no assumptions about
+addresses and sizes of sections. Pointers are 64 bits. Programs can be
+statically linked only.
-@item -mno-volatile-cache
-@opindex mno-volatile-cache
-Enable cache bypass for volatile references.
+@item -mstrict-align
+@opindex mstrict-align
+Do not assume that unaligned memory references are handled by the system.
-@end table
+@item -momit-leaf-frame-pointer
+@itemx -mno-omit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+@opindex mno-omit-leaf-frame-pointer
+Omit or keep the frame pointer in leaf functions. The former behaviour is the
+default.
-The following options fine tune code generation:
-@c code generation tuning options
-@table @gcctabopt
-@item -malign-call
-@opindex malign-call
-Do alignment optimizations for call instructions.
+@item -mtls-dialect=desc
+@opindex mtls-dialect=desc
+Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
+of TLS variables. This is the default.
-@item -mauto-modify-reg
-@opindex mauto-modify-reg
-Enable the use of pre/post modify with register displacement.
+@item -mtls-dialect=traditional
+@opindex mtls-dialect=traditional
+Use traditional TLS as the thread-local storage mechanism for dynamic accesses
+of TLS variables.
-@item -mbbit-peephole
-@opindex mbbit-peephole
-Enable bbit peephole2.
+@item -mtls-size=@var{size}
+@opindex mtls-size
+Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48.
+This option depends on binutils higher than 2.25.
-@item -mno-brcc
-@opindex mno-brcc
-This option disables a target-specific pass in @file{arc_reorg} to
-generate @code{BRcc} instructions. It has no effect on @code{BRcc}
-generation driven by the combiner pass.
+@item -mfix-cortex-a53-835769
+@itemx -mno-fix-cortex-a53-835769
+@opindex mfix-cortex-a53-835769
+@opindex mno-fix-cortex-a53-835769
+Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
+This involves inserting a NOP instruction between memory instructions and
+64-bit integer multiply-accumulate instructions.
-@item -mcase-vector-pcrel
-@opindex mcase-vector-pcrel
-Use pc-relative switch case tables - this enables case table shortening.
-This is the default for @option{-Os}.
+@item -mfix-cortex-a53-843419
+@itemx -mno-fix-cortex-a53-843419
+@opindex mfix-cortex-a53-843419
+@opindex mno-fix-cortex-a53-843419
+Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
+This erratum workaround is made at link time and this will only pass the
+corresponding flag to the linker.
-@item -mcompact-casesi
-@opindex mcompact-casesi
-Enable compact casesi pattern.
-This is the default for @option{-Os}.
+@item -mlow-precision-recip-sqrt
+@item -mno-low-precision-recip-sqrt
+@opindex -mlow-precision-recip-sqrt
+@opindex -mno-low-precision-recip-sqrt
+The square root estimate uses two steps instead of three for double-precision,
+and one step instead of two for single-precision.
+Thus reducing latency and precision.
+This is only relevant if @option{-ffast-math} activates
+reciprocal square root estimate instructions.
+Which in turn depends on the target processor.
-@item -mno-cond-exec
-@opindex mno-cond-exec
-Disable ARCompact specific pass to generate conditional execution instructions.
-Due to delay slot scheduling and interactions between operand numbers,
-literal sizes, instruction lengths, and the support for conditional execution,
-the target-independent pass to generate conditional execution is often lacking,
-so the ARC port has kept a special pass around that tries to find more
-conditional execution generating opportunities after register allocation,
-branch shortening, and delay slot scheduling have been done. This pass
-generally, but not always, improves performance and code size, at the cost of
-extra compilation time, which is why there is an option to switch it off.
-If you have a problem with call instructions exceeding their allowable
-offset range because they are conditionalized, you should consider using
-@option{-mmedium-calls} instead.
+@item -march=@var{name}
+@opindex march
+Specify the name of the target architecture and, optionally, one or
+more feature modifiers. This option has the form
+@option{-march=@var{arch}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}.
-@item -mearly-cbranchsi
-@opindex mearly-cbranchsi
-Enable pre-reload use of the cbranchsi pattern.
+The permissible values for @var{arch} are @samp{armv8-a},
+@samp{armv8.1-a} or @var{native}.
-@item -mexpand-adddi
-@opindex mexpand-adddi
-Expand @code{adddi3} and @code{subdi3} at rtl generation time into
-@code{add.f}, @code{adc} etc.
+The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
+support for the ARMv8.1 architecture extension. In particular, it
+enables the @samp{+crc} and @samp{+lse} features.
-@item -mindexed-loads
-@opindex mindexed-loads
-Enable the use of indexed loads. This can be problematic because some
-optimizers then assume that indexed stores exist, which is not
-the case.
+The value @samp{native} is available on native AArch64 GNU/Linux and
+causes the compiler to pick the architecture of the host system. This
+option has no effect if the compiler is unable to recognize the
+architecture of the host system,
-@item -mlra
-@opindex mlra
-Enable Local Register Allocation. This is still experimental for ARC,
-so by default the compiler uses standard reload
-(i.e. @option{-mno-lra}).
+The permissible values for @var{feature} are listed in the sub-section
+on @ref{aarch64-feature-modifiers,,@option{-march} and @option{-mcpu}
+Feature Modifiers}. Where conflicting feature modifiers are
+specified, the right-most feature is used.
-@item -mlra-priority-none
-@opindex mlra-priority-none
-Don't indicate any priority for target registers.
+GCC uses @var{name} to determine what kind of instructions it can emit
+when generating assembly code. If @option{-march} is specified
+without either of @option{-mtune} or @option{-mcpu} also being
+specified, the code is tuned to perform well across a range of target
+processors implementing the target architecture.
-@item -mlra-priority-compact
-@opindex mlra-priority-compact
-Indicate target register priority for r0..r3 / r12..r15.
+@item -mtune=@var{name}
+@opindex mtune
+Specify the name of the target processor for which GCC should tune the
+performance of the code. Permissible values for this option are:
+@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
+@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx},
+@samp{xgene1}.
-@item -mlra-priority-noncompact
-@opindex mlra-priority-noncompact
-Reduce target regsiter priority for r0..r3 / r12..r15.
+Additionally, this option can specify that GCC should tune the performance
+of the code for a big.LITTLE system. Permissible values for this
+option are: @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
-@item -mno-millicode
-@opindex mno-millicode
-When optimizing for size (using @option{-Os}), prologues and epilogues
-that have to save or restore a large number of registers are often
-shortened by using call to a special function in libgcc; this is
-referred to as a @emph{millicode} call. As these calls can pose
-performance issues, and/or cause linking issues when linking in a
-nonstandard way, this option is provided to turn off millicode call
-generation.
+Additionally on native AArch64 GNU/Linux systems the value
+@samp{native} is available. This option causes the compiler to pick
+the architecture of and tune the performance of the code for the
+processor of the host system. This option has no effect if the
+compiler is unable to recognize the architecture of the host system.
-@item -mmixed-code
-@opindex mmixed-code
-Tweak register allocation to help 16-bit instruction generation.
-This generally has the effect of decreasing the average instruction size
-while increasing the instruction count.
+Where none of @option{-mtune=}, @option{-mcpu=} or @option{-march=}
+are specified, the code is tuned to perform well across a range
+of target processors.
-@item -mq-class
-@opindex mq-class
-Enable 'q' instruction alternatives.
-This is the default for @option{-Os}.
+This option cannot be suffixed by feature modifiers.
-@item -mRcq
-@opindex mRcq
-Enable Rcq constraint handling - most short code generation depends on this.
-This is the default.
+@item -mcpu=@var{name}
+@opindex mcpu
+Specify the name of the target processor, optionally suffixed by one
+or more feature modifiers. This option has the form
+@option{-mcpu=@var{cpu}@r{@{}+@r{[}no@r{]}@var{feature}@r{@}*}}, where
+the permissible values for @var{cpu} are the same as those available
+for @option{-mtune}. The permissible values for @var{feature} are
+documented in the sub-section on
+@ref{aarch64-feature-modifiers,,@option{-march} and @option{-mcpu}
+Feature Modifiers}. Where conflicting feature modifiers are
+specified, the right-most feature is used.
-@item -mRcw
-@opindex mRcw
-Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
-This is the default.
+Additionally on native AArch64 GNU/Linux systems the value
+@samp{native} is available. This option causes the compiler to tune
+the performance of the code for the processor of the host system.
+This option has no effect if the compiler is unable to recognize the
+architecture of the host system.
-@item -msize-level=@var{level}
-@opindex msize-level
-Fine-tune size optimization with regards to instruction lengths and alignment.
-The recognized values for @var{level} are:
-@table @samp
-@item 0
-No size optimization. This level is deprecated and treated like @samp{1}.
+GCC uses @var{name} to determine what kind of instructions it can emit when
+generating assembly code (as if by @option{-march}) and to determine
+the target processor for which to tune for performance (as if
+by @option{-mtune}). Where this option is used in conjunction
+with @option{-march} or @option{-mtune}, those options take precedence
+over the appropriate part of this option.
-@item 1
-Short instructions are used opportunistically.
+@item -moverride=@var{string}
+@opindex moverride
+Override tuning decisions made by the back-end in response to a
+@option{-mtune=} switch. The syntax, semantics, and accepted values
+for @var{string} in this option are not guaranteed to be consistent
+across releases.
-@item 2
-In addition, alignment of loops and of code after barriers are dropped.
+This option is only intended to be useful when developing GCC.
-@item 3
-In addition, optional data alignment is dropped, and the option @option{Os} is enabled.
+@item -mpc-relative-literal-loads
+@opindex mpcrelativeliteralloads
+Enable PC relative literal loads. If this option is used, literal
+pools are assumed to have a range of up to 1MiB and an appropriate
+instruction sequence is used. This option has no impact when used
+with @option{-mcmodel=tiny}.
@end table
-This defaults to @samp{3} when @option{-Os} is in effect. Otherwise,
-the behavior when this is not set is equivalent to level @samp{1}.
-
-@item -mtune=@var{cpu}
-@opindex mtune
-Set instruction scheduling parameters for @var{cpu}, overriding any implied
-by @option{-mcpu=}.
-
-Supported values for @var{cpu} are
+@subsubsection @option{-march} and @option{-mcpu} Feature Modifiers
+@anchor{aarch64-feature-modifiers}
+@cindex @option{-march} feature modifiers
+@cindex @option{-mcpu} feature modifiers
+Feature modifiers used with @option{-march} and @option{-mcpu} can be any of
+the following and their inverses @option{no@var{feature}}:
@table @samp
-@item ARC600
-Tune for ARC600 cpu.
-
-@item ARC601
-Tune for ARC601 cpu.
-
-@item ARC700
-Tune for ARC700 cpu with standard multiplier block.
-
-@item ARC700-xmac
-Tune for ARC700 cpu with XMAC block.
-
-@item ARC725D
-Tune for ARC725D cpu.
-
-@item ARC750D
-Tune for ARC750D cpu.
+@item crc
+Enable CRC extension. This is on by default for
+@option{-march=armv8.1-a}.
+@item crypto
+Enable Crypto extension. This also enables Advanced SIMD and floating-point
+instructions.
+@item fp
+Enable floating-point instructions. This is on by default for all possible
+values for options @option{-march} and @option{-mcpu}.
+@item simd
+Enable Advanced SIMD instructions. This also enables floating-point
+instructions. This is on by default for all possible values for options
+@option{-march} and @option{-mcpu}.
+@item lse
+Enable Large System Extension instructions. This is on by default for
+@option{-march=armv8.1-a}.
@end table
-@item -mmultcost=@var{num}
-@opindex mmultcost
-Cost to assume for a multiply instruction, with @samp{4} being equal to a
-normal instruction.
-
-@item -munalign-prob-threshold=@var{probability}
-@opindex munalign-prob-threshold
-Set probability threshold for unaligning branches.
-When tuning for @samp{ARC700} and optimizing for speed, branches without
-filled delay slot are preferably emitted unaligned and long, unless
-profiling indicates that the probability for the branch to be taken
-is below @var{probability}. @xref{Cross-profiling}.
-The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
+That is, @option{crypto} implies @option{simd} implies @option{fp}.
+Conversely, @option{nofp} (or equivalently, @option{-mgeneral-regs-only})
+implies @option{nosimd} implies @option{nocrypto}.
-@end table
+@node Adapteva Epiphany Options
+@subsection Adapteva Epiphany Options
-The following options are maintained for backward compatibility, but
-are now deprecated and will be removed in a future release:
+These @samp{-m} options are defined for Adapteva Epiphany:
-@c Deprecated options
@table @gcctabopt
+@item -mhalf-reg-file
+@opindex mhalf-reg-file
+Don't allocate any register in the range @code{r32}@dots{}@code{r63}.
+That allows code to run on hardware variants that lack these registers.
-@item -margonaut
-@opindex margonaut
-Obsolete FPX.
+@item -mprefer-short-insn-regs
+@opindex mprefer-short-insn-regs
+Preferrentially allocate registers that allow short instruction generation.
+This can result in increased instruction count, so this may either reduce or
+increase overall code size.
-@item -mbig-endian
-@opindex mbig-endian
-@itemx -EB
-@opindex EB
-Compile code for big endian targets. Use of these options is now
-deprecated. Users wanting big-endian code, should use the
-@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets when
-building the tool chain, for which big-endian is the default.
+@item -mbranch-cost=@var{num}
+@opindex mbranch-cost
+Set the cost of branches to roughly @var{num} ``simple'' instructions.
+This cost is only a heuristic and is not guaranteed to produce
+consistent results across releases.
-@item -mlittle-endian
-@opindex mlittle-endian
-@itemx -EL
-@opindex EL
-Compile code for little endian targets. Use of these options is now
-deprecated. Users wanting little-endian code should use the
-@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets when
-building the tool chain, for which little-endian is the default.
+@item -mcmove
+@opindex mcmove
+Enable the generation of conditional moves.
-@item -mbarrel_shifter
-@opindex mbarrel_shifter
-Replaced by @option{-mbarrel-shifter}.
+@item -mnops=@var{num}
+@opindex mnops
+Emit @var{num} NOPs before every other generated instruction.
-@item -mdpfp_compact
-@opindex mdpfp_compact
-Replaced by @option{-mdpfp-compact}.
+@item -mno-soft-cmpsf
+@opindex mno-soft-cmpsf
+For single-precision floating-point comparisons, emit an @code{fsub} instruction
+and test the flags. This is faster than a software comparison, but can
+get incorrect results in the presence of NaNs, or when two different small
+numbers are compared such that their difference is calculated as zero.
+The default is @option{-msoft-cmpsf}, which uses slower, but IEEE-compliant,
+software comparisons.
-@item -mdpfp_fast
-@opindex mdpfp_fast
-Replaced by @option{-mdpfp-fast}.
+@item -mstack-offset=@var{num}
+@opindex mstack-offset
+Set the offset between the top of the stack and the stack pointer.
+E.g., a value of 8 means that the eight bytes in the range @code{sp+0@dots{}sp+7}
+can be used by leaf functions without stack allocation.
+Values other than @samp{8} or @samp{16} are untested and unlikely to work.
+Note also that this option changes the ABI; compiling a program with a
+different stack offset than the libraries have been compiled with
+generally does not work.
+This option can be useful if you want to evaluate if a different stack
+offset would give you better code, but to actually use a different stack
+offset to build working programs, it is recommended to configure the
+toolchain with the appropriate @option{--with-stack-offset=@var{num}} option.
-@item -mdsp_packa
-@opindex mdsp_packa
-Replaced by @option{-mdsp-packa}.
+@item -mno-round-nearest
+@opindex mno-round-nearest
+Make the scheduler assume that the rounding mode has been set to
+truncating. The default is @option{-mround-nearest}.
-@item -mEA
-@opindex mEA
-Replaced by @option{-mea}.
+@item -mlong-calls
+@opindex mlong-calls
+If not otherwise specified by an attribute, assume all calls might be beyond
+the offset range of the @code{b} / @code{bl} instructions, and therefore load the
+function address into a register before performing a (otherwise direct) call.
+This is the default.
-@item -mmac_24
-@opindex mmac_24
-Replaced by @option{-mmac-24}.
+@item -mshort-calls
+@opindex short-calls
+If not otherwise specified by an attribute, assume all direct calls are
+in the range of the @code{b} / @code{bl} instructions, so use these instructions
+for direct calls. The default is @option{-mlong-calls}.
-@item -mmac_d16
-@opindex mmac_d16
-Replaced by @option{-mmac-d16}.
+@item -msmall16
+@opindex msmall16
+Assume addresses can be loaded as 16-bit unsigned values. This does not
+apply to function addresses for which @option{-mlong-calls} semantics
+are in effect.
-@item -mspfp_compact
-@opindex mspfp_compact
-Replaced by @option{-mspfp-compact}.
+@item -mfp-mode=@var{mode}
+@opindex mfp-mode
+Set the prevailing mode of the floating-point unit.
+This determines the floating-point mode that is provided and expected
+at function call and return time. Making this mode match the mode you
+predominantly need at function start can make your programs smaller and
+faster by avoiding unnecessary mode switches.
-@item -mspfp_fast
-@opindex mspfp_fast
-Replaced by @option{-mspfp-fast}.
+@var{mode} can be set to one the following values:
-@item -mtune=@var{cpu}
-@opindex mtune
-Values @samp{arc600}, @samp{arc601}, @samp{arc700} and
-@samp{arc700-xmac} for @var{cpu} are replaced by @samp{ARC600},
-@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively
+@table @samp
+@item caller
+Any mode at function entry is valid, and retained or restored when
+the function returns, and when it calls other functions.
+This mode is useful for compiling libraries or other compilation units
+you might want to incorporate into different programs with different
+prevailing FPU modes, and the convenience of being able to use a single
+object file outweighs the size and speed overhead for any extra
+mode switching that might be needed, compared with what would be needed
+with a more specific choice of prevailing FPU mode.
-@item -multcost=@var{num}
-@opindex multcost
-Replaced by @option{-mmultcost}.
+@item truncate
+This is the mode used for floating-point calculations with
+truncating (i.e.@: round towards zero) rounding mode. That includes
+conversion from floating point to integer.
+
+@item round-nearest
+This is the mode used for floating-point calculations with
+round-to-nearest-or-even rounding mode.
+@item int
+This is the mode used to perform integer calculations in the FPU, e.g.@:
+integer multiply, or integer multiply-and-accumulate.
@end table
-@node ARM Options
-@subsection ARM Options
-@cindex ARM options
+The default is @option{-mfp-mode=caller}
-These @samp{-m} options are defined for the ARM port:
+@item -mnosplit-lohi
+@itemx -mno-postinc
+@itemx -mno-postmodify
+@opindex mnosplit-lohi
+@opindex mno-postinc
+@opindex mno-postmodify
+Code generation tweaks that disable, respectively, splitting of 32-bit
+loads, generation of post-increment addresses, and generation of
+post-modify addresses. The defaults are @option{msplit-lohi},
+@option{-mpost-inc}, and @option{-mpost-modify}.
-@table @gcctabopt
-@item -mabi=@var{name}
-@opindex mabi
-Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu},
-@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}.
+@item -mnovect-double
+@opindex mno-vect-double
+Change the preferred SIMD mode to SImode. The default is
+@option{-mvect-double}, which uses DImode as preferred SIMD mode.
-@item -mapcs-frame
-@opindex mapcs-frame
-Generate a stack frame that is compliant with the ARM Procedure Call
-Standard for all functions, even if this is not strictly necessary for
-correct execution of the code. Specifying @option{-fomit-frame-pointer}
-with this option causes the stack frames not to be generated for
-leaf functions. The default is @option{-mno-apcs-frame}.
-This option is deprecated.
+@item -max-vect-align=@var{num}
+@opindex max-vect-align
+The maximum alignment for SIMD vector mode types.
+@var{num} may be 4 or 8. The default is 8.
+Note that this is an ABI change, even though many library function
+interfaces are unaffected if they don't use SIMD vector modes
+in places that affect size and/or alignment of relevant types.
-@item -mapcs
-@opindex mapcs
-This is a synonym for @option{-mapcs-frame} and is deprecated.
+@item -msplit-vecmove-early
+@opindex msplit-vecmove-early
+Split vector moves into single word moves before reload. In theory this
+can give better register allocation, but so far the reverse seems to be
+generally the case.
-@ignore
-@c not currently implemented
-@item -mapcs-stack-check
-@opindex mapcs-stack-check
-Generate code to check the amount of stack space available upon entry to
-every function (that actually uses some stack space). If there is
-insufficient space available then either the function
-@code{__rt_stkovf_split_small} or @code{__rt_stkovf_split_big} is
-called, depending upon the amount of stack space required. The runtime
-system is required to provide these functions. The default is
-@option{-mno-apcs-stack-check}, since this produces smaller code.
+@item -m1reg-@var{reg}
+@opindex m1reg-
+Specify a register to hold the constant @minus{}1, which makes loading small negative
+constants and certain bitmasks faster.
+Allowable values for @var{reg} are @samp{r43} and @samp{r63},
+which specify use of that register as a fixed register,
+and @samp{none}, which means that no register is used for this
+purpose. The default is @option{-m1reg-none}.
-@c not currently implemented
-@item -mapcs-float
-@opindex mapcs-float
-Pass floating-point arguments using the floating-point registers. This is
-one of the variants of the APCS@. This option is recommended if the
-target hardware has a floating-point unit or if a lot of floating-point
-arithmetic is going to be performed by the code. The default is
-@option{-mno-apcs-float}, since the size of integer-only code is
-slightly increased if @option{-mapcs-float} is used.
+@end table
-@c not currently implemented
-@item -mapcs-reentrant
-@opindex mapcs-reentrant
-Generate reentrant, position-independent code. The default is
-@option{-mno-apcs-reentrant}.
-@end ignore
+@node ARC Options
+@subsection ARC Options
+@cindex ARC options
-@item -mthumb-interwork
-@opindex mthumb-interwork
-Generate code that supports calling between the ARM and Thumb
-instruction sets. Without this option, on pre-v5 architectures, the
-two instruction sets cannot be reliably used inside one program. The
-default is @option{-mno-thumb-interwork}, since slightly larger code
-is generated when @option{-mthumb-interwork} is specified. In AAPCS
-configurations this option is meaningless.
+The following options control the architecture variant for which code
+is being compiled:
-@item -mno-sched-prolog
-@opindex mno-sched-prolog
-Prevent the reordering of instructions in the function prologue, or the
-merging of those instruction with the instructions in the function's
-body. This means that all functions start with a recognizable set
-of instructions (or in fact one of a choice from a small set of
-different function prologues), and this information can be used to
-locate the start of functions inside an executable piece of code. The
-default is @option{-msched-prolog}.
+@c architecture variants
+@table @gcctabopt
-@item -mfloat-abi=@var{name}
-@opindex mfloat-abi
-Specifies which floating-point ABI to use. Permissible values
-are: @samp{soft}, @samp{softfp} and @samp{hard}.
+@item -mbarrel-shifter
+@opindex mbarrel-shifter
+Generate instructions supported by barrel shifter. This is the default
+unless @option{-mcpu=ARC601} or @samp{-mcpu=ARCEM} is in effect.
-Specifying @samp{soft} causes GCC to generate output containing
-library calls for floating-point operations.
-@samp{softfp} allows the generation of code using hardware floating-point
-instructions, but still uses the soft-float calling conventions.
-@samp{hard} allows generation of floating-point instructions
-and uses FPU-specific calling conventions.
+@item -mcpu=@var{cpu}
+@opindex mcpu
+Set architecture type, register usage, and instruction scheduling
+parameters for @var{cpu}. There are also shortcut alias options
+available for backward compatibility and convenience. Supported
+values for @var{cpu} are
-The default depends on the specific target configuration. Note that
-the hard-float and soft-float ABIs are not link-compatible; you must
-compile your entire program with the same ABI, and link with a
-compatible set of libraries.
+@table @samp
+@opindex mA6
+@opindex mARC600
+@item ARC600
+@item arc600
+Compile for ARC600. Aliases: @option{-mA6}, @option{-mARC600}.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a processor running in little-endian mode. This is
-the default for all standard configurations.
+@item ARC601
+@item arc601
+@opindex mARC601
+Compile for ARC601. Alias: @option{-mARC601}.
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a processor running in big-endian mode; the default is
-to compile code for a little-endian processor.
+@item ARC700
+@item arc700
+@opindex mA7
+@opindex mARC700
+Compile for ARC700. Aliases: @option{-mA7}, @option{-mARC700}.
+This is the default when configured with @option{--with-cpu=arc700}@.
-@item -march=@var{name}
-@opindex march
-This specifies the name of the target ARM architecture. GCC uses this
-name to determine what kind of instructions it can emit when generating
-assembly code. This option can be used in conjunction with or instead
-of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
-@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
-@samp{armv6}, @samp{armv6j},
-@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
-@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
-@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
-@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
+@item ARCEM
+@item arcem
+Compile for ARC EM.
-@option{-march=armv7ve} is the armv7-a architecture with virtualization
-extensions.
+@item ARCHS
+@item archs
+Compile for ARC HS.
+@end table
-@option{-march=armv8-a+crc} enables code generation for the ARMv8-A
-architecture together with the optional CRC32 extensions.
+@item -mdpfp
+@opindex mdpfp
+@itemx -mdpfp-compact
+@opindex mdpfp-compact
+FPX: Generate Double Precision FPX instructions, tuned for the compact
+implementation.
-@option{-march=native} causes the compiler to auto-detect the architecture
-of the build computer. At present, this feature is only supported on
-GNU/Linux, and not all architectures are recognized. If the auto-detect
-is unsuccessful the option has no effect.
+@item -mdpfp-fast
+@opindex mdpfp-fast
+FPX: Generate Double Precision FPX instructions, tuned for the fast
+implementation.
-@item -mtune=@var{name}
-@opindex mtune
-This option specifies the name of the target ARM processor for
-which GCC should tune the performance of the code.
-For some ARM implementations better performance can be obtained by using
-this option.
-Permissible names are: @samp{arm2}, @samp{arm250},
-@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
-@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
-@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
-@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
-@samp{arm720},
-@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm7tdmi-s},
-@samp{arm710t}, @samp{arm720t}, @samp{arm740t},
-@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
-@samp{strongarm1110},
-@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
-@samp{arm920t}, @samp{arm922t}, @samp{arm946e-s}, @samp{arm966e-s},
-@samp{arm968e-s}, @samp{arm926ej-s}, @samp{arm940t}, @samp{arm9tdmi},
-@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ej-s},
-@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
-@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
-@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
-@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
-@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
-@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
-@samp{cortex-r4},
-@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
-@samp{cortex-m4},
-@samp{cortex-m3},
-@samp{cortex-m1},
-@samp{cortex-m0},
-@samp{cortex-m0plus},
-@samp{cortex-m1.small-multiply},
-@samp{cortex-m0.small-multiply},
-@samp{cortex-m0plus.small-multiply},
-@samp{exynos-m1},
-@samp{qdf24xx},
-@samp{marvell-pj4},
-@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
-@samp{fa526}, @samp{fa626},
-@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
-@samp{xgene1}.
+@item -mno-dpfp-lrsr
+@opindex mno-dpfp-lrsr
+Disable LR and SR instructions from using FPX extension aux registers.
-Additionally, this option can specify that GCC should tune the performance
-of the code for a big.LITTLE system. Permissible names are:
-@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
-@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
+@item -mea
+@opindex mea
+Generate Extended arithmetic instructions. Currently only
+@code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are
+supported. This is always enabled for @option{-mcpu=ARC700}.
-@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
-performance for a blend of processors within architecture @var{arch}.
-The aim is to generate code that run well on the current most popular
-processors, balancing between optimizations that benefit some CPUs in the
-range, and avoiding performance pitfalls of other CPUs. The effects of
-this option may change in future GCC versions as CPU models come and go.
+@item -mno-mpy
+@opindex mno-mpy
+Do not generate mpy instructions for ARC700.
-@option{-mtune=native} causes the compiler to auto-detect the CPU
-of the build computer. At present, this feature is only supported on
-GNU/Linux, and not all architectures are recognized. If the auto-detect is
-unsuccessful the option has no effect.
+@item -mmul32x16
+@opindex mmul32x16
+Generate 32x16 bit multiply and mac instructions.
-@item -mcpu=@var{name}
-@opindex mcpu
-This specifies the name of the target ARM processor. GCC uses this name
-to derive the name of the target ARM architecture (as if specified
-by @option{-march}) and the ARM processor type for which to tune for
-performance (as if specified by @option{-mtune}). Where this option
-is used in conjunction with @option{-march} or @option{-mtune},
-those options take precedence over the appropriate part of this option.
+@item -mmul64
+@opindex mmul64
+Generate mul64 and mulu64 instructions. Only valid for @option{-mcpu=ARC600}.
-Permissible names for this option are the same as those for
-@option{-mtune}.
+@item -mnorm
+@opindex mnorm
+Generate norm instruction. This is the default if @option{-mcpu=ARC700}
+is in effect.
-@option{-mcpu=generic-@var{arch}} is also permissible, and is
-equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
-See @option{-mtune} for more information.
+@item -mspfp
+@opindex mspfp
+@itemx -mspfp-compact
+@opindex mspfp-compact
+FPX: Generate Single Precision FPX instructions, tuned for the compact
+implementation.
-@option{-mcpu=native} causes the compiler to auto-detect the CPU
-of the build computer. At present, this feature is only supported on
-GNU/Linux, and not all architectures are recognized. If the auto-detect
-is unsuccessful the option has no effect.
+@item -mspfp-fast
+@opindex mspfp-fast
+FPX: Generate Single Precision FPX instructions, tuned for the fast
+implementation.
-@item -mfpu=@var{name}
-@opindex mfpu
-This specifies what floating-point hardware (or hardware emulation) is
-available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
-@samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
-@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
-@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
-@samp{fpv5-d16}, @samp{fpv5-sp-d16},
-@samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
+@item -msimd
+@opindex msimd
+Enable generation of ARC SIMD instructions via target-specific
+builtins. Only valid for @option{-mcpu=ARC700}.
-If @option{-msoft-float} is specified this specifies the format of
-floating-point values.
+@item -msoft-float
+@opindex msoft-float
+This option ignored; it is provided for compatibility purposes only.
+Software floating point code is emitted by default, and this default
+can overridden by FPX options; @samp{mspfp}, @samp{mspfp-compact}, or
+@samp{mspfp-fast} for single precision, and @samp{mdpfp},
+@samp{mdpfp-compact}, or @samp{mdpfp-fast} for double precision.
-If the selected floating-point hardware includes the NEON extension
-(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
-operations are not generated by GCC's auto-vectorization pass unless
-@option{-funsafe-math-optimizations} is also specified. This is
-because NEON hardware does not fully implement the IEEE 754 standard for
-floating-point arithmetic (in particular denormal values are treated as
-zero), so the use of NEON instructions may lead to a loss of precision.
+@item -mswap
+@opindex mswap
+Generate swap instructions.
-You can also set the fpu name at function level by using the @code{target("fpu=")} function attributes (@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}).
+@item -matomic
+@opindex matomic
+This enables Locked Load/Store Conditional extension to implement
+atomic memopry built-in functions. Not available for ARC 6xx or ARC
+EM cores.
-@item -mfp16-format=@var{name}
-@opindex mfp16-format
-Specify the format of the @code{__fp16} half-precision floating-point type.
-Permissible names are @samp{none}, @samp{ieee}, and @samp{alternative};
-the default is @samp{none}, in which case the @code{__fp16} type is not
-defined. @xref{Half-Precision}, for more information.
+@item -mdiv-rem
+@opindex mdiv-rem
+Enable DIV/REM instructions for ARCv2 cores.
-@item -mstructure-size-boundary=@var{n}
-@opindex mstructure-size-boundary
-The sizes of all structures and unions are rounded up to a multiple
-of the number of bits set by this option. Permissible values are 8, 32
-and 64. The default value varies for different toolchains. For the COFF
-targeted toolchain the default value is 8. A value of 64 is only allowed
-if the underlying ABI supports it.
+@item -mcode-density
+@opindex mcode-density
+Enable code density instructions for ARC EM, default on for ARC HS.
-Specifying a larger number can produce faster, more efficient code, but
-can also increase the size of the program. Different values are potentially
-incompatible. Code compiled with one value cannot necessarily expect to
-work with code or libraries compiled with another value, if they exchange
-information using structures or unions.
+@item -mmpy-option=@var{multo}
+@opindex mmpy-option
+Compile ARCv2 code with a multiplier design option. @samp{wlh1} is
+the default value. The recognized values for @var{multo} are:
-@item -mabort-on-noreturn
-@opindex mabort-on-noreturn
-Generate a call to the function @code{abort} at the end of a
-@code{noreturn} function. It is executed if the function tries to
-return.
+@table @samp
+@item 0
+No multiplier available.
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Tells the compiler to perform function calls by first loading the
-address of the function into a register and then performing a subroutine
-call on this register. This switch is needed if the target function
-lies outside of the 64-megabyte addressing range of the offset-based
-version of subroutine call instruction.
+@item 1
+@opindex w
+The multiply option is set to w: 16x16 multiplier, fully pipelined.
+The following instructions are enabled: MPYW, and MPYUW.
-Even if this switch is enabled, not all function calls are turned
-into long calls. The heuristic is that static functions, functions
-that have the @code{short_call} attribute, functions that are inside
-the scope of a @code{#pragma no_long_calls} directive, and functions whose
-definitions have already been compiled within the current compilation
-unit are not turned into long calls. The exceptions to this rule are
-that weak function definitions, functions with the @code{long_call}
-attribute or the @code{section} attribute, and functions that are within
-the scope of a @code{#pragma long_calls} directive are always
-turned into long calls.
+@item 2
+@opindex wlh1
+The multiply option is set to wlh1: 32x32 multiplier, fully
+pipelined (1 stage). The following instructions are additionaly
+enabled: MPY, MPYU, MPYM, MPYMU, and MPY_S.
-This feature is not enabled by default. Specifying
-@option{-mno-long-calls} restores the default behavior, as does
-placing the function calls within the scope of a @code{#pragma
-long_calls_off} directive. Note these switches have no effect on how
-the compiler generates code to handle function calls via function
-pointers.
+@item 3
+@opindex wlh2
+The multiply option is set to wlh2: 32x32 multiplier, fully pipelined
+(2 stages). The following instructions are additionaly enabled: MPY,
+MPYU, MPYM, MPYMU, and MPY_S.
-@item -msingle-pic-base
-@opindex msingle-pic-base
-Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The runtime system is
-responsible for initializing this register with an appropriate value
-before execution begins.
+@item 4
+@opindex wlh3
+The multiply option is set to wlh3: Two 16x16 multiplier, blocking,
+sequential. The following instructions are additionaly enabled: MPY,
+MPYU, MPYM, MPYMU, and MPY_S.
-@item -mpic-register=@var{reg}
-@opindex mpic-register
-Specify the register to be used for PIC addressing.
-For standard PIC base case, the default is any suitable register
-determined by compiler. For single PIC base case, the default is
-@samp{R9} if target is EABI based or stack-checking is enabled,
-otherwise the default is @samp{R10}.
-
-@item -mpic-data-is-text-relative
-@opindex mpic-data-is-text-relative
-Assume that each data segments are relative to text segment at load time.
-Therefore, it permits addressing data using PC-relative operations.
-This option is on by default for targets other than VxWorks RTP.
-
-@item -mpoke-function-name
-@opindex mpoke-function-name
-Write the name of each function into the text section, directly
-preceding the function prologue. The generated code is similar to this:
-
-@smallexample
- t0
- .ascii "arm_poke_function_name", 0
- .align
- t1
- .word 0xff000000 + (t1 - t0)
- arm_poke_function_name
- mov ip, sp
- stmfd sp!, @{fp, ip, lr, pc@}
- sub fp, ip, #4
-@end smallexample
+@item 5
+@opindex wlh4
+The multiply option is set to wlh4: One 16x16 multiplier, blocking,
+sequential. The following instructions are additionaly enabled: MPY,
+MPYU, MPYM, MPYMU, and MPY_S.
-When performing a stack backtrace, code can inspect the value of
-@code{pc} stored at @code{fp + 0}. If the trace function then looks at
-location @code{pc - 12} and the top 8 bits are set, then we know that
-there is a function name embedded immediately preceding this location
-and has length @code{((pc[-3]) & 0xff000000)}.
+@item 6
+@opindex wlh5
+The multiply option is set to wlh5: One 32x4 multiplier, blocking,
+sequential. The following instructions are additionaly enabled: MPY,
+MPYU, MPYM, MPYMU, and MPY_S.
-@item -mthumb
-@itemx -marm
-@opindex marm
-@opindex mthumb
+@end table
-Select between generating code that executes in ARM and Thumb
-states. The default for most configurations is to generate code
-that executes in ARM state, but the default can be changed by
-configuring GCC with the @option{--with-mode=}@var{state}
-configure option.
+This option is only available for ARCv2 cores@.
-You can also override the ARM and Thumb mode for each function
-by using the @code{target("thumb")} and @code{target("arm")} function attributes
-(@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}).
+@end table
-@item -mtpcs-frame
-@opindex mtpcs-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all non-leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-tpcs-frame}.
+The following options are passed through to the assembler, and also
+define preprocessor macro symbols.
-@item -mtpcs-leaf-frame
-@opindex mtpcs-leaf-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
+@c Flags used by the assembler, but for which we define preprocessor
+@c macro symbols as well.
+@table @gcctabopt
+@item -mdsp-packa
+@opindex mdsp-packa
+Passed down to the assembler to enable the DSP Pack A extensions.
+Also sets the preprocessor symbol @code{__Xdsp_packa}.
-@item -mcallee-super-interworking
-@opindex mcallee-super-interworking
-Gives all externally visible functions in the file being compiled an ARM
-instruction set header which switches to Thumb mode before executing the
-rest of the function. This allows these functions to be called from
-non-interworking code. This option is not valid in AAPCS configurations
-because interworking is enabled by default.
+@item -mdvbf
+@opindex mdvbf
+Passed down to the assembler to enable the dual viterbi butterfly
+extension. Also sets the preprocessor symbol @code{__Xdvbf}.
-@item -mcaller-super-interworking
-@opindex mcaller-super-interworking
-Allows calls via function pointers (including virtual functions) to
-execute correctly regardless of whether the target code has been
-compiled for interworking or not. There is a small overhead in the cost
-of executing a function pointer if this option is enabled. This option
-is not valid in AAPCS configurations because interworking is enabled
-by default.
+@c ARC700 4.10 extension instruction
+@item -mlock
+@opindex mlock
+Passed down to the assembler to enable the Locked Load/Store
+Conditional extension. Also sets the preprocessor symbol
+@code{__Xlock}.
-@item -mtp=@var{name}
-@opindex mtp
-Specify the access model for the thread local storage pointer. The valid
-models are @samp{soft}, which generates calls to @code{__aeabi_read_tp},
-@samp{cp15}, which fetches the thread pointer from @code{cp15} directly
-(supported in the arm6k architecture), and @samp{auto}, which uses the
-best available method for the selected processor. The default setting is
-@samp{auto}.
+@item -mmac-d16
+@opindex mmac-d16
+Passed down to the assembler. Also sets the preprocessor symbol
+@code{__Xxmac_d16}.
-@item -mtls-dialect=@var{dialect}
-@opindex mtls-dialect
-Specify the dialect to use for accessing thread local storage. Two
-@var{dialect}s are supported---@samp{gnu} and @samp{gnu2}. The
-@samp{gnu} dialect selects the original GNU scheme for supporting
-local and global dynamic TLS models. The @samp{gnu2} dialect
-selects the GNU descriptor scheme, which provides better performance
-for shared libraries. The GNU descriptor scheme is compatible with
-the original scheme, but does require new assembler, linker and
-library support. Initial and local exec TLS models are unaffected by
-this option and always use the original scheme.
+@item -mmac-24
+@opindex mmac-24
+Passed down to the assembler. Also sets the preprocessor symbol
+@code{__Xxmac_24}.
-@item -mword-relocations
-@opindex mword-relocations
-Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).
-This is enabled by default on targets (uClinux, SymbianOS) where the runtime
-loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
-is specified.
+@c ARC700 4.10 extension instruction
+@item -mrtsc
+@opindex mrtsc
+Passed down to the assembler to enable the 64-bit Time-Stamp Counter
+extension instruction. Also sets the preprocessor symbol
+@code{__Xrtsc}.
-@item -mfix-cortex-m3-ldrd
-@opindex mfix-cortex-m3-ldrd
-Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
-with overlapping destination and base registers are used. This option avoids
-generating these instructions. This option is enabled by default when
-@option{-mcpu=cortex-m3} is specified.
+@c ARC700 4.10 extension instruction
+@item -mswape
+@opindex mswape
+Passed down to the assembler to enable the swap byte ordering
+extension instruction. Also sets the preprocessor symbol
+@code{__Xswape}.
-@item -munaligned-access
-@itemx -mno-unaligned-access
-@opindex munaligned-access
-@opindex mno-unaligned-access
-Enables (or disables) reading and writing of 16- and 32- bit values
-from addresses that are not 16- or 32- bit aligned. By default
-unaligned access is disabled for all pre-ARMv6 and all ARMv6-M
-architectures, and enabled for all other architectures. If unaligned
-access is not enabled then words in packed data structures are
-accessed a byte at a time.
+@item -mtelephony
+@opindex mtelephony
+Passed down to the assembler to enable dual and single operand
+instructions for telephony. Also sets the preprocessor symbol
+@code{__Xtelephony}.
-The ARM attribute @code{Tag_CPU_unaligned_access} is set in the
-generated object file to either true or false, depending upon the
-setting of this option. If unaligned access is enabled then the
-preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} is also
-defined.
+@item -mxy
+@opindex mxy
+Passed down to the assembler to enable the XY Memory extension. Also
+sets the preprocessor symbol @code{__Xxy}.
-@item -mneon-for-64bits
-@opindex mneon-for-64bits
-Enables using Neon to handle scalar 64-bits operations. This is
-disabled by default since the cost of moving data from core registers
-to Neon is high.
+@end table
-@item -mslow-flash-data
-@opindex mslow-flash-data
-Assume loading data from flash is slower than fetching instruction.
-Therefore literal load is minimized for better performance.
-This option is only supported when compiling for ARMv7 M-profile and
-off by default.
+The following options control how the assembly code is annotated:
-@item -masm-syntax-unified
-@opindex masm-syntax-unified
-Assume inline assembler is using unified asm syntax. The default is
-currently off which implies divided syntax. This option has no impact
-on Thumb2. However, this may change in future releases of GCC.
-Divided syntax should be considered deprecated.
+@c Assembly annotation options
+@table @gcctabopt
+@item -misize
+@opindex misize
+Annotate assembler instructions with estimated addresses.
-@item -mrestrict-it
-@opindex mrestrict-it
-Restricts generation of IT blocks to conform to the rules of ARMv8.
-IT blocks can only contain a single 16-bit instruction from a select
-set of instructions. This option is on by default for ARMv8 Thumb mode.
+@item -mannotate-align
+@opindex mannotate-align
+Explain what alignment considerations lead to the decision to make an
+instruction short or long.
-@item -mprint-tune-info
-@opindex mprint-tune-info
-Print CPU tuning information as comment in assembler file. This is
-an option used only for regression testing of the compiler and not
-intended for ordinary use in compiling code. This option is disabled
-by default.
@end table
-@node AVR Options
-@subsection AVR Options
-@cindex AVR Options
-
-These options are defined for AVR implementations:
+The following options are passed through to the linker:
+@c options passed through to the linker
@table @gcctabopt
-@item -mmcu=@var{mcu}
-@opindex mmcu
-Specify Atmel AVR instruction set architectures (ISA) or MCU type.
+@item -marclinux
+@opindex marclinux
+Passed through to the linker, to specify use of the @code{arclinux} emulation.
+This option is enabled by default in tool chains built for
+@w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets
+when profiling is not requested.
-The default for this option is@tie{}@samp{avr2}.
+@item -marclinux_prof
+@opindex marclinux_prof
+Passed through to the linker, to specify use of the
+@code{arclinux_prof} emulation. This option is enabled by default in
+tool chains built for @w{@code{arc-linux-uclibc}} and
+@w{@code{arceb-linux-uclibc}} targets when profiling is requested.
-GCC supports the following AVR devices and ISAs:
+@end table
-@include avr-mmcu.texi
+The following options control the semantics of generated code:
-@item -maccumulate-args
-@opindex maccumulate-args
-Accumulate outgoing function arguments and acquire/release the needed
-stack space for outgoing function arguments once in function
-prologue/epilogue. Without this option, outgoing arguments are pushed
-before calling a function and popped afterwards.
+@c semantically relevant code generation options
+@table @gcctabopt
+@item -mlong-calls
+@opindex mlong-calls
+Generate call insns as register indirect calls, thus providing access
+to the full 32-bit address range.
-Popping the arguments after the function call can be expensive on
-AVR so that accumulating the stack space might lead to smaller
-executables because arguments need not to be removed from the
-stack after such a function call.
+@item -mmedium-calls
+@opindex mmedium-calls
+Don't use less than 25 bit addressing range for calls, which is the
+offset available for an unconditional branch-and-link
+instruction. Conditional execution of function calls is suppressed, to
+allow use of the 25-bit range, rather than the 21-bit range with
+conditional branch-and-link. This is the default for tool chains built
+for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets.
-This option can lead to reduced code size for functions that perform
-several calls to functions that get their arguments on the stack like
-calls to printf-like functions.
+@item -mno-sdata
+@opindex mno-sdata
+Do not generate sdata references. This is the default for tool chains
+built for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}}
+targets.
-@item -mbranch-cost=@var{cost}
-@opindex mbranch-cost
-Set the branch costs for conditional branch instructions to
-@var{cost}. Reasonable values for @var{cost} are small, non-negative
-integers. The default branch cost is 0.
+@item -mucb-mcount
+@opindex mucb-mcount
+Instrument with mcount calls as used in UCB code. I.e. do the
+counting in the callee, not the caller. By default ARC instrumentation
+counts in the caller.
-@item -mcall-prologues
-@opindex mcall-prologues
-Functions prologues/epilogues are expanded as calls to appropriate
-subroutines. Code size is smaller.
+@item -mvolatile-cache
+@opindex mvolatile-cache
+Use ordinarily cached memory accesses for volatile references. This is the
+default.
-@item -mint8
-@opindex mint8
-Assume @code{int} to be 8-bit integer. This affects the sizes of all types: a
-@code{char} is 1 byte, an @code{int} is 1 byte, a @code{long} is 2 bytes,
-and @code{long long} is 4 bytes. Please note that this option does not
-conform to the C standards, but it results in smaller code
-size.
+@item -mno-volatile-cache
+@opindex mno-volatile-cache
+Enable cache bypass for volatile references.
-@item -mn-flash=@var{num}
-@opindex mn-flash
-Assume that the flash memory has a size of
-@var{num} times 64@tie{}KiB.
+@end table
-@item -mno-interrupts
-@opindex mno-interrupts
-Generated code is not compatible with hardware interrupts.
-Code size is smaller.
+The following options fine tune code generation:
+@c code generation tuning options
+@table @gcctabopt
+@item -malign-call
+@opindex malign-call
+Do alignment optimizations for call instructions.
-@item -mrelax
-@opindex mrelax
-Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
-@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
-Setting @option{-mrelax} just adds the @option{--mlink-relax} option to
-the assembler's command line and the @option{--relax} option to the
-linker's command line.
+@item -mauto-modify-reg
+@opindex mauto-modify-reg
+Enable the use of pre/post modify with register displacement.
-Jump relaxing is performed by the linker because jump offsets are not
-known before code is located. Therefore, the assembler code generated by the
-compiler is the same, but the instructions in the executable may
-differ from instructions in the assembler code.
+@item -mbbit-peephole
+@opindex mbbit-peephole
+Enable bbit peephole2.
-Relaxing must be turned on if linker stubs are needed, see the
-section on @code{EIND} and linker stubs below.
+@item -mno-brcc
+@opindex mno-brcc
+This option disables a target-specific pass in @file{arc_reorg} to
+generate @code{BRcc} instructions. It has no effect on @code{BRcc}
+generation driven by the combiner pass.
-@item -mrmw
-@opindex mrmw
-Assume that the device supports the Read-Modify-Write
-instructions @code{XCH}, @code{LAC}, @code{LAS} and @code{LAT}.
+@item -mcase-vector-pcrel
+@opindex mcase-vector-pcrel
+Use pc-relative switch case tables - this enables case table shortening.
+This is the default for @option{-Os}.
-@item -msp8
-@opindex msp8
-Treat the stack pointer register as an 8-bit register,
-i.e.@: assume the high byte of the stack pointer is zero.
-In general, you don't need to set this option by hand.
+@item -mcompact-casesi
+@opindex mcompact-casesi
+Enable compact casesi pattern.
+This is the default for @option{-Os}.
-This option is used internally by the compiler to select and
-build multilibs for architectures @code{avr2} and @code{avr25}.
-These architectures mix devices with and without @code{SPH}.
-For any setting other than @option{-mmcu=avr2} or @option{-mmcu=avr25}
-the compiler driver adds or removes this option from the compiler
-proper's command line, because the compiler then knows if the device
-or architecture has an 8-bit stack pointer and thus no @code{SPH}
-register or not.
+@item -mno-cond-exec
+@opindex mno-cond-exec
+Disable ARCompact specific pass to generate conditional execution instructions.
+Due to delay slot scheduling and interactions between operand numbers,
+literal sizes, instruction lengths, and the support for conditional execution,
+the target-independent pass to generate conditional execution is often lacking,
+so the ARC port has kept a special pass around that tries to find more
+conditional execution generating opportunities after register allocation,
+branch shortening, and delay slot scheduling have been done. This pass
+generally, but not always, improves performance and code size, at the cost of
+extra compilation time, which is why there is an option to switch it off.
+If you have a problem with call instructions exceeding their allowable
+offset range because they are conditionalized, you should consider using
+@option{-mmedium-calls} instead.
-@item -mstrict-X
-@opindex mstrict-X
-Use address register @code{X} in a way proposed by the hardware. This means
-that @code{X} is only used in indirect, post-increment or
-pre-decrement addressing.
+@item -mearly-cbranchsi
+@opindex mearly-cbranchsi
+Enable pre-reload use of the cbranchsi pattern.
-Without this option, the @code{X} register may be used in the same way
-as @code{Y} or @code{Z} which then is emulated by additional
-instructions.
-For example, loading a value with @code{X+const} addressing with a
-small non-negative @code{const < 64} to a register @var{Rn} is
-performed as
+@item -mexpand-adddi
+@opindex mexpand-adddi
+Expand @code{adddi3} and @code{subdi3} at rtl generation time into
+@code{add.f}, @code{adc} etc.
-@example
-adiw r26, const ; X += const
-ld @var{Rn}, X ; @var{Rn} = *X
-sbiw r26, const ; X -= const
-@end example
+@item -mindexed-loads
+@opindex mindexed-loads
+Enable the use of indexed loads. This can be problematic because some
+optimizers then assume that indexed stores exist, which is not
+the case.
-@item -mtiny-stack
-@opindex mtiny-stack
-Only change the lower 8@tie{}bits of the stack pointer.
+@item -mlra
+@opindex mlra
+Enable Local Register Allocation. This is still experimental for ARC,
+so by default the compiler uses standard reload
+(i.e. @option{-mno-lra}).
-@item -nodevicelib
-@opindex nodevicelib
-Don't link against AVR-LibC's device specific library @code{libdev.a}.
+@item -mlra-priority-none
+@opindex mlra-priority-none
+Don't indicate any priority for target registers.
-@item -Waddr-space-convert
-@opindex Waddr-space-convert
-Warn about conversions between address spaces in the case where the
-resulting address space is not contained in the incoming address space.
-@end table
+@item -mlra-priority-compact
+@opindex mlra-priority-compact
+Indicate target register priority for r0..r3 / r12..r15.
-@subsubsection @code{EIND} and Devices with More Than 128 Ki Bytes of Flash
-@cindex @code{EIND}
-Pointers in the implementation are 16@tie{}bits wide.
-The address of a function or label is represented as word address so
-that indirect jumps and calls can target any code address in the
-range of 64@tie{}Ki words.
+@item -mlra-priority-noncompact
+@opindex mlra-priority-noncompact
+Reduce target regsiter priority for r0..r3 / r12..r15.
-In order to facilitate indirect jump on devices with more than 128@tie{}Ki
-bytes of program memory space, there is a special function register called
-@code{EIND} that serves as most significant part of the target address
-when @code{EICALL} or @code{EIJMP} instructions are used.
+@item -mno-millicode
+@opindex mno-millicode
+When optimizing for size (using @option{-Os}), prologues and epilogues
+that have to save or restore a large number of registers are often
+shortened by using call to a special function in libgcc; this is
+referred to as a @emph{millicode} call. As these calls can pose
+performance issues, and/or cause linking issues when linking in a
+nonstandard way, this option is provided to turn off millicode call
+generation.
-Indirect jumps and calls on these devices are handled as follows by
-the compiler and are subject to some limitations:
+@item -mmixed-code
+@opindex mmixed-code
+Tweak register allocation to help 16-bit instruction generation.
+This generally has the effect of decreasing the average instruction size
+while increasing the instruction count.
-@itemize @bullet
+@item -mq-class
+@opindex mq-class
+Enable 'q' instruction alternatives.
+This is the default for @option{-Os}.
-@item
-The compiler never sets @code{EIND}.
+@item -mRcq
+@opindex mRcq
+Enable Rcq constraint handling - most short code generation depends on this.
+This is the default.
-@item
-The compiler uses @code{EIND} implicitely in @code{EICALL}/@code{EIJMP}
-instructions or might read @code{EIND} directly in order to emulate an
-indirect call/jump by means of a @code{RET} instruction.
+@item -mRcw
+@opindex mRcw
+Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
+This is the default.
-@item
-The compiler assumes that @code{EIND} never changes during the startup
-code or during the application. In particular, @code{EIND} is not
-saved/restored in function or interrupt service routine
-prologue/epilogue.
+@item -msize-level=@var{level}
+@opindex msize-level
+Fine-tune size optimization with regards to instruction lengths and alignment.
+The recognized values for @var{level} are:
+@table @samp
+@item 0
+No size optimization. This level is deprecated and treated like @samp{1}.
-@item
-For indirect calls to functions and computed goto, the linker
-generates @emph{stubs}. Stubs are jump pads sometimes also called
-@emph{trampolines}. Thus, the indirect call/jump jumps to such a stub.
-The stub contains a direct jump to the desired address.
+@item 1
+Short instructions are used opportunistically.
-@item
-Linker relaxation must be turned on so that the linker generates
-the stubs correctly in all situations. See the compiler option
-@option{-mrelax} and the linker option @option{--relax}.
-There are corner cases where the linker is supposed to generate stubs
-but aborts without relaxation and without a helpful error message.
+@item 2
+In addition, alignment of loops and of code after barriers are dropped.
-@item
-The default linker script is arranged for code with @code{EIND = 0}.
-If code is supposed to work for a setup with @code{EIND != 0}, a custom
-linker script has to be used in order to place the sections whose
-name start with @code{.trampolines} into the segment where @code{EIND}
-points to.
-
-@item
-The startup code from libgcc never sets @code{EIND}.
-Notice that startup code is a blend of code from libgcc and AVR-LibC.
-For the impact of AVR-LibC on @code{EIND}, see the
-@w{@uref{http://nongnu.org/avr-libc/user-manual/,AVR-LibC user manual}}.
+@item 3
+In addition, optional data alignment is dropped, and the option @option{Os} is enabled.
-@item
-It is legitimate for user-specific startup code to set up @code{EIND}
-early, for example by means of initialization code located in
-section @code{.init3}. Such code runs prior to general startup code
-that initializes RAM and calls constructors, but after the bit
-of startup code from AVR-LibC that sets @code{EIND} to the segment
-where the vector table is located.
-@example
-#include <avr/io.h>
+@end table
-static void
-__attribute__((section(".init3"),naked,used,no_instrument_function))
-init3_set_eind (void)
-@{
- __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
- "out %i0,r24" :: "n" (&EIND) : "r24","memory");
-@}
-@end example
+This defaults to @samp{3} when @option{-Os} is in effect. Otherwise,
+the behavior when this is not set is equivalent to level @samp{1}.
-@noindent
-The @code{__trampolines_start} symbol is defined in the linker script.
+@item -mtune=@var{cpu}
+@opindex mtune
+Set instruction scheduling parameters for @var{cpu}, overriding any implied
+by @option{-mcpu=}.
-@item
-Stubs are generated automatically by the linker if
-the following two conditions are met:
-@itemize @minus
+Supported values for @var{cpu} are
-@item The address of a label is taken by means of the @code{gs} modifier
-(short for @emph{generate stubs}) like so:
-@example
-LDI r24, lo8(gs(@var{func}))
-LDI r25, hi8(gs(@var{func}))
-@end example
-@item The final location of that label is in a code segment
-@emph{outside} the segment where the stubs are located.
-@end itemize
+@table @samp
+@item ARC600
+Tune for ARC600 cpu.
-@item
-The compiler emits such @code{gs} modifiers for code labels in the
-following situations:
-@itemize @minus
-@item Taking address of a function or code label.
-@item Computed goto.
-@item If prologue-save function is used, see @option{-mcall-prologues}
-command-line option.
-@item Switch/case dispatch tables. If you do not want such dispatch
-tables you can specify the @option{-fno-jump-tables} command-line option.
-@item C and C++ constructors/destructors called during startup/shutdown.
-@item If the tools hit a @code{gs()} modifier explained above.
-@end itemize
+@item ARC601
+Tune for ARC601 cpu.
-@item
-Jumping to non-symbolic addresses like so is @emph{not} supported:
+@item ARC700
+Tune for ARC700 cpu with standard multiplier block.
-@example
-int main (void)
-@{
- /* Call function at word address 0x2 */
- return ((int(*)(void)) 0x2)();
-@}
-@end example
+@item ARC700-xmac
+Tune for ARC700 cpu with XMAC block.
-Instead, a stub has to be set up, i.e.@: the function has to be called
-through a symbol (@code{func_4} in the example):
+@item ARC725D
+Tune for ARC725D cpu.
-@example
-int main (void)
-@{
- extern int func_4 (void);
+@item ARC750D
+Tune for ARC750D cpu.
- /* Call function at byte address 0x4 */
- return func_4();
-@}
-@end example
+@end table
-and the application be linked with @option{-Wl,--defsym,func_4=0x4}.
-Alternatively, @code{func_4} can be defined in the linker script.
-@end itemize
+@item -mmultcost=@var{num}
+@opindex mmultcost
+Cost to assume for a multiply instruction, with @samp{4} being equal to a
+normal instruction.
-@subsubsection Handling of the @code{RAMPD}, @code{RAMPX}, @code{RAMPY} and @code{RAMPZ} Special Function Registers
-@cindex @code{RAMPD}
-@cindex @code{RAMPX}
-@cindex @code{RAMPY}
-@cindex @code{RAMPZ}
-Some AVR devices support memories larger than the 64@tie{}KiB range
-that can be accessed with 16-bit pointers. To access memory locations
-outside this 64@tie{}KiB range, the contentent of a @code{RAMP}
-register is used as high part of the address:
-The @code{X}, @code{Y}, @code{Z} address register is concatenated
-with the @code{RAMPX}, @code{RAMPY}, @code{RAMPZ} special function
-register, respectively, to get a wide address. Similarly,
-@code{RAMPD} is used together with direct addressing.
+@item -munalign-prob-threshold=@var{probability}
+@opindex munalign-prob-threshold
+Set probability threshold for unaligning branches.
+When tuning for @samp{ARC700} and optimizing for speed, branches without
+filled delay slot are preferably emitted unaligned and long, unless
+profiling indicates that the probability for the branch to be taken
+is below @var{probability}. @xref{Cross-profiling}.
+The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
-@itemize
-@item
-The startup code initializes the @code{RAMP} special function
-registers with zero.
+@end table
-@item
-If a @ref{AVR Named Address Spaces,named address space} other than
-generic or @code{__flash} is used, then @code{RAMPZ} is set
-as needed before the operation.
+The following options are maintained for backward compatibility, but
+are now deprecated and will be removed in a future release:
-@item
-If the device supports RAM larger than 64@tie{}KiB and the compiler
-needs to change @code{RAMPZ} to accomplish an operation, @code{RAMPZ}
-is reset to zero after the operation.
+@c Deprecated options
+@table @gcctabopt
-@item
-If the device comes with a specific @code{RAMP} register, the ISR
-prologue/epilogue saves/restores that SFR and initializes it with
-zero in case the ISR code might (implicitly) use it.
+@item -margonaut
+@opindex margonaut
+Obsolete FPX.
-@item
-RAM larger than 64@tie{}KiB is not supported by GCC for AVR targets.
-If you use inline assembler to read from locations outside the
-16-bit address range and change one of the @code{RAMP} registers,
-you must reset it to zero after the access.
+@item -mbig-endian
+@opindex mbig-endian
+@itemx -EB
+@opindex EB
+Compile code for big endian targets. Use of these options is now
+deprecated. Users wanting big-endian code, should use the
+@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets when
+building the tool chain, for which big-endian is the default.
-@end itemize
+@item -mlittle-endian
+@opindex mlittle-endian
+@itemx -EL
+@opindex EL
+Compile code for little endian targets. Use of these options is now
+deprecated. Users wanting little-endian code should use the
+@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets when
+building the tool chain, for which little-endian is the default.
-@subsubsection AVR Built-in Macros
+@item -mbarrel_shifter
+@opindex mbarrel_shifter
+Replaced by @option{-mbarrel-shifter}.
-GCC defines several built-in macros so that the user code can test
-for the presence or absence of features. Almost any of the following
-built-in macros are deduced from device capabilities and thus
-triggered by the @option{-mmcu=} command-line option.
+@item -mdpfp_compact
+@opindex mdpfp_compact
+Replaced by @option{-mdpfp-compact}.
-For even more AVR-specific built-in macros see
-@ref{AVR Named Address Spaces} and @ref{AVR Built-in Functions}.
+@item -mdpfp_fast
+@opindex mdpfp_fast
+Replaced by @option{-mdpfp-fast}.
-@table @code
+@item -mdsp_packa
+@opindex mdsp_packa
+Replaced by @option{-mdsp-packa}.
-@item __AVR_ARCH__
-Build-in macro that resolves to a decimal number that identifies the
-architecture and depends on the @option{-mmcu=@var{mcu}} option.
-Possible values are:
+@item -mEA
+@opindex mEA
+Replaced by @option{-mea}.
-@code{2}, @code{25}, @code{3}, @code{31}, @code{35},
-@code{4}, @code{5}, @code{51}, @code{6}
+@item -mmac_24
+@opindex mmac_24
+Replaced by @option{-mmac-24}.
-for @var{mcu}=@code{avr2}, @code{avr25}, @code{avr3}, @code{avr31},
-@code{avr35}, @code{avr4}, @code{avr5}, @code{avr51}, @code{avr6},
+@item -mmac_d16
+@opindex mmac_d16
+Replaced by @option{-mmac-d16}.
-respectively and
+@item -mspfp_compact
+@opindex mspfp_compact
+Replaced by @option{-mspfp-compact}.
-@code{100}, @code{102}, @code{104},
-@code{105}, @code{106}, @code{107}
+@item -mspfp_fast
+@opindex mspfp_fast
+Replaced by @option{-mspfp-fast}.
-for @var{mcu}=@code{avrtiny}, @code{avrxmega2}, @code{avrxmega4},
-@code{avrxmega5}, @code{avrxmega6}, @code{avrxmega7}, respectively.
-If @var{mcu} specifies a device, this built-in macro is set
-accordingly. For example, with @option{-mmcu=atmega8} the macro is
-defined to @code{4}.
+@item -mtune=@var{cpu}
+@opindex mtune
+Values @samp{arc600}, @samp{arc601}, @samp{arc700} and
+@samp{arc700-xmac} for @var{cpu} are replaced by @samp{ARC600},
+@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively
-@item __AVR_@var{Device}__
-Setting @option{-mmcu=@var{device}} defines this built-in macro which reflects
-the device's name. For example, @option{-mmcu=atmega8} defines the
-built-in macro @code{__AVR_ATmega8__}, @option{-mmcu=attiny261a} defines
-@code{__AVR_ATtiny261A__}, etc.
+@item -multcost=@var{num}
+@opindex multcost
+Replaced by @option{-mmultcost}.
-The built-in macros' names follow
-the scheme @code{__AVR_@var{Device}__} where @var{Device} is
-the device name as from the AVR user manual. The difference between
-@var{Device} in the built-in macro and @var{device} in
-@option{-mmcu=@var{device}} is that the latter is always lowercase.
+@end table
-If @var{device} is not a device but only a core architecture like
-@samp{avr51}, this macro is not defined.
+@node ARM Options
+@subsection ARM Options
+@cindex ARM options
-@item __AVR_DEVICE_NAME__
-Setting @option{-mmcu=@var{device}} defines this built-in macro to
-the device's name. For example, with @option{-mmcu=atmega8} the macro
-is defined to @code{atmega8}.
+These @samp{-m} options are defined for the ARM port:
-If @var{device} is not a device but only a core architecture like
-@samp{avr51}, this macro is not defined.
+@table @gcctabopt
+@item -mabi=@var{name}
+@opindex mabi
+Generate code for the specified ABI@. Permissible values are: @samp{apcs-gnu},
+@samp{atpcs}, @samp{aapcs}, @samp{aapcs-linux} and @samp{iwmmxt}.
-@item __AVR_XMEGA__
-The device / architecture belongs to the XMEGA family of devices.
+@item -mapcs-frame
+@opindex mapcs-frame
+Generate a stack frame that is compliant with the ARM Procedure Call
+Standard for all functions, even if this is not strictly necessary for
+correct execution of the code. Specifying @option{-fomit-frame-pointer}
+with this option causes the stack frames not to be generated for
+leaf functions. The default is @option{-mno-apcs-frame}.
+This option is deprecated.
-@item __AVR_HAVE_ELPM__
-The device has the @code{ELPM} instruction.
+@item -mapcs
+@opindex mapcs
+This is a synonym for @option{-mapcs-frame} and is deprecated.
-@item __AVR_HAVE_ELPMX__
-The device has the @code{ELPM R@var{n},Z} and @code{ELPM
-R@var{n},Z+} instructions.
+@ignore
+@c not currently implemented
+@item -mapcs-stack-check
+@opindex mapcs-stack-check
+Generate code to check the amount of stack space available upon entry to
+every function (that actually uses some stack space). If there is
+insufficient space available then either the function
+@code{__rt_stkovf_split_small} or @code{__rt_stkovf_split_big} is
+called, depending upon the amount of stack space required. The runtime
+system is required to provide these functions. The default is
+@option{-mno-apcs-stack-check}, since this produces smaller code.
-@item __AVR_HAVE_MOVW__
-The device has the @code{MOVW} instruction to perform 16-bit
-register-register moves.
+@c not currently implemented
+@item -mapcs-float
+@opindex mapcs-float
+Pass floating-point arguments using the floating-point registers. This is
+one of the variants of the APCS@. This option is recommended if the
+target hardware has a floating-point unit or if a lot of floating-point
+arithmetic is going to be performed by the code. The default is
+@option{-mno-apcs-float}, since the size of integer-only code is
+slightly increased if @option{-mapcs-float} is used.
-@item __AVR_HAVE_LPMX__
-The device has the @code{LPM R@var{n},Z} and
-@code{LPM R@var{n},Z+} instructions.
+@c not currently implemented
+@item -mapcs-reentrant
+@opindex mapcs-reentrant
+Generate reentrant, position-independent code. The default is
+@option{-mno-apcs-reentrant}.
+@end ignore
-@item __AVR_HAVE_MUL__
-The device has a hardware multiplier.
+@item -mthumb-interwork
+@opindex mthumb-interwork
+Generate code that supports calling between the ARM and Thumb
+instruction sets. Without this option, on pre-v5 architectures, the
+two instruction sets cannot be reliably used inside one program. The
+default is @option{-mno-thumb-interwork}, since slightly larger code
+is generated when @option{-mthumb-interwork} is specified. In AAPCS
+configurations this option is meaningless.
-@item __AVR_HAVE_JMP_CALL__
-The device has the @code{JMP} and @code{CALL} instructions.
-This is the case for devices with at least 16@tie{}KiB of program
-memory.
+@item -mno-sched-prolog
+@opindex mno-sched-prolog
+Prevent the reordering of instructions in the function prologue, or the
+merging of those instruction with the instructions in the function's
+body. This means that all functions start with a recognizable set
+of instructions (or in fact one of a choice from a small set of
+different function prologues), and this information can be used to
+locate the start of functions inside an executable piece of code. The
+default is @option{-msched-prolog}.
-@item __AVR_HAVE_EIJMP_EICALL__
-@itemx __AVR_3_BYTE_PC__
-The device has the @code{EIJMP} and @code{EICALL} instructions.
-This is the case for devices with more than 128@tie{}KiB of program memory.
-This also means that the program counter
-(PC) is 3@tie{}bytes wide.
+@item -mfloat-abi=@var{name}
+@opindex mfloat-abi
+Specifies which floating-point ABI to use. Permissible values
+are: @samp{soft}, @samp{softfp} and @samp{hard}.
-@item __AVR_2_BYTE_PC__
-The program counter (PC) is 2@tie{}bytes wide. This is the case for devices
-with up to 128@tie{}KiB of program memory.
+Specifying @samp{soft} causes GCC to generate output containing
+library calls for floating-point operations.
+@samp{softfp} allows the generation of code using hardware floating-point
+instructions, but still uses the soft-float calling conventions.
+@samp{hard} allows generation of floating-point instructions
+and uses FPU-specific calling conventions.
-@item __AVR_HAVE_8BIT_SP__
-@itemx __AVR_HAVE_16BIT_SP__
-The stack pointer (SP) register is treated as 8-bit respectively
-16-bit register by the compiler.
-The definition of these macros is affected by @option{-mtiny-stack}.
+The default depends on the specific target configuration. Note that
+the hard-float and soft-float ABIs are not link-compatible; you must
+compile your entire program with the same ABI, and link with a
+compatible set of libraries.
-@item __AVR_HAVE_SPH__
-@itemx __AVR_SP8__
-The device has the SPH (high part of stack pointer) special function
-register or has an 8-bit stack pointer, respectively.
-The definition of these macros is affected by @option{-mmcu=} and
-in the cases of @option{-mmcu=avr2} and @option{-mmcu=avr25} also
-by @option{-msp8}.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a processor running in little-endian mode. This is
+the default for all standard configurations.
-@item __AVR_HAVE_RAMPD__
-@itemx __AVR_HAVE_RAMPX__
-@itemx __AVR_HAVE_RAMPY__
-@itemx __AVR_HAVE_RAMPZ__
-The device has the @code{RAMPD}, @code{RAMPX}, @code{RAMPY},
-@code{RAMPZ} special function register, respectively.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a processor running in big-endian mode; the default is
+to compile code for a little-endian processor.
-@item __NO_INTERRUPTS__
-This macro reflects the @option{-mno-interrupts} command-line option.
+@item -march=@var{name}
+@opindex march
+This specifies the name of the target ARM architecture. GCC uses this
+name to determine what kind of instructions it can emit when generating
+assembly code. This option can be used in conjunction with or instead
+of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
+@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
+@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te},
+@samp{armv6}, @samp{armv6j},
+@samp{armv6t2}, @samp{armv6z}, @samp{armv6kz}, @samp{armv6-m},
+@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m},
+@samp{armv7ve}, @samp{armv8-a}, @samp{armv8-a+crc}, @samp{armv8.1-a},
+@samp{armv8.1-a+crc}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
-@item __AVR_ERRATA_SKIP__
-@itemx __AVR_ERRATA_SKIP_JMP_CALL__
-Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
-instructions because of a hardware erratum. Skip instructions are
-@code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
-The second macro is only defined if @code{__AVR_HAVE_JMP_CALL__} is also
-set.
+@option{-march=armv7ve} is the armv7-a architecture with virtualization
+extensions.
-@item __AVR_ISA_RMW__
-The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).
+@option{-march=armv8-a+crc} enables code generation for the ARMv8-A
+architecture together with the optional CRC32 extensions.
-@item __AVR_SFR_OFFSET__=@var{offset}
-Instructions that can address I/O special function registers directly
-like @code{IN}, @code{OUT}, @code{SBI}, etc.@: may use a different
-address as if addressed by an instruction to access RAM like @code{LD}
-or @code{STS}. This offset depends on the device architecture and has
-to be subtracted from the RAM address in order to get the
-respective I/O@tie{}address.
+@option{-march=native} causes the compiler to auto-detect the architecture
+of the build computer. At present, this feature is only supported on
+GNU/Linux, and not all architectures are recognized. If the auto-detect
+is unsuccessful the option has no effect.
-@item __WITH_AVRLIBC__
-The compiler is configured to be used together with AVR-Libc.
-See the @option{--with-avrlibc} configure option.
+@item -mtune=@var{name}
+@opindex mtune
+This option specifies the name of the target ARM processor for
+which GCC should tune the performance of the code.
+For some ARM implementations better performance can be obtained by using
+this option.
+Permissible names are: @samp{arm2}, @samp{arm250},
+@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
+@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
+@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
+@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
+@samp{arm720},
+@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm7tdmi-s},
+@samp{arm710t}, @samp{arm720t}, @samp{arm740t},
+@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{strongarm1110},
+@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
+@samp{arm920t}, @samp{arm922t}, @samp{arm946e-s}, @samp{arm966e-s},
+@samp{arm968e-s}, @samp{arm926ej-s}, @samp{arm940t}, @samp{arm9tdmi},
+@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ej-s},
+@samp{arm10e}, @samp{arm1020e}, @samp{arm1022e},
+@samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp},
+@samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s},
+@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, @samp{cortex-a8},
+@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
+@samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72},
+@samp{cortex-r4},
+@samp{cortex-r4f}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-m7},
+@samp{cortex-m4},
+@samp{cortex-m3},
+@samp{cortex-m1},
+@samp{cortex-m0},
+@samp{cortex-m0plus},
+@samp{cortex-m1.small-multiply},
+@samp{cortex-m0.small-multiply},
+@samp{cortex-m0plus.small-multiply},
+@samp{exynos-m1},
+@samp{qdf24xx},
+@samp{marvell-pj4},
+@samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312},
+@samp{fa526}, @samp{fa626},
+@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te},
+@samp{xgene1}.
-@end table
+Additionally, this option can specify that GCC should tune the performance
+of the code for a big.LITTLE system. Permissible names are:
+@samp{cortex-a15.cortex-a7}, @samp{cortex-a17.cortex-a7},
+@samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53}.
-@node Blackfin Options
-@subsection Blackfin Options
-@cindex Blackfin Options
+@option{-mtune=generic-@var{arch}} specifies that GCC should tune the
+performance for a blend of processors within architecture @var{arch}.
+The aim is to generate code that run well on the current most popular
+processors, balancing between optimizations that benefit some CPUs in the
+range, and avoiding performance pitfalls of other CPUs. The effects of
+this option may change in future GCC versions as CPU models come and go.
-@table @gcctabopt
-@item -mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]}
-@opindex mcpu=
-Specifies the name of the target Blackfin processor. Currently, @var{cpu}
-can be one of @samp{bf512}, @samp{bf514}, @samp{bf516}, @samp{bf518},
-@samp{bf522}, @samp{bf523}, @samp{bf524}, @samp{bf525}, @samp{bf526},
-@samp{bf527}, @samp{bf531}, @samp{bf532}, @samp{bf533},
-@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
-@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
-@samp{bf542m}, @samp{bf544m}, @samp{bf547m}, @samp{bf548m}, @samp{bf549m},
-@samp{bf561}, @samp{bf592}.
+@option{-mtune=native} causes the compiler to auto-detect the CPU
+of the build computer. At present, this feature is only supported on
+GNU/Linux, and not all architectures are recognized. If the auto-detect is
+unsuccessful the option has no effect.
-The optional @var{sirevision} specifies the silicon revision of the target
-Blackfin processor. Any workarounds available for the targeted silicon revision
-are enabled. If @var{sirevision} is @samp{none}, no workarounds are enabled.
-If @var{sirevision} is @samp{any}, all workarounds for the targeted processor
-are enabled. The @code{__SILICON_REVISION__} macro is defined to two
-hexadecimal digits representing the major and minor numbers in the silicon
-revision. If @var{sirevision} is @samp{none}, the @code{__SILICON_REVISION__}
-is not defined. If @var{sirevision} is @samp{any}, the
-@code{__SILICON_REVISION__} is defined to be @code{0xffff}.
-If this optional @var{sirevision} is not used, GCC assumes the latest known
-silicon revision of the targeted Blackfin processor.
+@item -mcpu=@var{name}
+@opindex mcpu
+This specifies the name of the target ARM processor. GCC uses this name
+to derive the name of the target ARM architecture (as if specified
+by @option{-march}) and the ARM processor type for which to tune for
+performance (as if specified by @option{-mtune}). Where this option
+is used in conjunction with @option{-march} or @option{-mtune},
+those options take precedence over the appropriate part of this option.
-GCC defines a preprocessor macro for the specified @var{cpu}.
-For the @samp{bfin-elf} toolchain, this option causes the hardware BSP
-provided by libgloss to be linked in if @option{-msim} is not given.
-
-Without this option, @samp{bf532} is used as the processor by default.
-
-Note that support for @samp{bf561} is incomplete. For @samp{bf561},
-only the preprocessor macro is defined.
-
-@item -msim
-@opindex msim
-Specifies that the program will be run on the simulator. This causes
-the simulator BSP provided by libgloss to be linked in. This option
-has effect only for @samp{bfin-elf} toolchain.
-Certain other options, such as @option{-mid-shared-library} and
-@option{-mfdpic}, imply @option{-msim}.
-
-@item -momit-leaf-frame-pointer
-@opindex momit-leaf-frame-pointer
-Don't keep the frame pointer in a register for leaf functions. This
-avoids the instructions to save, set up and restore frame pointers and
-makes an extra register available in leaf functions. The option
-@option{-fomit-frame-pointer} removes the frame pointer for all functions,
-which might make debugging harder.
-
-@item -mspecld-anomaly
-@opindex mspecld-anomaly
-When enabled, the compiler ensures that the generated code does not
-contain speculative loads after jump instructions. If this option is used,
-@code{__WORKAROUND_SPECULATIVE_LOADS} is defined.
-
-@item -mno-specld-anomaly
-@opindex mno-specld-anomaly
-Don't generate extra code to prevent speculative loads from occurring.
-
-@item -mcsync-anomaly
-@opindex mcsync-anomaly
-When enabled, the compiler ensures that the generated code does not
-contain CSYNC or SSYNC instructions too soon after conditional branches.
-If this option is used, @code{__WORKAROUND_SPECULATIVE_SYNCS} is defined.
-
-@item -mno-csync-anomaly
-@opindex mno-csync-anomaly
-Don't generate extra code to prevent CSYNC or SSYNC instructions from
-occurring too soon after a conditional branch.
+Permissible names for this option are the same as those for
+@option{-mtune}.
-@item -mlow-64k
-@opindex mlow-64k
-When enabled, the compiler is free to take advantage of the knowledge that
-the entire program fits into the low 64k of memory.
+@option{-mcpu=generic-@var{arch}} is also permissible, and is
+equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}.
+See @option{-mtune} for more information.
-@item -mno-low-64k
-@opindex mno-low-64k
-Assume that the program is arbitrarily large. This is the default.
+@option{-mcpu=native} causes the compiler to auto-detect the CPU
+of the build computer. At present, this feature is only supported on
+GNU/Linux, and not all architectures are recognized. If the auto-detect
+is unsuccessful the option has no effect.
-@item -mstack-check-l1
-@opindex mstack-check-l1
-Do stack checking using information placed into L1 scratchpad memory by the
-uClinux kernel.
+@item -mfpu=@var{name}
+@opindex mfpu
+This specifies what floating-point hardware (or hardware emulation) is
+available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
+@samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
+@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
+@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
+@samp{fpv5-d16}, @samp{fpv5-sp-d16},
+@samp{fp-armv8}, @samp{neon-fp-armv8} and @samp{crypto-neon-fp-armv8}.
-@item -mid-shared-library
-@opindex mid-shared-library
-Generate code that supports shared libraries via the library ID method.
-This allows for execute in place and shared libraries in an environment
-without virtual memory management. This option implies @option{-fPIC}.
-With a @samp{bfin-elf} target, this option implies @option{-msim}.
+If @option{-msoft-float} is specified this specifies the format of
+floating-point values.
-@item -mno-id-shared-library
-@opindex mno-id-shared-library
-Generate code that doesn't assume ID-based shared libraries are being used.
-This is the default.
+If the selected floating-point hardware includes the NEON extension
+(e.g. @option{-mfpu}=@samp{neon}), note that floating-point
+operations are not generated by GCC's auto-vectorization pass unless
+@option{-funsafe-math-optimizations} is also specified. This is
+because NEON hardware does not fully implement the IEEE 754 standard for
+floating-point arithmetic (in particular denormal values are treated as
+zero), so the use of NEON instructions may lead to a loss of precision.
-@item -mleaf-id-shared-library
-@opindex mleaf-id-shared-library
-Generate code that supports shared libraries via the library ID method,
-but assumes that this library or executable won't link against any other
-ID shared libraries. That allows the compiler to use faster code for jumps
-and calls.
+You can also set the fpu name at function level by using the @code{target("fpu=")} function attributes (@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}).
-@item -mno-leaf-id-shared-library
-@opindex mno-leaf-id-shared-library
-Do not assume that the code being compiled won't link against any ID shared
-libraries. Slower code is generated for jump and call insns.
+@item -mfp16-format=@var{name}
+@opindex mfp16-format
+Specify the format of the @code{__fp16} half-precision floating-point type.
+Permissible names are @samp{none}, @samp{ieee}, and @samp{alternative};
+the default is @samp{none}, in which case the @code{__fp16} type is not
+defined. @xref{Half-Precision}, for more information.
-@item -mshared-library-id=n
-@opindex mshared-library-id
-Specifies the identification number of the ID-based shared library being
-compiled. Specifying a value of 0 generates more compact code; specifying
-other values forces the allocation of that number to the current
-library but is no more space- or time-efficient than omitting this option.
+@item -mstructure-size-boundary=@var{n}
+@opindex mstructure-size-boundary
+The sizes of all structures and unions are rounded up to a multiple
+of the number of bits set by this option. Permissible values are 8, 32
+and 64. The default value varies for different toolchains. For the COFF
+targeted toolchain the default value is 8. A value of 64 is only allowed
+if the underlying ABI supports it.
-@item -msep-data
-@opindex msep-data
-Generate code that allows the data segment to be located in a different
-area of memory from the text segment. This allows for execute in place in
-an environment without virtual memory management by eliminating relocations
-against the text section.
+Specifying a larger number can produce faster, more efficient code, but
+can also increase the size of the program. Different values are potentially
+incompatible. Code compiled with one value cannot necessarily expect to
+work with code or libraries compiled with another value, if they exchange
+information using structures or unions.
-@item -mno-sep-data
-@opindex mno-sep-data
-Generate code that assumes that the data segment follows the text segment.
-This is the default.
+@item -mabort-on-noreturn
+@opindex mabort-on-noreturn
+Generate a call to the function @code{abort} at the end of a
+@code{noreturn} function. It is executed if the function tries to
+return.
@item -mlong-calls
@itemx -mno-long-calls
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a subroutine
call on this register. This switch is needed if the target function
-lies outside of the 24-bit addressing range of the offset-based
+lies outside of the 64-megabyte addressing range of the offset-based
version of subroutine call instruction.
+Even if this switch is enabled, not all function calls are turned
+into long calls. The heuristic is that static functions, functions
+that have the @code{short_call} attribute, functions that are inside
+the scope of a @code{#pragma no_long_calls} directive, and functions whose
+definitions have already been compiled within the current compilation
+unit are not turned into long calls. The exceptions to this rule are
+that weak function definitions, functions with the @code{long_call}
+attribute or the @code{section} attribute, and functions that are within
+the scope of a @code{#pragma long_calls} directive are always
+turned into long calls.
+
This feature is not enabled by default. Specifying
-@option{-mno-long-calls} restores the default behavior. Note these
-switches have no effect on how the compiler generates code to handle
-function calls via function pointers.
+@option{-mno-long-calls} restores the default behavior, as does
+placing the function calls within the scope of a @code{#pragma
+long_calls_off} directive. Note these switches have no effect on how
+the compiler generates code to handle function calls via function
+pointers.
-@item -mfast-fp
-@opindex mfast-fp
-Link with the fast floating-point library. This library relaxes some of
-the IEEE floating-point standard's rules for checking inputs against
-Not-a-Number (NAN), in the interest of performance.
+@item -msingle-pic-base
+@opindex msingle-pic-base
+Treat the register used for PIC addressing as read-only, rather than
+loading it in the prologue for each function. The runtime system is
+responsible for initializing this register with an appropriate value
+before execution begins.
-@item -minline-plt
-@opindex minline-plt
-Enable inlining of PLT entries in function calls to functions that are
-not known to bind locally. It has no effect without @option{-mfdpic}.
+@item -mpic-register=@var{reg}
+@opindex mpic-register
+Specify the register to be used for PIC addressing.
+For standard PIC base case, the default is any suitable register
+determined by compiler. For single PIC base case, the default is
+@samp{R9} if target is EABI based or stack-checking is enabled,
+otherwise the default is @samp{R10}.
-@item -mmulticore
-@opindex mmulticore
-Build a standalone application for multicore Blackfin processors.
-This option causes proper start files and link scripts supporting
-multicore to be used, and defines the macro @code{__BFIN_MULTICORE}.
-It can only be used with @option{-mcpu=bf561@r{[}-@var{sirevision}@r{]}}.
+@item -mpic-data-is-text-relative
+@opindex mpic-data-is-text-relative
+Assume that each data segments are relative to text segment at load time.
+Therefore, it permits addressing data using PC-relative operations.
+This option is on by default for targets other than VxWorks RTP.
-This option can be used with @option{-mcorea} or @option{-mcoreb}, which
-selects the one-application-per-core programming model. Without
-@option{-mcorea} or @option{-mcoreb}, the single-application/dual-core
-programming model is used. In this model, the main function of Core B
-should be named as @code{coreb_main}.
+@item -mpoke-function-name
+@opindex mpoke-function-name
+Write the name of each function into the text section, directly
+preceding the function prologue. The generated code is similar to this:
-If this option is not used, the single-core application programming
-model is used.
+@smallexample
+ t0
+ .ascii "arm_poke_function_name", 0
+ .align
+ t1
+ .word 0xff000000 + (t1 - t0)
+ arm_poke_function_name
+ mov ip, sp
+ stmfd sp!, @{fp, ip, lr, pc@}
+ sub fp, ip, #4
+@end smallexample
-@item -mcorea
-@opindex mcorea
-Build a standalone application for Core A of BF561 when using
-the one-application-per-core programming model. Proper start files
-and link scripts are used to support Core A, and the macro
-@code{__BFIN_COREA} is defined.
-This option can only be used in conjunction with @option{-mmulticore}.
+When performing a stack backtrace, code can inspect the value of
+@code{pc} stored at @code{fp + 0}. If the trace function then looks at
+location @code{pc - 12} and the top 8 bits are set, then we know that
+there is a function name embedded immediately preceding this location
+and has length @code{((pc[-3]) & 0xff000000)}.
-@item -mcoreb
-@opindex mcoreb
-Build a standalone application for Core B of BF561 when using
-the one-application-per-core programming model. Proper start files
-and link scripts are used to support Core B, and the macro
-@code{__BFIN_COREB} is defined. When this option is used, @code{coreb_main}
-should be used instead of @code{main}.
-This option can only be used in conjunction with @option{-mmulticore}.
+@item -mthumb
+@itemx -marm
+@opindex marm
+@opindex mthumb
-@item -msdram
-@opindex msdram
-Build a standalone application for SDRAM. Proper start files and
-link scripts are used to put the application into SDRAM, and the macro
-@code{__BFIN_SDRAM} is defined.
-The loader should initialize SDRAM before loading the application.
+Select between generating code that executes in ARM and Thumb
+states. The default for most configurations is to generate code
+that executes in ARM state, but the default can be changed by
+configuring GCC with the @option{--with-mode=}@var{state}
+configure option.
-@item -micplb
-@opindex micplb
-Assume that ICPLBs are enabled at run time. This has an effect on certain
-anomaly workarounds. For Linux targets, the default is to assume ICPLBs
-are enabled; for standalone applications the default is off.
-@end table
+You can also override the ARM and Thumb mode for each function
+by using the @code{target("thumb")} and @code{target("arm")} function attributes
+(@pxref{ARM Function Attributes}) or pragmas (@pxref{Function Specific Option Pragmas}).
-@node C6X Options
-@subsection C6X Options
-@cindex C6X Options
+@item -mtpcs-frame
+@opindex mtpcs-frame
+Generate a stack frame that is compliant with the Thumb Procedure Call
+Standard for all non-leaf functions. (A leaf function is one that does
+not call any other functions.) The default is @option{-mno-tpcs-frame}.
-@table @gcctabopt
-@item -march=@var{name}
-@opindex march
-This specifies the name of the target architecture. GCC uses this
-name to determine what kind of instructions it can emit when generating
-assembly code. Permissible names are: @samp{c62x},
-@samp{c64x}, @samp{c64x+}, @samp{c67x}, @samp{c67x+}, @samp{c674x}.
+@item -mtpcs-leaf-frame
+@opindex mtpcs-leaf-frame
+Generate a stack frame that is compliant with the Thumb Procedure Call
+Standard for all leaf functions. (A leaf function is one that does
+not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a big-endian target.
+@item -mcallee-super-interworking
+@opindex mcallee-super-interworking
+Gives all externally visible functions in the file being compiled an ARM
+instruction set header which switches to Thumb mode before executing the
+rest of the function. This allows these functions to be called from
+non-interworking code. This option is not valid in AAPCS configurations
+because interworking is enabled by default.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a little-endian target. This is the default.
+@item -mcaller-super-interworking
+@opindex mcaller-super-interworking
+Allows calls via function pointers (including virtual functions) to
+execute correctly regardless of whether the target code has been
+compiled for interworking or not. There is a small overhead in the cost
+of executing a function pointer if this option is enabled. This option
+is not valid in AAPCS configurations because interworking is enabled
+by default.
-@item -msim
-@opindex msim
-Choose startup files and linker script suitable for the simulator.
+@item -mtp=@var{name}
+@opindex mtp
+Specify the access model for the thread local storage pointer. The valid
+models are @samp{soft}, which generates calls to @code{__aeabi_read_tp},
+@samp{cp15}, which fetches the thread pointer from @code{cp15} directly
+(supported in the arm6k architecture), and @samp{auto}, which uses the
+best available method for the selected processor. The default setting is
+@samp{auto}.
-@item -msdata=default
-@opindex msdata=default
-Put small global and static data in the @code{.neardata} section,
-which is pointed to by register @code{B14}. Put small uninitialized
-global and static data in the @code{.bss} section, which is adjacent
-to the @code{.neardata} section. Put small read-only data into the
-@code{.rodata} section. The corresponding sections used for large
-pieces of data are @code{.fardata}, @code{.far} and @code{.const}.
+@item -mtls-dialect=@var{dialect}
+@opindex mtls-dialect
+Specify the dialect to use for accessing thread local storage. Two
+@var{dialect}s are supported---@samp{gnu} and @samp{gnu2}. The
+@samp{gnu} dialect selects the original GNU scheme for supporting
+local and global dynamic TLS models. The @samp{gnu2} dialect
+selects the GNU descriptor scheme, which provides better performance
+for shared libraries. The GNU descriptor scheme is compatible with
+the original scheme, but does require new assembler, linker and
+library support. Initial and local exec TLS models are unaffected by
+this option and always use the original scheme.
-@item -msdata=all
-@opindex msdata=all
-Put all data, not just small objects, into the sections reserved for
-small data, and use addressing relative to the @code{B14} register to
-access them.
+@item -mword-relocations
+@opindex mword-relocations
+Only generate absolute relocations on word-sized values (i.e. R_ARM_ABS32).
+This is enabled by default on targets (uClinux, SymbianOS) where the runtime
+loader imposes this restriction, and when @option{-fpic} or @option{-fPIC}
+is specified.
-@item -msdata=none
-@opindex msdata=none
-Make no use of the sections reserved for small data, and use absolute
-addresses to access all data. Put all initialized global and static
-data in the @code{.fardata} section, and all uninitialized data in the
-@code{.far} section. Put all constant data into the @code{.const}
-section.
-@end table
+@item -mfix-cortex-m3-ldrd
+@opindex mfix-cortex-m3-ldrd
+Some Cortex-M3 cores can cause data corruption when @code{ldrd} instructions
+with overlapping destination and base registers are used. This option avoids
+generating these instructions. This option is enabled by default when
+@option{-mcpu=cortex-m3} is specified.
-@node CRIS Options
-@subsection CRIS Options
-@cindex CRIS Options
+@item -munaligned-access
+@itemx -mno-unaligned-access
+@opindex munaligned-access
+@opindex mno-unaligned-access
+Enables (or disables) reading and writing of 16- and 32- bit values
+from addresses that are not 16- or 32- bit aligned. By default
+unaligned access is disabled for all pre-ARMv6 and all ARMv6-M
+architectures, and enabled for all other architectures. If unaligned
+access is not enabled then words in packed data structures are
+accessed a byte at a time.
-These options are defined specifically for the CRIS ports.
+The ARM attribute @code{Tag_CPU_unaligned_access} is set in the
+generated object file to either true or false, depending upon the
+setting of this option. If unaligned access is enabled then the
+preprocessor symbol @code{__ARM_FEATURE_UNALIGNED} is also
+defined.
-@table @gcctabopt
-@item -march=@var{architecture-type}
-@itemx -mcpu=@var{architecture-type}
-@opindex march
-@opindex mcpu
-Generate code for the specified architecture. The choices for
-@var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
-respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX@.
-Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
-@samp{v10}.
+@item -mneon-for-64bits
+@opindex mneon-for-64bits
+Enables using Neon to handle scalar 64-bits operations. This is
+disabled by default since the cost of moving data from core registers
+to Neon is high.
-@item -mtune=@var{architecture-type}
-@opindex mtune
-Tune to @var{architecture-type} everything applicable about the generated
-code, except for the ABI and the set of available instructions. The
-choices for @var{architecture-type} are the same as for
-@option{-march=@var{architecture-type}}.
+@item -mslow-flash-data
+@opindex mslow-flash-data
+Assume loading data from flash is slower than fetching instruction.
+Therefore literal load is minimized for better performance.
+This option is only supported when compiling for ARMv7 M-profile and
+off by default.
-@item -mmax-stack-frame=@var{n}
-@opindex mmax-stack-frame
-Warn when the stack frame of a function exceeds @var{n} bytes.
+@item -masm-syntax-unified
+@opindex masm-syntax-unified
+Assume inline assembler is using unified asm syntax. The default is
+currently off which implies divided syntax. This option has no impact
+on Thumb2. However, this may change in future releases of GCC.
+Divided syntax should be considered deprecated.
-@item -metrax4
-@itemx -metrax100
-@opindex metrax4
-@opindex metrax100
-The options @option{-metrax4} and @option{-metrax100} are synonyms for
-@option{-march=v3} and @option{-march=v8} respectively.
+@item -mrestrict-it
+@opindex mrestrict-it
+Restricts generation of IT blocks to conform to the rules of ARMv8.
+IT blocks can only contain a single 16-bit instruction from a select
+set of instructions. This option is on by default for ARMv8 Thumb mode.
-@item -mmul-bug-workaround
-@itemx -mno-mul-bug-workaround
-@opindex mmul-bug-workaround
-@opindex mno-mul-bug-workaround
-Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
-models where it applies. This option is active by default.
+@item -mprint-tune-info
+@opindex mprint-tune-info
+Print CPU tuning information as comment in assembler file. This is
+an option used only for regression testing of the compiler and not
+intended for ordinary use in compiling code. This option is disabled
+by default.
+@end table
-@item -mpdebug
-@opindex mpdebug
-Enable CRIS-specific verbose debug-related information in the assembly
-code. This option also has the effect of turning off the @samp{#NO_APP}
-formatted-code indicator to the assembler at the beginning of the
-assembly file.
+@node AVR Options
+@subsection AVR Options
+@cindex AVR Options
-@item -mcc-init
-@opindex mcc-init
-Do not use condition-code results from previous instruction; always emit
-compare and test instructions before use of condition codes.
+These options are defined for AVR implementations:
-@item -mno-side-effects
-@opindex mno-side-effects
-Do not emit instructions with side effects in addressing modes other than
-post-increment.
+@table @gcctabopt
+@item -mmcu=@var{mcu}
+@opindex mmcu
+Specify Atmel AVR instruction set architectures (ISA) or MCU type.
-@item -mstack-align
-@itemx -mno-stack-align
-@itemx -mdata-align
-@itemx -mno-data-align
-@itemx -mconst-align
-@itemx -mno-const-align
-@opindex mstack-align
-@opindex mno-stack-align
-@opindex mdata-align
-@opindex mno-data-align
-@opindex mconst-align
-@opindex mno-const-align
-These options (@samp{no-} options) arrange (eliminate arrangements) for the
-stack frame, individual data and constants to be aligned for the maximum
-single data access size for the chosen CPU model. The default is to
-arrange for 32-bit alignment. ABI details such as structure layout are
-not affected by these options.
+The default for this option is@tie{}@samp{avr2}.
-@item -m32-bit
-@itemx -m16-bit
-@itemx -m8-bit
-@opindex m32-bit
-@opindex m16-bit
-@opindex m8-bit
-Similar to the stack- data- and const-align options above, these options
-arrange for stack frame, writable data and constants to all be 32-bit,
-16-bit or 8-bit aligned. The default is 32-bit alignment.
+GCC supports the following AVR devices and ISAs:
-@item -mno-prologue-epilogue
-@itemx -mprologue-epilogue
-@opindex mno-prologue-epilogue
-@opindex mprologue-epilogue
-With @option{-mno-prologue-epilogue}, the normal function prologue and
-epilogue which set up the stack frame are omitted and no return
-instructions or return sequences are generated in the code. Use this
-option only together with visual inspection of the compiled code: no
-warnings or errors are generated when call-saved registers must be saved,
-or storage for local variables needs to be allocated.
+@include avr-mmcu.texi
-@item -mno-gotplt
-@itemx -mgotplt
-@opindex mno-gotplt
-@opindex mgotplt
-With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
-instruction sequences that load addresses for functions from the PLT part
-of the GOT rather than (traditional on other architectures) calls to the
-PLT@. The default is @option{-mgotplt}.
+@item -maccumulate-args
+@opindex maccumulate-args
+Accumulate outgoing function arguments and acquire/release the needed
+stack space for outgoing function arguments once in function
+prologue/epilogue. Without this option, outgoing arguments are pushed
+before calling a function and popped afterwards.
-@item -melf
-@opindex melf
-Legacy no-op option only recognized with the cris-axis-elf and
-cris-axis-linux-gnu targets.
+Popping the arguments after the function call can be expensive on
+AVR so that accumulating the stack space might lead to smaller
+executables because arguments need not to be removed from the
+stack after such a function call.
-@item -mlinux
-@opindex mlinux
-Legacy no-op option only recognized with the cris-axis-linux-gnu target.
+This option can lead to reduced code size for functions that perform
+several calls to functions that get their arguments on the stack like
+calls to printf-like functions.
-@item -sim
-@opindex sim
-This option, recognized for the cris-axis-elf, arranges
-to link with input-output functions from a simulator library. Code,
-initialized data and zero-initialized data are allocated consecutively.
+@item -mbranch-cost=@var{cost}
+@opindex mbranch-cost
+Set the branch costs for conditional branch instructions to
+@var{cost}. Reasonable values for @var{cost} are small, non-negative
+integers. The default branch cost is 0.
-@item -sim2
-@opindex sim2
-Like @option{-sim}, but pass linker options to locate initialized data at
-0x40000000 and zero-initialized data at 0x80000000.
-@end table
+@item -mcall-prologues
+@opindex mcall-prologues
+Functions prologues/epilogues are expanded as calls to appropriate
+subroutines. Code size is smaller.
-@node CR16 Options
-@subsection CR16 Options
-@cindex CR16 Options
+@item -mint8
+@opindex mint8
+Assume @code{int} to be 8-bit integer. This affects the sizes of all types: a
+@code{char} is 1 byte, an @code{int} is 1 byte, a @code{long} is 2 bytes,
+and @code{long long} is 4 bytes. Please note that this option does not
+conform to the C standards, but it results in smaller code
+size.
-These options are defined specifically for the CR16 ports.
+@item -mn-flash=@var{num}
+@opindex mn-flash
+Assume that the flash memory has a size of
+@var{num} times 64@tie{}KiB.
-@table @gcctabopt
+@item -mno-interrupts
+@opindex mno-interrupts
+Generated code is not compatible with hardware interrupts.
+Code size is smaller.
-@item -mmac
-@opindex mmac
-Enable the use of multiply-accumulate instructions. Disabled by default.
+@item -mrelax
+@opindex mrelax
+Try to replace @code{CALL} resp.@: @code{JMP} instruction by the shorter
+@code{RCALL} resp.@: @code{RJMP} instruction if applicable.
+Setting @option{-mrelax} just adds the @option{--mlink-relax} option to
+the assembler's command line and the @option{--relax} option to the
+linker's command line.
-@item -mcr16cplus
-@itemx -mcr16c
-@opindex mcr16cplus
-@opindex mcr16c
-Generate code for CR16C or CR16C+ architecture. CR16C+ architecture
-is default.
+Jump relaxing is performed by the linker because jump offsets are not
+known before code is located. Therefore, the assembler code generated by the
+compiler is the same, but the instructions in the executable may
+differ from instructions in the assembler code.
-@item -msim
-@opindex msim
-Links the library libsim.a which is in compatible with simulator. Applicable
-to ELF compiler only.
+Relaxing must be turned on if linker stubs are needed, see the
+section on @code{EIND} and linker stubs below.
-@item -mint32
-@opindex mint32
-Choose integer type as 32-bit wide.
+@item -mrmw
+@opindex mrmw
+Assume that the device supports the Read-Modify-Write
+instructions @code{XCH}, @code{LAC}, @code{LAS} and @code{LAT}.
-@item -mbit-ops
-@opindex mbit-ops
-Generates @code{sbit}/@code{cbit} instructions for bit manipulations.
+@item -msp8
+@opindex msp8
+Treat the stack pointer register as an 8-bit register,
+i.e.@: assume the high byte of the stack pointer is zero.
+In general, you don't need to set this option by hand.
-@item -mdata-model=@var{model}
-@opindex mdata-model
-Choose a data model. The choices for @var{model} are @samp{near},
-@samp{far} or @samp{medium}. @samp{medium} is default.
-However, @samp{far} is not valid with @option{-mcr16c}, as the
-CR16C architecture does not support the far data model.
-@end table
+This option is used internally by the compiler to select and
+build multilibs for architectures @code{avr2} and @code{avr25}.
+These architectures mix devices with and without @code{SPH}.
+For any setting other than @option{-mmcu=avr2} or @option{-mmcu=avr25}
+the compiler driver adds or removes this option from the compiler
+proper's command line, because the compiler then knows if the device
+or architecture has an 8-bit stack pointer and thus no @code{SPH}
+register or not.
-@node Darwin Options
-@subsection Darwin Options
-@cindex Darwin options
+@item -mstrict-X
+@opindex mstrict-X
+Use address register @code{X} in a way proposed by the hardware. This means
+that @code{X} is only used in indirect, post-increment or
+pre-decrement addressing.
-These options are defined for all architectures running the Darwin operating
-system.
+Without this option, the @code{X} register may be used in the same way
+as @code{Y} or @code{Z} which then is emulated by additional
+instructions.
+For example, loading a value with @code{X+const} addressing with a
+small non-negative @code{const < 64} to a register @var{Rn} is
+performed as
-FSF GCC on Darwin does not create ``fat'' object files; it creates
-an object file for the single architecture that GCC was built to
-target. Apple's GCC on Darwin does create ``fat'' files if multiple
-@option{-arch} options are used; it does so by running the compiler or
-linker multiple times and joining the results together with
-@file{lipo}.
+@example
+adiw r26, const ; X += const
+ld @var{Rn}, X ; @var{Rn} = *X
+sbiw r26, const ; X -= const
+@end example
-The subtype of the file created (like @samp{ppc7400} or @samp{ppc970} or
-@samp{i686}) is determined by the flags that specify the ISA
-that GCC is targeting, like @option{-mcpu} or @option{-march}. The
-@option{-force_cpusubtype_ALL} option can be used to override this.
+@item -mtiny-stack
+@opindex mtiny-stack
+Only change the lower 8@tie{}bits of the stack pointer.
-The Darwin tools vary in their behavior when presented with an ISA
-mismatch. The assembler, @file{as}, only permits instructions to
-be used that are valid for the subtype of the file it is generating,
-so you cannot put 64-bit instructions in a @samp{ppc750} object file.
-The linker for shared libraries, @file{/usr/bin/libtool}, fails
-and prints an error if asked to create a shared library with a less
-restrictive subtype than its input files (for instance, trying to put
-a @samp{ppc970} object file in a @samp{ppc7400} library). The linker
-for executables, @command{ld}, quietly gives the executable the most
-restrictive subtype of any of its input files.
+@item -nodevicelib
+@opindex nodevicelib
+Don't link against AVR-LibC's device specific library @code{libdev.a}.
-@table @gcctabopt
-@item -F@var{dir}
-@opindex F
-Add the framework directory @var{dir} to the head of the list of
-directories to be searched for header files. These directories are
-interleaved with those specified by @option{-I} options and are
-scanned in a left-to-right order.
+@item -Waddr-space-convert
+@opindex Waddr-space-convert
+Warn about conversions between address spaces in the case where the
+resulting address space is not contained in the incoming address space.
+@end table
-A framework directory is a directory with frameworks in it. A
-framework is a directory with a @file{Headers} and/or
-@file{PrivateHeaders} directory contained directly in it that ends
-in @file{.framework}. The name of a framework is the name of this
-directory excluding the @file{.framework}. Headers associated with
-the framework are found in one of those two directories, with
-@file{Headers} being searched first. A subframework is a framework
-directory that is in a framework's @file{Frameworks} directory.
-Includes of subframework headers can only appear in a header of a
-framework that contains the subframework, or in a sibling subframework
-header. Two subframeworks are siblings if they occur in the same
-framework. A subframework should not have the same name as a
-framework; a warning is issued if this is violated. Currently a
-subframework cannot have subframeworks; in the future, the mechanism
-may be extended to support this. The standard frameworks can be found
-in @file{/System/Library/Frameworks} and
-@file{/Library/Frameworks}. An example include looks like
-@code{#include <Framework/header.h>}, where @file{Framework} denotes
-the name of the framework and @file{header.h} is found in the
-@file{PrivateHeaders} or @file{Headers} directory.
+@subsubsection @code{EIND} and Devices with More Than 128 Ki Bytes of Flash
+@cindex @code{EIND}
+Pointers in the implementation are 16@tie{}bits wide.
+The address of a function or label is represented as word address so
+that indirect jumps and calls can target any code address in the
+range of 64@tie{}Ki words.
-@item -iframework@var{dir}
-@opindex iframework
-Like @option{-F} except the directory is a treated as a system
-directory. The main difference between this @option{-iframework} and
-@option{-F} is that with @option{-iframework} the compiler does not
-warn about constructs contained within header files found via
-@var{dir}. This option is valid only for the C family of languages.
+In order to facilitate indirect jump on devices with more than 128@tie{}Ki
+bytes of program memory space, there is a special function register called
+@code{EIND} that serves as most significant part of the target address
+when @code{EICALL} or @code{EIJMP} instructions are used.
-@item -gused
-@opindex gused
-Emit debugging information for symbols that are used. For stabs
-debugging format, this enables @option{-feliminate-unused-debug-symbols}.
-This is by default ON@.
+Indirect jumps and calls on these devices are handled as follows by
+the compiler and are subject to some limitations:
-@item -gfull
-@opindex gfull
-Emit debugging information for all symbols and types.
+@itemize @bullet
-@item -mmacosx-version-min=@var{version}
-The earliest version of MacOS X that this executable will run on
-is @var{version}. Typical values of @var{version} include @code{10.1},
-@code{10.2}, and @code{10.3.9}.
+@item
+The compiler never sets @code{EIND}.
-If the compiler was built to use the system's headers by default,
-then the default for this option is the system version on which the
-compiler is running, otherwise the default is to make choices that
-are compatible with as many systems and code bases as possible.
+@item
+The compiler uses @code{EIND} implicitely in @code{EICALL}/@code{EIJMP}
+instructions or might read @code{EIND} directly in order to emulate an
+indirect call/jump by means of a @code{RET} instruction.
-@item -mkernel
-@opindex mkernel
-Enable kernel development mode. The @option{-mkernel} option sets
-@option{-static}, @option{-fno-common}, @option{-fno-use-cxa-atexit},
-@option{-fno-exceptions}, @option{-fno-non-call-exceptions},
-@option{-fapple-kext}, @option{-fno-weak} and @option{-fno-rtti} where
-applicable. This mode also sets @option{-mno-altivec},
-@option{-msoft-float}, @option{-fno-builtin} and
-@option{-mlong-branch} for PowerPC targets.
+@item
+The compiler assumes that @code{EIND} never changes during the startup
+code or during the application. In particular, @code{EIND} is not
+saved/restored in function or interrupt service routine
+prologue/epilogue.
-@item -mone-byte-bool
-@opindex mone-byte-bool
-Override the defaults for @code{bool} so that @code{sizeof(bool)==1}.
-By default @code{sizeof(bool)} is @code{4} when compiling for
-Darwin/PowerPC and @code{1} when compiling for Darwin/x86, so this
-option has no effect on x86.
+@item
+For indirect calls to functions and computed goto, the linker
+generates @emph{stubs}. Stubs are jump pads sometimes also called
+@emph{trampolines}. Thus, the indirect call/jump jumps to such a stub.
+The stub contains a direct jump to the desired address.
-@strong{Warning:} The @option{-mone-byte-bool} switch causes GCC
-to generate code that is not binary compatible with code generated
-without that switch. Using this switch may require recompiling all
-other modules in a program, including system libraries. Use this
-switch to conform to a non-default data model.
+@item
+Linker relaxation must be turned on so that the linker generates
+the stubs correctly in all situations. See the compiler option
+@option{-mrelax} and the linker option @option{--relax}.
+There are corner cases where the linker is supposed to generate stubs
+but aborts without relaxation and without a helpful error message.
-@item -mfix-and-continue
-@itemx -ffix-and-continue
-@itemx -findirect-data
-@opindex mfix-and-continue
-@opindex ffix-and-continue
-@opindex findirect-data
-Generate code suitable for fast turnaround development, such as to
-allow GDB to dynamically load @file{.o} files into already-running
-programs. @option{-findirect-data} and @option{-ffix-and-continue}
-are provided for backwards compatibility.
+@item
+The default linker script is arranged for code with @code{EIND = 0}.
+If code is supposed to work for a setup with @code{EIND != 0}, a custom
+linker script has to be used in order to place the sections whose
+name start with @code{.trampolines} into the segment where @code{EIND}
+points to.
-@item -all_load
-@opindex all_load
-Loads all members of static archive libraries.
-See man ld(1) for more information.
+@item
+The startup code from libgcc never sets @code{EIND}.
+Notice that startup code is a blend of code from libgcc and AVR-LibC.
+For the impact of AVR-LibC on @code{EIND}, see the
+@w{@uref{http://nongnu.org/avr-libc/user-manual/,AVR-LibC user manual}}.
-@item -arch_errors_fatal
-@opindex arch_errors_fatal
-Cause the errors having to do with files that have the wrong architecture
-to be fatal.
+@item
+It is legitimate for user-specific startup code to set up @code{EIND}
+early, for example by means of initialization code located in
+section @code{.init3}. Such code runs prior to general startup code
+that initializes RAM and calls constructors, but after the bit
+of startup code from AVR-LibC that sets @code{EIND} to the segment
+where the vector table is located.
+@example
+#include <avr/io.h>
-@item -bind_at_load
-@opindex bind_at_load
-Causes the output file to be marked such that the dynamic linker will
-bind all undefined references when the file is loaded or launched.
+static void
+__attribute__((section(".init3"),naked,used,no_instrument_function))
+init3_set_eind (void)
+@{
+ __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
+ "out %i0,r24" :: "n" (&EIND) : "r24","memory");
+@}
+@end example
-@item -bundle
-@opindex bundle
-Produce a Mach-o bundle format file.
-See man ld(1) for more information.
+@noindent
+The @code{__trampolines_start} symbol is defined in the linker script.
-@item -bundle_loader @var{executable}
-@opindex bundle_loader
-This option specifies the @var{executable} that will load the build
-output file being linked. See man ld(1) for more information.
+@item
+Stubs are generated automatically by the linker if
+the following two conditions are met:
+@itemize @minus
-@item -dynamiclib
-@opindex dynamiclib
-When passed this option, GCC produces a dynamic library instead of
-an executable when linking, using the Darwin @file{libtool} command.
+@item The address of a label is taken by means of the @code{gs} modifier
+(short for @emph{generate stubs}) like so:
+@example
+LDI r24, lo8(gs(@var{func}))
+LDI r25, hi8(gs(@var{func}))
+@end example
+@item The final location of that label is in a code segment
+@emph{outside} the segment where the stubs are located.
+@end itemize
-@item -force_cpusubtype_ALL
-@opindex force_cpusubtype_ALL
-This causes GCC's output file to have the @samp{ALL} subtype, instead of
-one controlled by the @option{-mcpu} or @option{-march} option.
+@item
+The compiler emits such @code{gs} modifiers for code labels in the
+following situations:
+@itemize @minus
+@item Taking address of a function or code label.
+@item Computed goto.
+@item If prologue-save function is used, see @option{-mcall-prologues}
+command-line option.
+@item Switch/case dispatch tables. If you do not want such dispatch
+tables you can specify the @option{-fno-jump-tables} command-line option.
+@item C and C++ constructors/destructors called during startup/shutdown.
+@item If the tools hit a @code{gs()} modifier explained above.
+@end itemize
-@item -allowable_client @var{client_name}
-@itemx -client_name
-@itemx -compatibility_version
-@itemx -current_version
-@itemx -dead_strip
-@itemx -dependency-file
-@itemx -dylib_file
-@itemx -dylinker_install_name
-@itemx -dynamic
-@itemx -exported_symbols_list
-@itemx -filelist
-@need 800
-@itemx -flat_namespace
-@itemx -force_flat_namespace
-@itemx -headerpad_max_install_names
-@itemx -image_base
-@itemx -init
-@itemx -install_name
-@itemx -keep_private_externs
-@itemx -multi_module
-@itemx -multiply_defined
-@itemx -multiply_defined_unused
-@need 800
-@itemx -noall_load
-@itemx -no_dead_strip_inits_and_terms
-@itemx -nofixprebinding
-@itemx -nomultidefs
-@itemx -noprebind
-@itemx -noseglinkedit
-@itemx -pagezero_size
-@itemx -prebind
-@itemx -prebind_all_twolevel_modules
-@itemx -private_bundle
-@need 800
-@itemx -read_only_relocs
-@itemx -sectalign
-@itemx -sectobjectsymbols
-@itemx -whyload
-@itemx -seg1addr
-@itemx -sectcreate
-@itemx -sectobjectsymbols
-@itemx -sectorder
-@itemx -segaddr
-@itemx -segs_read_only_addr
-@need 800
-@itemx -segs_read_write_addr
-@itemx -seg_addr_table
-@itemx -seg_addr_table_filename
-@itemx -seglinkedit
-@itemx -segprot
-@itemx -segs_read_only_addr
-@itemx -segs_read_write_addr
-@itemx -single_module
-@itemx -static
-@itemx -sub_library
-@need 800
-@itemx -sub_umbrella
-@itemx -twolevel_namespace
-@itemx -umbrella
-@itemx -undefined
-@itemx -unexported_symbols_list
-@itemx -weak_reference_mismatches
-@itemx -whatsloaded
-@opindex allowable_client
-@opindex client_name
-@opindex compatibility_version
-@opindex current_version
-@opindex dead_strip
-@opindex dependency-file
-@opindex dylib_file
-@opindex dylinker_install_name
-@opindex dynamic
-@opindex exported_symbols_list
-@opindex filelist
-@opindex flat_namespace
-@opindex force_flat_namespace
-@opindex headerpad_max_install_names
-@opindex image_base
-@opindex init
-@opindex install_name
-@opindex keep_private_externs
-@opindex multi_module
-@opindex multiply_defined
-@opindex multiply_defined_unused
-@opindex noall_load
-@opindex no_dead_strip_inits_and_terms
-@opindex nofixprebinding
-@opindex nomultidefs
-@opindex noprebind
-@opindex noseglinkedit
-@opindex pagezero_size
-@opindex prebind
-@opindex prebind_all_twolevel_modules
-@opindex private_bundle
-@opindex read_only_relocs
-@opindex sectalign
-@opindex sectobjectsymbols
-@opindex whyload
-@opindex seg1addr
-@opindex sectcreate
-@opindex sectobjectsymbols
-@opindex sectorder
-@opindex segaddr
-@opindex segs_read_only_addr
-@opindex segs_read_write_addr
-@opindex seg_addr_table
-@opindex seg_addr_table_filename
-@opindex seglinkedit
-@opindex segprot
-@opindex segs_read_only_addr
-@opindex segs_read_write_addr
-@opindex single_module
-@opindex static
-@opindex sub_library
-@opindex sub_umbrella
-@opindex twolevel_namespace
-@opindex umbrella
-@opindex undefined
-@opindex unexported_symbols_list
-@opindex weak_reference_mismatches
-@opindex whatsloaded
-These options are passed to the Darwin linker. The Darwin linker man page
-describes them in detail.
-@end table
+@item
+Jumping to non-symbolic addresses like so is @emph{not} supported:
-@node DEC Alpha Options
-@subsection DEC Alpha Options
+@example
+int main (void)
+@{
+ /* Call function at word address 0x2 */
+ return ((int(*)(void)) 0x2)();
+@}
+@end example
-These @samp{-m} options are defined for the DEC Alpha implementations:
+Instead, a stub has to be set up, i.e.@: the function has to be called
+through a symbol (@code{func_4} in the example):
-@table @gcctabopt
-@item -mno-soft-float
-@itemx -msoft-float
-@opindex mno-soft-float
-@opindex msoft-float
-Use (do not use) the hardware floating-point instructions for
-floating-point operations. When @option{-msoft-float} is specified,
-functions in @file{libgcc.a} are used to perform floating-point
-operations. Unless they are replaced by routines that emulate the
-floating-point operations, or compiled in such a way as to call such
-emulations routines, these routines issue floating-point
-operations. If you are compiling for an Alpha without floating-point
-operations, you must ensure that the library is built so as not to call
-them.
+@example
+int main (void)
+@{
+ extern int func_4 (void);
-Note that Alpha implementations without floating-point operations are
-required to have floating-point registers.
+ /* Call function at byte address 0x4 */
+ return func_4();
+@}
+@end example
-@item -mfp-reg
-@itemx -mno-fp-regs
-@opindex mfp-reg
-@opindex mno-fp-regs
-Generate code that uses (does not use) the floating-point register set.
-@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
-register set is not used, floating-point operands are passed in integer
-registers as if they were integers and floating-point results are passed
-in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
-so any function with a floating-point argument or return value called by code
-compiled with @option{-mno-fp-regs} must also be compiled with that
-option.
+and the application be linked with @option{-Wl,--defsym,func_4=0x4}.
+Alternatively, @code{func_4} can be defined in the linker script.
+@end itemize
-A typical use of this option is building a kernel that does not use,
-and hence need not save and restore, any floating-point registers.
+@subsubsection Handling of the @code{RAMPD}, @code{RAMPX}, @code{RAMPY} and @code{RAMPZ} Special Function Registers
+@cindex @code{RAMPD}
+@cindex @code{RAMPX}
+@cindex @code{RAMPY}
+@cindex @code{RAMPZ}
+Some AVR devices support memories larger than the 64@tie{}KiB range
+that can be accessed with 16-bit pointers. To access memory locations
+outside this 64@tie{}KiB range, the contentent of a @code{RAMP}
+register is used as high part of the address:
+The @code{X}, @code{Y}, @code{Z} address register is concatenated
+with the @code{RAMPX}, @code{RAMPY}, @code{RAMPZ} special function
+register, respectively, to get a wide address. Similarly,
+@code{RAMPD} is used together with direct addressing.
-@item -mieee
-@opindex mieee
-The Alpha architecture implements floating-point hardware optimized for
-maximum performance. It is mostly compliant with the IEEE floating-point
-standard. However, for full compliance, software assistance is
-required. This option generates code fully IEEE-compliant code
-@emph{except} that the @var{inexact-flag} is not maintained (see below).
-If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
-defined during compilation. The resulting code is less efficient but is
-able to correctly support denormalized numbers and exceptional IEEE
-values such as not-a-number and plus/minus infinity. Other Alpha
-compilers call this option @option{-ieee_with_no_inexact}.
+@itemize
+@item
+The startup code initializes the @code{RAMP} special function
+registers with zero.
-@item -mieee-with-inexact
-@opindex mieee-with-inexact
-This is like @option{-mieee} except the generated code also maintains
-the IEEE @var{inexact-flag}. Turning on this option causes the
-generated code to implement fully-compliant IEEE math. In addition to
-@code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
-macro. On some Alpha implementations the resulting code may execute
-significantly slower than the code generated by default. Since there is
-very little code that depends on the @var{inexact-flag}, you should
-normally not specify this option. Other Alpha compilers call this
-option @option{-ieee_with_inexact}.
+@item
+If a @ref{AVR Named Address Spaces,named address space} other than
+generic or @code{__flash} is used, then @code{RAMPZ} is set
+as needed before the operation.
-@item -mfp-trap-mode=@var{trap-mode}
-@opindex mfp-trap-mode
-This option controls what floating-point related traps are enabled.
-Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
-The trap mode can be set to one of four values:
+@item
+If the device supports RAM larger than 64@tie{}KiB and the compiler
+needs to change @code{RAMPZ} to accomplish an operation, @code{RAMPZ}
+is reset to zero after the operation.
-@table @samp
-@item n
-This is the default (normal) setting. The only traps that are enabled
-are the ones that cannot be disabled in software (e.g., division by zero
-trap).
+@item
+If the device comes with a specific @code{RAMP} register, the ISR
+prologue/epilogue saves/restores that SFR and initializes it with
+zero in case the ISR code might (implicitly) use it.
-@item u
-In addition to the traps enabled by @samp{n}, underflow traps are enabled
-as well.
+@item
+RAM larger than 64@tie{}KiB is not supported by GCC for AVR targets.
+If you use inline assembler to read from locations outside the
+16-bit address range and change one of the @code{RAMP} registers,
+you must reset it to zero after the access.
-@item su
-Like @samp{u}, but the instructions are marked to be safe for software
-completion (see Alpha architecture manual for details).
+@end itemize
-@item sui
-Like @samp{su}, but inexact traps are enabled as well.
-@end table
+@subsubsection AVR Built-in Macros
-@item -mfp-rounding-mode=@var{rounding-mode}
-@opindex mfp-rounding-mode
-Selects the IEEE rounding mode. Other Alpha compilers call this option
-@option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
-of:
+GCC defines several built-in macros so that the user code can test
+for the presence or absence of features. Almost any of the following
+built-in macros are deduced from device capabilities and thus
+triggered by the @option{-mmcu=} command-line option.
-@table @samp
-@item n
-Normal IEEE rounding mode. Floating-point numbers are rounded towards
-the nearest machine number or towards the even machine number in case
-of a tie.
+For even more AVR-specific built-in macros see
+@ref{AVR Named Address Spaces} and @ref{AVR Built-in Functions}.
-@item m
-Round towards minus infinity.
+@table @code
-@item c
-Chopped rounding mode. Floating-point numbers are rounded towards zero.
+@item __AVR_ARCH__
+Build-in macro that resolves to a decimal number that identifies the
+architecture and depends on the @option{-mmcu=@var{mcu}} option.
+Possible values are:
-@item d
-Dynamic rounding mode. A field in the floating-point control register
-(@var{fpcr}, see Alpha architecture reference manual) controls the
-rounding mode in effect. The C library initializes this register for
-rounding towards plus infinity. Thus, unless your program modifies the
-@var{fpcr}, @samp{d} corresponds to round towards plus infinity.
-@end table
+@code{2}, @code{25}, @code{3}, @code{31}, @code{35},
+@code{4}, @code{5}, @code{51}, @code{6}
-@item -mtrap-precision=@var{trap-precision}
-@opindex mtrap-precision
-In the Alpha architecture, floating-point traps are imprecise. This
-means without software assistance it is impossible to recover from a
-floating trap and program execution normally needs to be terminated.
-GCC can generate code that can assist operating system trap handlers
-in determining the exact location that caused a floating-point trap.
-Depending on the requirements of an application, different levels of
-precisions can be selected:
+for @var{mcu}=@code{avr2}, @code{avr25}, @code{avr3}, @code{avr31},
+@code{avr35}, @code{avr4}, @code{avr5}, @code{avr51}, @code{avr6},
-@table @samp
-@item p
-Program precision. This option is the default and means a trap handler
-can only identify which program caused a floating-point exception.
+respectively and
-@item f
-Function precision. The trap handler can determine the function that
-caused a floating-point exception.
+@code{100}, @code{102}, @code{104},
+@code{105}, @code{106}, @code{107}
-@item i
-Instruction precision. The trap handler can determine the exact
-instruction that caused a floating-point exception.
-@end table
+for @var{mcu}=@code{avrtiny}, @code{avrxmega2}, @code{avrxmega4},
+@code{avrxmega5}, @code{avrxmega6}, @code{avrxmega7}, respectively.
+If @var{mcu} specifies a device, this built-in macro is set
+accordingly. For example, with @option{-mmcu=atmega8} the macro is
+defined to @code{4}.
-Other Alpha compilers provide the equivalent options called
-@option{-scope_safe} and @option{-resumption_safe}.
+@item __AVR_@var{Device}__
+Setting @option{-mmcu=@var{device}} defines this built-in macro which reflects
+the device's name. For example, @option{-mmcu=atmega8} defines the
+built-in macro @code{__AVR_ATmega8__}, @option{-mmcu=attiny261a} defines
+@code{__AVR_ATtiny261A__}, etc.
-@item -mieee-conformant
-@opindex mieee-conformant
-This option marks the generated code as IEEE conformant. You must not
-use this option unless you also specify @option{-mtrap-precision=i} and either
-@option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
-is to emit the line @samp{.eflag 48} in the function prologue of the
-generated assembly file.
+The built-in macros' names follow
+the scheme @code{__AVR_@var{Device}__} where @var{Device} is
+the device name as from the AVR user manual. The difference between
+@var{Device} in the built-in macro and @var{device} in
+@option{-mmcu=@var{device}} is that the latter is always lowercase.
-@item -mbuild-constants
-@opindex mbuild-constants
-Normally GCC examines a 32- or 64-bit integer constant to
-see if it can construct it from smaller constants in two or three
-instructions. If it cannot, it outputs the constant as a literal and
-generates code to load it from the data segment at run time.
+If @var{device} is not a device but only a core architecture like
+@samp{avr51}, this macro is not defined.
-Use this option to require GCC to construct @emph{all} integer constants
-using code, even if it takes more instructions (the maximum is six).
+@item __AVR_DEVICE_NAME__
+Setting @option{-mmcu=@var{device}} defines this built-in macro to
+the device's name. For example, with @option{-mmcu=atmega8} the macro
+is defined to @code{atmega8}.
-You typically use this option to build a shared library dynamic
-loader. Itself a shared library, it must relocate itself in memory
-before it can find the variables and constants in its own data segment.
+If @var{device} is not a device but only a core architecture like
+@samp{avr51}, this macro is not defined.
-@item -mbwx
-@itemx -mno-bwx
-@itemx -mcix
-@itemx -mno-cix
-@itemx -mfix
-@itemx -mno-fix
-@itemx -mmax
-@itemx -mno-max
-@opindex mbwx
-@opindex mno-bwx
-@opindex mcix
-@opindex mno-cix
-@opindex mfix
-@opindex mno-fix
-@opindex mmax
-@opindex mno-max
-Indicate whether GCC should generate code to use the optional BWX,
-CIX, FIX and MAX instruction sets. The default is to use the instruction
-sets supported by the CPU type specified via @option{-mcpu=} option or that
-of the CPU on which GCC was built if none is specified.
+@item __AVR_XMEGA__
+The device / architecture belongs to the XMEGA family of devices.
-@item -mfloat-vax
-@itemx -mfloat-ieee
-@opindex mfloat-vax
-@opindex mfloat-ieee
-Generate code that uses (does not use) VAX F and G floating-point
-arithmetic instead of IEEE single and double precision.
+@item __AVR_HAVE_ELPM__
+The device has the @code{ELPM} instruction.
-@item -mexplicit-relocs
-@itemx -mno-explicit-relocs
-@opindex mexplicit-relocs
-@opindex mno-explicit-relocs
-Older Alpha assemblers provided no way to generate symbol relocations
-except via assembler macros. Use of these macros does not allow
-optimal instruction scheduling. GNU binutils as of version 2.12
-supports a new syntax that allows the compiler to explicitly mark
-which relocations should apply to which instructions. This option
-is mostly useful for debugging, as GCC detects the capabilities of
-the assembler when it is built and sets the default accordingly.
+@item __AVR_HAVE_ELPMX__
+The device has the @code{ELPM R@var{n},Z} and @code{ELPM
+R@var{n},Z+} instructions.
-@item -msmall-data
-@itemx -mlarge-data
-@opindex msmall-data
-@opindex mlarge-data
-When @option{-mexplicit-relocs} is in effect, static data is
-accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
-is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
-(the @code{.sdata} and @code{.sbss} sections) and are accessed via
-16-bit relocations off of the @code{$gp} register. This limits the
-size of the small data area to 64KB, but allows the variables to be
-directly accessed via a single instruction.
-
-The default is @option{-mlarge-data}. With this option the data area
-is limited to just below 2GB@. Programs that require more than 2GB of
-data must use @code{malloc} or @code{mmap} to allocate the data in the
-heap instead of in the program's data segment.
-
-When generating code for shared libraries, @option{-fpic} implies
-@option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
-
-@item -msmall-text
-@itemx -mlarge-text
-@opindex msmall-text
-@opindex mlarge-text
-When @option{-msmall-text} is used, the compiler assumes that the
-code of the entire program (or shared library) fits in 4MB, and is
-thus reachable with a branch instruction. When @option{-msmall-data}
-is used, the compiler can assume that all local symbols share the
-same @code{$gp} value, and thus reduce the number of instructions
-required for a function call from 4 to 1.
-
-The default is @option{-mlarge-text}.
-
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set and instruction scheduling parameters for
-machine type @var{cpu_type}. You can specify either the @samp{EV}
-style name or the corresponding chip number. GCC supports scheduling
-parameters for the EV4, EV5 and EV6 family of processors and
-chooses the default values for the instruction set from the processor
-you specify. If you do not specify a processor type, GCC defaults
-to the processor on which the compiler was built.
-
-Supported values for @var{cpu_type} are
+@item __AVR_HAVE_MOVW__
+The device has the @code{MOVW} instruction to perform 16-bit
+register-register moves.
-@table @samp
-@item ev4
-@itemx ev45
-@itemx 21064
-Schedules as an EV4 and has no instruction set extensions.
+@item __AVR_HAVE_LPMX__
+The device has the @code{LPM R@var{n},Z} and
+@code{LPM R@var{n},Z+} instructions.
-@item ev5
-@itemx 21164
-Schedules as an EV5 and has no instruction set extensions.
+@item __AVR_HAVE_MUL__
+The device has a hardware multiplier.
-@item ev56
-@itemx 21164a
-Schedules as an EV5 and supports the BWX extension.
+@item __AVR_HAVE_JMP_CALL__
+The device has the @code{JMP} and @code{CALL} instructions.
+This is the case for devices with at least 16@tie{}KiB of program
+memory.
-@item pca56
-@itemx 21164pc
-@itemx 21164PC
-Schedules as an EV5 and supports the BWX and MAX extensions.
+@item __AVR_HAVE_EIJMP_EICALL__
+@itemx __AVR_3_BYTE_PC__
+The device has the @code{EIJMP} and @code{EICALL} instructions.
+This is the case for devices with more than 128@tie{}KiB of program memory.
+This also means that the program counter
+(PC) is 3@tie{}bytes wide.
-@item ev6
-@itemx 21264
-Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
+@item __AVR_2_BYTE_PC__
+The program counter (PC) is 2@tie{}bytes wide. This is the case for devices
+with up to 128@tie{}KiB of program memory.
-@item ev67
-@itemx 21264a
-Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
-@end table
+@item __AVR_HAVE_8BIT_SP__
+@itemx __AVR_HAVE_16BIT_SP__
+The stack pointer (SP) register is treated as 8-bit respectively
+16-bit register by the compiler.
+The definition of these macros is affected by @option{-mtiny-stack}.
-Native toolchains also support the value @samp{native},
-which selects the best architecture option for the host processor.
-@option{-mcpu=native} has no effect if GCC does not recognize
-the processor.
+@item __AVR_HAVE_SPH__
+@itemx __AVR_SP8__
+The device has the SPH (high part of stack pointer) special function
+register or has an 8-bit stack pointer, respectively.
+The definition of these macros is affected by @option{-mmcu=} and
+in the cases of @option{-mmcu=avr2} and @option{-mmcu=avr25} also
+by @option{-msp8}.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set only the instruction scheduling parameters for machine type
-@var{cpu_type}. The instruction set is not changed.
+@item __AVR_HAVE_RAMPD__
+@itemx __AVR_HAVE_RAMPX__
+@itemx __AVR_HAVE_RAMPY__
+@itemx __AVR_HAVE_RAMPZ__
+The device has the @code{RAMPD}, @code{RAMPX}, @code{RAMPY},
+@code{RAMPZ} special function register, respectively.
-Native toolchains also support the value @samp{native},
-which selects the best architecture option for the host processor.
-@option{-mtune=native} has no effect if GCC does not recognize
-the processor.
+@item __NO_INTERRUPTS__
+This macro reflects the @option{-mno-interrupts} command-line option.
-@item -mmemory-latency=@var{time}
-@opindex mmemory-latency
-Sets the latency the scheduler should assume for typical memory
-references as seen by the application. This number is highly
-dependent on the memory access patterns used by the application
-and the size of the external cache on the machine.
+@item __AVR_ERRATA_SKIP__
+@itemx __AVR_ERRATA_SKIP_JMP_CALL__
+Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit
+instructions because of a hardware erratum. Skip instructions are
+@code{SBRS}, @code{SBRC}, @code{SBIS}, @code{SBIC} and @code{CPSE}.
+The second macro is only defined if @code{__AVR_HAVE_JMP_CALL__} is also
+set.
-Valid options for @var{time} are
+@item __AVR_ISA_RMW__
+The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).
-@table @samp
-@item @var{number}
-A decimal number representing clock cycles.
+@item __AVR_SFR_OFFSET__=@var{offset}
+Instructions that can address I/O special function registers directly
+like @code{IN}, @code{OUT}, @code{SBI}, etc.@: may use a different
+address as if addressed by an instruction to access RAM like @code{LD}
+or @code{STS}. This offset depends on the device architecture and has
+to be subtracted from the RAM address in order to get the
+respective I/O@tie{}address.
-@item L1
-@itemx L2
-@itemx L3
-@itemx main
-The compiler contains estimates of the number of clock cycles for
-``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
-(also called Dcache, Scache, and Bcache), as well as to main memory.
-Note that L3 is only valid for EV5.
+@item __WITH_AVRLIBC__
+The compiler is configured to be used together with AVR-Libc.
+See the @option{--with-avrlibc} configure option.
-@end table
@end table
-@node FR30 Options
-@subsection FR30 Options
-@cindex FR30 Options
-
-These options are defined specifically for the FR30 port.
+@node Blackfin Options
+@subsection Blackfin Options
+@cindex Blackfin Options
@table @gcctabopt
+@item -mcpu=@var{cpu}@r{[}-@var{sirevision}@r{]}
+@opindex mcpu=
+Specifies the name of the target Blackfin processor. Currently, @var{cpu}
+can be one of @samp{bf512}, @samp{bf514}, @samp{bf516}, @samp{bf518},
+@samp{bf522}, @samp{bf523}, @samp{bf524}, @samp{bf525}, @samp{bf526},
+@samp{bf527}, @samp{bf531}, @samp{bf532}, @samp{bf533},
+@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
+@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
+@samp{bf542m}, @samp{bf544m}, @samp{bf547m}, @samp{bf548m}, @samp{bf549m},
+@samp{bf561}, @samp{bf592}.
-@item -msmall-model
-@opindex msmall-model
-Use the small address space model. This can produce smaller code, but
-it does assume that all symbolic values and addresses fit into a
-20-bit range.
-
-@item -mno-lsim
-@opindex mno-lsim
-Assume that runtime support has been provided and so there is no need
-to include the simulator library (@file{libsim.a}) on the linker
-command line.
-
-@end table
+The optional @var{sirevision} specifies the silicon revision of the target
+Blackfin processor. Any workarounds available for the targeted silicon revision
+are enabled. If @var{sirevision} is @samp{none}, no workarounds are enabled.
+If @var{sirevision} is @samp{any}, all workarounds for the targeted processor
+are enabled. The @code{__SILICON_REVISION__} macro is defined to two
+hexadecimal digits representing the major and minor numbers in the silicon
+revision. If @var{sirevision} is @samp{none}, the @code{__SILICON_REVISION__}
+is not defined. If @var{sirevision} is @samp{any}, the
+@code{__SILICON_REVISION__} is defined to be @code{0xffff}.
+If this optional @var{sirevision} is not used, GCC assumes the latest known
+silicon revision of the targeted Blackfin processor.
-@node FT32 Options
-@subsection FT32 Options
-@cindex FT32 Options
+GCC defines a preprocessor macro for the specified @var{cpu}.
+For the @samp{bfin-elf} toolchain, this option causes the hardware BSP
+provided by libgloss to be linked in if @option{-msim} is not given.
-These options are defined specifically for the FT32 port.
+Without this option, @samp{bf532} is used as the processor by default.
-@table @gcctabopt
+Note that support for @samp{bf561} is incomplete. For @samp{bf561},
+only the preprocessor macro is defined.
@item -msim
@opindex msim
Specifies that the program will be run on the simulator. This causes
-an alternate runtime startup and library to be linked.
-You must not use this option when generating programs that will run on
-real hardware; you must provide your own runtime library for whatever
-I/O functions are needed.
+the simulator BSP provided by libgloss to be linked in. This option
+has effect only for @samp{bfin-elf} toolchain.
+Certain other options, such as @option{-mid-shared-library} and
+@option{-mfdpic}, imply @option{-msim}.
-@item -mlra
-@opindex mlra
-Enable Local Register Allocation. This is still experimental for FT32,
-so by default the compiler uses standard reload.
+@item -momit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up and restore frame pointers and
+makes an extra register available in leaf functions. The option
+@option{-fomit-frame-pointer} removes the frame pointer for all functions,
+which might make debugging harder.
-@end table
+@item -mspecld-anomaly
+@opindex mspecld-anomaly
+When enabled, the compiler ensures that the generated code does not
+contain speculative loads after jump instructions. If this option is used,
+@code{__WORKAROUND_SPECULATIVE_LOADS} is defined.
-@node FRV Options
-@subsection FRV Options
-@cindex FRV Options
+@item -mno-specld-anomaly
+@opindex mno-specld-anomaly
+Don't generate extra code to prevent speculative loads from occurring.
-@table @gcctabopt
-@item -mgpr-32
-@opindex mgpr-32
+@item -mcsync-anomaly
+@opindex mcsync-anomaly
+When enabled, the compiler ensures that the generated code does not
+contain CSYNC or SSYNC instructions too soon after conditional branches.
+If this option is used, @code{__WORKAROUND_SPECULATIVE_SYNCS} is defined.
-Only use the first 32 general-purpose registers.
+@item -mno-csync-anomaly
+@opindex mno-csync-anomaly
+Don't generate extra code to prevent CSYNC or SSYNC instructions from
+occurring too soon after a conditional branch.
-@item -mgpr-64
-@opindex mgpr-64
+@item -mlow-64k
+@opindex mlow-64k
+When enabled, the compiler is free to take advantage of the knowledge that
+the entire program fits into the low 64k of memory.
-Use all 64 general-purpose registers.
+@item -mno-low-64k
+@opindex mno-low-64k
+Assume that the program is arbitrarily large. This is the default.
-@item -mfpr-32
-@opindex mfpr-32
+@item -mstack-check-l1
+@opindex mstack-check-l1
+Do stack checking using information placed into L1 scratchpad memory by the
+uClinux kernel.
-Use only the first 32 floating-point registers.
+@item -mid-shared-library
+@opindex mid-shared-library
+Generate code that supports shared libraries via the library ID method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies @option{-fPIC}.
+With a @samp{bfin-elf} target, this option implies @option{-msim}.
-@item -mfpr-64
-@opindex mfpr-64
+@item -mno-id-shared-library
+@opindex mno-id-shared-library
+Generate code that doesn't assume ID-based shared libraries are being used.
+This is the default.
-Use all 64 floating-point registers.
+@item -mleaf-id-shared-library
+@opindex mleaf-id-shared-library
+Generate code that supports shared libraries via the library ID method,
+but assumes that this library or executable won't link against any other
+ID shared libraries. That allows the compiler to use faster code for jumps
+and calls.
-@item -mhard-float
-@opindex mhard-float
+@item -mno-leaf-id-shared-library
+@opindex mno-leaf-id-shared-library
+Do not assume that the code being compiled won't link against any ID shared
+libraries. Slower code is generated for jump and call insns.
-Use hardware instructions for floating-point operations.
+@item -mshared-library-id=n
+@opindex mshared-library-id
+Specifies the identification number of the ID-based shared library being
+compiled. Specifying a value of 0 generates more compact code; specifying
+other values forces the allocation of that number to the current
+library but is no more space- or time-efficient than omitting this option.
-@item -msoft-float
-@opindex msoft-float
+@item -msep-data
+@opindex msep-data
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute in place in
+an environment without virtual memory management by eliminating relocations
+against the text section.
-Use library routines for floating-point operations.
+@item -mno-sep-data
+@opindex mno-sep-data
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
-@item -malloc-cc
-@opindex malloc-cc
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Tells the compiler to perform function calls by first loading the
+address of the function into a register and then performing a subroutine
+call on this register. This switch is needed if the target function
+lies outside of the 24-bit addressing range of the offset-based
+version of subroutine call instruction.
-Dynamically allocate condition code registers.
+This feature is not enabled by default. Specifying
+@option{-mno-long-calls} restores the default behavior. Note these
+switches have no effect on how the compiler generates code to handle
+function calls via function pointers.
-@item -mfixed-cc
-@opindex mfixed-cc
+@item -mfast-fp
+@opindex mfast-fp
+Link with the fast floating-point library. This library relaxes some of
+the IEEE floating-point standard's rules for checking inputs against
+Not-a-Number (NAN), in the interest of performance.
-Do not try to dynamically allocate condition code registers, only
-use @code{icc0} and @code{fcc0}.
+@item -minline-plt
+@opindex minline-plt
+Enable inlining of PLT entries in function calls to functions that are
+not known to bind locally. It has no effect without @option{-mfdpic}.
-@item -mdword
-@opindex mdword
+@item -mmulticore
+@opindex mmulticore
+Build a standalone application for multicore Blackfin processors.
+This option causes proper start files and link scripts supporting
+multicore to be used, and defines the macro @code{__BFIN_MULTICORE}.
+It can only be used with @option{-mcpu=bf561@r{[}-@var{sirevision}@r{]}}.
-Change ABI to use double word insns.
+This option can be used with @option{-mcorea} or @option{-mcoreb}, which
+selects the one-application-per-core programming model. Without
+@option{-mcorea} or @option{-mcoreb}, the single-application/dual-core
+programming model is used. In this model, the main function of Core B
+should be named as @code{coreb_main}.
-@item -mno-dword
-@opindex mno-dword
+If this option is not used, the single-core application programming
+model is used.
-Do not use double word instructions.
+@item -mcorea
+@opindex mcorea
+Build a standalone application for Core A of BF561 when using
+the one-application-per-core programming model. Proper start files
+and link scripts are used to support Core A, and the macro
+@code{__BFIN_COREA} is defined.
+This option can only be used in conjunction with @option{-mmulticore}.
-@item -mdouble
-@opindex mdouble
+@item -mcoreb
+@opindex mcoreb
+Build a standalone application for Core B of BF561 when using
+the one-application-per-core programming model. Proper start files
+and link scripts are used to support Core B, and the macro
+@code{__BFIN_COREB} is defined. When this option is used, @code{coreb_main}
+should be used instead of @code{main}.
+This option can only be used in conjunction with @option{-mmulticore}.
-Use floating-point double instructions.
+@item -msdram
+@opindex msdram
+Build a standalone application for SDRAM. Proper start files and
+link scripts are used to put the application into SDRAM, and the macro
+@code{__BFIN_SDRAM} is defined.
+The loader should initialize SDRAM before loading the application.
-@item -mno-double
-@opindex mno-double
+@item -micplb
+@opindex micplb
+Assume that ICPLBs are enabled at run time. This has an effect on certain
+anomaly workarounds. For Linux targets, the default is to assume ICPLBs
+are enabled; for standalone applications the default is off.
+@end table
-Do not use floating-point double instructions.
+@node C6X Options
+@subsection C6X Options
+@cindex C6X Options
-@item -mmedia
-@opindex mmedia
+@table @gcctabopt
+@item -march=@var{name}
+@opindex march
+This specifies the name of the target architecture. GCC uses this
+name to determine what kind of instructions it can emit when generating
+assembly code. Permissible names are: @samp{c62x},
+@samp{c64x}, @samp{c64x+}, @samp{c67x}, @samp{c67x+}, @samp{c674x}.
-Use media instructions.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a big-endian target.
-@item -mno-media
-@opindex mno-media
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a little-endian target. This is the default.
-Do not use media instructions.
+@item -msim
+@opindex msim
+Choose startup files and linker script suitable for the simulator.
-@item -mmuladd
-@opindex mmuladd
+@item -msdata=default
+@opindex msdata=default
+Put small global and static data in the @code{.neardata} section,
+which is pointed to by register @code{B14}. Put small uninitialized
+global and static data in the @code{.bss} section, which is adjacent
+to the @code{.neardata} section. Put small read-only data into the
+@code{.rodata} section. The corresponding sections used for large
+pieces of data are @code{.fardata}, @code{.far} and @code{.const}.
-Use multiply and add/subtract instructions.
+@item -msdata=all
+@opindex msdata=all
+Put all data, not just small objects, into the sections reserved for
+small data, and use addressing relative to the @code{B14} register to
+access them.
-@item -mno-muladd
-@opindex mno-muladd
+@item -msdata=none
+@opindex msdata=none
+Make no use of the sections reserved for small data, and use absolute
+addresses to access all data. Put all initialized global and static
+data in the @code{.fardata} section, and all uninitialized data in the
+@code{.far} section. Put all constant data into the @code{.const}
+section.
+@end table
-Do not use multiply and add/subtract instructions.
+@node CRIS Options
+@subsection CRIS Options
+@cindex CRIS Options
-@item -mfdpic
-@opindex mfdpic
+These options are defined specifically for the CRIS ports.
-Select the FDPIC ABI, which uses function descriptors to represent
-pointers to functions. Without any PIC/PIE-related options, it
-implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
-assumes GOT entries and small data are within a 12-bit range from the
-GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
-are computed with 32 bits.
-With a @samp{bfin-elf} target, this option implies @option{-msim}.
+@table @gcctabopt
+@item -march=@var{architecture-type}
+@itemx -mcpu=@var{architecture-type}
+@opindex march
+@opindex mcpu
+Generate code for the specified architecture. The choices for
+@var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
+respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX@.
+Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
+@samp{v10}.
-@item -minline-plt
-@opindex minline-plt
+@item -mtune=@var{architecture-type}
+@opindex mtune
+Tune to @var{architecture-type} everything applicable about the generated
+code, except for the ABI and the set of available instructions. The
+choices for @var{architecture-type} are the same as for
+@option{-march=@var{architecture-type}}.
-Enable inlining of PLT entries in function calls to functions that are
-not known to bind locally. It has no effect without @option{-mfdpic}.
-It's enabled by default if optimizing for speed and compiling for
-shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
-optimization option such as @option{-O3} or above is present in the
-command line.
+@item -mmax-stack-frame=@var{n}
+@opindex mmax-stack-frame
+Warn when the stack frame of a function exceeds @var{n} bytes.
-@item -mTLS
-@opindex mTLS
+@item -metrax4
+@itemx -metrax100
+@opindex metrax4
+@opindex metrax100
+The options @option{-metrax4} and @option{-metrax100} are synonyms for
+@option{-march=v3} and @option{-march=v8} respectively.
-Assume a large TLS segment when generating thread-local code.
+@item -mmul-bug-workaround
+@itemx -mno-mul-bug-workaround
+@opindex mmul-bug-workaround
+@opindex mno-mul-bug-workaround
+Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
+models where it applies. This option is active by default.
-@item -mtls
-@opindex mtls
+@item -mpdebug
+@opindex mpdebug
+Enable CRIS-specific verbose debug-related information in the assembly
+code. This option also has the effect of turning off the @samp{#NO_APP}
+formatted-code indicator to the assembler at the beginning of the
+assembly file.
-Do not assume a large TLS segment when generating thread-local code.
+@item -mcc-init
+@opindex mcc-init
+Do not use condition-code results from previous instruction; always emit
+compare and test instructions before use of condition codes.
-@item -mgprel-ro
-@opindex mgprel-ro
-
-Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
-that is known to be in read-only sections. It's enabled by default,
-except for @option{-fpic} or @option{-fpie}: even though it may help
-make the global offset table smaller, it trades 1 instruction for 4.
-With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
-one of which may be shared by multiple symbols, and it avoids the need
-for a GOT entry for the referenced symbol, so it's more likely to be a
-win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
+@item -mno-side-effects
+@opindex mno-side-effects
+Do not emit instructions with side effects in addressing modes other than
+post-increment.
-@item -multilib-library-pic
-@opindex multilib-library-pic
+@item -mstack-align
+@itemx -mno-stack-align
+@itemx -mdata-align
+@itemx -mno-data-align
+@itemx -mconst-align
+@itemx -mno-const-align
+@opindex mstack-align
+@opindex mno-stack-align
+@opindex mdata-align
+@opindex mno-data-align
+@opindex mconst-align
+@opindex mno-const-align
+These options (@samp{no-} options) arrange (eliminate arrangements) for the
+stack frame, individual data and constants to be aligned for the maximum
+single data access size for the chosen CPU model. The default is to
+arrange for 32-bit alignment. ABI details such as structure layout are
+not affected by these options.
-Link with the (library, not FD) pic libraries. It's implied by
-@option{-mlibrary-pic}, as well as by @option{-fPIC} and
-@option{-fpic} without @option{-mfdpic}. You should never have to use
-it explicitly.
+@item -m32-bit
+@itemx -m16-bit
+@itemx -m8-bit
+@opindex m32-bit
+@opindex m16-bit
+@opindex m8-bit
+Similar to the stack- data- and const-align options above, these options
+arrange for stack frame, writable data and constants to all be 32-bit,
+16-bit or 8-bit aligned. The default is 32-bit alignment.
-@item -mlinked-fp
-@opindex mlinked-fp
+@item -mno-prologue-epilogue
+@itemx -mprologue-epilogue
+@opindex mno-prologue-epilogue
+@opindex mprologue-epilogue
+With @option{-mno-prologue-epilogue}, the normal function prologue and
+epilogue which set up the stack frame are omitted and no return
+instructions or return sequences are generated in the code. Use this
+option only together with visual inspection of the compiled code: no
+warnings or errors are generated when call-saved registers must be saved,
+or storage for local variables needs to be allocated.
-Follow the EABI requirement of always creating a frame pointer whenever
-a stack frame is allocated. This option is enabled by default and can
-be disabled with @option{-mno-linked-fp}.
+@item -mno-gotplt
+@itemx -mgotplt
+@opindex mno-gotplt
+@opindex mgotplt
+With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
+instruction sequences that load addresses for functions from the PLT part
+of the GOT rather than (traditional on other architectures) calls to the
+PLT@. The default is @option{-mgotplt}.
-@item -mlong-calls
-@opindex mlong-calls
+@item -melf
+@opindex melf
+Legacy no-op option only recognized with the cris-axis-elf and
+cris-axis-linux-gnu targets.
-Use indirect addressing to call functions outside the current
-compilation unit. This allows the functions to be placed anywhere
-within the 32-bit address space.
+@item -mlinux
+@opindex mlinux
+Legacy no-op option only recognized with the cris-axis-linux-gnu target.
-@item -malign-labels
-@opindex malign-labels
+@item -sim
+@opindex sim
+This option, recognized for the cris-axis-elf, arranges
+to link with input-output functions from a simulator library. Code,
+initialized data and zero-initialized data are allocated consecutively.
-Try to align labels to an 8-byte boundary by inserting NOPs into the
-previous packet. This option only has an effect when VLIW packing
-is enabled. It doesn't create new packets; it merely adds NOPs to
-existing ones.
+@item -sim2
+@opindex sim2
+Like @option{-sim}, but pass linker options to locate initialized data at
+0x40000000 and zero-initialized data at 0x80000000.
+@end table
-@item -mlibrary-pic
-@opindex mlibrary-pic
+@node CR16 Options
+@subsection CR16 Options
+@cindex CR16 Options
-Generate position-independent EABI code.
+These options are defined specifically for the CR16 ports.
-@item -macc-4
-@opindex macc-4
+@table @gcctabopt
-Use only the first four media accumulator registers.
+@item -mmac
+@opindex mmac
+Enable the use of multiply-accumulate instructions. Disabled by default.
-@item -macc-8
-@opindex macc-8
+@item -mcr16cplus
+@itemx -mcr16c
+@opindex mcr16cplus
+@opindex mcr16c
+Generate code for CR16C or CR16C+ architecture. CR16C+ architecture
+is default.
-Use all eight media accumulator registers.
+@item -msim
+@opindex msim
+Links the library libsim.a which is in compatible with simulator. Applicable
+to ELF compiler only.
-@item -mpack
-@opindex mpack
+@item -mint32
+@opindex mint32
+Choose integer type as 32-bit wide.
-Pack VLIW instructions.
+@item -mbit-ops
+@opindex mbit-ops
+Generates @code{sbit}/@code{cbit} instructions for bit manipulations.
-@item -mno-pack
-@opindex mno-pack
+@item -mdata-model=@var{model}
+@opindex mdata-model
+Choose a data model. The choices for @var{model} are @samp{near},
+@samp{far} or @samp{medium}. @samp{medium} is default.
+However, @samp{far} is not valid with @option{-mcr16c}, as the
+CR16C architecture does not support the far data model.
+@end table
-Do not pack VLIW instructions.
+@node Darwin Options
+@subsection Darwin Options
+@cindex Darwin options
-@item -mno-eflags
-@opindex mno-eflags
+These options are defined for all architectures running the Darwin operating
+system.
-Do not mark ABI switches in e_flags.
+FSF GCC on Darwin does not create ``fat'' object files; it creates
+an object file for the single architecture that GCC was built to
+target. Apple's GCC on Darwin does create ``fat'' files if multiple
+@option{-arch} options are used; it does so by running the compiler or
+linker multiple times and joining the results together with
+@file{lipo}.
-@item -mcond-move
-@opindex mcond-move
+The subtype of the file created (like @samp{ppc7400} or @samp{ppc970} or
+@samp{i686}) is determined by the flags that specify the ISA
+that GCC is targeting, like @option{-mcpu} or @option{-march}. The
+@option{-force_cpusubtype_ALL} option can be used to override this.
-Enable the use of conditional-move instructions (default).
+The Darwin tools vary in their behavior when presented with an ISA
+mismatch. The assembler, @file{as}, only permits instructions to
+be used that are valid for the subtype of the file it is generating,
+so you cannot put 64-bit instructions in a @samp{ppc750} object file.
+The linker for shared libraries, @file{/usr/bin/libtool}, fails
+and prints an error if asked to create a shared library with a less
+restrictive subtype than its input files (for instance, trying to put
+a @samp{ppc970} object file in a @samp{ppc7400} library). The linker
+for executables, @command{ld}, quietly gives the executable the most
+restrictive subtype of any of its input files.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@table @gcctabopt
+@item -F@var{dir}
+@opindex F
+Add the framework directory @var{dir} to the head of the list of
+directories to be searched for header files. These directories are
+interleaved with those specified by @option{-I} options and are
+scanned in a left-to-right order.
-@item -mno-cond-move
-@opindex mno-cond-move
+A framework directory is a directory with frameworks in it. A
+framework is a directory with a @file{Headers} and/or
+@file{PrivateHeaders} directory contained directly in it that ends
+in @file{.framework}. The name of a framework is the name of this
+directory excluding the @file{.framework}. Headers associated with
+the framework are found in one of those two directories, with
+@file{Headers} being searched first. A subframework is a framework
+directory that is in a framework's @file{Frameworks} directory.
+Includes of subframework headers can only appear in a header of a
+framework that contains the subframework, or in a sibling subframework
+header. Two subframeworks are siblings if they occur in the same
+framework. A subframework should not have the same name as a
+framework; a warning is issued if this is violated. Currently a
+subframework cannot have subframeworks; in the future, the mechanism
+may be extended to support this. The standard frameworks can be found
+in @file{/System/Library/Frameworks} and
+@file{/Library/Frameworks}. An example include looks like
+@code{#include <Framework/header.h>}, where @file{Framework} denotes
+the name of the framework and @file{header.h} is found in the
+@file{PrivateHeaders} or @file{Headers} directory.
-Disable the use of conditional-move instructions.
+@item -iframework@var{dir}
+@opindex iframework
+Like @option{-F} except the directory is a treated as a system
+directory. The main difference between this @option{-iframework} and
+@option{-F} is that with @option{-iframework} the compiler does not
+warn about constructs contained within header files found via
+@var{dir}. This option is valid only for the C family of languages.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -gused
+@opindex gused
+Emit debugging information for symbols that are used. For stabs
+debugging format, this enables @option{-feliminate-unused-debug-symbols}.
+This is by default ON@.
-@item -mscc
-@opindex mscc
+@item -gfull
+@opindex gfull
+Emit debugging information for all symbols and types.
-Enable the use of conditional set instructions (default).
+@item -mmacosx-version-min=@var{version}
+The earliest version of MacOS X that this executable will run on
+is @var{version}. Typical values of @var{version} include @code{10.1},
+@code{10.2}, and @code{10.3.9}.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+If the compiler was built to use the system's headers by default,
+then the default for this option is the system version on which the
+compiler is running, otherwise the default is to make choices that
+are compatible with as many systems and code bases as possible.
-@item -mno-scc
-@opindex mno-scc
+@item -mkernel
+@opindex mkernel
+Enable kernel development mode. The @option{-mkernel} option sets
+@option{-static}, @option{-fno-common}, @option{-fno-use-cxa-atexit},
+@option{-fno-exceptions}, @option{-fno-non-call-exceptions},
+@option{-fapple-kext}, @option{-fno-weak} and @option{-fno-rtti} where
+applicable. This mode also sets @option{-mno-altivec},
+@option{-msoft-float}, @option{-fno-builtin} and
+@option{-mlong-branch} for PowerPC targets.
-Disable the use of conditional set instructions.
+@item -mone-byte-bool
+@opindex mone-byte-bool
+Override the defaults for @code{bool} so that @code{sizeof(bool)==1}.
+By default @code{sizeof(bool)} is @code{4} when compiling for
+Darwin/PowerPC and @code{1} when compiling for Darwin/x86, so this
+option has no effect on x86.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
-
-@item -mcond-exec
-@opindex mcond-exec
+@strong{Warning:} The @option{-mone-byte-bool} switch causes GCC
+to generate code that is not binary compatible with code generated
+without that switch. Using this switch may require recompiling all
+other modules in a program, including system libraries. Use this
+switch to conform to a non-default data model.
-Enable the use of conditional execution (default).
+@item -mfix-and-continue
+@itemx -ffix-and-continue
+@itemx -findirect-data
+@opindex mfix-and-continue
+@opindex ffix-and-continue
+@opindex findirect-data
+Generate code suitable for fast turnaround development, such as to
+allow GDB to dynamically load @file{.o} files into already-running
+programs. @option{-findirect-data} and @option{-ffix-and-continue}
+are provided for backwards compatibility.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -all_load
+@opindex all_load
+Loads all members of static archive libraries.
+See man ld(1) for more information.
-@item -mno-cond-exec
-@opindex mno-cond-exec
+@item -arch_errors_fatal
+@opindex arch_errors_fatal
+Cause the errors having to do with files that have the wrong architecture
+to be fatal.
-Disable the use of conditional execution.
+@item -bind_at_load
+@opindex bind_at_load
+Causes the output file to be marked such that the dynamic linker will
+bind all undefined references when the file is loaded or launched.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -bundle
+@opindex bundle
+Produce a Mach-o bundle format file.
+See man ld(1) for more information.
-@item -mvliw-branch
-@opindex mvliw-branch
+@item -bundle_loader @var{executable}
+@opindex bundle_loader
+This option specifies the @var{executable} that will load the build
+output file being linked. See man ld(1) for more information.
-Run a pass to pack branches into VLIW instructions (default).
+@item -dynamiclib
+@opindex dynamiclib
+When passed this option, GCC produces a dynamic library instead of
+an executable when linking, using the Darwin @file{libtool} command.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -force_cpusubtype_ALL
+@opindex force_cpusubtype_ALL
+This causes GCC's output file to have the @samp{ALL} subtype, instead of
+one controlled by the @option{-mcpu} or @option{-march} option.
-@item -mno-vliw-branch
-@opindex mno-vliw-branch
+@item -allowable_client @var{client_name}
+@itemx -client_name
+@itemx -compatibility_version
+@itemx -current_version
+@itemx -dead_strip
+@itemx -dependency-file
+@itemx -dylib_file
+@itemx -dylinker_install_name
+@itemx -dynamic
+@itemx -exported_symbols_list
+@itemx -filelist
+@need 800
+@itemx -flat_namespace
+@itemx -force_flat_namespace
+@itemx -headerpad_max_install_names
+@itemx -image_base
+@itemx -init
+@itemx -install_name
+@itemx -keep_private_externs
+@itemx -multi_module
+@itemx -multiply_defined
+@itemx -multiply_defined_unused
+@need 800
+@itemx -noall_load
+@itemx -no_dead_strip_inits_and_terms
+@itemx -nofixprebinding
+@itemx -nomultidefs
+@itemx -noprebind
+@itemx -noseglinkedit
+@itemx -pagezero_size
+@itemx -prebind
+@itemx -prebind_all_twolevel_modules
+@itemx -private_bundle
+@need 800
+@itemx -read_only_relocs
+@itemx -sectalign
+@itemx -sectobjectsymbols
+@itemx -whyload
+@itemx -seg1addr
+@itemx -sectcreate
+@itemx -sectobjectsymbols
+@itemx -sectorder
+@itemx -segaddr
+@itemx -segs_read_only_addr
+@need 800
+@itemx -segs_read_write_addr
+@itemx -seg_addr_table
+@itemx -seg_addr_table_filename
+@itemx -seglinkedit
+@itemx -segprot
+@itemx -segs_read_only_addr
+@itemx -segs_read_write_addr
+@itemx -single_module
+@itemx -static
+@itemx -sub_library
+@need 800
+@itemx -sub_umbrella
+@itemx -twolevel_namespace
+@itemx -umbrella
+@itemx -undefined
+@itemx -unexported_symbols_list
+@itemx -weak_reference_mismatches
+@itemx -whatsloaded
+@opindex allowable_client
+@opindex client_name
+@opindex compatibility_version
+@opindex current_version
+@opindex dead_strip
+@opindex dependency-file
+@opindex dylib_file
+@opindex dylinker_install_name
+@opindex dynamic
+@opindex exported_symbols_list
+@opindex filelist
+@opindex flat_namespace
+@opindex force_flat_namespace
+@opindex headerpad_max_install_names
+@opindex image_base
+@opindex init
+@opindex install_name
+@opindex keep_private_externs
+@opindex multi_module
+@opindex multiply_defined
+@opindex multiply_defined_unused
+@opindex noall_load
+@opindex no_dead_strip_inits_and_terms
+@opindex nofixprebinding
+@opindex nomultidefs
+@opindex noprebind
+@opindex noseglinkedit
+@opindex pagezero_size
+@opindex prebind
+@opindex prebind_all_twolevel_modules
+@opindex private_bundle
+@opindex read_only_relocs
+@opindex sectalign
+@opindex sectobjectsymbols
+@opindex whyload
+@opindex seg1addr
+@opindex sectcreate
+@opindex sectobjectsymbols
+@opindex sectorder
+@opindex segaddr
+@opindex segs_read_only_addr
+@opindex segs_read_write_addr
+@opindex seg_addr_table
+@opindex seg_addr_table_filename
+@opindex seglinkedit
+@opindex segprot
+@opindex segs_read_only_addr
+@opindex segs_read_write_addr
+@opindex single_module
+@opindex static
+@opindex sub_library
+@opindex sub_umbrella
+@opindex twolevel_namespace
+@opindex umbrella
+@opindex undefined
+@opindex unexported_symbols_list
+@opindex weak_reference_mismatches
+@opindex whatsloaded
+These options are passed to the Darwin linker. The Darwin linker man page
+describes them in detail.
+@end table
-Do not run a pass to pack branches into VLIW instructions.
+@node DEC Alpha Options
+@subsection DEC Alpha Options
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+These @samp{-m} options are defined for the DEC Alpha implementations:
-@item -mmulti-cond-exec
-@opindex mmulti-cond-exec
+@table @gcctabopt
+@item -mno-soft-float
+@itemx -msoft-float
+@opindex mno-soft-float
+@opindex msoft-float
+Use (do not use) the hardware floating-point instructions for
+floating-point operations. When @option{-msoft-float} is specified,
+functions in @file{libgcc.a} are used to perform floating-point
+operations. Unless they are replaced by routines that emulate the
+floating-point operations, or compiled in such a way as to call such
+emulations routines, these routines issue floating-point
+operations. If you are compiling for an Alpha without floating-point
+operations, you must ensure that the library is built so as not to call
+them.
-Enable optimization of @code{&&} and @code{||} in conditional execution
-(default).
+Note that Alpha implementations without floating-point operations are
+required to have floating-point registers.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mfp-reg
+@itemx -mno-fp-regs
+@opindex mfp-reg
+@opindex mno-fp-regs
+Generate code that uses (does not use) the floating-point register set.
+@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
+register set is not used, floating-point operands are passed in integer
+registers as if they were integers and floating-point results are passed
+in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
+so any function with a floating-point argument or return value called by code
+compiled with @option{-mno-fp-regs} must also be compiled with that
+option.
-@item -mno-multi-cond-exec
-@opindex mno-multi-cond-exec
+A typical use of this option is building a kernel that does not use,
+and hence need not save and restore, any floating-point registers.
-Disable optimization of @code{&&} and @code{||} in conditional execution.
+@item -mieee
+@opindex mieee
+The Alpha architecture implements floating-point hardware optimized for
+maximum performance. It is mostly compliant with the IEEE floating-point
+standard. However, for full compliance, software assistance is
+required. This option generates code fully IEEE-compliant code
+@emph{except} that the @var{inexact-flag} is not maintained (see below).
+If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
+defined during compilation. The resulting code is less efficient but is
+able to correctly support denormalized numbers and exceptional IEEE
+values such as not-a-number and plus/minus infinity. Other Alpha
+compilers call this option @option{-ieee_with_no_inexact}.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mieee-with-inexact
+@opindex mieee-with-inexact
+This is like @option{-mieee} except the generated code also maintains
+the IEEE @var{inexact-flag}. Turning on this option causes the
+generated code to implement fully-compliant IEEE math. In addition to
+@code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
+macro. On some Alpha implementations the resulting code may execute
+significantly slower than the code generated by default. Since there is
+very little code that depends on the @var{inexact-flag}, you should
+normally not specify this option. Other Alpha compilers call this
+option @option{-ieee_with_inexact}.
-@item -mnested-cond-exec
-@opindex mnested-cond-exec
-
-Enable nested conditional execution optimizations (default).
+@item -mfp-trap-mode=@var{trap-mode}
+@opindex mfp-trap-mode
+This option controls what floating-point related traps are enabled.
+Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
+The trap mode can be set to one of four values:
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@table @samp
+@item n
+This is the default (normal) setting. The only traps that are enabled
+are the ones that cannot be disabled in software (e.g., division by zero
+trap).
-@item -mno-nested-cond-exec
-@opindex mno-nested-cond-exec
+@item u
+In addition to the traps enabled by @samp{n}, underflow traps are enabled
+as well.
-Disable nested conditional execution optimizations.
+@item su
+Like @samp{u}, but the instructions are marked to be safe for software
+completion (see Alpha architecture manual for details).
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item sui
+Like @samp{su}, but inexact traps are enabled as well.
+@end table
-@item -moptimize-membar
-@opindex moptimize-membar
+@item -mfp-rounding-mode=@var{rounding-mode}
+@opindex mfp-rounding-mode
+Selects the IEEE rounding mode. Other Alpha compilers call this option
+@option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
+of:
-This switch removes redundant @code{membar} instructions from the
-compiler-generated code. It is enabled by default.
+@table @samp
+@item n
+Normal IEEE rounding mode. Floating-point numbers are rounded towards
+the nearest machine number or towards the even machine number in case
+of a tie.
-@item -mno-optimize-membar
-@opindex mno-optimize-membar
+@item m
+Round towards minus infinity.
-This switch disables the automatic removal of redundant @code{membar}
-instructions from the generated code.
+@item c
+Chopped rounding mode. Floating-point numbers are rounded towards zero.
-@item -mtomcat-stats
-@opindex mtomcat-stats
+@item d
+Dynamic rounding mode. A field in the floating-point control register
+(@var{fpcr}, see Alpha architecture reference manual) controls the
+rounding mode in effect. The C library initializes this register for
+rounding towards plus infinity. Thus, unless your program modifies the
+@var{fpcr}, @samp{d} corresponds to round towards plus infinity.
+@end table
-Cause gas to print out tomcat statistics.
+@item -mtrap-precision=@var{trap-precision}
+@opindex mtrap-precision
+In the Alpha architecture, floating-point traps are imprecise. This
+means without software assistance it is impossible to recover from a
+floating trap and program execution normally needs to be terminated.
+GCC can generate code that can assist operating system trap handlers
+in determining the exact location that caused a floating-point trap.
+Depending on the requirements of an application, different levels of
+precisions can be selected:
-@item -mcpu=@var{cpu}
-@opindex mcpu
+@table @samp
+@item p
+Program precision. This option is the default and means a trap handler
+can only identify which program caused a floating-point exception.
-Select the processor type for which to generate code. Possible values are
-@samp{frv}, @samp{fr550}, @samp{tomcat}, @samp{fr500}, @samp{fr450},
-@samp{fr405}, @samp{fr400}, @samp{fr300} and @samp{simple}.
+@item f
+Function precision. The trap handler can determine the function that
+caused a floating-point exception.
+@item i
+Instruction precision. The trap handler can determine the exact
+instruction that caused a floating-point exception.
@end table
-@node GNU/Linux Options
-@subsection GNU/Linux Options
+Other Alpha compilers provide the equivalent options called
+@option{-scope_safe} and @option{-resumption_safe}.
-These @samp{-m} options are defined for GNU/Linux targets:
+@item -mieee-conformant
+@opindex mieee-conformant
+This option marks the generated code as IEEE conformant. You must not
+use this option unless you also specify @option{-mtrap-precision=i} and either
+@option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
+is to emit the line @samp{.eflag 48} in the function prologue of the
+generated assembly file.
-@table @gcctabopt
-@item -mglibc
-@opindex mglibc
-Use the GNU C library. This is the default except
-on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and
-@samp{*-*-linux-*android*} targets.
+@item -mbuild-constants
+@opindex mbuild-constants
+Normally GCC examines a 32- or 64-bit integer constant to
+see if it can construct it from smaller constants in two or three
+instructions. If it cannot, it outputs the constant as a literal and
+generates code to load it from the data segment at run time.
-@item -muclibc
-@opindex muclibc
-Use uClibc C library. This is the default on
-@samp{*-*-linux-*uclibc*} targets.
+Use this option to require GCC to construct @emph{all} integer constants
+using code, even if it takes more instructions (the maximum is six).
-@item -mmusl
-@opindex mmusl
-Use the musl C library. This is the default on
-@samp{*-*-linux-*musl*} targets.
+You typically use this option to build a shared library dynamic
+loader. Itself a shared library, it must relocate itself in memory
+before it can find the variables and constants in its own data segment.
-@item -mbionic
-@opindex mbionic
-Use Bionic C library. This is the default on
-@samp{*-*-linux-*android*} targets.
+@item -mbwx
+@itemx -mno-bwx
+@itemx -mcix
+@itemx -mno-cix
+@itemx -mfix
+@itemx -mno-fix
+@itemx -mmax
+@itemx -mno-max
+@opindex mbwx
+@opindex mno-bwx
+@opindex mcix
+@opindex mno-cix
+@opindex mfix
+@opindex mno-fix
+@opindex mmax
+@opindex mno-max
+Indicate whether GCC should generate code to use the optional BWX,
+CIX, FIX and MAX instruction sets. The default is to use the instruction
+sets supported by the CPU type specified via @option{-mcpu=} option or that
+of the CPU on which GCC was built if none is specified.
-@item -mandroid
-@opindex mandroid
-Compile code compatible with Android platform. This is the default on
-@samp{*-*-linux-*android*} targets.
+@item -mfloat-vax
+@itemx -mfloat-ieee
+@opindex mfloat-vax
+@opindex mfloat-ieee
+Generate code that uses (does not use) VAX F and G floating-point
+arithmetic instead of IEEE single and double precision.
-When compiling, this option enables @option{-mbionic}, @option{-fPIC},
-@option{-fno-exceptions} and @option{-fno-rtti} by default. When linking,
-this option makes the GCC driver pass Android-specific options to the linker.
-Finally, this option causes the preprocessor macro @code{__ANDROID__}
-to be defined.
+@item -mexplicit-relocs
+@itemx -mno-explicit-relocs
+@opindex mexplicit-relocs
+@opindex mno-explicit-relocs
+Older Alpha assemblers provided no way to generate symbol relocations
+except via assembler macros. Use of these macros does not allow
+optimal instruction scheduling. GNU binutils as of version 2.12
+supports a new syntax that allows the compiler to explicitly mark
+which relocations should apply to which instructions. This option
+is mostly useful for debugging, as GCC detects the capabilities of
+the assembler when it is built and sets the default accordingly.
-@item -tno-android-cc
-@opindex tno-android-cc
-Disable compilation effects of @option{-mandroid}, i.e., do not enable
-@option{-mbionic}, @option{-fPIC}, @option{-fno-exceptions} and
-@option{-fno-rtti} by default.
+@item -msmall-data
+@itemx -mlarge-data
+@opindex msmall-data
+@opindex mlarge-data
+When @option{-mexplicit-relocs} is in effect, static data is
+accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
+is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
+(the @code{.sdata} and @code{.sbss} sections) and are accessed via
+16-bit relocations off of the @code{$gp} register. This limits the
+size of the small data area to 64KB, but allows the variables to be
+directly accessed via a single instruction.
-@item -tno-android-ld
-@opindex tno-android-ld
-Disable linking effects of @option{-mandroid}, i.e., pass standard Linux
-linking options to the linker.
+The default is @option{-mlarge-data}. With this option the data area
+is limited to just below 2GB@. Programs that require more than 2GB of
+data must use @code{malloc} or @code{mmap} to allocate the data in the
+heap instead of in the program's data segment.
-@end table
+When generating code for shared libraries, @option{-fpic} implies
+@option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
-@node H8/300 Options
-@subsection H8/300 Options
+@item -msmall-text
+@itemx -mlarge-text
+@opindex msmall-text
+@opindex mlarge-text
+When @option{-msmall-text} is used, the compiler assumes that the
+code of the entire program (or shared library) fits in 4MB, and is
+thus reachable with a branch instruction. When @option{-msmall-data}
+is used, the compiler can assume that all local symbols share the
+same @code{$gp} value, and thus reduce the number of instructions
+required for a function call from 4 to 1.
-These @samp{-m} options are defined for the H8/300 implementations:
+The default is @option{-mlarge-text}.
-@table @gcctabopt
-@item -mrelax
-@opindex mrelax
-Shorten some address references at link time, when possible; uses the
-linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
-ld, Using ld}, for a fuller description.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set and instruction scheduling parameters for
+machine type @var{cpu_type}. You can specify either the @samp{EV}
+style name or the corresponding chip number. GCC supports scheduling
+parameters for the EV4, EV5 and EV6 family of processors and
+chooses the default values for the instruction set from the processor
+you specify. If you do not specify a processor type, GCC defaults
+to the processor on which the compiler was built.
-@item -mh
-@opindex mh
-Generate code for the H8/300H@.
+Supported values for @var{cpu_type} are
-@item -ms
-@opindex ms
-Generate code for the H8S@.
+@table @samp
+@item ev4
+@itemx ev45
+@itemx 21064
+Schedules as an EV4 and has no instruction set extensions.
-@item -mn
-@opindex mn
-Generate code for the H8S and H8/300H in the normal mode. This switch
-must be used either with @option{-mh} or @option{-ms}.
+@item ev5
+@itemx 21164
+Schedules as an EV5 and has no instruction set extensions.
-@item -ms2600
-@opindex ms2600
-Generate code for the H8S/2600. This switch must be used with @option{-ms}.
+@item ev56
+@itemx 21164a
+Schedules as an EV5 and supports the BWX extension.
-@item -mexr
-@opindex mexr
-Extended registers are stored on stack before execution of function
-with monitor attribute. Default option is @option{-mexr}.
-This option is valid only for H8S targets.
-
-@item -mno-exr
-@opindex mno-exr
-Extended registers are not stored on stack before execution of function
-with monitor attribute. Default option is @option{-mno-exr}.
-This option is valid only for H8S targets.
+@item pca56
+@itemx 21164pc
+@itemx 21164PC
+Schedules as an EV5 and supports the BWX and MAX extensions.
-@item -mint32
-@opindex mint32
-Make @code{int} data 32 bits by default.
+@item ev6
+@itemx 21264
+Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
-@item -malign-300
-@opindex malign-300
-On the H8/300H and H8S, use the same alignment rules as for the H8/300.
-The default for the H8/300H and H8S is to align longs and floats on
-4-byte boundaries.
-@option{-malign-300} causes them to be aligned on 2-byte boundaries.
-This option has no effect on the H8/300.
+@item ev67
+@itemx 21264a
+Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
@end table
-@node HPPA Options
-@subsection HPPA Options
-@cindex HPPA Options
+Native toolchains also support the value @samp{native},
+which selects the best architecture option for the host processor.
+@option{-mcpu=native} has no effect if GCC does not recognize
+the processor.
-These @samp{-m} options are defined for the HPPA family of computers:
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set only the instruction scheduling parameters for machine type
+@var{cpu_type}. The instruction set is not changed.
-@table @gcctabopt
-@item -march=@var{architecture-type}
-@opindex march
-Generate code for the specified architecture. The choices for
-@var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
-1.1, and @samp{2.0} for PA 2.0 processors. Refer to
-@file{/usr/lib/sched.models} on an HP-UX system to determine the proper
-architecture option for your machine. Code compiled for lower numbered
-architectures runs on higher numbered architectures, but not the
-other way around.
+Native toolchains also support the value @samp{native},
+which selects the best architecture option for the host processor.
+@option{-mtune=native} has no effect if GCC does not recognize
+the processor.
-@item -mpa-risc-1-0
-@itemx -mpa-risc-1-1
-@itemx -mpa-risc-2-0
-@opindex mpa-risc-1-0
-@opindex mpa-risc-1-1
-@opindex mpa-risc-2-0
-Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
+@item -mmemory-latency=@var{time}
+@opindex mmemory-latency
+Sets the latency the scheduler should assume for typical memory
+references as seen by the application. This number is highly
+dependent on the memory access patterns used by the application
+and the size of the external cache on the machine.
-@item -mjump-in-delay
-@opindex mjump-in-delay
-This option is ignored and provided for compatibility purposes only.
+Valid options for @var{time} are
-@item -mdisable-fpregs
-@opindex mdisable-fpregs
-Prevent floating-point registers from being used in any manner. This is
-necessary for compiling kernels that perform lazy context switching of
-floating-point registers. If you use this option and attempt to perform
-floating-point operations, the compiler aborts.
+@table @samp
+@item @var{number}
+A decimal number representing clock cycles.
-@item -mdisable-indexing
-@opindex mdisable-indexing
-Prevent the compiler from using indexing address modes. This avoids some
-rather obscure problems when compiling MIG generated code under MACH@.
+@item L1
+@itemx L2
+@itemx L3
+@itemx main
+The compiler contains estimates of the number of clock cycles for
+``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
+(also called Dcache, Scache, and Bcache), as well as to main memory.
+Note that L3 is only valid for EV5.
-@item -mno-space-regs
-@opindex mno-space-regs
-Generate code that assumes the target has no space registers. This allows
-GCC to generate faster indirect calls and use unscaled index address modes.
+@end table
+@end table
-Such code is suitable for level 0 PA systems and kernels.
+@node FR30 Options
+@subsection FR30 Options
+@cindex FR30 Options
-@item -mfast-indirect-calls
-@opindex mfast-indirect-calls
-Generate code that assumes calls never cross space boundaries. This
-allows GCC to emit code that performs faster indirect calls.
+These options are defined specifically for the FR30 port.
-This option does not work in the presence of shared libraries or nested
-functions.
+@table @gcctabopt
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator cannot use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
+@item -msmall-model
+@opindex msmall-model
+Use the small address space model. This can produce smaller code, but
+it does assume that all symbolic values and addresses fit into a
+20-bit range.
-@item -mlong-load-store
-@opindex mlong-load-store
-Generate 3-instruction load and store sequences as sometimes required by
-the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
-the HP compilers.
+@item -mno-lsim
+@opindex mno-lsim
+Assume that runtime support has been provided and so there is no need
+to include the simulator library (@file{libsim.a}) on the linker
+command line.
-@item -mportable-runtime
-@opindex mportable-runtime
-Use the portable calling conventions proposed by HP for ELF systems.
+@end table
-@item -mgas
-@opindex mgas
-Enable the use of assembler directives only GAS understands.
+@node FT32 Options
+@subsection FT32 Options
+@cindex FT32 Options
-@item -mschedule=@var{cpu-type}
-@opindex mschedule
-Schedule code according to the constraints for the machine type
-@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
-@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
-to @file{/usr/lib/sched.models} on an HP-UX system to determine the
-proper scheduling option for your machine. The default scheduling is
-@samp{8000}.
+These options are defined specifically for the FT32 port.
-@item -mlinker-opt
-@opindex mlinker-opt
-Enable the optimization pass in the HP-UX linker. Note this makes symbolic
-debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
-linkers in which they give bogus error messages when linking some programs.
+@table @gcctabopt
-@item -msoft-float
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all HPPA
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation.
+@item -msim
+@opindex msim
+Specifies that the program will be run on the simulator. This causes
+an alternate runtime startup and library to be linked.
+You must not use this option when generating programs that will run on
+real hardware; you must provide your own runtime library for whatever
+I/O functions are needed.
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
+@item -mlra
+@opindex mlra
+Enable Local Register Allocation. This is still experimental for FT32,
+so by default the compiler uses standard reload.
-@item -msio
-@opindex msio
-Generate the predefine, @code{_SIO}, for server IO@. The default is
-@option{-mwsio}. This generates the predefines, @code{__hp9000s700},
-@code{__hp9000s700__} and @code{_WSIO}, for workstation IO@. These
-options are available under HP-UX and HI-UX@.
+@end table
-@item -mgnu-ld
-@opindex mgnu-ld
-Use options specific to GNU @command{ld}.
-This passes @option{-shared} to @command{ld} when
-building a shared library. It is the default when GCC is configured,
-explicitly or implicitly, with the GNU linker. This option does not
-affect which @command{ld} is called; it only changes what parameters
-are passed to that @command{ld}.
-The @command{ld} that is called is determined by the
-@option{--with-ld} configure option, GCC's program search path, and
-finally by the user's @env{PATH}. The linker used by GCC can be printed
-using @samp{which `gcc -print-prog-name=ld`}. This option is only available
-on the 64-bit HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
+@node FRV Options
+@subsection FRV Options
+@cindex FRV Options
-@item -mhp-ld
-@opindex mhp-ld
-Use options specific to HP @command{ld}.
-This passes @option{-b} to @command{ld} when building
-a shared library and passes @option{+Accept TypeMismatch} to @command{ld} on all
-links. It is the default when GCC is configured, explicitly or
-implicitly, with the HP linker. This option does not affect
-which @command{ld} is called; it only changes what parameters are passed to that
-@command{ld}.
-The @command{ld} that is called is determined by the @option{--with-ld}
-configure option, GCC's program search path, and finally by the user's
-@env{PATH}. The linker used by GCC can be printed using @samp{which
-`gcc -print-prog-name=ld`}. This option is only available on the 64-bit
-HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
+@table @gcctabopt
+@item -mgpr-32
+@opindex mgpr-32
-@item -mlong-calls
-@opindex mno-long-calls
-Generate code that uses long call sequences. This ensures that a call
-is always able to reach linker generated stubs. The default is to generate
-long calls only when the distance from the call site to the beginning
-of the function or translation unit, as the case may be, exceeds a
-predefined limit set by the branch type being used. The limits for
-normal calls are 7,600,000 and 240,000 bytes, respectively for the
-PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
-240,000 bytes.
+Only use the first 32 general-purpose registers.
-Distances are measured from the beginning of functions when using the
-@option{-ffunction-sections} option, or when using the @option{-mgas}
-and @option{-mno-portable-runtime} options together under HP-UX with
-the SOM linker.
+@item -mgpr-64
+@opindex mgpr-64
-It is normally not desirable to use this option as it degrades
-performance. However, it may be useful in large applications,
-particularly when partial linking is used to build the application.
+Use all 64 general-purpose registers.
-The types of long calls used depends on the capabilities of the
-assembler and linker, and the type of code being generated. The
-impact on systems that support long absolute calls, and long pic
-symbol-difference or pc-relative calls should be relatively small.
-However, an indirect call is used on 32-bit ELF systems in pic code
-and it is quite long.
+@item -mfpr-32
+@opindex mfpr-32
-@item -munix=@var{unix-std}
-@opindex march
-Generate compiler predefines and select a startfile for the specified
-UNIX standard. The choices for @var{unix-std} are @samp{93}, @samp{95}
-and @samp{98}. @samp{93} is supported on all HP-UX versions. @samp{95}
-is available on HP-UX 10.10 and later. @samp{98} is available on HP-UX
-11.11 and later. The default values are @samp{93} for HP-UX 10.00,
-@samp{95} for HP-UX 10.10 though to 11.00, and @samp{98} for HP-UX 11.11
-and later.
+Use only the first 32 floating-point registers.
-@option{-munix=93} provides the same predefines as GCC 3.3 and 3.4.
-@option{-munix=95} provides additional predefines for @code{XOPEN_UNIX}
-and @code{_XOPEN_SOURCE_EXTENDED}, and the startfile @file{unix95.o}.
-@option{-munix=98} provides additional predefines for @code{_XOPEN_UNIX},
-@code{_XOPEN_SOURCE_EXTENDED}, @code{_INCLUDE__STDC_A1_SOURCE} and
-@code{_INCLUDE_XOPEN_SOURCE_500}, and the startfile @file{unix98.o}.
+@item -mfpr-64
+@opindex mfpr-64
-It is @emph{important} to note that this option changes the interfaces
-for various library routines. It also affects the operational behavior
-of the C library. Thus, @emph{extreme} care is needed in using this
-option.
+Use all 64 floating-point registers.
-Library code that is intended to operate with more than one UNIX
-standard must test, set and restore the variable @code{__xpg4_extended_mask}
-as appropriate. Most GNU software doesn't provide this capability.
+@item -mhard-float
+@opindex mhard-float
-@item -nolibdld
-@opindex nolibdld
-Suppress the generation of link options to search libdld.sl when the
-@option{-static} option is specified on HP-UX 10 and later.
+Use hardware instructions for floating-point operations.
-@item -static
-@opindex static
-The HP-UX implementation of setlocale in libc has a dependency on
-libdld.sl. There isn't an archive version of libdld.sl. Thus,
-when the @option{-static} option is specified, special link options
-are needed to resolve this dependency.
+@item -msoft-float
+@opindex msoft-float
-On HP-UX 10 and later, the GCC driver adds the necessary options to
-link with libdld.sl when the @option{-static} option is specified.
-This causes the resulting binary to be dynamic. On the 64-bit port,
-the linkers generate dynamic binaries by default in any case. The
-@option{-nolibdld} option can be used to prevent the GCC driver from
-adding these link options.
+Use library routines for floating-point operations.
-@item -threads
-@opindex threads
-Add support for multithreading with the @dfn{dce thread} library
-under HP-UX@. This option sets flags for both the preprocessor and
-linker.
-@end table
+@item -malloc-cc
+@opindex malloc-cc
-@node IA-64 Options
-@subsection IA-64 Options
-@cindex IA-64 Options
+Dynamically allocate condition code registers.
-These are the @samp{-m} options defined for the Intel IA-64 architecture.
+@item -mfixed-cc
+@opindex mfixed-cc
-@table @gcctabopt
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a big-endian target. This is the default for HP-UX@.
+Do not try to dynamically allocate condition code registers, only
+use @code{icc0} and @code{fcc0}.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a little-endian target. This is the default for AIX5
-and GNU/Linux.
+@item -mdword
+@opindex mdword
-@item -mgnu-as
-@itemx -mno-gnu-as
-@opindex mgnu-as
-@opindex mno-gnu-as
-Generate (or don't) code for the GNU assembler. This is the default.
-@c Also, this is the default if the configure option @option{--with-gnu-as}
-@c is used.
+Change ABI to use double word insns.
-@item -mgnu-ld
-@itemx -mno-gnu-ld
-@opindex mgnu-ld
-@opindex mno-gnu-ld
-Generate (or don't) code for the GNU linker. This is the default.
-@c Also, this is the default if the configure option @option{--with-gnu-ld}
-@c is used.
+@item -mno-dword
+@opindex mno-dword
-@item -mno-pic
-@opindex mno-pic
-Generate code that does not use a global pointer register. The result
-is not position independent code, and violates the IA-64 ABI@.
+Do not use double word instructions.
-@item -mvolatile-asm-stop
-@itemx -mno-volatile-asm-stop
-@opindex mvolatile-asm-stop
-@opindex mno-volatile-asm-stop
-Generate (or don't) a stop bit immediately before and after volatile asm
-statements.
+@item -mdouble
+@opindex mdouble
-@item -mregister-names
-@itemx -mno-register-names
-@opindex mregister-names
-@opindex mno-register-names
-Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
-the stacked registers. This may make assembler output more readable.
+Use floating-point double instructions.
-@item -mno-sdata
-@itemx -msdata
-@opindex mno-sdata
-@opindex msdata
-Disable (or enable) optimizations that use the small data section. This may
-be useful for working around optimizer bugs.
+@item -mno-double
+@opindex mno-double
-@item -mconstant-gp
-@opindex mconstant-gp
-Generate code that uses a single constant global pointer value. This is
-useful when compiling kernel code.
+Do not use floating-point double instructions.
-@item -mauto-pic
-@opindex mauto-pic
-Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
-This is useful when compiling firmware code.
+@item -mmedia
+@opindex mmedia
-@item -minline-float-divide-min-latency
-@opindex minline-float-divide-min-latency
-Generate code for inline divides of floating-point values
-using the minimum latency algorithm.
+Use media instructions.
-@item -minline-float-divide-max-throughput
-@opindex minline-float-divide-max-throughput
-Generate code for inline divides of floating-point values
-using the maximum throughput algorithm.
+@item -mno-media
+@opindex mno-media
-@item -mno-inline-float-divide
-@opindex mno-inline-float-divide
-Do not generate inline code for divides of floating-point values.
+Do not use media instructions.
-@item -minline-int-divide-min-latency
-@opindex minline-int-divide-min-latency
-Generate code for inline divides of integer values
-using the minimum latency algorithm.
+@item -mmuladd
+@opindex mmuladd
-@item -minline-int-divide-max-throughput
-@opindex minline-int-divide-max-throughput
-Generate code for inline divides of integer values
-using the maximum throughput algorithm.
+Use multiply and add/subtract instructions.
-@item -mno-inline-int-divide
-@opindex mno-inline-int-divide
-Do not generate inline code for divides of integer values.
+@item -mno-muladd
+@opindex mno-muladd
-@item -minline-sqrt-min-latency
-@opindex minline-sqrt-min-latency
-Generate code for inline square roots
-using the minimum latency algorithm.
+Do not use multiply and add/subtract instructions.
-@item -minline-sqrt-max-throughput
-@opindex minline-sqrt-max-throughput
-Generate code for inline square roots
-using the maximum throughput algorithm.
+@item -mfdpic
+@opindex mfdpic
-@item -mno-inline-sqrt
-@opindex mno-inline-sqrt
-Do not generate inline code for @code{sqrt}.
+Select the FDPIC ABI, which uses function descriptors to represent
+pointers to functions. Without any PIC/PIE-related options, it
+implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
+assumes GOT entries and small data are within a 12-bit range from the
+GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
+are computed with 32 bits.
+With a @samp{bfin-elf} target, this option implies @option{-msim}.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Do (don't) generate code that uses the fused multiply/add or multiply/subtract
-instructions. The default is to use these instructions.
+@item -minline-plt
+@opindex minline-plt
-@item -mno-dwarf2-asm
-@itemx -mdwarf2-asm
-@opindex mno-dwarf2-asm
-@opindex mdwarf2-asm
-Don't (or do) generate assembler code for the DWARF 2 line number debugging
-info. This may be useful when not using the GNU assembler.
+Enable inlining of PLT entries in function calls to functions that are
+not known to bind locally. It has no effect without @option{-mfdpic}.
+It's enabled by default if optimizing for speed and compiling for
+shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
+optimization option such as @option{-O3} or above is present in the
+command line.
-@item -mearly-stop-bits
-@itemx -mno-early-stop-bits
-@opindex mearly-stop-bits
-@opindex mno-early-stop-bits
-Allow stop bits to be placed earlier than immediately preceding the
-instruction that triggered the stop bit. This can improve instruction
-scheduling, but does not always do so.
+@item -mTLS
+@opindex mTLS
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator cannot use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
+Assume a large TLS segment when generating thread-local code.
-@item -mtls-size=@var{tls-size}
-@opindex mtls-size
-Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
-64.
+@item -mtls
+@opindex mtls
-@item -mtune=@var{cpu-type}
-@opindex mtune
-Tune the instruction scheduling for a particular CPU, Valid values are
-@samp{itanium}, @samp{itanium1}, @samp{merced}, @samp{itanium2},
-and @samp{mckinley}.
+Do not assume a large TLS segment when generating thread-local code.
-@item -milp32
-@itemx -mlp64
-@opindex milp32
-@opindex mlp64
-Generate code for a 32-bit or 64-bit environment.
-The 32-bit environment sets int, long and pointer to 32 bits.
-The 64-bit environment sets int to 32 bits and long and pointer
-to 64 bits. These are HP-UX specific flags.
+@item -mgprel-ro
+@opindex mgprel-ro
-@item -mno-sched-br-data-spec
-@itemx -msched-br-data-spec
-@opindex mno-sched-br-data-spec
-@opindex msched-br-data-spec
-(Dis/En)able data speculative scheduling before reload.
-This results in generation of @code{ld.a} instructions and
-the corresponding check instructions (@code{ld.c} / @code{chk.a}).
-The default is 'disable'.
+Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
+that is known to be in read-only sections. It's enabled by default,
+except for @option{-fpic} or @option{-fpie}: even though it may help
+make the global offset table smaller, it trades 1 instruction for 4.
+With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
+one of which may be shared by multiple symbols, and it avoids the need
+for a GOT entry for the referenced symbol, so it's more likely to be a
+win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
-@item -msched-ar-data-spec
-@itemx -mno-sched-ar-data-spec
-@opindex msched-ar-data-spec
-@opindex mno-sched-ar-data-spec
-(En/Dis)able data speculative scheduling after reload.
-This results in generation of @code{ld.a} instructions and
-the corresponding check instructions (@code{ld.c} / @code{chk.a}).
-The default is 'enable'.
+@item -multilib-library-pic
+@opindex multilib-library-pic
-@item -mno-sched-control-spec
-@itemx -msched-control-spec
-@opindex mno-sched-control-spec
-@opindex msched-control-spec
-(Dis/En)able control speculative scheduling. This feature is
-available only during region scheduling (i.e.@: before reload).
-This results in generation of the @code{ld.s} instructions and
-the corresponding check instructions @code{chk.s}.
-The default is 'disable'.
+Link with the (library, not FD) pic libraries. It's implied by
+@option{-mlibrary-pic}, as well as by @option{-fPIC} and
+@option{-fpic} without @option{-mfdpic}. You should never have to use
+it explicitly.
-@item -msched-br-in-data-spec
-@itemx -mno-sched-br-in-data-spec
-@opindex msched-br-in-data-spec
-@opindex mno-sched-br-in-data-spec
-(En/Dis)able speculative scheduling of the instructions that
-are dependent on the data speculative loads before reload.
-This is effective only with @option{-msched-br-data-spec} enabled.
-The default is 'enable'.
+@item -mlinked-fp
+@opindex mlinked-fp
-@item -msched-ar-in-data-spec
-@itemx -mno-sched-ar-in-data-spec
-@opindex msched-ar-in-data-spec
-@opindex mno-sched-ar-in-data-spec
-(En/Dis)able speculative scheduling of the instructions that
-are dependent on the data speculative loads after reload.
-This is effective only with @option{-msched-ar-data-spec} enabled.
-The default is 'enable'.
+Follow the EABI requirement of always creating a frame pointer whenever
+a stack frame is allocated. This option is enabled by default and can
+be disabled with @option{-mno-linked-fp}.
-@item -msched-in-control-spec
-@itemx -mno-sched-in-control-spec
-@opindex msched-in-control-spec
-@opindex mno-sched-in-control-spec
-(En/Dis)able speculative scheduling of the instructions that
-are dependent on the control speculative loads.
-This is effective only with @option{-msched-control-spec} enabled.
-The default is 'enable'.
+@item -mlong-calls
+@opindex mlong-calls
-@item -mno-sched-prefer-non-data-spec-insns
-@itemx -msched-prefer-non-data-spec-insns
-@opindex mno-sched-prefer-non-data-spec-insns
-@opindex msched-prefer-non-data-spec-insns
-If enabled, data-speculative instructions are chosen for schedule
-only if there are no other choices at the moment. This makes
-the use of the data speculation much more conservative.
-The default is 'disable'.
+Use indirect addressing to call functions outside the current
+compilation unit. This allows the functions to be placed anywhere
+within the 32-bit address space.
-@item -mno-sched-prefer-non-control-spec-insns
-@itemx -msched-prefer-non-control-spec-insns
-@opindex mno-sched-prefer-non-control-spec-insns
-@opindex msched-prefer-non-control-spec-insns
-If enabled, control-speculative instructions are chosen for schedule
-only if there are no other choices at the moment. This makes
-the use of the control speculation much more conservative.
-The default is 'disable'.
+@item -malign-labels
+@opindex malign-labels
-@item -mno-sched-count-spec-in-critical-path
-@itemx -msched-count-spec-in-critical-path
-@opindex mno-sched-count-spec-in-critical-path
-@opindex msched-count-spec-in-critical-path
-If enabled, speculative dependencies are considered during
-computation of the instructions priorities. This makes the use of the
-speculation a bit more conservative.
-The default is 'disable'.
+Try to align labels to an 8-byte boundary by inserting NOPs into the
+previous packet. This option only has an effect when VLIW packing
+is enabled. It doesn't create new packets; it merely adds NOPs to
+existing ones.
-@item -msched-spec-ldc
-@opindex msched-spec-ldc
-Use a simple data speculation check. This option is on by default.
+@item -mlibrary-pic
+@opindex mlibrary-pic
-@item -msched-control-spec-ldc
-@opindex msched-spec-ldc
-Use a simple check for control speculation. This option is on by default.
+Generate position-independent EABI code.
-@item -msched-stop-bits-after-every-cycle
-@opindex msched-stop-bits-after-every-cycle
-Place a stop bit after every cycle when scheduling. This option is on
-by default.
+@item -macc-4
+@opindex macc-4
-@item -msched-fp-mem-deps-zero-cost
-@opindex msched-fp-mem-deps-zero-cost
-Assume that floating-point stores and loads are not likely to cause a conflict
-when placed into the same instruction group. This option is disabled by
-default.
+Use only the first four media accumulator registers.
-@item -msel-sched-dont-check-control-spec
-@opindex msel-sched-dont-check-control-spec
-Generate checks for control speculation in selective scheduling.
-This flag is disabled by default.
+@item -macc-8
+@opindex macc-8
-@item -msched-max-memory-insns=@var{max-insns}
-@opindex msched-max-memory-insns
-Limit on the number of memory insns per instruction group, giving lower
-priority to subsequent memory insns attempting to schedule in the same
-instruction group. Frequently useful to prevent cache bank conflicts.
-The default value is 1.
+Use all eight media accumulator registers.
-@item -msched-max-memory-insns-hard-limit
-@opindex msched-max-memory-insns-hard-limit
-Makes the limit specified by @option{msched-max-memory-insns} a hard limit,
-disallowing more than that number in an instruction group.
-Otherwise, the limit is ``soft'', meaning that non-memory operations
-are preferred when the limit is reached, but memory operations may still
-be scheduled.
+@item -mpack
+@opindex mpack
-@end table
+Pack VLIW instructions.
-@node LM32 Options
-@subsection LM32 Options
-@cindex LM32 options
+@item -mno-pack
+@opindex mno-pack
-These @option{-m} options are defined for the LatticeMico32 architecture:
+Do not pack VLIW instructions.
-@table @gcctabopt
-@item -mbarrel-shift-enabled
-@opindex mbarrel-shift-enabled
-Enable barrel-shift instructions.
+@item -mno-eflags
+@opindex mno-eflags
-@item -mdivide-enabled
-@opindex mdivide-enabled
-Enable divide and modulus instructions.
+Do not mark ABI switches in e_flags.
-@item -mmultiply-enabled
-@opindex multiply-enabled
-Enable multiply instructions.
+@item -mcond-move
+@opindex mcond-move
-@item -msign-extend-enabled
-@opindex msign-extend-enabled
-Enable sign extend instructions.
+Enable the use of conditional-move instructions (default).
-@item -muser-enabled
-@opindex muser-enabled
-Enable user-defined instructions.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@end table
+@item -mno-cond-move
+@opindex mno-cond-move
-@node M32C Options
-@subsection M32C Options
-@cindex M32C options
+Disable the use of conditional-move instructions.
-@table @gcctabopt
-@item -mcpu=@var{name}
-@opindex mcpu=
-Select the CPU for which code is generated. @var{name} may be one of
-@samp{r8c} for the R8C/Tiny series, @samp{m16c} for the M16C (up to
-/60) series, @samp{m32cm} for the M16C/80 series, or @samp{m32c} for
-the M32C/80 series.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -msim
-@opindex msim
-Specifies that the program will be run on the simulator. This causes
-an alternate runtime library to be linked in which supports, for
-example, file I/O@. You must not use this option when generating
-programs that will run on real hardware; you must provide your own
-runtime library for whatever I/O functions are needed.
+@item -mscc
+@opindex mscc
-@item -memregs=@var{number}
-@opindex memregs=
-Specifies the number of memory-based pseudo-registers GCC uses
-during code generation. These pseudo-registers are used like real
-registers, so there is a tradeoff between GCC's ability to fit the
-code into available registers, and the performance penalty of using
-memory instead of registers. Note that all modules in a program must
-be compiled with the same value for this option. Because of that, you
-must not use this option with GCC's default runtime libraries.
+Enable the use of conditional set instructions (default).
-@end table
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@node M32R/D Options
-@subsection M32R/D Options
-@cindex M32R/D options
+@item -mno-scc
+@opindex mno-scc
-These @option{-m} options are defined for Renesas M32R/D architectures:
+Disable the use of conditional set instructions.
-@table @gcctabopt
-@item -m32r2
-@opindex m32r2
-Generate code for the M32R/2@.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -m32rx
-@opindex m32rx
-Generate code for the M32R/X@.
+@item -mcond-exec
+@opindex mcond-exec
-@item -m32r
-@opindex m32r
-Generate code for the M32R@. This is the default.
+Enable the use of conditional execution (default).
-@item -mmodel=small
-@opindex mmodel=small
-Assume all objects live in the lower 16MB of memory (so that their addresses
-can be loaded with the @code{ld24} instruction), and assume all subroutines
-are reachable with the @code{bl} instruction.
-This is the default.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-The addressability of a particular object can be set with the
-@code{model} attribute.
+@item -mno-cond-exec
+@opindex mno-cond-exec
-@item -mmodel=medium
-@opindex mmodel=medium
-Assume objects may be anywhere in the 32-bit address space (the compiler
-generates @code{seth/add3} instructions to load their addresses), and
-assume all subroutines are reachable with the @code{bl} instruction.
+Disable the use of conditional execution.
-@item -mmodel=large
-@opindex mmodel=large
-Assume objects may be anywhere in the 32-bit address space (the compiler
-generates @code{seth/add3} instructions to load their addresses), and
-assume subroutines may not be reachable with the @code{bl} instruction
-(the compiler generates the much slower @code{seth/add3/jl}
-instruction sequence).
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -msdata=none
-@opindex msdata=none
-Disable use of the small data area. Variables are put into
-one of @code{.data}, @code{.bss}, or @code{.rodata} (unless the
-@code{section} attribute has been specified).
-This is the default.
+@item -mvliw-branch
+@opindex mvliw-branch
-The small data area consists of sections @code{.sdata} and @code{.sbss}.
-Objects may be explicitly put in the small data area with the
-@code{section} attribute using one of these sections.
+Run a pass to pack branches into VLIW instructions (default).
-@item -msdata=sdata
-@opindex msdata=sdata
-Put small global and static data in the small data area, but do not
-generate special code to reference them.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -msdata=use
-@opindex msdata=use
-Put small global and static data in the small data area, and generate
-special instructions to reference them.
+@item -mno-vliw-branch
+@opindex mno-vliw-branch
-@item -G @var{num}
-@opindex G
-@cindex smaller data references
-Put global and static objects less than or equal to @var{num} bytes
-into the small data or BSS sections instead of the normal data or BSS
-sections. The default value of @var{num} is 8.
-The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
-for this option to have any effect.
+Do not run a pass to pack branches into VLIW instructions.
-All modules should be compiled with the same @option{-G @var{num}} value.
-Compiling with different values of @var{num} may or may not work; if it
-doesn't the linker gives an error message---incorrect code is not
-generated.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -mdebug
-@opindex mdebug
-Makes the M32R-specific code in the compiler display some statistics
-that might help in debugging programs.
+@item -mmulti-cond-exec
+@opindex mmulti-cond-exec
-@item -malign-loops
-@opindex malign-loops
-Align all loops to a 32-byte boundary.
+Enable optimization of @code{&&} and @code{||} in conditional execution
+(default).
-@item -mno-align-loops
-@opindex mno-align-loops
-Do not enforce a 32-byte alignment for loops. This is the default.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -missue-rate=@var{number}
-@opindex missue-rate=@var{number}
-Issue @var{number} instructions per cycle. @var{number} can only be 1
-or 2.
+@item -mno-multi-cond-exec
+@opindex mno-multi-cond-exec
-@item -mbranch-cost=@var{number}
-@opindex mbranch-cost=@var{number}
-@var{number} can only be 1 or 2. If it is 1 then branches are
-preferred over conditional code, if it is 2, then the opposite applies.
+Disable optimization of @code{&&} and @code{||} in conditional execution.
-@item -mflush-trap=@var{number}
-@opindex mflush-trap=@var{number}
-Specifies the trap number to use to flush the cache. The default is
-12. Valid numbers are between 0 and 15 inclusive.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -mno-flush-trap
-@opindex mno-flush-trap
-Specifies that the cache cannot be flushed by using a trap.
+@item -mnested-cond-exec
+@opindex mnested-cond-exec
-@item -mflush-func=@var{name}
-@opindex mflush-func=@var{name}
-Specifies the name of the operating system function to call to flush
-the cache. The default is @samp{_flush_cache}, but a function call
-is only used if a trap is not available.
+Enable nested conditional execution optimizations (default).
-@item -mno-flush-func
-@opindex mno-flush-func
-Indicates that there is no OS function for flushing the cache.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@end table
+@item -mno-nested-cond-exec
+@opindex mno-nested-cond-exec
-@node M680x0 Options
-@subsection M680x0 Options
-@cindex M680x0 options
+Disable nested conditional execution optimizations.
-These are the @samp{-m} options defined for M680x0 and ColdFire processors.
-The default settings depend on which architecture was selected when
-the compiler was configured; the defaults for the most common choices
-are given below.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@table @gcctabopt
-@item -march=@var{arch}
-@opindex march
-Generate code for a specific M680x0 or ColdFire instruction set
-architecture. Permissible values of @var{arch} for M680x0
-architectures are: @samp{68000}, @samp{68010}, @samp{68020},
-@samp{68030}, @samp{68040}, @samp{68060} and @samp{cpu32}. ColdFire
-architectures are selected according to Freescale's ISA classification
-and the permissible values are: @samp{isaa}, @samp{isaaplus},
-@samp{isab} and @samp{isac}.
+@item -moptimize-membar
+@opindex moptimize-membar
-GCC defines a macro @code{__mcf@var{arch}__} whenever it is generating
-code for a ColdFire target. The @var{arch} in this macro is one of the
-@option{-march} arguments given above.
+This switch removes redundant @code{membar} instructions from the
+compiler-generated code. It is enabled by default.
-When used together, @option{-march} and @option{-mtune} select code
-that runs on a family of similar processors but that is optimized
-for a particular microarchitecture.
+@item -mno-optimize-membar
+@opindex mno-optimize-membar
+
+This switch disables the automatic removal of redundant @code{membar}
+instructions from the generated code.
+
+@item -mtomcat-stats
+@opindex mtomcat-stats
+
+Cause gas to print out tomcat statistics.
@item -mcpu=@var{cpu}
@opindex mcpu
-Generate code for a specific M680x0 or ColdFire processor.
-The M680x0 @var{cpu}s are: @samp{68000}, @samp{68010}, @samp{68020},
-@samp{68030}, @samp{68040}, @samp{68060}, @samp{68302}, @samp{68332}
-and @samp{cpu32}. The ColdFire @var{cpu}s are given by the table
-below, which also classifies the CPUs into families:
-@multitable @columnfractions 0.20 0.80
-@item @strong{Family} @tab @strong{@samp{-mcpu} arguments}
-@item @samp{51} @tab @samp{51} @samp{51ac} @samp{51ag} @samp{51cn} @samp{51em} @samp{51je} @samp{51jf} @samp{51jg} @samp{51jm} @samp{51mm} @samp{51qe} @samp{51qm}
-@item @samp{5206} @tab @samp{5202} @samp{5204} @samp{5206}
-@item @samp{5206e} @tab @samp{5206e}
-@item @samp{5208} @tab @samp{5207} @samp{5208}
-@item @samp{5211a} @tab @samp{5210a} @samp{5211a}
-@item @samp{5213} @tab @samp{5211} @samp{5212} @samp{5213}
-@item @samp{5216} @tab @samp{5214} @samp{5216}
-@item @samp{52235} @tab @samp{52230} @samp{52231} @samp{52232} @samp{52233} @samp{52234} @samp{52235}
-@item @samp{5225} @tab @samp{5224} @samp{5225}
-@item @samp{52259} @tab @samp{52252} @samp{52254} @samp{52255} @samp{52256} @samp{52258} @samp{52259}
-@item @samp{5235} @tab @samp{5232} @samp{5233} @samp{5234} @samp{5235} @samp{523x}
-@item @samp{5249} @tab @samp{5249}
-@item @samp{5250} @tab @samp{5250}
-@item @samp{5271} @tab @samp{5270} @samp{5271}
-@item @samp{5272} @tab @samp{5272}
-@item @samp{5275} @tab @samp{5274} @samp{5275}
-@item @samp{5282} @tab @samp{5280} @samp{5281} @samp{5282} @samp{528x}
-@item @samp{53017} @tab @samp{53011} @samp{53012} @samp{53013} @samp{53014} @samp{53015} @samp{53016} @samp{53017}
-@item @samp{5307} @tab @samp{5307}
-@item @samp{5329} @tab @samp{5327} @samp{5328} @samp{5329} @samp{532x}
-@item @samp{5373} @tab @samp{5372} @samp{5373} @samp{537x}
-@item @samp{5407} @tab @samp{5407}
-@item @samp{5475} @tab @samp{5470} @samp{5471} @samp{5472} @samp{5473} @samp{5474} @samp{5475} @samp{547x} @samp{5480} @samp{5481} @samp{5482} @samp{5483} @samp{5484} @samp{5485}
-@end multitable
+Select the processor type for which to generate code. Possible values are
+@samp{frv}, @samp{fr550}, @samp{tomcat}, @samp{fr500}, @samp{fr450},
+@samp{fr405}, @samp{fr400}, @samp{fr300} and @samp{simple}.
-@option{-mcpu=@var{cpu}} overrides @option{-march=@var{arch}} if
-@var{arch} is compatible with @var{cpu}. Other combinations of
-@option{-mcpu} and @option{-march} are rejected.
+@end table
-GCC defines the macro @code{__mcf_cpu_@var{cpu}} when ColdFire target
-@var{cpu} is selected. It also defines @code{__mcf_family_@var{family}},
-where the value of @var{family} is given by the table above.
+@node GNU/Linux Options
+@subsection GNU/Linux Options
-@item -mtune=@var{tune}
-@opindex mtune
-Tune the code for a particular microarchitecture within the
-constraints set by @option{-march} and @option{-mcpu}.
-The M680x0 microarchitectures are: @samp{68000}, @samp{68010},
-@samp{68020}, @samp{68030}, @samp{68040}, @samp{68060}
-and @samp{cpu32}. The ColdFire microarchitectures
-are: @samp{cfv1}, @samp{cfv2}, @samp{cfv3}, @samp{cfv4} and @samp{cfv4e}.
+These @samp{-m} options are defined for GNU/Linux targets:
-You can also use @option{-mtune=68020-40} for code that needs
-to run relatively well on 68020, 68030 and 68040 targets.
-@option{-mtune=68020-60} is similar but includes 68060 targets
-as well. These two options select the same tuning decisions as
-@option{-m68020-40} and @option{-m68020-60} respectively.
+@table @gcctabopt
+@item -mglibc
+@opindex mglibc
+Use the GNU C library. This is the default except
+on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and
+@samp{*-*-linux-*android*} targets.
-GCC defines the macros @code{__mc@var{arch}} and @code{__mc@var{arch}__}
-when tuning for 680x0 architecture @var{arch}. It also defines
-@code{mc@var{arch}} unless either @option{-ansi} or a non-GNU @option{-std}
-option is used. If GCC is tuning for a range of architectures,
-as selected by @option{-mtune=68020-40} or @option{-mtune=68020-60},
-it defines the macros for every architecture in the range.
+@item -muclibc
+@opindex muclibc
+Use uClibc C library. This is the default on
+@samp{*-*-linux-*uclibc*} targets.
-GCC also defines the macro @code{__m@var{uarch}__} when tuning for
-ColdFire microarchitecture @var{uarch}, where @var{uarch} is one
-of the arguments given above.
+@item -mmusl
+@opindex mmusl
+Use the musl C library. This is the default on
+@samp{*-*-linux-*musl*} targets.
-@item -m68000
-@itemx -mc68000
-@opindex m68000
-@opindex mc68000
-Generate output for a 68000. This is the default
-when the compiler is configured for 68000-based systems.
-It is equivalent to @option{-march=68000}.
+@item -mbionic
+@opindex mbionic
+Use Bionic C library. This is the default on
+@samp{*-*-linux-*android*} targets.
-Use this option for microcontrollers with a 68000 or EC000 core,
-including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
+@item -mandroid
+@opindex mandroid
+Compile code compatible with Android platform. This is the default on
+@samp{*-*-linux-*android*} targets.
-@item -m68010
-@opindex m68010
-Generate output for a 68010. This is the default
-when the compiler is configured for 68010-based systems.
-It is equivalent to @option{-march=68010}.
+When compiling, this option enables @option{-mbionic}, @option{-fPIC},
+@option{-fno-exceptions} and @option{-fno-rtti} by default. When linking,
+this option makes the GCC driver pass Android-specific options to the linker.
+Finally, this option causes the preprocessor macro @code{__ANDROID__}
+to be defined.
-@item -m68020
-@itemx -mc68020
-@opindex m68020
-@opindex mc68020
-Generate output for a 68020. This is the default
-when the compiler is configured for 68020-based systems.
-It is equivalent to @option{-march=68020}.
+@item -tno-android-cc
+@opindex tno-android-cc
+Disable compilation effects of @option{-mandroid}, i.e., do not enable
+@option{-mbionic}, @option{-fPIC}, @option{-fno-exceptions} and
+@option{-fno-rtti} by default.
-@item -m68030
-@opindex m68030
-Generate output for a 68030. This is the default when the compiler is
-configured for 68030-based systems. It is equivalent to
-@option{-march=68030}.
+@item -tno-android-ld
+@opindex tno-android-ld
+Disable linking effects of @option{-mandroid}, i.e., pass standard Linux
+linking options to the linker.
-@item -m68040
-@opindex m68040
-Generate output for a 68040. This is the default when the compiler is
-configured for 68040-based systems. It is equivalent to
-@option{-march=68040}.
+@end table
-This option inhibits the use of 68881/68882 instructions that have to be
-emulated by software on the 68040. Use this option if your 68040 does not
-have code to emulate those instructions.
+@node H8/300 Options
+@subsection H8/300 Options
-@item -m68060
-@opindex m68060
-Generate output for a 68060. This is the default when the compiler is
-configured for 68060-based systems. It is equivalent to
-@option{-march=68060}.
+These @samp{-m} options are defined for the H8/300 implementations:
-This option inhibits the use of 68020 and 68881/68882 instructions that
-have to be emulated by software on the 68060. Use this option if your 68060
-does not have code to emulate those instructions.
+@table @gcctabopt
+@item -mrelax
+@opindex mrelax
+Shorten some address references at link time, when possible; uses the
+linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
+ld, Using ld}, for a fuller description.
-@item -mcpu32
-@opindex mcpu32
-Generate output for a CPU32. This is the default
-when the compiler is configured for CPU32-based systems.
-It is equivalent to @option{-march=cpu32}.
+@item -mh
+@opindex mh
+Generate code for the H8/300H@.
-Use this option for microcontrollers with a
-CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
-68336, 68340, 68341, 68349 and 68360.
+@item -ms
+@opindex ms
+Generate code for the H8S@.
-@item -m5200
-@opindex m5200
-Generate output for a 520X ColdFire CPU@. This is the default
-when the compiler is configured for 520X-based systems.
-It is equivalent to @option{-mcpu=5206}, and is now deprecated
-in favor of that option.
+@item -mn
+@opindex mn
+Generate code for the H8S and H8/300H in the normal mode. This switch
+must be used either with @option{-mh} or @option{-ms}.
-Use this option for microcontroller with a 5200 core, including
-the MCF5202, MCF5203, MCF5204 and MCF5206.
+@item -ms2600
+@opindex ms2600
+Generate code for the H8S/2600. This switch must be used with @option{-ms}.
-@item -m5206e
-@opindex m5206e
-Generate output for a 5206e ColdFire CPU@. The option is now
-deprecated in favor of the equivalent @option{-mcpu=5206e}.
+@item -mexr
+@opindex mexr
+Extended registers are stored on stack before execution of function
+with monitor attribute. Default option is @option{-mexr}.
+This option is valid only for H8S targets.
-@item -m528x
-@opindex m528x
-Generate output for a member of the ColdFire 528X family.
-The option is now deprecated in favor of the equivalent
-@option{-mcpu=528x}.
+@item -mno-exr
+@opindex mno-exr
+Extended registers are not stored on stack before execution of function
+with monitor attribute. Default option is @option{-mno-exr}.
+This option is valid only for H8S targets.
-@item -m5307
-@opindex m5307
-Generate output for a ColdFire 5307 CPU@. The option is now deprecated
-in favor of the equivalent @option{-mcpu=5307}.
+@item -mint32
+@opindex mint32
+Make @code{int} data 32 bits by default.
-@item -m5407
-@opindex m5407
-Generate output for a ColdFire 5407 CPU@. The option is now deprecated
-in favor of the equivalent @option{-mcpu=5407}.
+@item -malign-300
+@opindex malign-300
+On the H8/300H and H8S, use the same alignment rules as for the H8/300.
+The default for the H8/300H and H8S is to align longs and floats on
+4-byte boundaries.
+@option{-malign-300} causes them to be aligned on 2-byte boundaries.
+This option has no effect on the H8/300.
+@end table
-@item -mcfv4e
-@opindex mcfv4e
-Generate output for a ColdFire V4e family CPU (e.g.@: 547x/548x).
-This includes use of hardware floating-point instructions.
-The option is equivalent to @option{-mcpu=547x}, and is now
-deprecated in favor of that option.
+@node HPPA Options
+@subsection HPPA Options
+@cindex HPPA Options
-@item -m68020-40
-@opindex m68020-40
-Generate output for a 68040, without using any of the new instructions.
-This results in code that can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68040.
+These @samp{-m} options are defined for the HPPA family of computers:
-The option is equivalent to @option{-march=68020} @option{-mtune=68020-40}.
+@table @gcctabopt
+@item -march=@var{architecture-type}
+@opindex march
+Generate code for the specified architecture. The choices for
+@var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
+1.1, and @samp{2.0} for PA 2.0 processors. Refer to
+@file{/usr/lib/sched.models} on an HP-UX system to determine the proper
+architecture option for your machine. Code compiled for lower numbered
+architectures runs on higher numbered architectures, but not the
+other way around.
-@item -m68020-60
-@opindex m68020-60
-Generate output for a 68060, without using any of the new instructions.
-This results in code that can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68060.
+@item -mpa-risc-1-0
+@itemx -mpa-risc-1-1
+@itemx -mpa-risc-2-0
+@opindex mpa-risc-1-0
+@opindex mpa-risc-1-1
+@opindex mpa-risc-2-0
+Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
-The option is equivalent to @option{-march=68020} @option{-mtune=68020-60}.
+@item -mjump-in-delay
+@opindex mjump-in-delay
+This option is ignored and provided for compatibility purposes only.
-@item -mhard-float
-@itemx -m68881
-@opindex mhard-float
-@opindex m68881
-Generate floating-point instructions. This is the default for 68020
-and above, and for ColdFire devices that have an FPU@. It defines the
-macro @code{__HAVE_68881__} on M680x0 targets and @code{__mcffpu__}
-on ColdFire targets.
+@item -mdisable-fpregs
+@opindex mdisable-fpregs
+Prevent floating-point registers from being used in any manner. This is
+necessary for compiling kernels that perform lazy context switching of
+floating-point registers. If you use this option and attempt to perform
+floating-point operations, the compiler aborts.
-@item -msoft-float
-@opindex msoft-float
-Do not generate floating-point instructions; use library calls instead.
-This is the default for 68000, 68010, and 68832 targets. It is also
-the default for ColdFire devices that have no FPU.
+@item -mdisable-indexing
+@opindex mdisable-indexing
+Prevent the compiler from using indexing address modes. This avoids some
+rather obscure problems when compiling MIG generated code under MACH@.
-@item -mdiv
-@itemx -mno-div
-@opindex mdiv
-@opindex mno-div
-Generate (do not generate) ColdFire hardware divide and remainder
-instructions. If @option{-march} is used without @option{-mcpu},
-the default is ``on'' for ColdFire architectures and ``off'' for M680x0
-architectures. Otherwise, the default is taken from the target CPU
-(either the default CPU, or the one specified by @option{-mcpu}). For
-example, the default is ``off'' for @option{-mcpu=5206} and ``on'' for
-@option{-mcpu=5206e}.
+@item -mno-space-regs
+@opindex mno-space-regs
+Generate code that assumes the target has no space registers. This allows
+GCC to generate faster indirect calls and use unscaled index address modes.
-GCC defines the macro @code{__mcfhwdiv__} when this option is enabled.
+Such code is suitable for level 0 PA systems and kernels.
-@item -mshort
-@opindex mshort
-Consider type @code{int} to be 16 bits wide, like @code{short int}.
-Additionally, parameters passed on the stack are also aligned to a
-16-bit boundary even on targets whose API mandates promotion to 32-bit.
+@item -mfast-indirect-calls
+@opindex mfast-indirect-calls
+Generate code that assumes calls never cross space boundaries. This
+allows GCC to emit code that performs faster indirect calls.
-@item -mno-short
-@opindex mno-short
-Do not consider type @code{int} to be 16 bits wide. This is the default.
+This option does not work in the presence of shared libraries or nested
+functions.
-@item -mnobitfield
-@itemx -mno-bitfield
-@opindex mnobitfield
-@opindex mno-bitfield
-Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
-and @option{-m5200} options imply @w{@option{-mnobitfield}}.
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator cannot use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
-@item -mbitfield
-@opindex mbitfield
-Do use the bit-field instructions. The @option{-m68020} option implies
-@option{-mbitfield}. This is the default if you use a configuration
-designed for a 68020.
+@item -mlong-load-store
+@opindex mlong-load-store
+Generate 3-instruction load and store sequences as sometimes required by
+the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
+the HP compilers.
-@item -mrtd
-@opindex mrtd
-Use a different function-calling convention, in which functions
-that take a fixed number of arguments return with the @code{rtd}
-instruction, which pops their arguments while returning. This
-saves one instruction in the caller since there is no need to pop
-the arguments there.
+@item -mportable-runtime
+@opindex mportable-runtime
+Use the portable calling conventions proposed by HP for ELF systems.
-This calling convention is incompatible with the one normally
-used on Unix, so you cannot use it if you need to call libraries
-compiled with the Unix compiler.
+@item -mgas
+@opindex mgas
+Enable the use of assembler directives only GAS understands.
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including @code{printf});
-otherwise incorrect code is generated for calls to those
-functions.
+@item -mschedule=@var{cpu-type}
+@opindex mschedule
+Schedule code according to the constraints for the machine type
+@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
+@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
+to @file{/usr/lib/sched.models} on an HP-UX system to determine the
+proper scheduling option for your machine. The default scheduling is
+@samp{8000}.
-In addition, seriously incorrect code results if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
+@item -mlinker-opt
+@opindex mlinker-opt
+Enable the optimization pass in the HP-UX linker. Note this makes symbolic
+debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
+linkers in which they give bogus error messages when linking some programs.
-The @code{rtd} instruction is supported by the 68010, 68020, 68030,
-68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
+@item -msoft-float
+@opindex msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries are not available for all HPPA
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross-compilation.
-@item -mno-rtd
-@opindex mno-rtd
-Do not use the calling conventions selected by @option{-mrtd}.
-This is the default.
-
-@item -malign-int
-@itemx -mno-align-int
-@opindex malign-int
-@opindex mno-align-int
-Control whether GCC aligns @code{int}, @code{long}, @code{long long},
-@code{float}, @code{double}, and @code{long double} variables on a 32-bit
-boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
-Aligning variables on 32-bit boundaries produces code that runs somewhat
-faster on processors with 32-bit busses at the expense of more memory.
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-@strong{Warning:} if you use the @option{-malign-int} switch, GCC
-aligns structures containing the above types differently than
-most published application binary interface specifications for the m68k.
+@item -msio
+@opindex msio
+Generate the predefine, @code{_SIO}, for server IO@. The default is
+@option{-mwsio}. This generates the predefines, @code{__hp9000s700},
+@code{__hp9000s700__} and @code{_WSIO}, for workstation IO@. These
+options are available under HP-UX and HI-UX@.
-@item -mpcrel
-@opindex mpcrel
-Use the pc-relative addressing mode of the 68000 directly, instead of
-using a global offset table. At present, this option implies @option{-fpic},
-allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
-not presently supported with @option{-mpcrel}, though this could be supported for
-68020 and higher processors.
+@item -mgnu-ld
+@opindex mgnu-ld
+Use options specific to GNU @command{ld}.
+This passes @option{-shared} to @command{ld} when
+building a shared library. It is the default when GCC is configured,
+explicitly or implicitly, with the GNU linker. This option does not
+affect which @command{ld} is called; it only changes what parameters
+are passed to that @command{ld}.
+The @command{ld} that is called is determined by the
+@option{--with-ld} configure option, GCC's program search path, and
+finally by the user's @env{PATH}. The linker used by GCC can be printed
+using @samp{which `gcc -print-prog-name=ld`}. This option is only available
+on the 64-bit HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
-@item -mno-strict-align
-@itemx -mstrict-align
-@opindex mno-strict-align
-@opindex mstrict-align
-Do not (do) assume that unaligned memory references are handled by
-the system.
+@item -mhp-ld
+@opindex mhp-ld
+Use options specific to HP @command{ld}.
+This passes @option{-b} to @command{ld} when building
+a shared library and passes @option{+Accept TypeMismatch} to @command{ld} on all
+links. It is the default when GCC is configured, explicitly or
+implicitly, with the HP linker. This option does not affect
+which @command{ld} is called; it only changes what parameters are passed to that
+@command{ld}.
+The @command{ld} that is called is determined by the @option{--with-ld}
+configure option, GCC's program search path, and finally by the user's
+@env{PATH}. The linker used by GCC can be printed using @samp{which
+`gcc -print-prog-name=ld`}. This option is only available on the 64-bit
+HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.
-@item -msep-data
-Generate code that allows the data segment to be located in a different
-area of memory from the text segment. This allows for execute-in-place in
-an environment without virtual memory management. This option implies
-@option{-fPIC}.
+@item -mlong-calls
+@opindex mno-long-calls
+Generate code that uses long call sequences. This ensures that a call
+is always able to reach linker generated stubs. The default is to generate
+long calls only when the distance from the call site to the beginning
+of the function or translation unit, as the case may be, exceeds a
+predefined limit set by the branch type being used. The limits for
+normal calls are 7,600,000 and 240,000 bytes, respectively for the
+PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
+240,000 bytes.
-@item -mno-sep-data
-Generate code that assumes that the data segment follows the text segment.
-This is the default.
+Distances are measured from the beginning of functions when using the
+@option{-ffunction-sections} option, or when using the @option{-mgas}
+and @option{-mno-portable-runtime} options together under HP-UX with
+the SOM linker.
-@item -mid-shared-library
-Generate code that supports shared libraries via the library ID method.
-This allows for execute-in-place and shared libraries in an environment
-without virtual memory management. This option implies @option{-fPIC}.
+It is normally not desirable to use this option as it degrades
+performance. However, it may be useful in large applications,
+particularly when partial linking is used to build the application.
-@item -mno-id-shared-library
-Generate code that doesn't assume ID-based shared libraries are being used.
-This is the default.
+The types of long calls used depends on the capabilities of the
+assembler and linker, and the type of code being generated. The
+impact on systems that support long absolute calls, and long pic
+symbol-difference or pc-relative calls should be relatively small.
+However, an indirect call is used on 32-bit ELF systems in pic code
+and it is quite long.
-@item -mshared-library-id=n
-Specifies the identification number of the ID-based shared library being
-compiled. Specifying a value of 0 generates more compact code; specifying
-other values forces the allocation of that number to the current
-library, but is no more space- or time-efficient than omitting this option.
+@item -munix=@var{unix-std}
+@opindex march
+Generate compiler predefines and select a startfile for the specified
+UNIX standard. The choices for @var{unix-std} are @samp{93}, @samp{95}
+and @samp{98}. @samp{93} is supported on all HP-UX versions. @samp{95}
+is available on HP-UX 10.10 and later. @samp{98} is available on HP-UX
+11.11 and later. The default values are @samp{93} for HP-UX 10.00,
+@samp{95} for HP-UX 10.10 though to 11.00, and @samp{98} for HP-UX 11.11
+and later.
-@item -mxgot
-@itemx -mno-xgot
-@opindex mxgot
-@opindex mno-xgot
-When generating position-independent code for ColdFire, generate code
-that works if the GOT has more than 8192 entries. This code is
-larger and slower than code generated without this option. On M680x0
-processors, this option is not needed; @option{-fPIC} suffices.
+@option{-munix=93} provides the same predefines as GCC 3.3 and 3.4.
+@option{-munix=95} provides additional predefines for @code{XOPEN_UNIX}
+and @code{_XOPEN_SOURCE_EXTENDED}, and the startfile @file{unix95.o}.
+@option{-munix=98} provides additional predefines for @code{_XOPEN_UNIX},
+@code{_XOPEN_SOURCE_EXTENDED}, @code{_INCLUDE__STDC_A1_SOURCE} and
+@code{_INCLUDE_XOPEN_SOURCE_500}, and the startfile @file{unix98.o}.
-GCC normally uses a single instruction to load values from the GOT@.
-While this is relatively efficient, it only works if the GOT
-is smaller than about 64k. Anything larger causes the linker
-to report an error such as:
+It is @emph{important} to note that this option changes the interfaces
+for various library routines. It also affects the operational behavior
+of the C library. Thus, @emph{extreme} care is needed in using this
+option.
-@cindex relocation truncated to fit (ColdFire)
-@smallexample
-relocation truncated to fit: R_68K_GOT16O foobar
-@end smallexample
+Library code that is intended to operate with more than one UNIX
+standard must test, set and restore the variable @code{__xpg4_extended_mask}
+as appropriate. Most GNU software doesn't provide this capability.
-If this happens, you should recompile your code with @option{-mxgot}.
-It should then work with very large GOTs. However, code generated with
-@option{-mxgot} is less efficient, since it takes 4 instructions to fetch
-the value of a global symbol.
+@item -nolibdld
+@opindex nolibdld
+Suppress the generation of link options to search libdld.sl when the
+@option{-static} option is specified on HP-UX 10 and later.
-Note that some linkers, including newer versions of the GNU linker,
-can create multiple GOTs and sort GOT entries. If you have such a linker,
-you should only need to use @option{-mxgot} when compiling a single
-object file that accesses more than 8192 GOT entries. Very few do.
+@item -static
+@opindex static
+The HP-UX implementation of setlocale in libc has a dependency on
+libdld.sl. There isn't an archive version of libdld.sl. Thus,
+when the @option{-static} option is specified, special link options
+are needed to resolve this dependency.
-These options have no effect unless GCC is generating
-position-independent code.
+On HP-UX 10 and later, the GCC driver adds the necessary options to
+link with libdld.sl when the @option{-static} option is specified.
+This causes the resulting binary to be dynamic. On the 64-bit port,
+the linkers generate dynamic binaries by default in any case. The
+@option{-nolibdld} option can be used to prevent the GCC driver from
+adding these link options.
+@item -threads
+@opindex threads
+Add support for multithreading with the @dfn{dce thread} library
+under HP-UX@. This option sets flags for both the preprocessor and
+linker.
@end table
-@node MCore Options
-@subsection MCore Options
-@cindex MCore options
+@node IA-64 Options
+@subsection IA-64 Options
+@cindex IA-64 Options
-These are the @samp{-m} options defined for the Motorola M*Core
-processors.
+These are the @samp{-m} options defined for the Intel IA-64 architecture.
@table @gcctabopt
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a big-endian target. This is the default for HP-UX@.
-@item -mhardlit
-@itemx -mno-hardlit
-@opindex mhardlit
-@opindex mno-hardlit
-Inline constants into the code stream if it can be done in two
-instructions or less.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a little-endian target. This is the default for AIX5
+and GNU/Linux.
-@item -mdiv
-@itemx -mno-div
-@opindex mdiv
-@opindex mno-div
-Use the divide instruction. (Enabled by default).
+@item -mgnu-as
+@itemx -mno-gnu-as
+@opindex mgnu-as
+@opindex mno-gnu-as
+Generate (or don't) code for the GNU assembler. This is the default.
+@c Also, this is the default if the configure option @option{--with-gnu-as}
+@c is used.
-@item -mrelax-immediate
-@itemx -mno-relax-immediate
-@opindex mrelax-immediate
-@opindex mno-relax-immediate
-Allow arbitrary-sized immediates in bit operations.
+@item -mgnu-ld
+@itemx -mno-gnu-ld
+@opindex mgnu-ld
+@opindex mno-gnu-ld
+Generate (or don't) code for the GNU linker. This is the default.
+@c Also, this is the default if the configure option @option{--with-gnu-ld}
+@c is used.
-@item -mwide-bitfields
-@itemx -mno-wide-bitfields
-@opindex mwide-bitfields
-@opindex mno-wide-bitfields
-Always treat bit-fields as @code{int}-sized.
+@item -mno-pic
+@opindex mno-pic
+Generate code that does not use a global pointer register. The result
+is not position independent code, and violates the IA-64 ABI@.
-@item -m4byte-functions
-@itemx -mno-4byte-functions
-@opindex m4byte-functions
-@opindex mno-4byte-functions
-Force all functions to be aligned to a 4-byte boundary.
+@item -mvolatile-asm-stop
+@itemx -mno-volatile-asm-stop
+@opindex mvolatile-asm-stop
+@opindex mno-volatile-asm-stop
+Generate (or don't) a stop bit immediately before and after volatile asm
+statements.
-@item -mcallgraph-data
-@itemx -mno-callgraph-data
-@opindex mcallgraph-data
-@opindex mno-callgraph-data
-Emit callgraph information.
+@item -mregister-names
+@itemx -mno-register-names
+@opindex mregister-names
+@opindex mno-register-names
+Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
+the stacked registers. This may make assembler output more readable.
-@item -mslow-bytes
-@itemx -mno-slow-bytes
-@opindex mslow-bytes
-@opindex mno-slow-bytes
-Prefer word access when reading byte quantities.
-
-@item -mlittle-endian
-@itemx -mbig-endian
-@opindex mlittle-endian
-@opindex mbig-endian
-Generate code for a little-endian target.
-
-@item -m210
-@itemx -m340
-@opindex m210
-@opindex m340
-Generate code for the 210 processor.
+@item -mno-sdata
+@itemx -msdata
+@opindex mno-sdata
+@opindex msdata
+Disable (or enable) optimizations that use the small data section. This may
+be useful for working around optimizer bugs.
-@item -mno-lsim
-@opindex mno-lsim
-Assume that runtime support has been provided and so omit the
-simulator library (@file{libsim.a)} from the linker command line.
+@item -mconstant-gp
+@opindex mconstant-gp
+Generate code that uses a single constant global pointer value. This is
+useful when compiling kernel code.
-@item -mstack-increment=@var{size}
-@opindex mstack-increment
-Set the maximum amount for a single stack increment operation. Large
-values can increase the speed of programs that contain functions
-that need a large amount of stack space, but they can also trigger a
-segmentation fault if the stack is extended too much. The default
-value is 0x1000.
+@item -mauto-pic
+@opindex mauto-pic
+Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
+This is useful when compiling firmware code.
-@end table
+@item -minline-float-divide-min-latency
+@opindex minline-float-divide-min-latency
+Generate code for inline divides of floating-point values
+using the minimum latency algorithm.
-@node MeP Options
-@subsection MeP Options
-@cindex MeP options
+@item -minline-float-divide-max-throughput
+@opindex minline-float-divide-max-throughput
+Generate code for inline divides of floating-point values
+using the maximum throughput algorithm.
-@table @gcctabopt
+@item -mno-inline-float-divide
+@opindex mno-inline-float-divide
+Do not generate inline code for divides of floating-point values.
-@item -mabsdiff
-@opindex mabsdiff
-Enables the @code{abs} instruction, which is the absolute difference
-between two registers.
+@item -minline-int-divide-min-latency
+@opindex minline-int-divide-min-latency
+Generate code for inline divides of integer values
+using the minimum latency algorithm.
-@item -mall-opts
-@opindex mall-opts
-Enables all the optional instructions---average, multiply, divide, bit
-operations, leading zero, absolute difference, min/max, clip, and
-saturation.
+@item -minline-int-divide-max-throughput
+@opindex minline-int-divide-max-throughput
+Generate code for inline divides of integer values
+using the maximum throughput algorithm.
+@item -mno-inline-int-divide
+@opindex mno-inline-int-divide
+Do not generate inline code for divides of integer values.
-@item -maverage
-@opindex maverage
-Enables the @code{ave} instruction, which computes the average of two
-registers.
+@item -minline-sqrt-min-latency
+@opindex minline-sqrt-min-latency
+Generate code for inline square roots
+using the minimum latency algorithm.
-@item -mbased=@var{n}
-@opindex mbased=
-Variables of size @var{n} bytes or smaller are placed in the
-@code{.based} section by default. Based variables use the @code{$tp}
-register as a base register, and there is a 128-byte limit to the
-@code{.based} section.
+@item -minline-sqrt-max-throughput
+@opindex minline-sqrt-max-throughput
+Generate code for inline square roots
+using the maximum throughput algorithm.
-@item -mbitops
-@opindex mbitops
-Enables the bit operation instructions---bit test (@code{btstm}), set
-(@code{bsetm}), clear (@code{bclrm}), invert (@code{bnotm}), and
-test-and-set (@code{tas}).
+@item -mno-inline-sqrt
+@opindex mno-inline-sqrt
+Do not generate inline code for @code{sqrt}.
-@item -mc=@var{name}
-@opindex mc=
-Selects which section constant data is placed in. @var{name} may
-be @samp{tiny}, @samp{near}, or @samp{far}.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Do (don't) generate code that uses the fused multiply/add or multiply/subtract
+instructions. The default is to use these instructions.
-@item -mclip
-@opindex mclip
-Enables the @code{clip} instruction. Note that @option{-mclip} is not
-useful unless you also provide @option{-mminmax}.
+@item -mno-dwarf2-asm
+@itemx -mdwarf2-asm
+@opindex mno-dwarf2-asm
+@opindex mdwarf2-asm
+Don't (or do) generate assembler code for the DWARF 2 line number debugging
+info. This may be useful when not using the GNU assembler.
-@item -mconfig=@var{name}
-@opindex mconfig=
-Selects one of the built-in core configurations. Each MeP chip has
-one or more modules in it; each module has a core CPU and a variety of
-coprocessors, optional instructions, and peripherals. The
-@code{MeP-Integrator} tool, not part of GCC, provides these
-configurations through this option; using this option is the same as
-using all the corresponding command-line options. The default
-configuration is @samp{default}.
+@item -mearly-stop-bits
+@itemx -mno-early-stop-bits
+@opindex mearly-stop-bits
+@opindex mno-early-stop-bits
+Allow stop bits to be placed earlier than immediately preceding the
+instruction that triggered the stop bit. This can improve instruction
+scheduling, but does not always do so.
-@item -mcop
-@opindex mcop
-Enables the coprocessor instructions. By default, this is a 32-bit
-coprocessor. Note that the coprocessor is normally enabled via the
-@option{-mconfig=} option.
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator cannot use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
-@item -mcop32
-@opindex mcop32
-Enables the 32-bit coprocessor's instructions.
+@item -mtls-size=@var{tls-size}
+@opindex mtls-size
+Specify bit size of immediate TLS offsets. Valid values are 14, 22, and
+64.
-@item -mcop64
-@opindex mcop64
-Enables the 64-bit coprocessor's instructions.
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune the instruction scheduling for a particular CPU, Valid values are
+@samp{itanium}, @samp{itanium1}, @samp{merced}, @samp{itanium2},
+and @samp{mckinley}.
-@item -mivc2
-@opindex mivc2
-Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor.
+@item -milp32
+@itemx -mlp64
+@opindex milp32
+@opindex mlp64
+Generate code for a 32-bit or 64-bit environment.
+The 32-bit environment sets int, long and pointer to 32 bits.
+The 64-bit environment sets int to 32 bits and long and pointer
+to 64 bits. These are HP-UX specific flags.
-@item -mdc
-@opindex mdc
-Causes constant variables to be placed in the @code{.near} section.
+@item -mno-sched-br-data-spec
+@itemx -msched-br-data-spec
+@opindex mno-sched-br-data-spec
+@opindex msched-br-data-spec
+(Dis/En)able data speculative scheduling before reload.
+This results in generation of @code{ld.a} instructions and
+the corresponding check instructions (@code{ld.c} / @code{chk.a}).
+The default is 'disable'.
-@item -mdiv
-@opindex mdiv
-Enables the @code{div} and @code{divu} instructions.
+@item -msched-ar-data-spec
+@itemx -mno-sched-ar-data-spec
+@opindex msched-ar-data-spec
+@opindex mno-sched-ar-data-spec
+(En/Dis)able data speculative scheduling after reload.
+This results in generation of @code{ld.a} instructions and
+the corresponding check instructions (@code{ld.c} / @code{chk.a}).
+The default is 'enable'.
-@item -meb
-@opindex meb
-Generate big-endian code.
+@item -mno-sched-control-spec
+@itemx -msched-control-spec
+@opindex mno-sched-control-spec
+@opindex msched-control-spec
+(Dis/En)able control speculative scheduling. This feature is
+available only during region scheduling (i.e.@: before reload).
+This results in generation of the @code{ld.s} instructions and
+the corresponding check instructions @code{chk.s}.
+The default is 'disable'.
-@item -mel
-@opindex mel
-Generate little-endian code.
+@item -msched-br-in-data-spec
+@itemx -mno-sched-br-in-data-spec
+@opindex msched-br-in-data-spec
+@opindex mno-sched-br-in-data-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads before reload.
+This is effective only with @option{-msched-br-data-spec} enabled.
+The default is 'enable'.
-@item -mio-volatile
-@opindex mio-volatile
-Tells the compiler that any variable marked with the @code{io}
-attribute is to be considered volatile.
+@item -msched-ar-in-data-spec
+@itemx -mno-sched-ar-in-data-spec
+@opindex msched-ar-in-data-spec
+@opindex mno-sched-ar-in-data-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the data speculative loads after reload.
+This is effective only with @option{-msched-ar-data-spec} enabled.
+The default is 'enable'.
-@item -ml
-@opindex ml
-Causes variables to be assigned to the @code{.far} section by default.
+@item -msched-in-control-spec
+@itemx -mno-sched-in-control-spec
+@opindex msched-in-control-spec
+@opindex mno-sched-in-control-spec
+(En/Dis)able speculative scheduling of the instructions that
+are dependent on the control speculative loads.
+This is effective only with @option{-msched-control-spec} enabled.
+The default is 'enable'.
-@item -mleadz
-@opindex mleadz
-Enables the @code{leadz} (leading zero) instruction.
+@item -mno-sched-prefer-non-data-spec-insns
+@itemx -msched-prefer-non-data-spec-insns
+@opindex mno-sched-prefer-non-data-spec-insns
+@opindex msched-prefer-non-data-spec-insns
+If enabled, data-speculative instructions are chosen for schedule
+only if there are no other choices at the moment. This makes
+the use of the data speculation much more conservative.
+The default is 'disable'.
-@item -mm
-@opindex mm
-Causes variables to be assigned to the @code{.near} section by default.
+@item -mno-sched-prefer-non-control-spec-insns
+@itemx -msched-prefer-non-control-spec-insns
+@opindex mno-sched-prefer-non-control-spec-insns
+@opindex msched-prefer-non-control-spec-insns
+If enabled, control-speculative instructions are chosen for schedule
+only if there are no other choices at the moment. This makes
+the use of the control speculation much more conservative.
+The default is 'disable'.
-@item -mminmax
-@opindex mminmax
-Enables the @code{min} and @code{max} instructions.
+@item -mno-sched-count-spec-in-critical-path
+@itemx -msched-count-spec-in-critical-path
+@opindex mno-sched-count-spec-in-critical-path
+@opindex msched-count-spec-in-critical-path
+If enabled, speculative dependencies are considered during
+computation of the instructions priorities. This makes the use of the
+speculation a bit more conservative.
+The default is 'disable'.
-@item -mmult
-@opindex mmult
-Enables the multiplication and multiply-accumulate instructions.
+@item -msched-spec-ldc
+@opindex msched-spec-ldc
+Use a simple data speculation check. This option is on by default.
-@item -mno-opts
-@opindex mno-opts
-Disables all the optional instructions enabled by @option{-mall-opts}.
+@item -msched-control-spec-ldc
+@opindex msched-spec-ldc
+Use a simple check for control speculation. This option is on by default.
-@item -mrepeat
-@opindex mrepeat
-Enables the @code{repeat} and @code{erepeat} instructions, used for
-low-overhead looping.
+@item -msched-stop-bits-after-every-cycle
+@opindex msched-stop-bits-after-every-cycle
+Place a stop bit after every cycle when scheduling. This option is on
+by default.
-@item -ms
-@opindex ms
-Causes all variables to default to the @code{.tiny} section. Note
-that there is a 65536-byte limit to this section. Accesses to these
-variables use the @code{%gp} base register.
+@item -msched-fp-mem-deps-zero-cost
+@opindex msched-fp-mem-deps-zero-cost
+Assume that floating-point stores and loads are not likely to cause a conflict
+when placed into the same instruction group. This option is disabled by
+default.
-@item -msatur
-@opindex msatur
-Enables the saturation instructions. Note that the compiler does not
-currently generate these itself, but this option is included for
-compatibility with other tools, like @code{as}.
+@item -msel-sched-dont-check-control-spec
+@opindex msel-sched-dont-check-control-spec
+Generate checks for control speculation in selective scheduling.
+This flag is disabled by default.
-@item -msdram
-@opindex msdram
-Link the SDRAM-based runtime instead of the default ROM-based runtime.
+@item -msched-max-memory-insns=@var{max-insns}
+@opindex msched-max-memory-insns
+Limit on the number of memory insns per instruction group, giving lower
+priority to subsequent memory insns attempting to schedule in the same
+instruction group. Frequently useful to prevent cache bank conflicts.
+The default value is 1.
-@item -msim
-@opindex msim
-Link the simulator run-time libraries.
+@item -msched-max-memory-insns-hard-limit
+@opindex msched-max-memory-insns-hard-limit
+Makes the limit specified by @option{msched-max-memory-insns} a hard limit,
+disallowing more than that number in an instruction group.
+Otherwise, the limit is ``soft'', meaning that non-memory operations
+are preferred when the limit is reached, but memory operations may still
+be scheduled.
-@item -msimnovec
-@opindex msimnovec
-Link the simulator runtime libraries, excluding built-in support
-for reset and exception vectors and tables.
+@end table
-@item -mtf
-@opindex mtf
-Causes all functions to default to the @code{.far} section. Without
-this option, functions default to the @code{.near} section.
+@node LM32 Options
+@subsection LM32 Options
+@cindex LM32 options
-@item -mtiny=@var{n}
-@opindex mtiny=
-Variables that are @var{n} bytes or smaller are allocated to the
-@code{.tiny} section. These variables use the @code{$gp} base
-register. The default for this option is 4, but note that there's a
-65536-byte limit to the @code{.tiny} section.
+These @option{-m} options are defined for the LatticeMico32 architecture:
-@end table
+@table @gcctabopt
+@item -mbarrel-shift-enabled
+@opindex mbarrel-shift-enabled
+Enable barrel-shift instructions.
-@node MicroBlaze Options
-@subsection MicroBlaze Options
-@cindex MicroBlaze Options
+@item -mdivide-enabled
+@opindex mdivide-enabled
+Enable divide and modulus instructions.
-@table @gcctabopt
+@item -mmultiply-enabled
+@opindex multiply-enabled
+Enable multiply instructions.
-@item -msoft-float
-@opindex msoft-float
-Use software emulation for floating point (default).
+@item -msign-extend-enabled
+@opindex msign-extend-enabled
+Enable sign extend instructions.
-@item -mhard-float
-@opindex mhard-float
-Use hardware floating-point instructions.
+@item -muser-enabled
+@opindex muser-enabled
+Enable user-defined instructions.
-@item -mmemcpy
-@opindex mmemcpy
-Do not optimize block moves, use @code{memcpy}.
+@end table
-@item -mno-clearbss
-@opindex mno-clearbss
-This option is deprecated. Use @option{-fno-zero-initialized-in-bss} instead.
+@node M32C Options
+@subsection M32C Options
+@cindex M32C options
-@item -mcpu=@var{cpu-type}
+@table @gcctabopt
+@item -mcpu=@var{name}
@opindex mcpu=
-Use features of, and schedule code for, the given CPU.
-Supported values are in the format @samp{v@var{X}.@var{YY}.@var{Z}},
-where @var{X} is a major version, @var{YY} is the minor version, and
-@var{Z} is compatibility code. Example values are @samp{v3.00.a},
-@samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v5.00.b}, @samp{v6.00.a}.
+Select the CPU for which code is generated. @var{name} may be one of
+@samp{r8c} for the R8C/Tiny series, @samp{m16c} for the M16C (up to
+/60) series, @samp{m32cm} for the M16C/80 series, or @samp{m32c} for
+the M32C/80 series.
-@item -mxl-soft-mul
-@opindex mxl-soft-mul
-Use software multiply emulation (default).
+@item -msim
+@opindex msim
+Specifies that the program will be run on the simulator. This causes
+an alternate runtime library to be linked in which supports, for
+example, file I/O@. You must not use this option when generating
+programs that will run on real hardware; you must provide your own
+runtime library for whatever I/O functions are needed.
-@item -mxl-soft-div
-@opindex mxl-soft-div
-Use software emulation for divides (default).
+@item -memregs=@var{number}
+@opindex memregs=
+Specifies the number of memory-based pseudo-registers GCC uses
+during code generation. These pseudo-registers are used like real
+registers, so there is a tradeoff between GCC's ability to fit the
+code into available registers, and the performance penalty of using
+memory instead of registers. Note that all modules in a program must
+be compiled with the same value for this option. Because of that, you
+must not use this option with GCC's default runtime libraries.
-@item -mxl-barrel-shift
-@opindex mxl-barrel-shift
-Use the hardware barrel shifter.
+@end table
-@item -mxl-pattern-compare
-@opindex mxl-pattern-compare
-Use pattern compare instructions.
+@node M32R/D Options
+@subsection M32R/D Options
+@cindex M32R/D options
-@item -msmall-divides
-@opindex msmall-divides
-Use table lookup optimization for small signed integer divisions.
+These @option{-m} options are defined for Renesas M32R/D architectures:
-@item -mxl-stack-check
-@opindex mxl-stack-check
-This option is deprecated. Use @option{-fstack-check} instead.
+@table @gcctabopt
+@item -m32r2
+@opindex m32r2
+Generate code for the M32R/2@.
-@item -mxl-gp-opt
-@opindex mxl-gp-opt
-Use GP-relative @code{.sdata}/@code{.sbss} sections.
+@item -m32rx
+@opindex m32rx
+Generate code for the M32R/X@.
-@item -mxl-multiply-high
-@opindex mxl-multiply-high
-Use multiply high instructions for high part of 32x32 multiply.
+@item -m32r
+@opindex m32r
+Generate code for the M32R@. This is the default.
-@item -mxl-float-convert
-@opindex mxl-float-convert
-Use hardware floating-point conversion instructions.
+@item -mmodel=small
+@opindex mmodel=small
+Assume all objects live in the lower 16MB of memory (so that their addresses
+can be loaded with the @code{ld24} instruction), and assume all subroutines
+are reachable with the @code{bl} instruction.
+This is the default.
-@item -mxl-float-sqrt
-@opindex mxl-float-sqrt
-Use hardware floating-point square root instruction.
+The addressability of a particular object can be set with the
+@code{model} attribute.
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a big-endian target.
+@item -mmodel=medium
+@opindex mmodel=medium
+Assume objects may be anywhere in the 32-bit address space (the compiler
+generates @code{seth/add3} instructions to load their addresses), and
+assume all subroutines are reachable with the @code{bl} instruction.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a little-endian target.
+@item -mmodel=large
+@opindex mmodel=large
+Assume objects may be anywhere in the 32-bit address space (the compiler
+generates @code{seth/add3} instructions to load their addresses), and
+assume subroutines may not be reachable with the @code{bl} instruction
+(the compiler generates the much slower @code{seth/add3/jl}
+instruction sequence).
-@item -mxl-reorder
-@opindex mxl-reorder
-Use reorder instructions (swap and byte reversed load/store).
+@item -msdata=none
+@opindex msdata=none
+Disable use of the small data area. Variables are put into
+one of @code{.data}, @code{.bss}, or @code{.rodata} (unless the
+@code{section} attribute has been specified).
+This is the default.
-@item -mxl-mode-@var{app-model}
-Select application model @var{app-model}. Valid models are
-@table @samp
-@item executable
-normal executable (default), uses startup code @file{crt0.o}.
+The small data area consists of sections @code{.sdata} and @code{.sbss}.
+Objects may be explicitly put in the small data area with the
+@code{section} attribute using one of these sections.
-@item xmdstub
-for use with Xilinx Microprocessor Debugger (XMD) based
-software intrusive debug agent called xmdstub. This uses startup file
-@file{crt1.o} and sets the start address of the program to 0x800.
+@item -msdata=sdata
+@opindex msdata=sdata
+Put small global and static data in the small data area, but do not
+generate special code to reference them.
-@item bootstrap
-for applications that are loaded using a bootloader.
-This model uses startup file @file{crt2.o} which does not contain a processor
-reset vector handler. This is suitable for transferring control on a
-processor reset to the bootloader rather than the application.
+@item -msdata=use
+@opindex msdata=use
+Put small global and static data in the small data area, and generate
+special instructions to reference them.
-@item novectors
-for applications that do not require any of the
-MicroBlaze vectors. This option may be useful for applications running
-within a monitoring application. This model uses @file{crt3.o} as a startup file.
-@end table
+@item -G @var{num}
+@opindex G
+@cindex smaller data references
+Put global and static objects less than or equal to @var{num} bytes
+into the small data or BSS sections instead of the normal data or BSS
+sections. The default value of @var{num} is 8.
+The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
+for this option to have any effect.
-Option @option{-xl-mode-@var{app-model}} is a deprecated alias for
-@option{-mxl-mode-@var{app-model}}.
+All modules should be compiled with the same @option{-G @var{num}} value.
+Compiling with different values of @var{num} may or may not work; if it
+doesn't the linker gives an error message---incorrect code is not
+generated.
-@end table
+@item -mdebug
+@opindex mdebug
+Makes the M32R-specific code in the compiler display some statistics
+that might help in debugging programs.
-@node MIPS Options
-@subsection MIPS Options
-@cindex MIPS options
+@item -malign-loops
+@opindex malign-loops
+Align all loops to a 32-byte boundary.
-@table @gcctabopt
+@item -mno-align-loops
+@opindex mno-align-loops
+Do not enforce a 32-byte alignment for loops. This is the default.
-@item -EB
-@opindex EB
-Generate big-endian code.
+@item -missue-rate=@var{number}
+@opindex missue-rate=@var{number}
+Issue @var{number} instructions per cycle. @var{number} can only be 1
+or 2.
-@item -EL
-@opindex EL
-Generate little-endian code. This is the default for @samp{mips*el-*-*}
-configurations.
+@item -mbranch-cost=@var{number}
+@opindex mbranch-cost=@var{number}
+@var{number} can only be 1 or 2. If it is 1 then branches are
+preferred over conditional code, if it is 2, then the opposite applies.
-@item -march=@var{arch}
-@opindex march
-Generate code that runs on @var{arch}, which can be the name of a
-generic MIPS ISA, or the name of a particular processor.
-The ISA names are:
-@samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
-@samp{mips32}, @samp{mips32r2}, @samp{mips32r3}, @samp{mips32r5},
-@samp{mips32r6}, @samp{mips64}, @samp{mips64r2}, @samp{mips64r3},
-@samp{mips64r5} and @samp{mips64r6}.
-The processor names are:
-@samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc},
-@samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd},
-@samp{5kc}, @samp{5kf},
-@samp{20kc},
-@samp{24kc}, @samp{24kf2_1}, @samp{24kf1_1},
-@samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1},
-@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{34kn},
-@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
-@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
-@samp{i6400},
-@samp{interaptiv},
-@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
-@samp{m4k},
-@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
-@samp{m5100}, @samp{m5101},
-@samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3},
-@samp{orion},
-@samp{p5600},
-@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
-@samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000},
-@samp{rm7000}, @samp{rm9000},
-@samp{r10000}, @samp{r12000}, @samp{r14000}, @samp{r16000},
-@samp{sb1},
-@samp{sr71000},
-@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
-@samp{vr5000}, @samp{vr5400}, @samp{vr5500},
-@samp{xlr} and @samp{xlp}.
-The special value @samp{from-abi} selects the
-most compatible architecture for the selected ABI (that is,
-@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
+@item -mflush-trap=@var{number}
+@opindex mflush-trap=@var{number}
+Specifies the trap number to use to flush the cache. The default is
+12. Valid numbers are between 0 and 15 inclusive.
-The native Linux/GNU toolchain also supports the value @samp{native},
-which selects the best architecture option for the host processor.
-@option{-march=native} has no effect if GCC does not recognize
-the processor.
+@item -mno-flush-trap
+@opindex mno-flush-trap
+Specifies that the cache cannot be flushed by using a trap.
-In processor names, a final @samp{000} can be abbreviated as @samp{k}
-(for example, @option{-march=r2k}). Prefixes are optional, and
-@samp{vr} may be written @samp{r}.
+@item -mflush-func=@var{name}
+@opindex mflush-func=@var{name}
+Specifies the name of the operating system function to call to flush
+the cache. The default is @samp{_flush_cache}, but a function call
+is only used if a trap is not available.
-Names of the form @samp{@var{n}f2_1} refer to processors with
-FPUs clocked at half the rate of the core, names of the form
-@samp{@var{n}f1_1} refer to processors with FPUs clocked at the same
-rate as the core, and names of the form @samp{@var{n}f3_2} refer to
-processors with FPUs clocked a ratio of 3:2 with respect to the core.
-For compatibility reasons, @samp{@var{n}f} is accepted as a synonym
-for @samp{@var{n}f2_1} while @samp{@var{n}x} and @samp{@var{b}fx} are
-accepted as synonyms for @samp{@var{n}f1_1}.
+@item -mno-flush-func
+@opindex mno-flush-func
+Indicates that there is no OS function for flushing the cache.
-GCC defines two macros based on the value of this option. The first
-is @code{_MIPS_ARCH}, which gives the name of target architecture, as
-a string. The second has the form @code{_MIPS_ARCH_@var{foo}},
-where @var{foo} is the capitalized value of @code{_MIPS_ARCH}@.
-For example, @option{-march=r2000} sets @code{_MIPS_ARCH}
-to @code{"r2000"} and defines the macro @code{_MIPS_ARCH_R2000}.
+@end table
-Note that the @code{_MIPS_ARCH} macro uses the processor names given
-above. In other words, it has the full prefix and does not
-abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
-the macro names the resolved architecture (either @code{"mips1"} or
-@code{"mips3"}). It names the default architecture when no
-@option{-march} option is given.
+@node M680x0 Options
+@subsection M680x0 Options
+@cindex M680x0 options
-@item -mtune=@var{arch}
-@opindex mtune
-Optimize for @var{arch}. Among other things, this option controls
-the way instructions are scheduled, and the perceived cost of arithmetic
-operations. The list of @var{arch} values is the same as for
-@option{-march}.
+These are the @samp{-m} options defined for M680x0 and ColdFire processors.
+The default settings depend on which architecture was selected when
+the compiler was configured; the defaults for the most common choices
+are given below.
-When this option is not used, GCC optimizes for the processor
-specified by @option{-march}. By using @option{-march} and
-@option{-mtune} together, it is possible to generate code that
-runs on a family of processors, but optimize the code for one
-particular member of that family.
+@table @gcctabopt
+@item -march=@var{arch}
+@opindex march
+Generate code for a specific M680x0 or ColdFire instruction set
+architecture. Permissible values of @var{arch} for M680x0
+architectures are: @samp{68000}, @samp{68010}, @samp{68020},
+@samp{68030}, @samp{68040}, @samp{68060} and @samp{cpu32}. ColdFire
+architectures are selected according to Freescale's ISA classification
+and the permissible values are: @samp{isaa}, @samp{isaaplus},
+@samp{isab} and @samp{isac}.
-@option{-mtune} defines the macros @code{_MIPS_TUNE} and
-@code{_MIPS_TUNE_@var{foo}}, which work in the same way as the
-@option{-march} ones described above.
+GCC defines a macro @code{__mcf@var{arch}__} whenever it is generating
+code for a ColdFire target. The @var{arch} in this macro is one of the
+@option{-march} arguments given above.
-@item -mips1
-@opindex mips1
-Equivalent to @option{-march=mips1}.
+When used together, @option{-march} and @option{-mtune} select code
+that runs on a family of similar processors but that is optimized
+for a particular microarchitecture.
-@item -mips2
-@opindex mips2
-Equivalent to @option{-march=mips2}.
+@item -mcpu=@var{cpu}
+@opindex mcpu
+Generate code for a specific M680x0 or ColdFire processor.
+The M680x0 @var{cpu}s are: @samp{68000}, @samp{68010}, @samp{68020},
+@samp{68030}, @samp{68040}, @samp{68060}, @samp{68302}, @samp{68332}
+and @samp{cpu32}. The ColdFire @var{cpu}s are given by the table
+below, which also classifies the CPUs into families:
-@item -mips3
-@opindex mips3
-Equivalent to @option{-march=mips3}.
+@multitable @columnfractions 0.20 0.80
+@item @strong{Family} @tab @strong{@samp{-mcpu} arguments}
+@item @samp{51} @tab @samp{51} @samp{51ac} @samp{51ag} @samp{51cn} @samp{51em} @samp{51je} @samp{51jf} @samp{51jg} @samp{51jm} @samp{51mm} @samp{51qe} @samp{51qm}
+@item @samp{5206} @tab @samp{5202} @samp{5204} @samp{5206}
+@item @samp{5206e} @tab @samp{5206e}
+@item @samp{5208} @tab @samp{5207} @samp{5208}
+@item @samp{5211a} @tab @samp{5210a} @samp{5211a}
+@item @samp{5213} @tab @samp{5211} @samp{5212} @samp{5213}
+@item @samp{5216} @tab @samp{5214} @samp{5216}
+@item @samp{52235} @tab @samp{52230} @samp{52231} @samp{52232} @samp{52233} @samp{52234} @samp{52235}
+@item @samp{5225} @tab @samp{5224} @samp{5225}
+@item @samp{52259} @tab @samp{52252} @samp{52254} @samp{52255} @samp{52256} @samp{52258} @samp{52259}
+@item @samp{5235} @tab @samp{5232} @samp{5233} @samp{5234} @samp{5235} @samp{523x}
+@item @samp{5249} @tab @samp{5249}
+@item @samp{5250} @tab @samp{5250}
+@item @samp{5271} @tab @samp{5270} @samp{5271}
+@item @samp{5272} @tab @samp{5272}
+@item @samp{5275} @tab @samp{5274} @samp{5275}
+@item @samp{5282} @tab @samp{5280} @samp{5281} @samp{5282} @samp{528x}
+@item @samp{53017} @tab @samp{53011} @samp{53012} @samp{53013} @samp{53014} @samp{53015} @samp{53016} @samp{53017}
+@item @samp{5307} @tab @samp{5307}
+@item @samp{5329} @tab @samp{5327} @samp{5328} @samp{5329} @samp{532x}
+@item @samp{5373} @tab @samp{5372} @samp{5373} @samp{537x}
+@item @samp{5407} @tab @samp{5407}
+@item @samp{5475} @tab @samp{5470} @samp{5471} @samp{5472} @samp{5473} @samp{5474} @samp{5475} @samp{547x} @samp{5480} @samp{5481} @samp{5482} @samp{5483} @samp{5484} @samp{5485}
+@end multitable
-@item -mips4
-@opindex mips4
-Equivalent to @option{-march=mips4}.
+@option{-mcpu=@var{cpu}} overrides @option{-march=@var{arch}} if
+@var{arch} is compatible with @var{cpu}. Other combinations of
+@option{-mcpu} and @option{-march} are rejected.
-@item -mips32
-@opindex mips32
-Equivalent to @option{-march=mips32}.
+GCC defines the macro @code{__mcf_cpu_@var{cpu}} when ColdFire target
+@var{cpu} is selected. It also defines @code{__mcf_family_@var{family}},
+where the value of @var{family} is given by the table above.
-@item -mips32r3
-@opindex mips32r3
-Equivalent to @option{-march=mips32r3}.
+@item -mtune=@var{tune}
+@opindex mtune
+Tune the code for a particular microarchitecture within the
+constraints set by @option{-march} and @option{-mcpu}.
+The M680x0 microarchitectures are: @samp{68000}, @samp{68010},
+@samp{68020}, @samp{68030}, @samp{68040}, @samp{68060}
+and @samp{cpu32}. The ColdFire microarchitectures
+are: @samp{cfv1}, @samp{cfv2}, @samp{cfv3}, @samp{cfv4} and @samp{cfv4e}.
-@item -mips32r5
-@opindex mips32r5
-Equivalent to @option{-march=mips32r5}.
+You can also use @option{-mtune=68020-40} for code that needs
+to run relatively well on 68020, 68030 and 68040 targets.
+@option{-mtune=68020-60} is similar but includes 68060 targets
+as well. These two options select the same tuning decisions as
+@option{-m68020-40} and @option{-m68020-60} respectively.
-@item -mips32r6
-@opindex mips32r6
-Equivalent to @option{-march=mips32r6}.
-
-@item -mips64
-@opindex mips64
-Equivalent to @option{-march=mips64}.
-
-@item -mips64r2
-@opindex mips64r2
-Equivalent to @option{-march=mips64r2}.
+GCC defines the macros @code{__mc@var{arch}} and @code{__mc@var{arch}__}
+when tuning for 680x0 architecture @var{arch}. It also defines
+@code{mc@var{arch}} unless either @option{-ansi} or a non-GNU @option{-std}
+option is used. If GCC is tuning for a range of architectures,
+as selected by @option{-mtune=68020-40} or @option{-mtune=68020-60},
+it defines the macros for every architecture in the range.
-@item -mips64r3
-@opindex mips64r3
-Equivalent to @option{-march=mips64r3}.
+GCC also defines the macro @code{__m@var{uarch}__} when tuning for
+ColdFire microarchitecture @var{uarch}, where @var{uarch} is one
+of the arguments given above.
-@item -mips64r5
-@opindex mips64r5
-Equivalent to @option{-march=mips64r5}.
+@item -m68000
+@itemx -mc68000
+@opindex m68000
+@opindex mc68000
+Generate output for a 68000. This is the default
+when the compiler is configured for 68000-based systems.
+It is equivalent to @option{-march=68000}.
-@item -mips64r6
-@opindex mips64r6
-Equivalent to @option{-march=mips64r6}.
+Use this option for microcontrollers with a 68000 or EC000 core,
+including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
-@item -mips16
-@itemx -mno-mips16
-@opindex mips16
-@opindex mno-mips16
-Generate (do not generate) MIPS16 code. If GCC is targeting a
-MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE@.
+@item -m68010
+@opindex m68010
+Generate output for a 68010. This is the default
+when the compiler is configured for 68010-based systems.
+It is equivalent to @option{-march=68010}.
-MIPS16 code generation can also be controlled on a per-function basis
-by means of @code{mips16} and @code{nomips16} attributes.
-@xref{Function Attributes}, for more information.
+@item -m68020
+@itemx -mc68020
+@opindex m68020
+@opindex mc68020
+Generate output for a 68020. This is the default
+when the compiler is configured for 68020-based systems.
+It is equivalent to @option{-march=68020}.
-@item -mflip-mips16
-@opindex mflip-mips16
-Generate MIPS16 code on alternating functions. This option is provided
-for regression testing of mixed MIPS16/non-MIPS16 code generation, and is
-not intended for ordinary use in compiling user code.
+@item -m68030
+@opindex m68030
+Generate output for a 68030. This is the default when the compiler is
+configured for 68030-based systems. It is equivalent to
+@option{-march=68030}.
-@item -minterlink-compressed
-@item -mno-interlink-compressed
-@opindex minterlink-compressed
-@opindex mno-interlink-compressed
-Require (do not require) that code using the standard (uncompressed) MIPS ISA
-be link-compatible with MIPS16 and microMIPS code, and vice versa.
+@item -m68040
+@opindex m68040
+Generate output for a 68040. This is the default when the compiler is
+configured for 68040-based systems. It is equivalent to
+@option{-march=68040}.
-For example, code using the standard ISA encoding cannot jump directly
-to MIPS16 or microMIPS code; it must either use a call or an indirect jump.
-@option{-minterlink-compressed} therefore disables direct jumps unless GCC
-knows that the target of the jump is not compressed.
+This option inhibits the use of 68881/68882 instructions that have to be
+emulated by software on the 68040. Use this option if your 68040 does not
+have code to emulate those instructions.
-@item -minterlink-mips16
-@itemx -mno-interlink-mips16
-@opindex minterlink-mips16
-@opindex mno-interlink-mips16
-Aliases of @option{-minterlink-compressed} and
-@option{-mno-interlink-compressed}. These options predate the microMIPS ASE
-and are retained for backwards compatibility.
+@item -m68060
+@opindex m68060
+Generate output for a 68060. This is the default when the compiler is
+configured for 68060-based systems. It is equivalent to
+@option{-march=68060}.
-@item -mabi=32
-@itemx -mabi=o64
-@itemx -mabi=n32
-@itemx -mabi=64
-@itemx -mabi=eabi
-@opindex mabi=32
-@opindex mabi=o64
-@opindex mabi=n32
-@opindex mabi=64
-@opindex mabi=eabi
-Generate code for the given ABI@.
+This option inhibits the use of 68020 and 68881/68882 instructions that
+have to be emulated by software on the 68060. Use this option if your 68060
+does not have code to emulate those instructions.
-Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
-generates 64-bit code when you select a 64-bit architecture, but you
-can use @option{-mgp32} to get 32-bit code instead.
+@item -mcpu32
+@opindex mcpu32
+Generate output for a CPU32. This is the default
+when the compiler is configured for CPU32-based systems.
+It is equivalent to @option{-march=cpu32}.
-For information about the O64 ABI, see
-@uref{http://gcc.gnu.org/@/projects/@/mipso64-abi.html}.
+Use this option for microcontrollers with a
+CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
+68336, 68340, 68341, 68349 and 68360.
-GCC supports a variant of the o32 ABI in which floating-point registers
-are 64 rather than 32 bits wide. You can select this combination with
-@option{-mabi=32} @option{-mfp64}. This ABI relies on the @code{mthc1}
-and @code{mfhc1} instructions and is therefore only supported for
-MIPS32R2, MIPS32R3 and MIPS32R5 processors.
+@item -m5200
+@opindex m5200
+Generate output for a 520X ColdFire CPU@. This is the default
+when the compiler is configured for 520X-based systems.
+It is equivalent to @option{-mcpu=5206}, and is now deprecated
+in favor of that option.
-The register assignments for arguments and return values remain the
-same, but each scalar value is passed in a single 64-bit register
-rather than a pair of 32-bit registers. For example, scalar
-floating-point values are returned in @samp{$f0} only, not a
-@samp{$f0}/@samp{$f1} pair. The set of call-saved registers also
-remains the same in that the even-numbered double-precision registers
-are saved.
+Use this option for microcontroller with a 5200 core, including
+the MCF5202, MCF5203, MCF5204 and MCF5206.
-Two additional variants of the o32 ABI are supported to enable
-a transition from 32-bit to 64-bit registers. These are FPXX
-(@option{-mfpxx}) and FP64A (@option{-mfp64} @option{-mno-odd-spreg}).
-The FPXX extension mandates that all code must execute correctly
-when run using 32-bit or 64-bit registers. The code can be interlinked
-with either FP32 or FP64, but not both.
-The FP64A extension is similar to the FP64 extension but forbids the
-use of odd-numbered single-precision registers. This can be used
-in conjunction with the @code{FRE} mode of FPUs in MIPS32R5
-processors and allows both FP32 and FP64A code to interlink and
-run in the same process without changing FPU modes.
+@item -m5206e
+@opindex m5206e
+Generate output for a 5206e ColdFire CPU@. The option is now
+deprecated in favor of the equivalent @option{-mcpu=5206e}.
-@item -mabicalls
-@itemx -mno-abicalls
-@opindex mabicalls
-@opindex mno-abicalls
-Generate (do not generate) code that is suitable for SVR4-style
-dynamic objects. @option{-mabicalls} is the default for SVR4-based
-systems.
+@item -m528x
+@opindex m528x
+Generate output for a member of the ColdFire 528X family.
+The option is now deprecated in favor of the equivalent
+@option{-mcpu=528x}.
-@item -mshared
-@itemx -mno-shared
-Generate (do not generate) code that is fully position-independent,
-and that can therefore be linked into shared libraries. This option
-only affects @option{-mabicalls}.
+@item -m5307
+@opindex m5307
+Generate output for a ColdFire 5307 CPU@. The option is now deprecated
+in favor of the equivalent @option{-mcpu=5307}.
-All @option{-mabicalls} code has traditionally been position-independent,
-regardless of options like @option{-fPIC} and @option{-fpic}. However,
-as an extension, the GNU toolchain allows executables to use absolute
-accesses for locally-binding symbols. It can also use shorter GP
-initialization sequences and generate direct calls to locally-defined
-functions. This mode is selected by @option{-mno-shared}.
+@item -m5407
+@opindex m5407
+Generate output for a ColdFire 5407 CPU@. The option is now deprecated
+in favor of the equivalent @option{-mcpu=5407}.
-@option{-mno-shared} depends on binutils 2.16 or higher and generates
-objects that can only be linked by the GNU linker. However, the option
-does not affect the ABI of the final executable; it only affects the ABI
-of relocatable objects. Using @option{-mno-shared} generally makes
-executables both smaller and quicker.
+@item -mcfv4e
+@opindex mcfv4e
+Generate output for a ColdFire V4e family CPU (e.g.@: 547x/548x).
+This includes use of hardware floating-point instructions.
+The option is equivalent to @option{-mcpu=547x}, and is now
+deprecated in favor of that option.
-@option{-mshared} is the default.
+@item -m68020-40
+@opindex m68020-40
+Generate output for a 68040, without using any of the new instructions.
+This results in code that can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68040.
-@item -mplt
-@itemx -mno-plt
-@opindex mplt
-@opindex mno-plt
-Assume (do not assume) that the static and dynamic linkers
-support PLTs and copy relocations. This option only affects
-@option{-mno-shared -mabicalls}. For the n64 ABI, this option
-has no effect without @option{-msym32}.
+The option is equivalent to @option{-march=68020} @option{-mtune=68020-40}.
-You can make @option{-mplt} the default by configuring
-GCC with @option{--with-mips-plt}. The default is
-@option{-mno-plt} otherwise.
+@item -m68020-60
+@opindex m68020-60
+Generate output for a 68060, without using any of the new instructions.
+This results in code that can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68060.
-@item -mxgot
-@itemx -mno-xgot
-@opindex mxgot
-@opindex mno-xgot
-Lift (do not lift) the usual restrictions on the size of the global
-offset table.
+The option is equivalent to @option{-march=68020} @option{-mtune=68020-60}.
-GCC normally uses a single instruction to load values from the GOT@.
-While this is relatively efficient, it only works if the GOT
-is smaller than about 64k. Anything larger causes the linker
-to report an error such as:
+@item -mhard-float
+@itemx -m68881
+@opindex mhard-float
+@opindex m68881
+Generate floating-point instructions. This is the default for 68020
+and above, and for ColdFire devices that have an FPU@. It defines the
+macro @code{__HAVE_68881__} on M680x0 targets and @code{__mcffpu__}
+on ColdFire targets.
-@cindex relocation truncated to fit (MIPS)
-@smallexample
-relocation truncated to fit: R_MIPS_GOT16 foobar
-@end smallexample
+@item -msoft-float
+@opindex msoft-float
+Do not generate floating-point instructions; use library calls instead.
+This is the default for 68000, 68010, and 68832 targets. It is also
+the default for ColdFire devices that have no FPU.
-If this happens, you should recompile your code with @option{-mxgot}.
-This works with very large GOTs, although the code is also
-less efficient, since it takes three instructions to fetch the
-value of a global symbol.
+@item -mdiv
+@itemx -mno-div
+@opindex mdiv
+@opindex mno-div
+Generate (do not generate) ColdFire hardware divide and remainder
+instructions. If @option{-march} is used without @option{-mcpu},
+the default is ``on'' for ColdFire architectures and ``off'' for M680x0
+architectures. Otherwise, the default is taken from the target CPU
+(either the default CPU, or the one specified by @option{-mcpu}). For
+example, the default is ``off'' for @option{-mcpu=5206} and ``on'' for
+@option{-mcpu=5206e}.
-Note that some linkers can create multiple GOTs. If you have such a
-linker, you should only need to use @option{-mxgot} when a single object
-file accesses more than 64k's worth of GOT entries. Very few do.
+GCC defines the macro @code{__mcfhwdiv__} when this option is enabled.
-These options have no effect unless GCC is generating position
-independent code.
+@item -mshort
+@opindex mshort
+Consider type @code{int} to be 16 bits wide, like @code{short int}.
+Additionally, parameters passed on the stack are also aligned to a
+16-bit boundary even on targets whose API mandates promotion to 32-bit.
-@item -mgp32
-@opindex mgp32
-Assume that general-purpose registers are 32 bits wide.
+@item -mno-short
+@opindex mno-short
+Do not consider type @code{int} to be 16 bits wide. This is the default.
-@item -mgp64
-@opindex mgp64
-Assume that general-purpose registers are 64 bits wide.
+@item -mnobitfield
+@itemx -mno-bitfield
+@opindex mnobitfield
+@opindex mno-bitfield
+Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
+and @option{-m5200} options imply @w{@option{-mnobitfield}}.
-@item -mfp32
-@opindex mfp32
-Assume that floating-point registers are 32 bits wide.
+@item -mbitfield
+@opindex mbitfield
+Do use the bit-field instructions. The @option{-m68020} option implies
+@option{-mbitfield}. This is the default if you use a configuration
+designed for a 68020.
-@item -mfp64
-@opindex mfp64
-Assume that floating-point registers are 64 bits wide.
+@item -mrtd
+@opindex mrtd
+Use a different function-calling convention, in which functions
+that take a fixed number of arguments return with the @code{rtd}
+instruction, which pops their arguments while returning. This
+saves one instruction in the caller since there is no need to pop
+the arguments there.
-@item -mfpxx
-@opindex mfpxx
-Do not assume the width of floating-point registers.
+This calling convention is incompatible with the one normally
+used on Unix, so you cannot use it if you need to call libraries
+compiled with the Unix compiler.
-@item -mhard-float
-@opindex mhard-float
-Use floating-point coprocessor instructions.
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including @code{printf});
+otherwise incorrect code is generated for calls to those
+functions.
-@item -msoft-float
-@opindex msoft-float
-Do not use floating-point coprocessor instructions. Implement
-floating-point calculations using library calls instead.
+In addition, seriously incorrect code results if you call a
+function with too many arguments. (Normally, extra arguments are
+harmlessly ignored.)
-@item -mno-float
-@opindex mno-float
-Equivalent to @option{-msoft-float}, but additionally asserts that the
-program being compiled does not perform any floating-point operations.
-This option is presently supported only by some bare-metal MIPS
-configurations, where it may select a special set of libraries
-that lack all floating-point support (including, for example, the
-floating-point @code{printf} formats).
-If code compiled with @option{-mno-float} accidentally contains
-floating-point operations, it is likely to suffer a link-time
-or run-time failure.
+The @code{rtd} instruction is supported by the 68010, 68020, 68030,
+68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
-@item -msingle-float
-@opindex msingle-float
-Assume that the floating-point coprocessor only supports single-precision
-operations.
+@item -mno-rtd
+@opindex mno-rtd
+Do not use the calling conventions selected by @option{-mrtd}.
+This is the default.
-@item -mdouble-float
-@opindex mdouble-float
-Assume that the floating-point coprocessor supports double-precision
-operations. This is the default.
+@item -malign-int
+@itemx -mno-align-int
+@opindex malign-int
+@opindex mno-align-int
+Control whether GCC aligns @code{int}, @code{long}, @code{long long},
+@code{float}, @code{double}, and @code{long double} variables on a 32-bit
+boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
+Aligning variables on 32-bit boundaries produces code that runs somewhat
+faster on processors with 32-bit busses at the expense of more memory.
-@item -modd-spreg
-@itemx -mno-odd-spreg
-@opindex modd-spreg
-@opindex mno-odd-spreg
-Enable the use of odd-numbered single-precision floating-point registers
-for the o32 ABI. This is the default for processors that are known to
-support these registers. When using the o32 FPXX ABI, @option{-mno-odd-spreg}
-is set by default.
+@strong{Warning:} if you use the @option{-malign-int} switch, GCC
+aligns structures containing the above types differently than
+most published application binary interface specifications for the m68k.
-@item -mabs=2008
-@itemx -mabs=legacy
-@opindex mabs=2008
-@opindex mabs=legacy
-These options control the treatment of the special not-a-number (NaN)
-IEEE 754 floating-point data with the @code{abs.@i{fmt}} and
-@code{neg.@i{fmt}} machine instructions.
+@item -mpcrel
+@opindex mpcrel
+Use the pc-relative addressing mode of the 68000 directly, instead of
+using a global offset table. At present, this option implies @option{-fpic},
+allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
+not presently supported with @option{-mpcrel}, though this could be supported for
+68020 and higher processors.
-By default or when @option{-mabs=legacy} is used the legacy
-treatment is selected. In this case these instructions are considered
-arithmetic and avoided where correct operation is required and the
-input operand might be a NaN. A longer sequence of instructions that
-manipulate the sign bit of floating-point datum manually is used
-instead unless the @option{-ffinite-math-only} option has also been
-specified.
+@item -mno-strict-align
+@itemx -mstrict-align
+@opindex mno-strict-align
+@opindex mstrict-align
+Do not (do) assume that unaligned memory references are handled by
+the system.
-The @option{-mabs=2008} option selects the IEEE 754-2008 treatment. In
-this case these instructions are considered non-arithmetic and therefore
-operating correctly in all cases, including in particular where the
-input operand is a NaN. These instructions are therefore always used
-for the respective operations.
+@item -msep-data
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute-in-place in
+an environment without virtual memory management. This option implies
+@option{-fPIC}.
-@item -mnan=2008
-@itemx -mnan=legacy
-@opindex mnan=2008
-@opindex mnan=legacy
-These options control the encoding of the special not-a-number (NaN)
-IEEE 754 floating-point data.
+@item -mno-sep-data
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
-The @option{-mnan=legacy} option selects the legacy encoding. In this
-case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
-significand field being 0, whereas signalling NaNs (sNaNs) are denoted
-by the first bit of their trailing significand field being 1.
+@item -mid-shared-library
+Generate code that supports shared libraries via the library ID method.
+This allows for execute-in-place and shared libraries in an environment
+without virtual memory management. This option implies @option{-fPIC}.
-The @option{-mnan=2008} option selects the IEEE 754-2008 encoding. In
-this case qNaNs are denoted by the first bit of their trailing
-significand field being 1, whereas sNaNs are denoted by the first bit of
-their trailing significand field being 0.
+@item -mno-id-shared-library
+Generate code that doesn't assume ID-based shared libraries are being used.
+This is the default.
-The default is @option{-mnan=legacy} unless GCC has been configured with
-@option{--with-nan=2008}.
+@item -mshared-library-id=n
+Specifies the identification number of the ID-based shared library being
+compiled. Specifying a value of 0 generates more compact code; specifying
+other values forces the allocation of that number to the current
+library, but is no more space- or time-efficient than omitting this option.
-@item -mllsc
-@itemx -mno-llsc
-@opindex mllsc
-@opindex mno-llsc
-Use (do not use) @samp{ll}, @samp{sc}, and @samp{sync} instructions to
-implement atomic memory built-in functions. When neither option is
-specified, GCC uses the instructions if the target architecture
-supports them.
+@item -mxgot
+@itemx -mno-xgot
+@opindex mxgot
+@opindex mno-xgot
+When generating position-independent code for ColdFire, generate code
+that works if the GOT has more than 8192 entries. This code is
+larger and slower than code generated without this option. On M680x0
+processors, this option is not needed; @option{-fPIC} suffices.
-@option{-mllsc} is useful if the runtime environment can emulate the
-instructions and @option{-mno-llsc} can be useful when compiling for
-nonstandard ISAs. You can make either option the default by
-configuring GCC with @option{--with-llsc} and @option{--without-llsc}
-respectively. @option{--with-llsc} is the default for some
-configurations; see the installation documentation for details.
+GCC normally uses a single instruction to load values from the GOT@.
+While this is relatively efficient, it only works if the GOT
+is smaller than about 64k. Anything larger causes the linker
+to report an error such as:
-@item -mdsp
-@itemx -mno-dsp
-@opindex mdsp
-@opindex mno-dsp
-Use (do not use) revision 1 of the MIPS DSP ASE@.
-@xref{MIPS DSP Built-in Functions}. This option defines the
-preprocessor macro @code{__mips_dsp}. It also defines
-@code{__mips_dsp_rev} to 1.
+@cindex relocation truncated to fit (ColdFire)
+@smallexample
+relocation truncated to fit: R_68K_GOT16O foobar
+@end smallexample
-@item -mdspr2
-@itemx -mno-dspr2
-@opindex mdspr2
-@opindex mno-dspr2
-Use (do not use) revision 2 of the MIPS DSP ASE@.
-@xref{MIPS DSP Built-in Functions}. This option defines the
-preprocessor macros @code{__mips_dsp} and @code{__mips_dspr2}.
-It also defines @code{__mips_dsp_rev} to 2.
+If this happens, you should recompile your code with @option{-mxgot}.
+It should then work with very large GOTs. However, code generated with
+@option{-mxgot} is less efficient, since it takes 4 instructions to fetch
+the value of a global symbol.
-@item -msmartmips
-@itemx -mno-smartmips
-@opindex msmartmips
-@opindex mno-smartmips
-Use (do not use) the MIPS SmartMIPS ASE.
+Note that some linkers, including newer versions of the GNU linker,
+can create multiple GOTs and sort GOT entries. If you have such a linker,
+you should only need to use @option{-mxgot} when compiling a single
+object file that accesses more than 8192 GOT entries. Very few do.
-@item -mpaired-single
-@itemx -mno-paired-single
-@opindex mpaired-single
-@opindex mno-paired-single
-Use (do not use) paired-single floating-point instructions.
-@xref{MIPS Paired-Single Support}. This option requires
-hardware floating-point support to be enabled.
-
-@item -mdmx
-@itemx -mno-mdmx
-@opindex mdmx
-@opindex mno-mdmx
-Use (do not use) MIPS Digital Media Extension instructions.
-This option can only be used when generating 64-bit code and requires
-hardware floating-point support to be enabled.
+These options have no effect unless GCC is generating
+position-independent code.
-@item -mips3d
-@itemx -mno-mips3d
-@opindex mips3d
-@opindex mno-mips3d
-Use (do not use) the MIPS-3D ASE@. @xref{MIPS-3D Built-in Functions}.
-The option @option{-mips3d} implies @option{-mpaired-single}.
+@end table
-@item -mmicromips
-@itemx -mno-micromips
-@opindex mmicromips
-@opindex mno-mmicromips
-Generate (do not generate) microMIPS code.
+@node MCore Options
+@subsection MCore Options
+@cindex MCore options
-MicroMIPS code generation can also be controlled on a per-function basis
-by means of @code{micromips} and @code{nomicromips} attributes.
-@xref{Function Attributes}, for more information.
+These are the @samp{-m} options defined for the Motorola M*Core
+processors.
-@item -mmt
-@itemx -mno-mt
-@opindex mmt
-@opindex mno-mt
-Use (do not use) MT Multithreading instructions.
+@table @gcctabopt
-@item -mmcu
-@itemx -mno-mcu
-@opindex mmcu
-@opindex mno-mcu
-Use (do not use) the MIPS MCU ASE instructions.
+@item -mhardlit
+@itemx -mno-hardlit
+@opindex mhardlit
+@opindex mno-hardlit
+Inline constants into the code stream if it can be done in two
+instructions or less.
-@item -meva
-@itemx -mno-eva
-@opindex meva
-@opindex mno-eva
-Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
+@item -mdiv
+@itemx -mno-div
+@opindex mdiv
+@opindex mno-div
+Use the divide instruction. (Enabled by default).
-@item -mvirt
-@itemx -mno-virt
-@opindex mvirt
-@opindex mno-virt
-Use (do not use) the MIPS Virtualization Application Specific instructions.
+@item -mrelax-immediate
+@itemx -mno-relax-immediate
+@opindex mrelax-immediate
+@opindex mno-relax-immediate
+Allow arbitrary-sized immediates in bit operations.
-@item -mxpa
-@itemx -mno-xpa
-@opindex mxpa
-@opindex mno-xpa
-Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
+@item -mwide-bitfields
+@itemx -mno-wide-bitfields
+@opindex mwide-bitfields
+@opindex mno-wide-bitfields
+Always treat bit-fields as @code{int}-sized.
-@item -mlong64
-@opindex mlong64
-Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
-an explanation of the default and the way that the pointer size is
-determined.
+@item -m4byte-functions
+@itemx -mno-4byte-functions
+@opindex m4byte-functions
+@opindex mno-4byte-functions
+Force all functions to be aligned to a 4-byte boundary.
-@item -mlong32
-@opindex mlong32
-Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
+@item -mcallgraph-data
+@itemx -mno-callgraph-data
+@opindex mcallgraph-data
+@opindex mno-callgraph-data
+Emit callgraph information.
-The default size of @code{int}s, @code{long}s and pointers depends on
-the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
-uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
-32-bit @code{long}s. Pointers are the same size as @code{long}s,
-or the same size as integer registers, whichever is smaller.
+@item -mslow-bytes
+@itemx -mno-slow-bytes
+@opindex mslow-bytes
+@opindex mno-slow-bytes
+Prefer word access when reading byte quantities.
-@item -msym32
-@itemx -mno-sym32
-@opindex msym32
-@opindex mno-sym32
-Assume (do not assume) that all symbols have 32-bit values, regardless
-of the selected ABI@. This option is useful in combination with
-@option{-mabi=64} and @option{-mno-abicalls} because it allows GCC
-to generate shorter and faster references to symbolic addresses.
+@item -mlittle-endian
+@itemx -mbig-endian
+@opindex mlittle-endian
+@opindex mbig-endian
+Generate code for a little-endian target.
-@item -G @var{num}
-@opindex G
-Put definitions of externally-visible data in a small data section
-if that data is no bigger than @var{num} bytes. GCC can then generate
-more efficient accesses to the data; see @option{-mgpopt} for details.
+@item -m210
+@itemx -m340
+@opindex m210
+@opindex m340
+Generate code for the 210 processor.
-The default @option{-G} option depends on the configuration.
+@item -mno-lsim
+@opindex mno-lsim
+Assume that runtime support has been provided and so omit the
+simulator library (@file{libsim.a)} from the linker command line.
-@item -mlocal-sdata
-@itemx -mno-local-sdata
-@opindex mlocal-sdata
-@opindex mno-local-sdata
-Extend (do not extend) the @option{-G} behavior to local data too,
-such as to static variables in C@. @option{-mlocal-sdata} is the
-default for all configurations.
+@item -mstack-increment=@var{size}
+@opindex mstack-increment
+Set the maximum amount for a single stack increment operation. Large
+values can increase the speed of programs that contain functions
+that need a large amount of stack space, but they can also trigger a
+segmentation fault if the stack is extended too much. The default
+value is 0x1000.
-If the linker complains that an application is using too much small data,
-you might want to try rebuilding the less performance-critical parts with
-@option{-mno-local-sdata}. You might also want to build large
-libraries with @option{-mno-local-sdata}, so that the libraries leave
-more room for the main program.
+@end table
-@item -mextern-sdata
-@itemx -mno-extern-sdata
-@opindex mextern-sdata
-@opindex mno-extern-sdata
-Assume (do not assume) that externally-defined data is in
-a small data section if the size of that data is within the @option{-G} limit.
-@option{-mextern-sdata} is the default for all configurations.
+@node MeP Options
+@subsection MeP Options
+@cindex MeP options
-If you compile a module @var{Mod} with @option{-mextern-sdata} @option{-G
-@var{num}} @option{-mgpopt}, and @var{Mod} references a variable @var{Var}
-that is no bigger than @var{num} bytes, you must make sure that @var{Var}
-is placed in a small data section. If @var{Var} is defined by another
-module, you must either compile that module with a high-enough
-@option{-G} setting or attach a @code{section} attribute to @var{Var}'s
-definition. If @var{Var} is common, you must link the application
-with a high-enough @option{-G} setting.
+@table @gcctabopt
-The easiest way of satisfying these restrictions is to compile
-and link every module with the same @option{-G} option. However,
-you may wish to build a library that supports several different
-small data limits. You can do this by compiling the library with
-the highest supported @option{-G} setting and additionally using
-@option{-mno-extern-sdata} to stop the library from making assumptions
-about externally-defined data.
+@item -mabsdiff
+@opindex mabsdiff
+Enables the @code{abs} instruction, which is the absolute difference
+between two registers.
-@item -mgpopt
-@itemx -mno-gpopt
-@opindex mgpopt
-@opindex mno-gpopt
-Use (do not use) GP-relative accesses for symbols that are known to be
-in a small data section; see @option{-G}, @option{-mlocal-sdata} and
-@option{-mextern-sdata}. @option{-mgpopt} is the default for all
-configurations.
+@item -mall-opts
+@opindex mall-opts
+Enables all the optional instructions---average, multiply, divide, bit
+operations, leading zero, absolute difference, min/max, clip, and
+saturation.
-@option{-mno-gpopt} is useful for cases where the @code{$gp} register
-might not hold the value of @code{_gp}. For example, if the code is
-part of a library that might be used in a boot monitor, programs that
-call boot monitor routines pass an unknown value in @code{$gp}.
-(In such situations, the boot monitor itself is usually compiled
-with @option{-G0}.)
-@option{-mno-gpopt} implies @option{-mno-local-sdata} and
-@option{-mno-extern-sdata}.
+@item -maverage
+@opindex maverage
+Enables the @code{ave} instruction, which computes the average of two
+registers.
-@item -membedded-data
-@itemx -mno-embedded-data
-@opindex membedded-data
-@opindex mno-embedded-data
-Allocate variables to the read-only data section first if possible, then
-next in the small data section if possible, otherwise in data. This gives
-slightly slower code than the default, but reduces the amount of RAM required
-when executing, and thus may be preferred for some embedded systems.
+@item -mbased=@var{n}
+@opindex mbased=
+Variables of size @var{n} bytes or smaller are placed in the
+@code{.based} section by default. Based variables use the @code{$tp}
+register as a base register, and there is a 128-byte limit to the
+@code{.based} section.
-@item -muninit-const-in-rodata
-@itemx -mno-uninit-const-in-rodata
-@opindex muninit-const-in-rodata
-@opindex mno-uninit-const-in-rodata
-Put uninitialized @code{const} variables in the read-only data section.
-This option is only meaningful in conjunction with @option{-membedded-data}.
+@item -mbitops
+@opindex mbitops
+Enables the bit operation instructions---bit test (@code{btstm}), set
+(@code{bsetm}), clear (@code{bclrm}), invert (@code{bnotm}), and
+test-and-set (@code{tas}).
-@item -mcode-readable=@var{setting}
-@opindex mcode-readable
-Specify whether GCC may generate code that reads from executable sections.
-There are three possible settings:
+@item -mc=@var{name}
+@opindex mc=
+Selects which section constant data is placed in. @var{name} may
+be @samp{tiny}, @samp{near}, or @samp{far}.
-@table @gcctabopt
-@item -mcode-readable=yes
-Instructions may freely access executable sections. This is the
-default setting.
+@item -mclip
+@opindex mclip
+Enables the @code{clip} instruction. Note that @option{-mclip} is not
+useful unless you also provide @option{-mminmax}.
-@item -mcode-readable=pcrel
-MIPS16 PC-relative load instructions can access executable sections,
-but other instructions must not do so. This option is useful on 4KSc
-and 4KSd processors when the code TLBs have the Read Inhibit bit set.
-It is also useful on processors that can be configured to have a dual
-instruction/data SRAM interface and that, like the M4K, automatically
-redirect PC-relative loads to the instruction RAM.
+@item -mconfig=@var{name}
+@opindex mconfig=
+Selects one of the built-in core configurations. Each MeP chip has
+one or more modules in it; each module has a core CPU and a variety of
+coprocessors, optional instructions, and peripherals. The
+@code{MeP-Integrator} tool, not part of GCC, provides these
+configurations through this option; using this option is the same as
+using all the corresponding command-line options. The default
+configuration is @samp{default}.
-@item -mcode-readable=no
-Instructions must not access executable sections. This option can be
-useful on targets that are configured to have a dual instruction/data
-SRAM interface but that (unlike the M4K) do not automatically redirect
-PC-relative loads to the instruction RAM.
-@end table
+@item -mcop
+@opindex mcop
+Enables the coprocessor instructions. By default, this is a 32-bit
+coprocessor. Note that the coprocessor is normally enabled via the
+@option{-mconfig=} option.
-@item -msplit-addresses
-@itemx -mno-split-addresses
-@opindex msplit-addresses
-@opindex mno-split-addresses
-Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
-relocation operators. This option has been superseded by
-@option{-mexplicit-relocs} but is retained for backwards compatibility.
+@item -mcop32
+@opindex mcop32
+Enables the 32-bit coprocessor's instructions.
-@item -mexplicit-relocs
-@itemx -mno-explicit-relocs
-@opindex mexplicit-relocs
-@opindex mno-explicit-relocs
-Use (do not use) assembler relocation operators when dealing with symbolic
-addresses. The alternative, selected by @option{-mno-explicit-relocs},
-is to use assembler macros instead.
+@item -mcop64
+@opindex mcop64
+Enables the 64-bit coprocessor's instructions.
-@option{-mexplicit-relocs} is the default if GCC was configured
-to use an assembler that supports relocation operators.
+@item -mivc2
+@opindex mivc2
+Enables IVC2 scheduling. IVC2 is a 64-bit VLIW coprocessor.
-@item -mcheck-zero-division
-@itemx -mno-check-zero-division
-@opindex mcheck-zero-division
-@opindex mno-check-zero-division
-Trap (do not trap) on integer division by zero.
+@item -mdc
+@opindex mdc
+Causes constant variables to be placed in the @code{.near} section.
-The default is @option{-mcheck-zero-division}.
+@item -mdiv
+@opindex mdiv
+Enables the @code{div} and @code{divu} instructions.
-@item -mdivide-traps
-@itemx -mdivide-breaks
-@opindex mdivide-traps
-@opindex mdivide-breaks
-MIPS systems check for division by zero by generating either a
-conditional trap or a break instruction. Using traps results in
-smaller code, but is only supported on MIPS II and later. Also, some
-versions of the Linux kernel have a bug that prevents trap from
-generating the proper signal (@code{SIGFPE}). Use @option{-mdivide-traps} to
-allow conditional traps on architectures that support them and
-@option{-mdivide-breaks} to force the use of breaks.
+@item -meb
+@opindex meb
+Generate big-endian code.
-The default is usually @option{-mdivide-traps}, but this can be
-overridden at configure time using @option{--with-divide=breaks}.
-Divide-by-zero checks can be completely disabled using
-@option{-mno-check-zero-division}.
+@item -mel
+@opindex mel
+Generate little-endian code.
-@item -mmemcpy
-@itemx -mno-memcpy
-@opindex mmemcpy
-@opindex mno-memcpy
-Force (do not force) the use of @code{memcpy} for non-trivial block
-moves. The default is @option{-mno-memcpy}, which allows GCC to inline
-most constant-sized copies.
+@item -mio-volatile
+@opindex mio-volatile
+Tells the compiler that any variable marked with the @code{io}
+attribute is to be considered volatile.
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Disable (do not disable) use of the @code{jal} instruction. Calling
-functions using @code{jal} is more efficient but requires the caller
-and callee to be in the same 256 megabyte segment.
+@item -ml
+@opindex ml
+Causes variables to be assigned to the @code{.far} section by default.
-This option has no effect on abicalls code. The default is
-@option{-mno-long-calls}.
+@item -mleadz
+@opindex mleadz
+Enables the @code{leadz} (leading zero) instruction.
-@item -mmad
-@itemx -mno-mad
-@opindex mmad
-@opindex mno-mad
-Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
-instructions, as provided by the R4650 ISA@.
+@item -mm
+@opindex mm
+Causes variables to be assigned to the @code{.near} section by default.
-@item -mimadd
-@itemx -mno-imadd
-@opindex mimadd
-@opindex mno-imadd
-Enable (disable) use of the @code{madd} and @code{msub} integer
-instructions. The default is @option{-mimadd} on architectures
-that support @code{madd} and @code{msub} except for the 74k
-architecture where it was found to generate slower code.
+@item -mminmax
+@opindex mminmax
+Enables the @code{min} and @code{max} instructions.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Enable (disable) use of the floating-point multiply-accumulate
-instructions, when they are available. The default is
-@option{-mfused-madd}.
+@item -mmult
+@opindex mmult
+Enables the multiplication and multiply-accumulate instructions.
-On the R8000 CPU when multiply-accumulate instructions are used,
-the intermediate product is calculated to infinite precision
-and is not subject to the FCSR Flush to Zero bit. This may be
-undesirable in some circumstances. On other processors the result
-is numerically identical to the equivalent computation using
-separate multiply, add, subtract and negate instructions.
+@item -mno-opts
+@opindex mno-opts
+Disables all the optional instructions enabled by @option{-mall-opts}.
-@item -nocpp
-@opindex nocpp
-Tell the MIPS assembler to not run its preprocessor over user
-assembler files (with a @samp{.s} suffix) when assembling them.
+@item -mrepeat
+@opindex mrepeat
+Enables the @code{repeat} and @code{erepeat} instructions, used for
+low-overhead looping.
-@item -mfix-24k
-@item -mno-fix-24k
-@opindex mfix-24k
-@opindex mno-fix-24k
-Work around the 24K E48 (lost data on stores during refill) errata.
-The workarounds are implemented by the assembler rather than by GCC@.
+@item -ms
+@opindex ms
+Causes all variables to default to the @code{.tiny} section. Note
+that there is a 65536-byte limit to this section. Accesses to these
+variables use the @code{%gp} base register.
-@item -mfix-r4000
-@itemx -mno-fix-r4000
-@opindex mfix-r4000
-@opindex mno-fix-r4000
-Work around certain R4000 CPU errata:
-@itemize @minus
-@item
-A double-word or a variable shift may give an incorrect result if executed
-immediately after starting an integer division.
-@item
-A double-word or a variable shift may give an incorrect result if executed
-while an integer multiplication is in progress.
-@item
-An integer division may give an incorrect result if started in a delay slot
-of a taken branch or a jump.
-@end itemize
+@item -msatur
+@opindex msatur
+Enables the saturation instructions. Note that the compiler does not
+currently generate these itself, but this option is included for
+compatibility with other tools, like @code{as}.
-@item -mfix-r4400
-@itemx -mno-fix-r4400
-@opindex mfix-r4400
-@opindex mno-fix-r4400
-Work around certain R4400 CPU errata:
-@itemize @minus
-@item
-A double-word or a variable shift may give an incorrect result if executed
-immediately after starting an integer division.
-@end itemize
+@item -msdram
+@opindex msdram
+Link the SDRAM-based runtime instead of the default ROM-based runtime.
-@item -mfix-r10000
-@itemx -mno-fix-r10000
-@opindex mfix-r10000
-@opindex mno-fix-r10000
-Work around certain R10000 errata:
-@itemize @minus
-@item
-@code{ll}/@code{sc} sequences may not behave atomically on revisions
-prior to 3.0. They may deadlock on revisions 2.6 and earlier.
-@end itemize
+@item -msim
+@opindex msim
+Link the simulator run-time libraries.
-This option can only be used if the target architecture supports
-branch-likely instructions. @option{-mfix-r10000} is the default when
-@option{-march=r10000} is used; @option{-mno-fix-r10000} is the default
-otherwise.
+@item -msimnovec
+@opindex msimnovec
+Link the simulator runtime libraries, excluding built-in support
+for reset and exception vectors and tables.
-@item -mfix-rm7000
-@itemx -mno-fix-rm7000
-@opindex mfix-rm7000
-Work around the RM7000 @code{dmult}/@code{dmultu} errata. The
-workarounds are implemented by the assembler rather than by GCC@.
+@item -mtf
+@opindex mtf
+Causes all functions to default to the @code{.far} section. Without
+this option, functions default to the @code{.near} section.
-@item -mfix-vr4120
-@itemx -mno-fix-vr4120
-@opindex mfix-vr4120
-Work around certain VR4120 errata:
-@itemize @minus
-@item
-@code{dmultu} does not always produce the correct result.
-@item
-@code{div} and @code{ddiv} do not always produce the correct result if one
-of the operands is negative.
-@end itemize
-The workarounds for the division errata rely on special functions in
-@file{libgcc.a}. At present, these functions are only provided by
-the @code{mips64vr*-elf} configurations.
+@item -mtiny=@var{n}
+@opindex mtiny=
+Variables that are @var{n} bytes or smaller are allocated to the
+@code{.tiny} section. These variables use the @code{$gp} base
+register. The default for this option is 4, but note that there's a
+65536-byte limit to the @code{.tiny} section.
-Other VR4120 errata require a NOP to be inserted between certain pairs of
-instructions. These errata are handled by the assembler, not by GCC itself.
+@end table
-@item -mfix-vr4130
-@opindex mfix-vr4130
-Work around the VR4130 @code{mflo}/@code{mfhi} errata. The
-workarounds are implemented by the assembler rather than by GCC,
-although GCC avoids using @code{mflo} and @code{mfhi} if the
-VR4130 @code{macc}, @code{macchi}, @code{dmacc} and @code{dmacchi}
-instructions are available instead.
-
-@item -mfix-sb1
-@itemx -mno-fix-sb1
-@opindex mfix-sb1
-Work around certain SB-1 CPU core errata.
-(This flag currently works around the SB-1 revision 2
-``F1'' and ``F2'' floating-point errata.)
-
-@item -mr10k-cache-barrier=@var{setting}
-@opindex mr10k-cache-barrier
-Specify whether GCC should insert cache barriers to avoid the
-side-effects of speculation on R10K processors.
-
-In common with many processors, the R10K tries to predict the outcome
-of a conditional branch and speculatively executes instructions from
-the ``taken'' branch. It later aborts these instructions if the
-predicted outcome is wrong. However, on the R10K, even aborted
-instructions can have side effects.
-
-This problem only affects kernel stores and, depending on the system,
-kernel loads. As an example, a speculatively-executed store may load
-the target memory into cache and mark the cache line as dirty, even if
-the store itself is later aborted. If a DMA operation writes to the
-same area of memory before the ``dirty'' line is flushed, the cached
-data overwrites the DMA-ed data. See the R10K processor manual
-for a full description, including other potential problems.
+@node MicroBlaze Options
+@subsection MicroBlaze Options
+@cindex MicroBlaze Options
-One workaround is to insert cache barrier instructions before every memory
-access that might be speculatively executed and that might have side
-effects even if aborted. @option{-mr10k-cache-barrier=@var{setting}}
-controls GCC's implementation of this workaround. It assumes that
-aborted accesses to any byte in the following regions does not have
-side effects:
+@table @gcctabopt
-@enumerate
-@item
-the memory occupied by the current function's stack frame;
+@item -msoft-float
+@opindex msoft-float
+Use software emulation for floating point (default).
-@item
-the memory occupied by an incoming stack argument;
+@item -mhard-float
+@opindex mhard-float
+Use hardware floating-point instructions.
-@item
-the memory occupied by an object with a link-time-constant address.
-@end enumerate
+@item -mmemcpy
+@opindex mmemcpy
+Do not optimize block moves, use @code{memcpy}.
-It is the kernel's responsibility to ensure that speculative
-accesses to these regions are indeed safe.
+@item -mno-clearbss
+@opindex mno-clearbss
+This option is deprecated. Use @option{-fno-zero-initialized-in-bss} instead.
-If the input program contains a function declaration such as:
+@item -mcpu=@var{cpu-type}
+@opindex mcpu=
+Use features of, and schedule code for, the given CPU.
+Supported values are in the format @samp{v@var{X}.@var{YY}.@var{Z}},
+where @var{X} is a major version, @var{YY} is the minor version, and
+@var{Z} is compatibility code. Example values are @samp{v3.00.a},
+@samp{v4.00.b}, @samp{v5.00.a}, @samp{v5.00.b}, @samp{v5.00.b}, @samp{v6.00.a}.
-@smallexample
-void foo (void);
-@end smallexample
+@item -mxl-soft-mul
+@opindex mxl-soft-mul
+Use software multiply emulation (default).
-then the implementation of @code{foo} must allow @code{j foo} and
-@code{jal foo} to be executed speculatively. GCC honors this
-restriction for functions it compiles itself. It expects non-GCC
-functions (such as hand-written assembly code) to do the same.
+@item -mxl-soft-div
+@opindex mxl-soft-div
+Use software emulation for divides (default).
-The option has three forms:
+@item -mxl-barrel-shift
+@opindex mxl-barrel-shift
+Use the hardware barrel shifter.
-@table @gcctabopt
-@item -mr10k-cache-barrier=load-store
-Insert a cache barrier before a load or store that might be
-speculatively executed and that might have side effects even
-if aborted.
+@item -mxl-pattern-compare
+@opindex mxl-pattern-compare
+Use pattern compare instructions.
-@item -mr10k-cache-barrier=store
-Insert a cache barrier before a store that might be speculatively
-executed and that might have side effects even if aborted.
+@item -msmall-divides
+@opindex msmall-divides
+Use table lookup optimization for small signed integer divisions.
-@item -mr10k-cache-barrier=none
-Disable the insertion of cache barriers. This is the default setting.
-@end table
+@item -mxl-stack-check
+@opindex mxl-stack-check
+This option is deprecated. Use @option{-fstack-check} instead.
-@item -mflush-func=@var{func}
-@itemx -mno-flush-func
-@opindex mflush-func
-Specifies the function to call to flush the I and D caches, or to not
-call any such function. If called, the function must take the same
-arguments as the common @code{_flush_func}, that is, the address of the
-memory range for which the cache is being flushed, the size of the
-memory range, and the number 3 (to flush both caches). The default
-depends on the target GCC was configured for, but commonly is either
-@code{_flush_func} or @code{__cpu_flush}.
+@item -mxl-gp-opt
+@opindex mxl-gp-opt
+Use GP-relative @code{.sdata}/@code{.sbss} sections.
-@item mbranch-cost=@var{num}
-@opindex mbranch-cost
-Set the cost of branches to roughly @var{num} ``simple'' instructions.
-This cost is only a heuristic and is not guaranteed to produce
-consistent results across releases. A zero cost redundantly selects
-the default, which is based on the @option{-mtune} setting.
+@item -mxl-multiply-high
+@opindex mxl-multiply-high
+Use multiply high instructions for high part of 32x32 multiply.
-@item -mbranch-likely
-@itemx -mno-branch-likely
-@opindex mbranch-likely
-@opindex mno-branch-likely
-Enable or disable use of Branch Likely instructions, regardless of the
-default for the selected architecture. By default, Branch Likely
-instructions may be generated if they are supported by the selected
-architecture. An exception is for the MIPS32 and MIPS64 architectures
-and processors that implement those architectures; for those, Branch
-Likely instructions are not be generated by default because the MIPS32
-and MIPS64 architectures specifically deprecate their use.
+@item -mxl-float-convert
+@opindex mxl-float-convert
+Use hardware floating-point conversion instructions.
-@item -mcompact-branches=never
-@itemx -mcompact-branches=optimal
-@itemx -mcompact-branches=always
-@opindex mcompact-branches=never
-@opindex mcompact-branches=optimal
-@opindex mcompact-branches=always
-These options control which form of branches will be generated. The
-default is @option{-mcompact-branches=optimal}.
+@item -mxl-float-sqrt
+@opindex mxl-float-sqrt
+Use hardware floating-point square root instruction.
-The @option{-mcompact-branches=never} option ensures that compact branch
-instructions will never be generated.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a big-endian target.
-The @option{-mcompact-branches=always} option ensures that a compact
-branch instruction will be generated if available. If a compact branch
-instruction is not available, a delay slot form of the branch will be
-used instead.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a little-endian target.
-This option is supported from MIPS Release 6 onwards.
+@item -mxl-reorder
+@opindex mxl-reorder
+Use reorder instructions (swap and byte reversed load/store).
-The @option{-mcompact-branches=optimal} option will cause a delay slot
-branch to be used if one is available in the current ISA and the delay
-slot is successfully filled. If the delay slot is not filled, a compact
-branch will be chosen if one is available.
+@item -mxl-mode-@var{app-model}
+Select application model @var{app-model}. Valid models are
+@table @samp
+@item executable
+normal executable (default), uses startup code @file{crt0.o}.
-@item -mfp-exceptions
-@itemx -mno-fp-exceptions
-@opindex mfp-exceptions
-Specifies whether FP exceptions are enabled. This affects how
-FP instructions are scheduled for some processors.
-The default is that FP exceptions are
-enabled.
+@item xmdstub
+for use with Xilinx Microprocessor Debugger (XMD) based
+software intrusive debug agent called xmdstub. This uses startup file
+@file{crt1.o} and sets the start address of the program to 0x800.
-For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
-64-bit code, then we can use both FP pipes. Otherwise, we can only use one
-FP pipe.
+@item bootstrap
+for applications that are loaded using a bootloader.
+This model uses startup file @file{crt2.o} which does not contain a processor
+reset vector handler. This is suitable for transferring control on a
+processor reset to the bootloader rather than the application.
-@item -mvr4130-align
-@itemx -mno-vr4130-align
-@opindex mvr4130-align
-The VR4130 pipeline is two-way superscalar, but can only issue two
-instructions together if the first one is 8-byte aligned. When this
-option is enabled, GCC aligns pairs of instructions that it
-thinks should execute in parallel.
+@item novectors
+for applications that do not require any of the
+MicroBlaze vectors. This option may be useful for applications running
+within a monitoring application. This model uses @file{crt3.o} as a startup file.
+@end table
-This option only has an effect when optimizing for the VR4130.
-It normally makes code faster, but at the expense of making it bigger.
-It is enabled by default at optimization level @option{-O3}.
+Option @option{-xl-mode-@var{app-model}} is a deprecated alias for
+@option{-mxl-mode-@var{app-model}}.
-@item -msynci
-@itemx -mno-synci
-@opindex msynci
-Enable (disable) generation of @code{synci} instructions on
-architectures that support it. The @code{synci} instructions (if
-enabled) are generated when @code{__builtin___clear_cache} is
-compiled.
+@end table
-This option defaults to @option{-mno-synci}, but the default can be
-overridden by configuring GCC with @option{--with-synci}.
+@node MIPS Options
+@subsection MIPS Options
+@cindex MIPS options
-When compiling code for single processor systems, it is generally safe
-to use @code{synci}. However, on many multi-core (SMP) systems, it
-does not invalidate the instruction caches on all cores and may lead
-to undefined behavior.
+@table @gcctabopt
-@item -mrelax-pic-calls
-@itemx -mno-relax-pic-calls
-@opindex mrelax-pic-calls
-Try to turn PIC calls that are normally dispatched via register
-@code{$25} into direct calls. This is only possible if the linker can
-resolve the destination at link-time and if the destination is within
-range for a direct call.
+@item -EB
+@opindex EB
+Generate big-endian code.
-@option{-mrelax-pic-calls} is the default if GCC was configured to use
-an assembler and a linker that support the @code{.reloc} assembly
-directive and @option{-mexplicit-relocs} is in effect. With
-@option{-mno-explicit-relocs}, this optimization can be performed by the
-assembler and the linker alone without help from the compiler.
+@item -EL
+@opindex EL
+Generate little-endian code. This is the default for @samp{mips*el-*-*}
+configurations.
-@item -mmcount-ra-address
-@itemx -mno-mcount-ra-address
-@opindex mmcount-ra-address
-@opindex mno-mcount-ra-address
-Emit (do not emit) code that allows @code{_mcount} to modify the
-calling function's return address. When enabled, this option extends
-the usual @code{_mcount} interface with a new @var{ra-address}
-parameter, which has type @code{intptr_t *} and is passed in register
-@code{$12}. @code{_mcount} can then modify the return address by
-doing both of the following:
-@itemize
-@item
-Returning the new address in register @code{$31}.
-@item
-Storing the new address in @code{*@var{ra-address}},
-if @var{ra-address} is nonnull.
-@end itemize
+@item -march=@var{arch}
+@opindex march
+Generate code that runs on @var{arch}, which can be the name of a
+generic MIPS ISA, or the name of a particular processor.
+The ISA names are:
+@samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
+@samp{mips32}, @samp{mips32r2}, @samp{mips32r3}, @samp{mips32r5},
+@samp{mips32r6}, @samp{mips64}, @samp{mips64r2}, @samp{mips64r3},
+@samp{mips64r5} and @samp{mips64r6}.
+The processor names are:
+@samp{4kc}, @samp{4km}, @samp{4kp}, @samp{4ksc},
+@samp{4kec}, @samp{4kem}, @samp{4kep}, @samp{4ksd},
+@samp{5kc}, @samp{5kf},
+@samp{20kc},
+@samp{24kc}, @samp{24kf2_1}, @samp{24kf1_1},
+@samp{24kec}, @samp{24kef2_1}, @samp{24kef1_1},
+@samp{34kc}, @samp{34kf2_1}, @samp{34kf1_1}, @samp{34kn},
+@samp{74kc}, @samp{74kf2_1}, @samp{74kf1_1}, @samp{74kf3_2},
+@samp{1004kc}, @samp{1004kf2_1}, @samp{1004kf1_1},
+@samp{i6400},
+@samp{interaptiv},
+@samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a},
+@samp{m4k},
+@samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec},
+@samp{m5100}, @samp{m5101},
+@samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3},
+@samp{orion},
+@samp{p5600},
+@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
+@samp{r4600}, @samp{r4650}, @samp{r4700}, @samp{r6000}, @samp{r8000},
+@samp{rm7000}, @samp{rm9000},
+@samp{r10000}, @samp{r12000}, @samp{r14000}, @samp{r16000},
+@samp{sb1},
+@samp{sr71000},
+@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
+@samp{vr5000}, @samp{vr5400}, @samp{vr5500},
+@samp{xlr} and @samp{xlp}.
+The special value @samp{from-abi} selects the
+most compatible architecture for the selected ABI (that is,
+@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
-The default is @option{-mno-mcount-ra-address}.
+The native Linux/GNU toolchain also supports the value @samp{native},
+which selects the best architecture option for the host processor.
+@option{-march=native} has no effect if GCC does not recognize
+the processor.
-@item -mframe-header-opt
-@itemx -mno-frame-header-opt
-@opindex mframe-header-opt
-Enable (disable) frame header optimization in the o32 ABI. When using the
-o32 ABI, calling functions will allocate 16 bytes on the stack for the called
-function to write out register arguments. When enabled, this optimization
-will suppress the allocation of the frame header if it can be determined that
-it is unused.
+In processor names, a final @samp{000} can be abbreviated as @samp{k}
+(for example, @option{-march=r2k}). Prefixes are optional, and
+@samp{vr} may be written @samp{r}.
-This optimization is off by default at all optimization levels.
+Names of the form @samp{@var{n}f2_1} refer to processors with
+FPUs clocked at half the rate of the core, names of the form
+@samp{@var{n}f1_1} refer to processors with FPUs clocked at the same
+rate as the core, and names of the form @samp{@var{n}f3_2} refer to
+processors with FPUs clocked a ratio of 3:2 with respect to the core.
+For compatibility reasons, @samp{@var{n}f} is accepted as a synonym
+for @samp{@var{n}f2_1} while @samp{@var{n}x} and @samp{@var{b}fx} are
+accepted as synonyms for @samp{@var{n}f1_1}.
-@end table
+GCC defines two macros based on the value of this option. The first
+is @code{_MIPS_ARCH}, which gives the name of target architecture, as
+a string. The second has the form @code{_MIPS_ARCH_@var{foo}},
+where @var{foo} is the capitalized value of @code{_MIPS_ARCH}@.
+For example, @option{-march=r2000} sets @code{_MIPS_ARCH}
+to @code{"r2000"} and defines the macro @code{_MIPS_ARCH_R2000}.
-@node MMIX Options
-@subsection MMIX Options
-@cindex MMIX Options
+Note that the @code{_MIPS_ARCH} macro uses the processor names given
+above. In other words, it has the full prefix and does not
+abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
+the macro names the resolved architecture (either @code{"mips1"} or
+@code{"mips3"}). It names the default architecture when no
+@option{-march} option is given.
-These options are defined for the MMIX:
+@item -mtune=@var{arch}
+@opindex mtune
+Optimize for @var{arch}. Among other things, this option controls
+the way instructions are scheduled, and the perceived cost of arithmetic
+operations. The list of @var{arch} values is the same as for
+@option{-march}.
-@table @gcctabopt
-@item -mlibfuncs
-@itemx -mno-libfuncs
-@opindex mlibfuncs
-@opindex mno-libfuncs
-Specify that intrinsic library functions are being compiled, passing all
-values in registers, no matter the size.
+When this option is not used, GCC optimizes for the processor
+specified by @option{-march}. By using @option{-march} and
+@option{-mtune} together, it is possible to generate code that
+runs on a family of processors, but optimize the code for one
+particular member of that family.
-@item -mepsilon
-@itemx -mno-epsilon
-@opindex mepsilon
-@opindex mno-epsilon
-Generate floating-point comparison instructions that compare with respect
-to the @code{rE} epsilon register.
+@option{-mtune} defines the macros @code{_MIPS_TUNE} and
+@code{_MIPS_TUNE_@var{foo}}, which work in the same way as the
+@option{-march} ones described above.
-@item -mabi=mmixware
-@itemx -mabi=gnu
-@opindex mabi=mmixware
-@opindex mabi=gnu
-Generate code that passes function parameters and return values that (in
-the called function) are seen as registers @code{$0} and up, as opposed to
-the GNU ABI which uses global registers @code{$231} and up.
+@item -mips1
+@opindex mips1
+Equivalent to @option{-march=mips1}.
-@item -mzero-extend
-@itemx -mno-zero-extend
-@opindex mzero-extend
-@opindex mno-zero-extend
-When reading data from memory in sizes shorter than 64 bits, use (do not
-use) zero-extending load instructions by default, rather than
-sign-extending ones.
+@item -mips2
+@opindex mips2
+Equivalent to @option{-march=mips2}.
-@item -mknuthdiv
-@itemx -mno-knuthdiv
-@opindex mknuthdiv
-@opindex mno-knuthdiv
-Make the result of a division yielding a remainder have the same sign as
-the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
-remainder follows the sign of the dividend. Both methods are
-arithmetically valid, the latter being almost exclusively used.
+@item -mips3
+@opindex mips3
+Equivalent to @option{-march=mips3}.
-@item -mtoplevel-symbols
-@itemx -mno-toplevel-symbols
-@opindex mtoplevel-symbols
-@opindex mno-toplevel-symbols
-Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
-code can be used with the @code{PREFIX} assembly directive.
+@item -mips4
+@opindex mips4
+Equivalent to @option{-march=mips4}.
-@item -melf
-@opindex melf
-Generate an executable in the ELF format, rather than the default
-@samp{mmo} format used by the @command{mmix} simulator.
+@item -mips32
+@opindex mips32
+Equivalent to @option{-march=mips32}.
-@item -mbranch-predict
-@itemx -mno-branch-predict
-@opindex mbranch-predict
-@opindex mno-branch-predict
-Use (do not use) the probable-branch instructions, when static branch
-prediction indicates a probable branch.
+@item -mips32r3
+@opindex mips32r3
+Equivalent to @option{-march=mips32r3}.
-@item -mbase-addresses
-@itemx -mno-base-addresses
-@opindex mbase-addresses
-@opindex mno-base-addresses
-Generate (do not generate) code that uses @emph{base addresses}. Using a
-base address automatically generates a request (handled by the assembler
-and the linker) for a constant to be set up in a global register. The
-register is used for one or more base address requests within the range 0
-to 255 from the value held in the register. The generally leads to short
-and fast code, but the number of different data items that can be
-addressed is limited. This means that a program that uses lots of static
-data may require @option{-mno-base-addresses}.
+@item -mips32r5
+@opindex mips32r5
+Equivalent to @option{-march=mips32r5}.
-@item -msingle-exit
-@itemx -mno-single-exit
-@opindex msingle-exit
-@opindex mno-single-exit
-Force (do not force) generated code to have a single exit point in each
-function.
-@end table
+@item -mips32r6
+@opindex mips32r6
+Equivalent to @option{-march=mips32r6}.
-@node MN10300 Options
-@subsection MN10300 Options
-@cindex MN10300 options
+@item -mips64
+@opindex mips64
+Equivalent to @option{-march=mips64}.
-These @option{-m} options are defined for Matsushita MN10300 architectures:
+@item -mips64r2
+@opindex mips64r2
+Equivalent to @option{-march=mips64r2}.
-@table @gcctabopt
-@item -mmult-bug
-@opindex mmult-bug
-Generate code to avoid bugs in the multiply instructions for the MN10300
-processors. This is the default.
+@item -mips64r3
+@opindex mips64r3
+Equivalent to @option{-march=mips64r3}.
-@item -mno-mult-bug
-@opindex mno-mult-bug
-Do not generate code to avoid bugs in the multiply instructions for the
-MN10300 processors.
+@item -mips64r5
+@opindex mips64r5
+Equivalent to @option{-march=mips64r5}.
-@item -mam33
-@opindex mam33
-Generate code using features specific to the AM33 processor.
+@item -mips64r6
+@opindex mips64r6
+Equivalent to @option{-march=mips64r6}.
-@item -mno-am33
-@opindex mno-am33
-Do not generate code using features specific to the AM33 processor. This
-is the default.
+@item -mips16
+@itemx -mno-mips16
+@opindex mips16
+@opindex mno-mips16
+Generate (do not generate) MIPS16 code. If GCC is targeting a
+MIPS32 or MIPS64 architecture, it makes use of the MIPS16e ASE@.
-@item -mam33-2
-@opindex mam33-2
-Generate code using features specific to the AM33/2.0 processor.
+MIPS16 code generation can also be controlled on a per-function basis
+by means of @code{mips16} and @code{nomips16} attributes.
+@xref{Function Attributes}, for more information.
-@item -mam34
-@opindex mam34
-Generate code using features specific to the AM34 processor.
+@item -mflip-mips16
+@opindex mflip-mips16
+Generate MIPS16 code on alternating functions. This option is provided
+for regression testing of mixed MIPS16/non-MIPS16 code generation, and is
+not intended for ordinary use in compiling user code.
-@item -mtune=@var{cpu-type}
-@opindex mtune
-Use the timing characteristics of the indicated CPU type when
-scheduling instructions. This does not change the targeted processor
-type. The CPU type must be one of @samp{mn10300}, @samp{am33},
-@samp{am33-2} or @samp{am34}.
-
-@item -mreturn-pointer-on-d0
-@opindex mreturn-pointer-on-d0
-When generating a function that returns a pointer, return the pointer
-in both @code{a0} and @code{d0}. Otherwise, the pointer is returned
-only in @code{a0}, and attempts to call such functions without a prototype
-result in errors. Note that this option is on by default; use
-@option{-mno-return-pointer-on-d0} to disable it.
-
-@item -mno-crt0
-@opindex mno-crt0
-Do not link in the C run-time initialization object file.
+@item -minterlink-compressed
+@item -mno-interlink-compressed
+@opindex minterlink-compressed
+@opindex mno-interlink-compressed
+Require (do not require) that code using the standard (uncompressed) MIPS ISA
+be link-compatible with MIPS16 and microMIPS code, and vice versa.
-@item -mrelax
-@opindex mrelax
-Indicate to the linker that it should perform a relaxation optimization pass
-to shorten branches, calls and absolute memory addresses. This option only
-has an effect when used on the command line for the final link step.
+For example, code using the standard ISA encoding cannot jump directly
+to MIPS16 or microMIPS code; it must either use a call or an indirect jump.
+@option{-minterlink-compressed} therefore disables direct jumps unless GCC
+knows that the target of the jump is not compressed.
-This option makes symbolic debugging impossible.
+@item -minterlink-mips16
+@itemx -mno-interlink-mips16
+@opindex minterlink-mips16
+@opindex mno-interlink-mips16
+Aliases of @option{-minterlink-compressed} and
+@option{-mno-interlink-compressed}. These options predate the microMIPS ASE
+and are retained for backwards compatibility.
-@item -mliw
-@opindex mliw
-Allow the compiler to generate @emph{Long Instruction Word}
-instructions if the target is the @samp{AM33} or later. This is the
-default. This option defines the preprocessor macro @code{__LIW__}.
+@item -mabi=32
+@itemx -mabi=o64
+@itemx -mabi=n32
+@itemx -mabi=64
+@itemx -mabi=eabi
+@opindex mabi=32
+@opindex mabi=o64
+@opindex mabi=n32
+@opindex mabi=64
+@opindex mabi=eabi
+Generate code for the given ABI@.
-@item -mnoliw
-@opindex mnoliw
-Do not allow the compiler to generate @emph{Long Instruction Word}
-instructions. This option defines the preprocessor macro
-@code{__NO_LIW__}.
+Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
+generates 64-bit code when you select a 64-bit architecture, but you
+can use @option{-mgp32} to get 32-bit code instead.
-@item -msetlb
-@opindex msetlb
-Allow the compiler to generate the @emph{SETLB} and @emph{Lcc}
-instructions if the target is the @samp{AM33} or later. This is the
-default. This option defines the preprocessor macro @code{__SETLB__}.
+For information about the O64 ABI, see
+@uref{http://gcc.gnu.org/@/projects/@/mipso64-abi.html}.
-@item -mnosetlb
-@opindex mnosetlb
-Do not allow the compiler to generate @emph{SETLB} or @emph{Lcc}
-instructions. This option defines the preprocessor macro
-@code{__NO_SETLB__}.
+GCC supports a variant of the o32 ABI in which floating-point registers
+are 64 rather than 32 bits wide. You can select this combination with
+@option{-mabi=32} @option{-mfp64}. This ABI relies on the @code{mthc1}
+and @code{mfhc1} instructions and is therefore only supported for
+MIPS32R2, MIPS32R3 and MIPS32R5 processors.
-@end table
+The register assignments for arguments and return values remain the
+same, but each scalar value is passed in a single 64-bit register
+rather than a pair of 32-bit registers. For example, scalar
+floating-point values are returned in @samp{$f0} only, not a
+@samp{$f0}/@samp{$f1} pair. The set of call-saved registers also
+remains the same in that the even-numbered double-precision registers
+are saved.
-@node Moxie Options
-@subsection Moxie Options
-@cindex Moxie Options
+Two additional variants of the o32 ABI are supported to enable
+a transition from 32-bit to 64-bit registers. These are FPXX
+(@option{-mfpxx}) and FP64A (@option{-mfp64} @option{-mno-odd-spreg}).
+The FPXX extension mandates that all code must execute correctly
+when run using 32-bit or 64-bit registers. The code can be interlinked
+with either FP32 or FP64, but not both.
+The FP64A extension is similar to the FP64 extension but forbids the
+use of odd-numbered single-precision registers. This can be used
+in conjunction with the @code{FRE} mode of FPUs in MIPS32R5
+processors and allows both FP32 and FP64A code to interlink and
+run in the same process without changing FPU modes.
-@table @gcctabopt
+@item -mabicalls
+@itemx -mno-abicalls
+@opindex mabicalls
+@opindex mno-abicalls
+Generate (do not generate) code that is suitable for SVR4-style
+dynamic objects. @option{-mabicalls} is the default for SVR4-based
+systems.
-@item -meb
-@opindex meb
-Generate big-endian code. This is the default for @samp{moxie-*-*}
-configurations.
+@item -mshared
+@itemx -mno-shared
+Generate (do not generate) code that is fully position-independent,
+and that can therefore be linked into shared libraries. This option
+only affects @option{-mabicalls}.
-@item -mel
-@opindex mel
-Generate little-endian code.
+All @option{-mabicalls} code has traditionally been position-independent,
+regardless of options like @option{-fPIC} and @option{-fpic}. However,
+as an extension, the GNU toolchain allows executables to use absolute
+accesses for locally-binding symbols. It can also use shorter GP
+initialization sequences and generate direct calls to locally-defined
+functions. This mode is selected by @option{-mno-shared}.
-@item -mmul.x
-@opindex mmul.x
-Generate mul.x and umul.x instructions. This is the default for
-@samp{moxiebox-*-*} configurations.
+@option{-mno-shared} depends on binutils 2.16 or higher and generates
+objects that can only be linked by the GNU linker. However, the option
+does not affect the ABI of the final executable; it only affects the ABI
+of relocatable objects. Using @option{-mno-shared} generally makes
+executables both smaller and quicker.
-@item -mno-crt0
-@opindex mno-crt0
-Do not link in the C run-time initialization object file.
+@option{-mshared} is the default.
-@end table
+@item -mplt
+@itemx -mno-plt
+@opindex mplt
+@opindex mno-plt
+Assume (do not assume) that the static and dynamic linkers
+support PLTs and copy relocations. This option only affects
+@option{-mno-shared -mabicalls}. For the n64 ABI, this option
+has no effect without @option{-msym32}.
-@node MSP430 Options
-@subsection MSP430 Options
-@cindex MSP430 Options
+You can make @option{-mplt} the default by configuring
+GCC with @option{--with-mips-plt}. The default is
+@option{-mno-plt} otherwise.
-These options are defined for the MSP430:
+@item -mxgot
+@itemx -mno-xgot
+@opindex mxgot
+@opindex mno-xgot
+Lift (do not lift) the usual restrictions on the size of the global
+offset table.
-@table @gcctabopt
+GCC normally uses a single instruction to load values from the GOT@.
+While this is relatively efficient, it only works if the GOT
+is smaller than about 64k. Anything larger causes the linker
+to report an error such as:
-@item -masm-hex
-@opindex masm-hex
-Force assembly output to always use hex constants. Normally such
-constants are signed decimals, but this option is available for
-testsuite and/or aesthetic purposes.
+@cindex relocation truncated to fit (MIPS)
+@smallexample
+relocation truncated to fit: R_MIPS_GOT16 foobar
+@end smallexample
-@item -mmcu=
-@opindex mmcu=
-Select the MCU to target. This is used to create a C preprocessor
-symbol based upon the MCU name, converted to upper case and pre- and
-post-fixed with @samp{__}. This in turn is used by the
-@file{msp430.h} header file to select an MCU-specific supplementary
-header file.
+If this happens, you should recompile your code with @option{-mxgot}.
+This works with very large GOTs, although the code is also
+less efficient, since it takes three instructions to fetch the
+value of a global symbol.
-The option also sets the ISA to use. If the MCU name is one that is
-known to only support the 430 ISA then that is selected, otherwise the
-430X ISA is selected. A generic MCU name of @samp{msp430} can also be
-used to select the 430 ISA. Similarly the generic @samp{msp430x} MCU
-name selects the 430X ISA.
+Note that some linkers can create multiple GOTs. If you have such a
+linker, you should only need to use @option{-mxgot} when a single object
+file accesses more than 64k's worth of GOT entries. Very few do.
-In addition an MCU-specific linker script is added to the linker
-command line. The script's name is the name of the MCU with
-@file{.ld} appended. Thus specifying @option{-mmcu=xxx} on the @command{gcc}
-command line defines the C preprocessor symbol @code{__XXX__} and
-cause the linker to search for a script called @file{xxx.ld}.
+These options have no effect unless GCC is generating position
+independent code.
-This option is also passed on to the assembler.
+@item -mgp32
+@opindex mgp32
+Assume that general-purpose registers are 32 bits wide.
-@item -mwarn-mcu
-@itemx -mno-warn-mcu
-@opindex mwarn-mcu
-@opindex mno-warn-mcu
-This option enables or disables warnings about conflicts between the
-MCU name specified by the @option{-mmcu} option and the ISA set by the
-@option{-mcpu} option and/or the hardware multiply support set by the
-@option{-mhwmult} option. It also toggles warnings about unrecognised
-MCU names. This option is on by default.
+@item -mgp64
+@opindex mgp64
+Assume that general-purpose registers are 64 bits wide.
-@item -mcpu=
-@opindex mcpu=
-Specifies the ISA to use. Accepted values are @samp{msp430},
-@samp{msp430x} and @samp{msp430xv2}. This option is deprecated. The
-@option{-mmcu=} option should be used to select the ISA.
+@item -mfp32
+@opindex mfp32
+Assume that floating-point registers are 32 bits wide.
-@item -msim
-@opindex msim
-Link to the simulator runtime libraries and linker script. Overrides
-any scripts that would be selected by the @option{-mmcu=} option.
+@item -mfp64
+@opindex mfp64
+Assume that floating-point registers are 64 bits wide.
-@item -mlarge
-@opindex mlarge
-Use large-model addressing (20-bit pointers, 32-bit @code{size_t}).
+@item -mfpxx
+@opindex mfpxx
+Do not assume the width of floating-point registers.
-@item -msmall
-@opindex msmall
-Use small-model addressing (16-bit pointers, 16-bit @code{size_t}).
+@item -mhard-float
+@opindex mhard-float
+Use floating-point coprocessor instructions.
-@item -mrelax
-@opindex mrelax
-This option is passed to the assembler and linker, and allows the
-linker to perform certain optimizations that cannot be done until
-the final link.
+@item -msoft-float
+@opindex msoft-float
+Do not use floating-point coprocessor instructions. Implement
+floating-point calculations using library calls instead.
-@item mhwmult=
-@opindex mhwmult=
-Describes the type of hardware multiply supported by the target.
-Accepted values are @samp{none} for no hardware multiply, @samp{16bit}
-for the original 16-bit-only multiply supported by early MCUs.
-@samp{32bit} for the 16/32-bit multiply supported by later MCUs and
-@samp{f5series} for the 16/32-bit multiply supported by F5-series MCUs.
-A value of @samp{auto} can also be given. This tells GCC to deduce
-the hardware multiply support based upon the MCU name provided by the
-@option{-mmcu} option. If no @option{-mmcu} option is specified or if
-the MCU name is not recognised then no hardware multiply support is
-assumed. @code{auto} is the default setting.
+@item -mno-float
+@opindex mno-float
+Equivalent to @option{-msoft-float}, but additionally asserts that the
+program being compiled does not perform any floating-point operations.
+This option is presently supported only by some bare-metal MIPS
+configurations, where it may select a special set of libraries
+that lack all floating-point support (including, for example, the
+floating-point @code{printf} formats).
+If code compiled with @option{-mno-float} accidentally contains
+floating-point operations, it is likely to suffer a link-time
+or run-time failure.
-Hardware multiplies are normally performed by calling a library
-routine. This saves space in the generated code. When compiling at
-@option{-O3} or higher however the hardware multiplier is invoked
-inline. This makes for bigger, but faster code.
+@item -msingle-float
+@opindex msingle-float
+Assume that the floating-point coprocessor only supports single-precision
+operations.
-The hardware multiply routines disable interrupts whilst running and
-restore the previous interrupt state when they finish. This makes
-them safe to use inside interrupt handlers as well as in normal code.
+@item -mdouble-float
+@opindex mdouble-float
+Assume that the floating-point coprocessor supports double-precision
+operations. This is the default.
-@item -minrt
-@opindex minrt
-Enable the use of a minimum runtime environment - no static
-initializers or constructors. This is intended for memory-constrained
-devices. The compiler includes special symbols in some objects
-that tell the linker and runtime which code fragments are required.
+@item -modd-spreg
+@itemx -mno-odd-spreg
+@opindex modd-spreg
+@opindex mno-odd-spreg
+Enable the use of odd-numbered single-precision floating-point registers
+for the o32 ABI. This is the default for processors that are known to
+support these registers. When using the o32 FPXX ABI, @option{-mno-odd-spreg}
+is set by default.
-@item -mcode-region=
-@itemx -mdata-region=
-@opindex mcode-region
-@opindex mdata-region
-These options tell the compiler where to place functions and data that
-do not have one of the @code{lower}, @code{upper}, @code{either} or
-@code{section} attributes. Possible values are @code{lower},
-@code{upper}, @code{either} or @code{any}. The first three behave
-like the corresponding attribute. The fourth possible value -
-@code{any} - is the default. It leaves placement entirely up to the
-linker script and how it assigns the standard sections (.text, .data
-etc) to the memory regions.
+@item -mabs=2008
+@itemx -mabs=legacy
+@opindex mabs=2008
+@opindex mabs=legacy
+These options control the treatment of the special not-a-number (NaN)
+IEEE 754 floating-point data with the @code{abs.@i{fmt}} and
+@code{neg.@i{fmt}} machine instructions.
-@item -msilicon-errata=
-@opindex msilicon-errata
-This option passes on a request to assembler to enable the fixes for
-the named silicon errata.
+By default or when @option{-mabs=legacy} is used the legacy
+treatment is selected. In this case these instructions are considered
+arithmetic and avoided where correct operation is required and the
+input operand might be a NaN. A longer sequence of instructions that
+manipulate the sign bit of floating-point datum manually is used
+instead unless the @option{-ffinite-math-only} option has also been
+specified.
-@item -msilicon-errata-warn=
-@opindex msilicon-errata-warn
-This option passes on a request to the assembler to enable warning
-messages when a silicon errata might need to be applied.
+The @option{-mabs=2008} option selects the IEEE 754-2008 treatment. In
+this case these instructions are considered non-arithmetic and therefore
+operating correctly in all cases, including in particular where the
+input operand is a NaN. These instructions are therefore always used
+for the respective operations.
-@end table
+@item -mnan=2008
+@itemx -mnan=legacy
+@opindex mnan=2008
+@opindex mnan=legacy
+These options control the encoding of the special not-a-number (NaN)
+IEEE 754 floating-point data.
-@node NDS32 Options
-@subsection NDS32 Options
-@cindex NDS32 Options
+The @option{-mnan=legacy} option selects the legacy encoding. In this
+case quiet NaNs (qNaNs) are denoted by the first bit of their trailing
+significand field being 0, whereas signalling NaNs (sNaNs) are denoted
+by the first bit of their trailing significand field being 1.
-These options are defined for NDS32 implementations:
+The @option{-mnan=2008} option selects the IEEE 754-2008 encoding. In
+this case qNaNs are denoted by the first bit of their trailing
+significand field being 1, whereas sNaNs are denoted by the first bit of
+their trailing significand field being 0.
-@table @gcctabopt
+The default is @option{-mnan=legacy} unless GCC has been configured with
+@option{--with-nan=2008}.
-@item -mbig-endian
-@opindex mbig-endian
-Generate code in big-endian mode.
+@item -mllsc
+@itemx -mno-llsc
+@opindex mllsc
+@opindex mno-llsc
+Use (do not use) @samp{ll}, @samp{sc}, and @samp{sync} instructions to
+implement atomic memory built-in functions. When neither option is
+specified, GCC uses the instructions if the target architecture
+supports them.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code in little-endian mode.
+@option{-mllsc} is useful if the runtime environment can emulate the
+instructions and @option{-mno-llsc} can be useful when compiling for
+nonstandard ISAs. You can make either option the default by
+configuring GCC with @option{--with-llsc} and @option{--without-llsc}
+respectively. @option{--with-llsc} is the default for some
+configurations; see the installation documentation for details.
-@item -mreduced-regs
-@opindex mreduced-regs
-Use reduced-set registers for register allocation.
+@item -mdsp
+@itemx -mno-dsp
+@opindex mdsp
+@opindex mno-dsp
+Use (do not use) revision 1 of the MIPS DSP ASE@.
+@xref{MIPS DSP Built-in Functions}. This option defines the
+preprocessor macro @code{__mips_dsp}. It also defines
+@code{__mips_dsp_rev} to 1.
-@item -mfull-regs
-@opindex mfull-regs
-Use full-set registers for register allocation.
+@item -mdspr2
+@itemx -mno-dspr2
+@opindex mdspr2
+@opindex mno-dspr2
+Use (do not use) revision 2 of the MIPS DSP ASE@.
+@xref{MIPS DSP Built-in Functions}. This option defines the
+preprocessor macros @code{__mips_dsp} and @code{__mips_dspr2}.
+It also defines @code{__mips_dsp_rev} to 2.
-@item -mcmov
-@opindex mcmov
-Generate conditional move instructions.
+@item -msmartmips
+@itemx -mno-smartmips
+@opindex msmartmips
+@opindex mno-smartmips
+Use (do not use) the MIPS SmartMIPS ASE.
-@item -mno-cmov
-@opindex mno-cmov
-Do not generate conditional move instructions.
+@item -mpaired-single
+@itemx -mno-paired-single
+@opindex mpaired-single
+@opindex mno-paired-single
+Use (do not use) paired-single floating-point instructions.
+@xref{MIPS Paired-Single Support}. This option requires
+hardware floating-point support to be enabled.
-@item -mperf-ext
-@opindex mperf-ext
-Generate performance extension instructions.
+@item -mdmx
+@itemx -mno-mdmx
+@opindex mdmx
+@opindex mno-mdmx
+Use (do not use) MIPS Digital Media Extension instructions.
+This option can only be used when generating 64-bit code and requires
+hardware floating-point support to be enabled.
-@item -mno-perf-ext
-@opindex mno-perf-ext
-Do not generate performance extension instructions.
+@item -mips3d
+@itemx -mno-mips3d
+@opindex mips3d
+@opindex mno-mips3d
+Use (do not use) the MIPS-3D ASE@. @xref{MIPS-3D Built-in Functions}.
+The option @option{-mips3d} implies @option{-mpaired-single}.
-@item -mv3push
-@opindex mv3push
-Generate v3 push25/pop25 instructions.
+@item -mmicromips
+@itemx -mno-micromips
+@opindex mmicromips
+@opindex mno-mmicromips
+Generate (do not generate) microMIPS code.
-@item -mno-v3push
-@opindex mno-v3push
-Do not generate v3 push25/pop25 instructions.
+MicroMIPS code generation can also be controlled on a per-function basis
+by means of @code{micromips} and @code{nomicromips} attributes.
+@xref{Function Attributes}, for more information.
-@item -m16-bit
-@opindex m16-bit
-Generate 16-bit instructions.
+@item -mmt
+@itemx -mno-mt
+@opindex mmt
+@opindex mno-mt
+Use (do not use) MT Multithreading instructions.
-@item -mno-16-bit
-@opindex mno-16-bit
-Do not generate 16-bit instructions.
+@item -mmcu
+@itemx -mno-mcu
+@opindex mmcu
+@opindex mno-mcu
+Use (do not use) the MIPS MCU ASE instructions.
-@item -misr-vector-size=@var{num}
-@opindex misr-vector-size
-Specify the size of each interrupt vector, which must be 4 or 16.
+@item -meva
+@itemx -mno-eva
+@opindex meva
+@opindex mno-eva
+Use (do not use) the MIPS Enhanced Virtual Addressing instructions.
-@item -mcache-block-size=@var{num}
-@opindex mcache-block-size
-Specify the size of each cache block,
-which must be a power of 2 between 4 and 512.
+@item -mvirt
+@itemx -mno-virt
+@opindex mvirt
+@opindex mno-virt
+Use (do not use) the MIPS Virtualization Application Specific instructions.
-@item -march=@var{arch}
-@opindex march
-Specify the name of the target architecture.
+@item -mxpa
+@itemx -mno-xpa
+@opindex mxpa
+@opindex mno-xpa
+Use (do not use) the MIPS eXtended Physical Address (XPA) instructions.
-@item -mcmodel=@var{code-model}
-@opindex mcmodel
-Set the code model to one of
-@table @asis
-@item @samp{small}
-All the data and read-only data segments must be within 512KB addressing space.
-The text segment must be within 16MB addressing space.
-@item @samp{medium}
-The data segment must be within 512KB while the read-only data segment can be
-within 4GB addressing space. The text segment should be still within 16MB
-addressing space.
-@item @samp{large}
-All the text and data segments can be within 4GB addressing space.
-@end table
+@item -mlong64
+@opindex mlong64
+Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
+an explanation of the default and the way that the pointer size is
+determined.
-@item -mctor-dtor
-@opindex mctor-dtor
-Enable constructor/destructor feature.
+@item -mlong32
+@opindex mlong32
+Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
-@item -mrelax
-@opindex mrelax
-Guide linker to relax instructions.
+The default size of @code{int}s, @code{long}s and pointers depends on
+the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
+uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
+32-bit @code{long}s. Pointers are the same size as @code{long}s,
+or the same size as integer registers, whichever is smaller.
-@end table
+@item -msym32
+@itemx -mno-sym32
+@opindex msym32
+@opindex mno-sym32
+Assume (do not assume) that all symbols have 32-bit values, regardless
+of the selected ABI@. This option is useful in combination with
+@option{-mabi=64} and @option{-mno-abicalls} because it allows GCC
+to generate shorter and faster references to symbolic addresses.
-@node Nios II Options
-@subsection Nios II Options
-@cindex Nios II options
-@cindex Altera Nios II options
+@item -G @var{num}
+@opindex G
+Put definitions of externally-visible data in a small data section
+if that data is no bigger than @var{num} bytes. GCC can then generate
+more efficient accesses to the data; see @option{-mgpopt} for details.
-These are the options defined for the Altera Nios II processor.
+The default @option{-G} option depends on the configuration.
-@table @gcctabopt
+@item -mlocal-sdata
+@itemx -mno-local-sdata
+@opindex mlocal-sdata
+@opindex mno-local-sdata
+Extend (do not extend) the @option{-G} behavior to local data too,
+such as to static variables in C@. @option{-mlocal-sdata} is the
+default for all configurations.
-@item -G @var{num}
-@opindex G
-@cindex smaller data references
-Put global and static objects less than or equal to @var{num} bytes
-into the small data or BSS sections instead of the normal data or BSS
-sections. The default value of @var{num} is 8.
+If the linker complains that an application is using too much small data,
+you might want to try rebuilding the less performance-critical parts with
+@option{-mno-local-sdata}. You might also want to build large
+libraries with @option{-mno-local-sdata}, so that the libraries leave
+more room for the main program.
+
+@item -mextern-sdata
+@itemx -mno-extern-sdata
+@opindex mextern-sdata
+@opindex mno-extern-sdata
+Assume (do not assume) that externally-defined data is in
+a small data section if the size of that data is within the @option{-G} limit.
+@option{-mextern-sdata} is the default for all configurations.
+
+If you compile a module @var{Mod} with @option{-mextern-sdata} @option{-G
+@var{num}} @option{-mgpopt}, and @var{Mod} references a variable @var{Var}
+that is no bigger than @var{num} bytes, you must make sure that @var{Var}
+is placed in a small data section. If @var{Var} is defined by another
+module, you must either compile that module with a high-enough
+@option{-G} setting or attach a @code{section} attribute to @var{Var}'s
+definition. If @var{Var} is common, you must link the application
+with a high-enough @option{-G} setting.
+
+The easiest way of satisfying these restrictions is to compile
+and link every module with the same @option{-G} option. However,
+you may wish to build a library that supports several different
+small data limits. You can do this by compiling the library with
+the highest supported @option{-G} setting and additionally using
+@option{-mno-extern-sdata} to stop the library from making assumptions
+about externally-defined data.
-@item -mgpopt=@var{option}
@item -mgpopt
@itemx -mno-gpopt
@opindex mgpopt
@opindex mno-gpopt
-Generate (do not generate) GP-relative accesses. The following
-@var{option} names are recognized:
+Use (do not use) GP-relative accesses for symbols that are known to be
+in a small data section; see @option{-G}, @option{-mlocal-sdata} and
+@option{-mextern-sdata}. @option{-mgpopt} is the default for all
+configurations.
-@table @samp
+@option{-mno-gpopt} is useful for cases where the @code{$gp} register
+might not hold the value of @code{_gp}. For example, if the code is
+part of a library that might be used in a boot monitor, programs that
+call boot monitor routines pass an unknown value in @code{$gp}.
+(In such situations, the boot monitor itself is usually compiled
+with @option{-G0}.)
-@item none
-Do not generate GP-relative accesses.
+@option{-mno-gpopt} implies @option{-mno-local-sdata} and
+@option{-mno-extern-sdata}.
-@item local
-Generate GP-relative accesses for small data objects that are not
-external, weak, or uninitialized common symbols.
-Also use GP-relative addressing for objects that
-have been explicitly placed in a small data section via a @code{section}
-attribute.
+@item -membedded-data
+@itemx -mno-embedded-data
+@opindex membedded-data
+@opindex mno-embedded-data
+Allocate variables to the read-only data section first if possible, then
+next in the small data section if possible, otherwise in data. This gives
+slightly slower code than the default, but reduces the amount of RAM required
+when executing, and thus may be preferred for some embedded systems.
-@item global
-As for @samp{local}, but also generate GP-relative accesses for
-small data objects that are external, weak, or common. If you use this option,
-you must ensure that all parts of your program (including libraries) are
-compiled with the same @option{-G} setting.
+@item -muninit-const-in-rodata
+@itemx -mno-uninit-const-in-rodata
+@opindex muninit-const-in-rodata
+@opindex mno-uninit-const-in-rodata
+Put uninitialized @code{const} variables in the read-only data section.
+This option is only meaningful in conjunction with @option{-membedded-data}.
-@item data
-Generate GP-relative accesses for all data objects in the program. If you
-use this option, the entire data and BSS segments
-of your program must fit in 64K of memory and you must use an appropriate
-linker script to allocate them within the addressible range of the
-global pointer.
+@item -mcode-readable=@var{setting}
+@opindex mcode-readable
+Specify whether GCC may generate code that reads from executable sections.
+There are three possible settings:
-@item all
-Generate GP-relative addresses for function pointers as well as data
-pointers. If you use this option, the entire text, data, and BSS segments
-of your program must fit in 64K of memory and you must use an appropriate
-linker script to allocate them within the addressible range of the
-global pointer.
+@table @gcctabopt
+@item -mcode-readable=yes
+Instructions may freely access executable sections. This is the
+default setting.
-@end table
+@item -mcode-readable=pcrel
+MIPS16 PC-relative load instructions can access executable sections,
+but other instructions must not do so. This option is useful on 4KSc
+and 4KSd processors when the code TLBs have the Read Inhibit bit set.
+It is also useful on processors that can be configured to have a dual
+instruction/data SRAM interface and that, like the M4K, automatically
+redirect PC-relative loads to the instruction RAM.
-@option{-mgpopt} is equivalent to @option{-mgpopt=local}, and
-@option{-mno-gpopt} is equivalent to @option{-mgpopt=none}.
+@item -mcode-readable=no
+Instructions must not access executable sections. This option can be
+useful on targets that are configured to have a dual instruction/data
+SRAM interface but that (unlike the M4K) do not automatically redirect
+PC-relative loads to the instruction RAM.
+@end table
-The default is @option{-mgpopt} except when @option{-fpic} or
-@option{-fPIC} is specified to generate position-independent code.
-Note that the Nios II ABI does not permit GP-relative accesses from
-shared libraries.
+@item -msplit-addresses
+@itemx -mno-split-addresses
+@opindex msplit-addresses
+@opindex mno-split-addresses
+Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
+relocation operators. This option has been superseded by
+@option{-mexplicit-relocs} but is retained for backwards compatibility.
-You may need to specify @option{-mno-gpopt} explicitly when building
-programs that include large amounts of small data, including large
-GOT data sections. In this case, the 16-bit offset for GP-relative
-addressing may not be large enough to allow access to the entire
-small data section.
+@item -mexplicit-relocs
+@itemx -mno-explicit-relocs
+@opindex mexplicit-relocs
+@opindex mno-explicit-relocs
+Use (do not use) assembler relocation operators when dealing with symbolic
+addresses. The alternative, selected by @option{-mno-explicit-relocs},
+is to use assembler macros instead.
-@item -mel
-@itemx -meb
-@opindex mel
-@opindex meb
-Generate little-endian (default) or big-endian (experimental) code,
-respectively.
+@option{-mexplicit-relocs} is the default if GCC was configured
+to use an assembler that supports relocation operators.
-@item -march=@var{arch}
-@opindex march
-This specifies the name of the target Nios II architecture. GCC uses this
-name to determine what kind of instructions it can emit when generating
-assembly code. Permissible names are: @samp{r1}, @samp{r2}.
+@item -mcheck-zero-division
+@itemx -mno-check-zero-division
+@opindex mcheck-zero-division
+@opindex mno-check-zero-division
+Trap (do not trap) on integer division by zero.
-The preprocessor macro @code{__nios2_arch__} is available to programs,
-with value 1 or 2, indicating the targeted ISA level.
+The default is @option{-mcheck-zero-division}.
-@item -mbypass-cache
-@itemx -mno-bypass-cache
-@opindex mno-bypass-cache
-@opindex mbypass-cache
-Force all load and store instructions to always bypass cache by
-using I/O variants of the instructions. The default is not to
-bypass the cache.
+@item -mdivide-traps
+@itemx -mdivide-breaks
+@opindex mdivide-traps
+@opindex mdivide-breaks
+MIPS systems check for division by zero by generating either a
+conditional trap or a break instruction. Using traps results in
+smaller code, but is only supported on MIPS II and later. Also, some
+versions of the Linux kernel have a bug that prevents trap from
+generating the proper signal (@code{SIGFPE}). Use @option{-mdivide-traps} to
+allow conditional traps on architectures that support them and
+@option{-mdivide-breaks} to force the use of breaks.
-@item -mno-cache-volatile
-@itemx -mcache-volatile
-@opindex mcache-volatile
-@opindex mno-cache-volatile
-Volatile memory access bypass the cache using the I/O variants of
-the load and store instructions. The default is not to bypass the cache.
+The default is usually @option{-mdivide-traps}, but this can be
+overridden at configure time using @option{--with-divide=breaks}.
+Divide-by-zero checks can be completely disabled using
+@option{-mno-check-zero-division}.
-@item -mno-fast-sw-div
-@itemx -mfast-sw-div
-@opindex mno-fast-sw-div
-@opindex mfast-sw-div
-Do not use table-based fast divide for small numbers. The default
-is to use the fast divide at @option{-O3} and above.
+@item -mmemcpy
+@itemx -mno-memcpy
+@opindex mmemcpy
+@opindex mno-memcpy
+Force (do not force) the use of @code{memcpy} for non-trivial block
+moves. The default is @option{-mno-memcpy}, which allows GCC to inline
+most constant-sized copies.
-@item -mno-hw-mul
-@itemx -mhw-mul
-@itemx -mno-hw-mulx
-@itemx -mhw-mulx
-@itemx -mno-hw-div
-@itemx -mhw-div
-@opindex mno-hw-mul
-@opindex mhw-mul
-@opindex mno-hw-mulx
-@opindex mhw-mulx
-@opindex mno-hw-div
-@opindex mhw-div
-Enable or disable emitting @code{mul}, @code{mulx} and @code{div} family of
-instructions by the compiler. The default is to emit @code{mul}
-and not emit @code{div} and @code{mulx}.
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Disable (do not disable) use of the @code{jal} instruction. Calling
+functions using @code{jal} is more efficient but requires the caller
+and callee to be in the same 256 megabyte segment.
-@item -mbmx
-@itemx -mno-bmx
-@itemx -mcdx
-@itemx -mno-cdx
-Enable or disable generation of Nios II R2 BMX (bit manipulation) and
-CDX (code density) instructions. Enabling these instructions also
-requires @option{-march=r2}. Since these instructions are optional
-extensions to the R2 architecture, the default is not to emit them.
+This option has no effect on abicalls code. The default is
+@option{-mno-long-calls}.
-@item -mcustom-@var{insn}=@var{N}
-@itemx -mno-custom-@var{insn}
-@opindex mcustom-@var{insn}
-@opindex mno-custom-@var{insn}
-Each @option{-mcustom-@var{insn}=@var{N}} option enables use of a
-custom instruction with encoding @var{N} when generating code that uses
-@var{insn}. For example, @option{-mcustom-fadds=253} generates custom
-instruction 253 for single-precision floating-point add operations instead
-of the default behavior of using a library call.
+@item -mmad
+@itemx -mno-mad
+@opindex mmad
+@opindex mno-mad
+Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
+instructions, as provided by the R4650 ISA@.
-The following values of @var{insn} are supported. Except as otherwise
-noted, floating-point operations are expected to be implemented with
-normal IEEE 754 semantics and correspond directly to the C operators or the
-equivalent GCC built-in functions (@pxref{Other Builtins}).
+@item -mimadd
+@itemx -mno-imadd
+@opindex mimadd
+@opindex mno-imadd
+Enable (disable) use of the @code{madd} and @code{msub} integer
+instructions. The default is @option{-mimadd} on architectures
+that support @code{madd} and @code{msub} except for the 74k
+architecture where it was found to generate slower code.
-Single-precision floating point:
-@table @asis
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Enable (disable) use of the floating-point multiply-accumulate
+instructions, when they are available. The default is
+@option{-mfused-madd}.
-@item @samp{fadds}, @samp{fsubs}, @samp{fdivs}, @samp{fmuls}
-Binary arithmetic operations.
+On the R8000 CPU when multiply-accumulate instructions are used,
+the intermediate product is calculated to infinite precision
+and is not subject to the FCSR Flush to Zero bit. This may be
+undesirable in some circumstances. On other processors the result
+is numerically identical to the equivalent computation using
+separate multiply, add, subtract and negate instructions.
-@item @samp{fnegs}
-Unary negation.
+@item -nocpp
+@opindex nocpp
+Tell the MIPS assembler to not run its preprocessor over user
+assembler files (with a @samp{.s} suffix) when assembling them.
-@item @samp{fabss}
-Unary absolute value.
+@item -mfix-24k
+@item -mno-fix-24k
+@opindex mfix-24k
+@opindex mno-fix-24k
+Work around the 24K E48 (lost data on stores during refill) errata.
+The workarounds are implemented by the assembler rather than by GCC@.
-@item @samp{fcmpeqs}, @samp{fcmpges}, @samp{fcmpgts}, @samp{fcmples}, @samp{fcmplts}, @samp{fcmpnes}
-Comparison operations.
+@item -mfix-r4000
+@itemx -mno-fix-r4000
+@opindex mfix-r4000
+@opindex mno-fix-r4000
+Work around certain R4000 CPU errata:
+@itemize @minus
+@item
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+@item
+A double-word or a variable shift may give an incorrect result if executed
+while an integer multiplication is in progress.
+@item
+An integer division may give an incorrect result if started in a delay slot
+of a taken branch or a jump.
+@end itemize
-@item @samp{fmins}, @samp{fmaxs}
-Floating-point minimum and maximum. These instructions are only
-generated if @option{-ffinite-math-only} is specified.
+@item -mfix-r4400
+@itemx -mno-fix-r4400
+@opindex mfix-r4400
+@opindex mno-fix-r4400
+Work around certain R4400 CPU errata:
+@itemize @minus
+@item
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+@end itemize
-@item @samp{fsqrts}
-Unary square root operation.
+@item -mfix-r10000
+@itemx -mno-fix-r10000
+@opindex mfix-r10000
+@opindex mno-fix-r10000
+Work around certain R10000 errata:
+@itemize @minus
+@item
+@code{ll}/@code{sc} sequences may not behave atomically on revisions
+prior to 3.0. They may deadlock on revisions 2.6 and earlier.
+@end itemize
-@item @samp{fcoss}, @samp{fsins}, @samp{ftans}, @samp{fatans}, @samp{fexps}, @samp{flogs}
-Floating-point trigonometric and exponential functions. These instructions
-are only generated if @option{-funsafe-math-optimizations} is also specified.
+This option can only be used if the target architecture supports
+branch-likely instructions. @option{-mfix-r10000} is the default when
+@option{-march=r10000} is used; @option{-mno-fix-r10000} is the default
+otherwise.
-@end table
+@item -mfix-rm7000
+@itemx -mno-fix-rm7000
+@opindex mfix-rm7000
+Work around the RM7000 @code{dmult}/@code{dmultu} errata. The
+workarounds are implemented by the assembler rather than by GCC@.
-Double-precision floating point:
-@table @asis
+@item -mfix-vr4120
+@itemx -mno-fix-vr4120
+@opindex mfix-vr4120
+Work around certain VR4120 errata:
+@itemize @minus
+@item
+@code{dmultu} does not always produce the correct result.
+@item
+@code{div} and @code{ddiv} do not always produce the correct result if one
+of the operands is negative.
+@end itemize
+The workarounds for the division errata rely on special functions in
+@file{libgcc.a}. At present, these functions are only provided by
+the @code{mips64vr*-elf} configurations.
-@item @samp{faddd}, @samp{fsubd}, @samp{fdivd}, @samp{fmuld}
-Binary arithmetic operations.
+Other VR4120 errata require a NOP to be inserted between certain pairs of
+instructions. These errata are handled by the assembler, not by GCC itself.
-@item @samp{fnegd}
-Unary negation.
+@item -mfix-vr4130
+@opindex mfix-vr4130
+Work around the VR4130 @code{mflo}/@code{mfhi} errata. The
+workarounds are implemented by the assembler rather than by GCC,
+although GCC avoids using @code{mflo} and @code{mfhi} if the
+VR4130 @code{macc}, @code{macchi}, @code{dmacc} and @code{dmacchi}
+instructions are available instead.
-@item @samp{fabsd}
-Unary absolute value.
+@item -mfix-sb1
+@itemx -mno-fix-sb1
+@opindex mfix-sb1
+Work around certain SB-1 CPU core errata.
+(This flag currently works around the SB-1 revision 2
+``F1'' and ``F2'' floating-point errata.)
-@item @samp{fcmpeqd}, @samp{fcmpged}, @samp{fcmpgtd}, @samp{fcmpled}, @samp{fcmpltd}, @samp{fcmpned}
-Comparison operations.
+@item -mr10k-cache-barrier=@var{setting}
+@opindex mr10k-cache-barrier
+Specify whether GCC should insert cache barriers to avoid the
+side-effects of speculation on R10K processors.
-@item @samp{fmind}, @samp{fmaxd}
-Double-precision minimum and maximum. These instructions are only
-generated if @option{-ffinite-math-only} is specified.
+In common with many processors, the R10K tries to predict the outcome
+of a conditional branch and speculatively executes instructions from
+the ``taken'' branch. It later aborts these instructions if the
+predicted outcome is wrong. However, on the R10K, even aborted
+instructions can have side effects.
-@item @samp{fsqrtd}
-Unary square root operation.
+This problem only affects kernel stores and, depending on the system,
+kernel loads. As an example, a speculatively-executed store may load
+the target memory into cache and mark the cache line as dirty, even if
+the store itself is later aborted. If a DMA operation writes to the
+same area of memory before the ``dirty'' line is flushed, the cached
+data overwrites the DMA-ed data. See the R10K processor manual
+for a full description, including other potential problems.
-@item @samp{fcosd}, @samp{fsind}, @samp{ftand}, @samp{fatand}, @samp{fexpd}, @samp{flogd}
-Double-precision trigonometric and exponential functions. These instructions
-are only generated if @option{-funsafe-math-optimizations} is also specified.
+One workaround is to insert cache barrier instructions before every memory
+access that might be speculatively executed and that might have side
+effects even if aborted. @option{-mr10k-cache-barrier=@var{setting}}
+controls GCC's implementation of this workaround. It assumes that
+aborted accesses to any byte in the following regions does not have
+side effects:
-@end table
+@enumerate
+@item
+the memory occupied by the current function's stack frame;
-Conversions:
-@table @asis
-@item @samp{fextsd}
-Conversion from single precision to double precision.
+@item
+the memory occupied by an incoming stack argument;
-@item @samp{ftruncds}
-Conversion from double precision to single precision.
+@item
+the memory occupied by an object with a link-time-constant address.
+@end enumerate
-@item @samp{fixsi}, @samp{fixsu}, @samp{fixdi}, @samp{fixdu}
-Conversion from floating point to signed or unsigned integer types, with
-truncation towards zero.
+It is the kernel's responsibility to ensure that speculative
+accesses to these regions are indeed safe.
-@item @samp{round}
-Conversion from single-precision floating point to signed integer,
-rounding to the nearest integer and ties away from zero.
-This corresponds to the @code{__builtin_lroundf} function when
-@option{-fno-math-errno} is used.
+If the input program contains a function declaration such as:
-@item @samp{floatis}, @samp{floatus}, @samp{floatid}, @samp{floatud}
-Conversion from signed or unsigned integer types to floating-point types.
+@smallexample
+void foo (void);
+@end smallexample
-@end table
+then the implementation of @code{foo} must allow @code{j foo} and
+@code{jal foo} to be executed speculatively. GCC honors this
+restriction for functions it compiles itself. It expects non-GCC
+functions (such as hand-written assembly code) to do the same.
-In addition, all of the following transfer instructions for internal
-registers X and Y must be provided to use any of the double-precision
-floating-point instructions. Custom instructions taking two
-double-precision source operands expect the first operand in the
-64-bit register X. The other operand (or only operand of a unary
-operation) is given to the custom arithmetic instruction with the
-least significant half in source register @var{src1} and the most
-significant half in @var{src2}. A custom instruction that returns a
-double-precision result returns the most significant 32 bits in the
-destination register and the other half in 32-bit register Y.
-GCC automatically generates the necessary code sequences to write
-register X and/or read register Y when double-precision floating-point
-instructions are used.
-
-@table @asis
-
-@item @samp{fwrx}
-Write @var{src1} into the least significant half of X and @var{src2} into
-the most significant half of X.
+The option has three forms:
-@item @samp{fwry}
-Write @var{src1} into Y.
+@table @gcctabopt
+@item -mr10k-cache-barrier=load-store
+Insert a cache barrier before a load or store that might be
+speculatively executed and that might have side effects even
+if aborted.
-@item @samp{frdxhi}, @samp{frdxlo}
-Read the most or least (respectively) significant half of X and store it in
-@var{dest}.
+@item -mr10k-cache-barrier=store
+Insert a cache barrier before a store that might be speculatively
+executed and that might have side effects even if aborted.
-@item @samp{frdy}
-Read the value of Y and store it into @var{dest}.
+@item -mr10k-cache-barrier=none
+Disable the insertion of cache barriers. This is the default setting.
@end table
-Note that you can gain more local control over generation of Nios II custom
-instructions by using the @code{target("custom-@var{insn}=@var{N}")}
-and @code{target("no-custom-@var{insn}")} function attributes
-(@pxref{Function Attributes})
-or pragmas (@pxref{Function Specific Option Pragmas}).
-
-@item -mcustom-fpu-cfg=@var{name}
-@opindex mcustom-fpu-cfg
+@item -mflush-func=@var{func}
+@itemx -mno-flush-func
+@opindex mflush-func
+Specifies the function to call to flush the I and D caches, or to not
+call any such function. If called, the function must take the same
+arguments as the common @code{_flush_func}, that is, the address of the
+memory range for which the cache is being flushed, the size of the
+memory range, and the number 3 (to flush both caches). The default
+depends on the target GCC was configured for, but commonly is either
+@code{_flush_func} or @code{__cpu_flush}.
-This option enables a predefined, named set of custom instruction encodings
-(see @option{-mcustom-@var{insn}} above).
-Currently, the following sets are defined:
+@item mbranch-cost=@var{num}
+@opindex mbranch-cost
+Set the cost of branches to roughly @var{num} ``simple'' instructions.
+This cost is only a heuristic and is not guaranteed to produce
+consistent results across releases. A zero cost redundantly selects
+the default, which is based on the @option{-mtune} setting.
-@option{-mcustom-fpu-cfg=60-1} is equivalent to:
-@gccoptlist{-mcustom-fmuls=252 @gol
--mcustom-fadds=253 @gol
--mcustom-fsubs=254 @gol
--fsingle-precision-constant}
+@item -mbranch-likely
+@itemx -mno-branch-likely
+@opindex mbranch-likely
+@opindex mno-branch-likely
+Enable or disable use of Branch Likely instructions, regardless of the
+default for the selected architecture. By default, Branch Likely
+instructions may be generated if they are supported by the selected
+architecture. An exception is for the MIPS32 and MIPS64 architectures
+and processors that implement those architectures; for those, Branch
+Likely instructions are not be generated by default because the MIPS32
+and MIPS64 architectures specifically deprecate their use.
-@option{-mcustom-fpu-cfg=60-2} is equivalent to:
-@gccoptlist{-mcustom-fmuls=252 @gol
--mcustom-fadds=253 @gol
--mcustom-fsubs=254 @gol
--mcustom-fdivs=255 @gol
--fsingle-precision-constant}
+@item -mcompact-branches=never
+@itemx -mcompact-branches=optimal
+@itemx -mcompact-branches=always
+@opindex mcompact-branches=never
+@opindex mcompact-branches=optimal
+@opindex mcompact-branches=always
+These options control which form of branches will be generated. The
+default is @option{-mcompact-branches=optimal}.
-@option{-mcustom-fpu-cfg=72-3} is equivalent to:
-@gccoptlist{-mcustom-floatus=243 @gol
--mcustom-fixsi=244 @gol
--mcustom-floatis=245 @gol
--mcustom-fcmpgts=246 @gol
--mcustom-fcmples=249 @gol
--mcustom-fcmpeqs=250 @gol
--mcustom-fcmpnes=251 @gol
--mcustom-fmuls=252 @gol
--mcustom-fadds=253 @gol
--mcustom-fsubs=254 @gol
--mcustom-fdivs=255 @gol
--fsingle-precision-constant}
+The @option{-mcompact-branches=never} option ensures that compact branch
+instructions will never be generated.
-Custom instruction assignments given by individual
-@option{-mcustom-@var{insn}=} options override those given by
-@option{-mcustom-fpu-cfg=}, regardless of the
-order of the options on the command line.
+The @option{-mcompact-branches=always} option ensures that a compact
+branch instruction will be generated if available. If a compact branch
+instruction is not available, a delay slot form of the branch will be
+used instead.
-Note that you can gain more local control over selection of a FPU
-configuration by using the @code{target("custom-fpu-cfg=@var{name}")}
-function attribute (@pxref{Function Attributes})
-or pragma (@pxref{Function Specific Option Pragmas}).
+This option is supported from MIPS Release 6 onwards.
-@end table
+The @option{-mcompact-branches=optimal} option will cause a delay slot
+branch to be used if one is available in the current ISA and the delay
+slot is successfully filled. If the delay slot is not filled, a compact
+branch will be chosen if one is available.
-These additional @samp{-m} options are available for the Altera Nios II
-ELF (bare-metal) target:
+@item -mfp-exceptions
+@itemx -mno-fp-exceptions
+@opindex mfp-exceptions
+Specifies whether FP exceptions are enabled. This affects how
+FP instructions are scheduled for some processors.
+The default is that FP exceptions are
+enabled.
-@table @gcctabopt
+For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
+64-bit code, then we can use both FP pipes. Otherwise, we can only use one
+FP pipe.
-@item -mhal
-@opindex mhal
-Link with HAL BSP. This suppresses linking with the GCC-provided C runtime
-startup and termination code, and is typically used in conjunction with
-@option{-msys-crt0=} to specify the location of the alternate startup code
-provided by the HAL BSP.
+@item -mvr4130-align
+@itemx -mno-vr4130-align
+@opindex mvr4130-align
+The VR4130 pipeline is two-way superscalar, but can only issue two
+instructions together if the first one is 8-byte aligned. When this
+option is enabled, GCC aligns pairs of instructions that it
+thinks should execute in parallel.
-@item -msmallc
-@opindex msmallc
-Link with a limited version of the C library, @option{-lsmallc}, rather than
-Newlib.
+This option only has an effect when optimizing for the VR4130.
+It normally makes code faster, but at the expense of making it bigger.
+It is enabled by default at optimization level @option{-O3}.
-@item -msys-crt0=@var{startfile}
-@opindex msys-crt0
-@var{startfile} is the file name of the startfile (crt0) to use
-when linking. This option is only useful in conjunction with @option{-mhal}.
+@item -msynci
+@itemx -mno-synci
+@opindex msynci
+Enable (disable) generation of @code{synci} instructions on
+architectures that support it. The @code{synci} instructions (if
+enabled) are generated when @code{__builtin___clear_cache} is
+compiled.
-@item -msys-lib=@var{systemlib}
-@opindex msys-lib
-@var{systemlib} is the library name of the library that provides
-low-level system calls required by the C library,
-e.g. @code{read} and @code{write}.
-This option is typically used to link with a library provided by a HAL BSP.
+This option defaults to @option{-mno-synci}, but the default can be
+overridden by configuring GCC with @option{--with-synci}.
-@end table
+When compiling code for single processor systems, it is generally safe
+to use @code{synci}. However, on many multi-core (SMP) systems, it
+does not invalidate the instruction caches on all cores and may lead
+to undefined behavior.
-@node Nvidia PTX Options
-@subsection Nvidia PTX Options
-@cindex Nvidia PTX options
-@cindex nvptx options
+@item -mrelax-pic-calls
+@itemx -mno-relax-pic-calls
+@opindex mrelax-pic-calls
+Try to turn PIC calls that are normally dispatched via register
+@code{$25} into direct calls. This is only possible if the linker can
+resolve the destination at link-time and if the destination is within
+range for a direct call.
-These options are defined for Nvidia PTX:
+@option{-mrelax-pic-calls} is the default if GCC was configured to use
+an assembler and a linker that support the @code{.reloc} assembly
+directive and @option{-mexplicit-relocs} is in effect. With
+@option{-mno-explicit-relocs}, this optimization can be performed by the
+assembler and the linker alone without help from the compiler.
-@table @gcctabopt
+@item -mmcount-ra-address
+@itemx -mno-mcount-ra-address
+@opindex mmcount-ra-address
+@opindex mno-mcount-ra-address
+Emit (do not emit) code that allows @code{_mcount} to modify the
+calling function's return address. When enabled, this option extends
+the usual @code{_mcount} interface with a new @var{ra-address}
+parameter, which has type @code{intptr_t *} and is passed in register
+@code{$12}. @code{_mcount} can then modify the return address by
+doing both of the following:
+@itemize
+@item
+Returning the new address in register @code{$31}.
+@item
+Storing the new address in @code{*@var{ra-address}},
+if @var{ra-address} is nonnull.
+@end itemize
-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for 32-bit or 64-bit ABI.
+The default is @option{-mno-mcount-ra-address}.
-@item -mmainkernel
-@opindex mmainkernel
-Link in code for a __main kernel. This is for stand-alone instead of
-offloading execution.
+@item -mframe-header-opt
+@itemx -mno-frame-header-opt
+@opindex mframe-header-opt
+Enable (disable) frame header optimization in the o32 ABI. When using the
+o32 ABI, calling functions will allocate 16 bytes on the stack for the called
+function to write out register arguments. When enabled, this optimization
+will suppress the allocation of the frame header if it can be determined that
+it is unused.
-@item -moptimize
-@opindex moptimize
-Apply partitioned execution optimizations. This is the default when any
-level of optimization is selected.
+This optimization is off by default at all optimization levels.
@end table
-@node PDP-11 Options
-@subsection PDP-11 Options
-@cindex PDP-11 Options
+@node MMIX Options
+@subsection MMIX Options
+@cindex MMIX Options
-These options are defined for the PDP-11:
+These options are defined for the MMIX:
@table @gcctabopt
-@item -mfpu
-@opindex mfpu
-Use hardware FPP floating point. This is the default. (FIS floating
-point on the PDP-11/40 is not supported.)
-
-@item -msoft-float
-@opindex msoft-float
-Do not use hardware floating point.
+@item -mlibfuncs
+@itemx -mno-libfuncs
+@opindex mlibfuncs
+@opindex mno-libfuncs
+Specify that intrinsic library functions are being compiled, passing all
+values in registers, no matter the size.
-@item -mac0
-@opindex mac0
-Return floating-point results in ac0 (fr0 in Unix assembler syntax).
+@item -mepsilon
+@itemx -mno-epsilon
+@opindex mepsilon
+@opindex mno-epsilon
+Generate floating-point comparison instructions that compare with respect
+to the @code{rE} epsilon register.
-@item -mno-ac0
-@opindex mno-ac0
-Return floating-point results in memory. This is the default.
+@item -mabi=mmixware
+@itemx -mabi=gnu
+@opindex mabi=mmixware
+@opindex mabi=gnu
+Generate code that passes function parameters and return values that (in
+the called function) are seen as registers @code{$0} and up, as opposed to
+the GNU ABI which uses global registers @code{$231} and up.
-@item -m40
-@opindex m40
-Generate code for a PDP-11/40.
+@item -mzero-extend
+@itemx -mno-zero-extend
+@opindex mzero-extend
+@opindex mno-zero-extend
+When reading data from memory in sizes shorter than 64 bits, use (do not
+use) zero-extending load instructions by default, rather than
+sign-extending ones.
-@item -m45
-@opindex m45
-Generate code for a PDP-11/45. This is the default.
+@item -mknuthdiv
+@itemx -mno-knuthdiv
+@opindex mknuthdiv
+@opindex mno-knuthdiv
+Make the result of a division yielding a remainder have the same sign as
+the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
+remainder follows the sign of the dividend. Both methods are
+arithmetically valid, the latter being almost exclusively used.
-@item -m10
-@opindex m10
-Generate code for a PDP-11/10.
+@item -mtoplevel-symbols
+@itemx -mno-toplevel-symbols
+@opindex mtoplevel-symbols
+@opindex mno-toplevel-symbols
+Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
+code can be used with the @code{PREFIX} assembly directive.
-@item -mbcopy-builtin
-@opindex mbcopy-builtin
-Use inline @code{movmemhi} patterns for copying memory. This is the
-default.
+@item -melf
+@opindex melf
+Generate an executable in the ELF format, rather than the default
+@samp{mmo} format used by the @command{mmix} simulator.
-@item -mbcopy
-@opindex mbcopy
-Do not use inline @code{movmemhi} patterns for copying memory.
+@item -mbranch-predict
+@itemx -mno-branch-predict
+@opindex mbranch-predict
+@opindex mno-branch-predict
+Use (do not use) the probable-branch instructions, when static branch
+prediction indicates a probable branch.
-@item -mint16
-@itemx -mno-int32
-@opindex mint16
-@opindex mno-int32
-Use 16-bit @code{int}. This is the default.
+@item -mbase-addresses
+@itemx -mno-base-addresses
+@opindex mbase-addresses
+@opindex mno-base-addresses
+Generate (do not generate) code that uses @emph{base addresses}. Using a
+base address automatically generates a request (handled by the assembler
+and the linker) for a constant to be set up in a global register. The
+register is used for one or more base address requests within the range 0
+to 255 from the value held in the register. The generally leads to short
+and fast code, but the number of different data items that can be
+addressed is limited. This means that a program that uses lots of static
+data may require @option{-mno-base-addresses}.
-@item -mint32
-@itemx -mno-int16
-@opindex mint32
-@opindex mno-int16
-Use 32-bit @code{int}.
+@item -msingle-exit
+@itemx -mno-single-exit
+@opindex msingle-exit
+@opindex mno-single-exit
+Force (do not force) generated code to have a single exit point in each
+function.
+@end table
-@item -mfloat64
-@itemx -mno-float32
-@opindex mfloat64
-@opindex mno-float32
-Use 64-bit @code{float}. This is the default.
+@node MN10300 Options
+@subsection MN10300 Options
+@cindex MN10300 options
-@item -mfloat32
-@itemx -mno-float64
-@opindex mfloat32
-@opindex mno-float64
-Use 32-bit @code{float}.
+These @option{-m} options are defined for Matsushita MN10300 architectures:
-@item -mabshi
-@opindex mabshi
-Use @code{abshi2} pattern. This is the default.
+@table @gcctabopt
+@item -mmult-bug
+@opindex mmult-bug
+Generate code to avoid bugs in the multiply instructions for the MN10300
+processors. This is the default.
-@item -mno-abshi
-@opindex mno-abshi
-Do not use @code{abshi2} pattern.
+@item -mno-mult-bug
+@opindex mno-mult-bug
+Do not generate code to avoid bugs in the multiply instructions for the
+MN10300 processors.
-@item -mbranch-expensive
-@opindex mbranch-expensive
-Pretend that branches are expensive. This is for experimenting with
-code generation only.
+@item -mam33
+@opindex mam33
+Generate code using features specific to the AM33 processor.
-@item -mbranch-cheap
-@opindex mbranch-cheap
-Do not pretend that branches are expensive. This is the default.
+@item -mno-am33
+@opindex mno-am33
+Do not generate code using features specific to the AM33 processor. This
+is the default.
-@item -munix-asm
-@opindex munix-asm
-Use Unix assembler syntax. This is the default when configured for
-@samp{pdp11-*-bsd}.
+@item -mam33-2
+@opindex mam33-2
+Generate code using features specific to the AM33/2.0 processor.
-@item -mdec-asm
-@opindex mdec-asm
-Use DEC assembler syntax. This is the default when configured for any
-PDP-11 target other than @samp{pdp11-*-bsd}.
-@end table
+@item -mam34
+@opindex mam34
+Generate code using features specific to the AM34 processor.
-@node picoChip Options
-@subsection picoChip Options
-@cindex picoChip options
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Use the timing characteristics of the indicated CPU type when
+scheduling instructions. This does not change the targeted processor
+type. The CPU type must be one of @samp{mn10300}, @samp{am33},
+@samp{am33-2} or @samp{am34}.
-These @samp{-m} options are defined for picoChip implementations:
+@item -mreturn-pointer-on-d0
+@opindex mreturn-pointer-on-d0
+When generating a function that returns a pointer, return the pointer
+in both @code{a0} and @code{d0}. Otherwise, the pointer is returned
+only in @code{a0}, and attempts to call such functions without a prototype
+result in errors. Note that this option is on by default; use
+@option{-mno-return-pointer-on-d0} to disable it.
-@table @gcctabopt
+@item -mno-crt0
+@opindex mno-crt0
+Do not link in the C run-time initialization object file.
-@item -mae=@var{ae_type}
-@opindex mcpu
-Set the instruction set, register set, and instruction scheduling
-parameters for array element type @var{ae_type}. Supported values
-for @var{ae_type} are @samp{ANY}, @samp{MUL}, and @samp{MAC}.
+@item -mrelax
+@opindex mrelax
+Indicate to the linker that it should perform a relaxation optimization pass
+to shorten branches, calls and absolute memory addresses. This option only
+has an effect when used on the command line for the final link step.
-@option{-mae=ANY} selects a completely generic AE type. Code
-generated with this option runs on any of the other AE types. The
-code is not as efficient as it would be if compiled for a specific
-AE type, and some types of operation (e.g., multiplication) do not
-work properly on all types of AE.
+This option makes symbolic debugging impossible.
-@option{-mae=MUL} selects a MUL AE type. This is the most useful AE type
-for compiled code, and is the default.
+@item -mliw
+@opindex mliw
+Allow the compiler to generate @emph{Long Instruction Word}
+instructions if the target is the @samp{AM33} or later. This is the
+default. This option defines the preprocessor macro @code{__LIW__}.
-@option{-mae=MAC} selects a DSP-style MAC AE. Code compiled with this
-option may suffer from poor performance of byte (char) manipulation,
-since the DSP AE does not provide hardware support for byte load/stores.
+@item -mnoliw
+@opindex mnoliw
+Do not allow the compiler to generate @emph{Long Instruction Word}
+instructions. This option defines the preprocessor macro
+@code{__NO_LIW__}.
-@item -msymbol-as-address
-Enable the compiler to directly use a symbol name as an address in a
-load/store instruction, without first loading it into a
-register. Typically, the use of this option generates larger
-programs, which run faster than when the option isn't used. However, the
-results vary from program to program, so it is left as a user option,
-rather than being permanently enabled.
+@item -msetlb
+@opindex msetlb
+Allow the compiler to generate the @emph{SETLB} and @emph{Lcc}
+instructions if the target is the @samp{AM33} or later. This is the
+default. This option defines the preprocessor macro @code{__SETLB__}.
-@item -mno-inefficient-warnings
-Disables warnings about the generation of inefficient code. These
-warnings can be generated, for example, when compiling code that
-performs byte-level memory operations on the MAC AE type. The MAC AE has
-no hardware support for byte-level memory operations, so all byte
-load/stores must be synthesized from word load/store operations. This is
-inefficient and a warning is generated to indicate
-that you should rewrite the code to avoid byte operations, or to target
-an AE type that has the necessary hardware support. This option disables
-these warnings.
+@item -mnosetlb
+@opindex mnosetlb
+Do not allow the compiler to generate @emph{SETLB} or @emph{Lcc}
+instructions. This option defines the preprocessor macro
+@code{__NO_SETLB__}.
@end table
-@node PowerPC Options
-@subsection PowerPC Options
-@cindex PowerPC options
-
-These are listed under @xref{RS/6000 and PowerPC Options}.
-
-@node RL78 Options
-@subsection RL78 Options
-@cindex RL78 Options
+@node Moxie Options
+@subsection Moxie Options
+@cindex Moxie Options
@table @gcctabopt
-@item -msim
-@opindex msim
-Links in additional target libraries to support operation within a
-simulator.
+@item -meb
+@opindex meb
+Generate big-endian code. This is the default for @samp{moxie-*-*}
+configurations.
-@item -mmul=none
-@itemx -mmul=g10
-@itemx -mmul=g13
-@itemx -mmul=g14
-@itemx -mmul=rl78
-@opindex mmul
-Specifies the type of hardware multiplication and division support to
-be used. The simplest is @code{none}, which uses software for both
-multiplication and division. This is the default. The @code{g13}
-value is for the hardware multiply/divide peripheral found on the
-RL78/G13 (S2 core) targets. The @code{g14} value selects the use of
-the multiplication and division instructions supported by the RL78/G14
-(S3 core) parts. The value @code{rl78} is an alias for @code{g14} and
-the value @code{mg10} is an alias for @code{none}.
+@item -mel
+@opindex mel
+Generate little-endian code.
-In addition a C preprocessor macro is defined, based upon the setting
-of this option. Possible values are: @code{__RL78_MUL_NONE__},
-@code{__RL78_MUL_G13__} or @code{__RL78_MUL_G14__}.
+@item -mmul.x
+@opindex mmul.x
+Generate mul.x and umul.x instructions. This is the default for
+@samp{moxiebox-*-*} configurations.
-@item -mcpu=g10
-@itemx -mcpu=g13
-@itemx -mcpu=g14
-@itemx -mcpu=rl78
-@opindex mcpu
-Specifies the RL78 core to target. The default is the G14 core, also
-known as an S3 core or just RL78. The G13 or S2 core does not have
-multiply or divide instructions, instead it uses a hardware peripheral
-for these operations. The G10 or S1 core does not have register
-banks, so it uses a different calling convention.
+@item -mno-crt0
+@opindex mno-crt0
+Do not link in the C run-time initialization object file.
-If this option is set it also selects the type of hardware multiply
-support to use, unless this is overridden by an explicit
-@option{-mmul=none} option on the command line. Thus specifying
-@option{-mcpu=g13} enables the use of the G13 hardware multiply
-peripheral and specifying @option{-mcpu=g10} disables the use of
-hardware multipications altogether.
+@end table
-Note, although the RL78/G14 core is the default target, specifying
-@option{-mcpu=g14} or @option{-mcpu=rl78} on the command line does
-change the behaviour of the toolchain since it also enables G14
-hardware multiply support. If these options are not specified on the
-command line then software multiplication routines will be used even
-though the code targets the RL78 core. This is for backwards
-compatibility with older toolchains which did not have hardware
-multiply and divide support.
+@node MSP430 Options
+@subsection MSP430 Options
+@cindex MSP430 Options
-In addition a C preprocessor macro is defined, based upon the setting
-of this option. Possible values are: @code{__RL78_G10__},
-@code{__RL78_G13__} or @code{__RL78_G14__}.
+These options are defined for the MSP430:
-@item -mg10
-@itemx -mg13
-@itemx -mg14
-@itemx -mrl78
-@opindex mg10
-@opindex mg13
-@opindex mg14
-@opindex mrl78
-These are aliases for the corresponding @option{-mcpu=} option. They
-are provided for backwards compatibility.
+@table @gcctabopt
-@item -mallregs
-@opindex mallregs
-Allow the compiler to use all of the available registers. By default
-registers @code{r24..r31} are reserved for use in interrupt handlers.
-With this option enabled these registers can be used in ordinary
-functions as well.
+@item -masm-hex
+@opindex masm-hex
+Force assembly output to always use hex constants. Normally such
+constants are signed decimals, but this option is available for
+testsuite and/or aesthetic purposes.
-@item -m64bit-doubles
-@itemx -m32bit-doubles
-@opindex m64bit-doubles
-@opindex m32bit-doubles
-Make the @code{double} data type be 64 bits (@option{-m64bit-doubles})
-or 32 bits (@option{-m32bit-doubles}) in size. The default is
-@option{-m32bit-doubles}.
+@item -mmcu=
+@opindex mmcu=
+Select the MCU to target. This is used to create a C preprocessor
+symbol based upon the MCU name, converted to upper case and pre- and
+post-fixed with @samp{__}. This in turn is used by the
+@file{msp430.h} header file to select an MCU-specific supplementary
+header file.
-@end table
+The option also sets the ISA to use. If the MCU name is one that is
+known to only support the 430 ISA then that is selected, otherwise the
+430X ISA is selected. A generic MCU name of @samp{msp430} can also be
+used to select the 430 ISA. Similarly the generic @samp{msp430x} MCU
+name selects the 430X ISA.
-@node RS/6000 and PowerPC Options
-@subsection IBM RS/6000 and PowerPC Options
-@cindex RS/6000 and PowerPC Options
-@cindex IBM RS/6000 and PowerPC Options
+In addition an MCU-specific linker script is added to the linker
+command line. The script's name is the name of the MCU with
+@file{.ld} appended. Thus specifying @option{-mmcu=xxx} on the @command{gcc}
+command line defines the C preprocessor symbol @code{__XXX__} and
+cause the linker to search for a script called @file{xxx.ld}.
-These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
-@table @gcctabopt
-@item -mpowerpc-gpopt
-@itemx -mno-powerpc-gpopt
-@itemx -mpowerpc-gfxopt
-@itemx -mno-powerpc-gfxopt
-@need 800
-@itemx -mpowerpc64
-@itemx -mno-powerpc64
-@itemx -mmfcrf
-@itemx -mno-mfcrf
-@itemx -mpopcntb
-@itemx -mno-popcntb
-@itemx -mpopcntd
-@itemx -mno-popcntd
-@itemx -mfprnd
-@itemx -mno-fprnd
-@need 800
-@itemx -mcmpb
-@itemx -mno-cmpb
-@itemx -mmfpgpr
-@itemx -mno-mfpgpr
-@itemx -mhard-dfp
-@itemx -mno-hard-dfp
-@opindex mpowerpc-gpopt
-@opindex mno-powerpc-gpopt
-@opindex mpowerpc-gfxopt
-@opindex mno-powerpc-gfxopt
-@opindex mpowerpc64
-@opindex mno-powerpc64
-@opindex mmfcrf
-@opindex mno-mfcrf
-@opindex mpopcntb
-@opindex mno-popcntb
-@opindex mpopcntd
-@opindex mno-popcntd
-@opindex mfprnd
-@opindex mno-fprnd
-@opindex mcmpb
-@opindex mno-cmpb
-@opindex mmfpgpr
-@opindex mno-mfpgpr
-@opindex mhard-dfp
-@opindex mno-hard-dfp
-You use these options to specify which instructions are available on the
-processor you are using. The default value of these options is
-determined when configuring GCC@. Specifying the
-@option{-mcpu=@var{cpu_type}} overrides the specification of these
-options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
-rather than the options listed above.
+This option is also passed on to the assembler.
-Specifying @option{-mpowerpc-gpopt} allows
-GCC to use the optional PowerPC architecture instructions in the
-General Purpose group, including floating-point square root. Specifying
-@option{-mpowerpc-gfxopt} allows GCC to
-use the optional PowerPC architecture instructions in the Graphics
-group, including floating-point select.
+@item -mwarn-mcu
+@itemx -mno-warn-mcu
+@opindex mwarn-mcu
+@opindex mno-warn-mcu
+This option enables or disables warnings about conflicts between the
+MCU name specified by the @option{-mmcu} option and the ISA set by the
+@option{-mcpu} option and/or the hardware multiply support set by the
+@option{-mhwmult} option. It also toggles warnings about unrecognised
+MCU names. This option is on by default.
-The @option{-mmfcrf} option allows GCC to generate the move from
-condition register field instruction implemented on the POWER4
-processor and other processors that support the PowerPC V2.01
-architecture.
-The @option{-mpopcntb} option allows GCC to generate the popcount and
-double-precision FP reciprocal estimate instruction implemented on the
-POWER5 processor and other processors that support the PowerPC V2.02
-architecture.
-The @option{-mpopcntd} option allows GCC to generate the popcount
-instruction implemented on the POWER7 processor and other processors
-that support the PowerPC V2.06 architecture.
-The @option{-mfprnd} option allows GCC to generate the FP round to
-integer instructions implemented on the POWER5+ processor and other
-processors that support the PowerPC V2.03 architecture.
-The @option{-mcmpb} option allows GCC to generate the compare bytes
-instruction implemented on the POWER6 processor and other processors
-that support the PowerPC V2.05 architecture.
-The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
-general-purpose register instructions implemented on the POWER6X
-processor and other processors that support the extended PowerPC V2.05
-architecture.
-The @option{-mhard-dfp} option allows GCC to generate the decimal
-floating-point instructions implemented on some POWER processors.
+@item -mcpu=
+@opindex mcpu=
+Specifies the ISA to use. Accepted values are @samp{msp430},
+@samp{msp430x} and @samp{msp430xv2}. This option is deprecated. The
+@option{-mmcu=} option should be used to select the ISA.
-The @option{-mpowerpc64} option allows GCC to generate the additional
-64-bit instructions that are found in the full PowerPC64 architecture
-and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
-@option{-mno-powerpc64}.
+@item -msim
+@opindex msim
+Link to the simulator runtime libraries and linker script. Overrides
+any scripts that would be selected by the @option{-mmcu=} option.
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set architecture type, register usage, and
-instruction scheduling parameters for machine type @var{cpu_type}.
-Supported values for @var{cpu_type} are @samp{401}, @samp{403},
-@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
-@samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603},
-@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
-@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
-@samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
-@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
-@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
-@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
-@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
-and @samp{rs64}.
+@item -mlarge
+@opindex mlarge
+Use large-model addressing (20-bit pointers, 32-bit @code{size_t}).
-@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
-@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
-endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC
-architecture machine types, with an appropriate, generic processor
-model assumed for scheduling purposes.
+@item -msmall
+@opindex msmall
+Use small-model addressing (16-bit pointers, 16-bit @code{size_t}).
-The other options specify a specific processor. Code generated under
-those options runs best on that processor, and may not run at all on
-others.
+@item -mrelax
+@opindex mrelax
+This option is passed to the assembler and linker, and allows the
+linker to perform certain optimizations that cannot be done until
+the final link.
-The @option{-mcpu} options automatically enable or disable the
-following options:
+@item mhwmult=
+@opindex mhwmult=
+Describes the type of hardware multiply supported by the target.
+Accepted values are @samp{none} for no hardware multiply, @samp{16bit}
+for the original 16-bit-only multiply supported by early MCUs.
+@samp{32bit} for the 16/32-bit multiply supported by later MCUs and
+@samp{f5series} for the 16/32-bit multiply supported by F5-series MCUs.
+A value of @samp{auto} can also be given. This tells GCC to deduce
+the hardware multiply support based upon the MCU name provided by the
+@option{-mmcu} option. If no @option{-mmcu} option is specified or if
+the MCU name is not recognised then no hardware multiply support is
+assumed. @code{auto} is the default setting.
-@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
--mpopcntb -mpopcntd -mpowerpc64 @gol
--mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
--msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
--mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
--mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
--mpower9-fusion -mpower9-vector}
+Hardware multiplies are normally performed by calling a library
+routine. This saves space in the generated code. When compiling at
+@option{-O3} or higher however the hardware multiplier is invoked
+inline. This makes for bigger, but faster code.
-The particular options set for any particular CPU varies between
-compiler versions, depending on what setting seems to produce optimal
-code for that CPU; it doesn't necessarily reflect the actual hardware's
-capabilities. If you wish to set an individual option to a particular
-value, you may specify it after the @option{-mcpu} option, like
-@option{-mcpu=970 -mno-altivec}.
+The hardware multiply routines disable interrupts whilst running and
+restore the previous interrupt state when they finish. This makes
+them safe to use inside interrupt handlers as well as in normal code.
-On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
-not enabled or disabled by the @option{-mcpu} option at present because
-AIX does not have full support for these options. You may still
-enable or disable them individually if you're sure it'll work in your
-environment.
+@item -minrt
+@opindex minrt
+Enable the use of a minimum runtime environment - no static
+initializers or constructors. This is intended for memory-constrained
+devices. The compiler includes special symbols in some objects
+that tell the linker and runtime which code fragments are required.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set the instruction scheduling parameters for machine type
-@var{cpu_type}, but do not set the architecture type or register usage,
-as @option{-mcpu=@var{cpu_type}} does. The same
-values for @var{cpu_type} are used for @option{-mtune} as for
-@option{-mcpu}. If both are specified, the code generated uses the
-architecture and registers set by @option{-mcpu}, but the
-scheduling parameters set by @option{-mtune}.
+@item -mcode-region=
+@itemx -mdata-region=
+@opindex mcode-region
+@opindex mdata-region
+These options tell the compiler where to place functions and data that
+do not have one of the @code{lower}, @code{upper}, @code{either} or
+@code{section} attributes. Possible values are @code{lower},
+@code{upper}, @code{either} or @code{any}. The first three behave
+like the corresponding attribute. The fourth possible value -
+@code{any} - is the default. It leaves placement entirely up to the
+linker script and how it assigns the standard sections (.text, .data
+etc) to the memory regions.
-@item -mcmodel=small
-@opindex mcmodel=small
-Generate PowerPC64 code for the small model: The TOC is limited to
-64k.
+@item -msilicon-errata=
+@opindex msilicon-errata
+This option passes on a request to assembler to enable the fixes for
+the named silicon errata.
-@item -mcmodel=medium
-@opindex mcmodel=medium
-Generate PowerPC64 code for the medium model: The TOC and other static
-data may be up to a total of 4G in size.
+@item -msilicon-errata-warn=
+@opindex msilicon-errata-warn
+This option passes on a request to the assembler to enable warning
+messages when a silicon errata might need to be applied.
-@item -mcmodel=large
-@opindex mcmodel=large
-Generate PowerPC64 code for the large model: The TOC may be up to 4G
-in size. Other data and code is only limited by the 64-bit address
-space.
+@end table
-@item -maltivec
-@itemx -mno-altivec
-@opindex maltivec
-@opindex mno-altivec
-Generate code that uses (does not use) AltiVec instructions, and also
-enable the use of built-in functions that allow more direct access to
-the AltiVec instruction set. You may also need to set
-@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
-enhancements.
+@node NDS32 Options
+@subsection NDS32 Options
+@cindex NDS32 Options
-When @option{-maltivec} is used, rather than @option{-maltivec=le} or
-@option{-maltivec=be}, the element order for Altivec intrinsics such
-as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert}
-match array element order corresponding to the endianness of the
-target. That is, element zero identifies the leftmost element in a
-vector register when targeting a big-endian platform, and identifies
-the rightmost element in a vector register when targeting a
-little-endian platform.
+These options are defined for NDS32 implementations:
-@item -maltivec=be
-@opindex maltivec=be
-Generate Altivec instructions using big-endian element order,
-regardless of whether the target is big- or little-endian. This is
-the default when targeting a big-endian platform.
+@table @gcctabopt
-The element order is used to interpret element numbers in Altivec
-intrinsics such as @code{vec_splat}, @code{vec_extract}, and
-@code{vec_insert}. By default, these match array element order
-corresponding to the endianness for the target.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code in big-endian mode.
-@item -maltivec=le
-@opindex maltivec=le
-Generate Altivec instructions using little-endian element order,
-regardless of whether the target is big- or little-endian. This is
-the default when targeting a little-endian platform. This option is
-currently ignored when targeting a big-endian platform.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code in little-endian mode.
-The element order is used to interpret element numbers in Altivec
-intrinsics such as @code{vec_splat}, @code{vec_extract}, and
-@code{vec_insert}. By default, these match array element order
-corresponding to the endianness for the target.
+@item -mreduced-regs
+@opindex mreduced-regs
+Use reduced-set registers for register allocation.
-@item -mvrsave
-@itemx -mno-vrsave
-@opindex mvrsave
-@opindex mno-vrsave
-Generate VRSAVE instructions when generating AltiVec code.
+@item -mfull-regs
+@opindex mfull-regs
+Use full-set registers for register allocation.
-@item -mgen-cell-microcode
-@opindex mgen-cell-microcode
-Generate Cell microcode instructions.
+@item -mcmov
+@opindex mcmov
+Generate conditional move instructions.
-@item -mwarn-cell-microcode
-@opindex mwarn-cell-microcode
-Warn when a Cell microcode instruction is emitted. An example
-of a Cell microcode instruction is a variable shift.
+@item -mno-cmov
+@opindex mno-cmov
+Do not generate conditional move instructions.
-@item -msecure-plt
-@opindex msecure-plt
-Generate code that allows @command{ld} and @command{ld.so}
-to build executables and shared
-libraries with non-executable @code{.plt} and @code{.got} sections.
-This is a PowerPC
-32-bit SYSV ABI option.
+@item -mperf-ext
+@opindex mperf-ext
+Generate performance extension instructions.
-@item -mbss-plt
-@opindex mbss-plt
-Generate code that uses a BSS @code{.plt} section that @command{ld.so}
-fills in, and
-requires @code{.plt} and @code{.got}
-sections that are both writable and executable.
-This is a PowerPC 32-bit SYSV ABI option.
+@item -mno-perf-ext
+@opindex mno-perf-ext
+Do not generate performance extension instructions.
-@item -misel
-@itemx -mno-isel
-@opindex misel
-@opindex mno-isel
-This switch enables or disables the generation of ISEL instructions.
+@item -mv3push
+@opindex mv3push
+Generate v3 push25/pop25 instructions.
-@item -misel=@var{yes/no}
-This switch has been deprecated. Use @option{-misel} and
-@option{-mno-isel} instead.
+@item -mno-v3push
+@opindex mno-v3push
+Do not generate v3 push25/pop25 instructions.
-@item -mspe
-@itemx -mno-spe
-@opindex mspe
-@opindex mno-spe
-This switch enables or disables the generation of SPE simd
-instructions.
+@item -m16-bit
+@opindex m16-bit
+Generate 16-bit instructions.
-@item -mpaired
-@itemx -mno-paired
-@opindex mpaired
-@opindex mno-paired
-This switch enables or disables the generation of PAIRED simd
-instructions.
+@item -mno-16-bit
+@opindex mno-16-bit
+Do not generate 16-bit instructions.
-@item -mspe=@var{yes/no}
-This option has been deprecated. Use @option{-mspe} and
-@option{-mno-spe} instead.
+@item -misr-vector-size=@var{num}
+@opindex misr-vector-size
+Specify the size of each interrupt vector, which must be 4 or 16.
-@item -mvsx
-@itemx -mno-vsx
-@opindex mvsx
-@opindex mno-vsx
-Generate code that uses (does not use) vector/scalar (VSX)
-instructions, and also enable the use of built-in functions that allow
-more direct access to the VSX instruction set.
+@item -mcache-block-size=@var{num}
+@opindex mcache-block-size
+Specify the size of each cache block,
+which must be a power of 2 between 4 and 512.
-@item -mcrypto
-@itemx -mno-crypto
-@opindex mcrypto
-@opindex mno-crypto
-Enable the use (disable) of the built-in functions that allow direct
-access to the cryptographic instructions that were added in version
-2.07 of the PowerPC ISA.
+@item -march=@var{arch}
+@opindex march
+Specify the name of the target architecture.
-@item -mdirect-move
-@itemx -mno-direct-move
-@opindex mdirect-move
-@opindex mno-direct-move
-Generate code that uses (does not use) the instructions to move data
-between the general purpose registers and the vector/scalar (VSX)
-registers that were added in version 2.07 of the PowerPC ISA.
+@item -mcmodel=@var{code-model}
+@opindex mcmodel
+Set the code model to one of
+@table @asis
+@item @samp{small}
+All the data and read-only data segments must be within 512KB addressing space.
+The text segment must be within 16MB addressing space.
+@item @samp{medium}
+The data segment must be within 512KB while the read-only data segment can be
+within 4GB addressing space. The text segment should be still within 16MB
+addressing space.
+@item @samp{large}
+All the text and data segments can be within 4GB addressing space.
+@end table
-@item -mpower8-fusion
-@itemx -mno-power8-fusion
-@opindex mpower8-fusion
-@opindex mno-power8-fusion
-Generate code that keeps (does not keeps) some integer operations
-adjacent so that the instructions can be fused together on power8 and
-later processors.
+@item -mctor-dtor
+@opindex mctor-dtor
+Enable constructor/destructor feature.
-@item -mpower8-vector
-@itemx -mno-power8-vector
-@opindex mpower8-vector
-@opindex mno-power8-vector
-Generate code that uses (does not use) the vector and scalar
-instructions that were added in version 2.07 of the PowerPC ISA. Also
-enable the use of built-in functions that allow more direct access to
-the vector instructions.
-
-@item -mquad-memory
-@itemx -mno-quad-memory
-@opindex mquad-memory
-@opindex mno-quad-memory
-Generate code that uses (does not use) the non-atomic quad word memory
-instructions. The @option{-mquad-memory} option requires use of
-64-bit mode.
+@item -mrelax
+@opindex mrelax
+Guide linker to relax instructions.
-@item -mquad-memory-atomic
-@itemx -mno-quad-memory-atomic
-@opindex mquad-memory-atomic
-@opindex mno-quad-memory-atomic
-Generate code that uses (does not use) the atomic quad word memory
-instructions. The @option{-mquad-memory-atomic} option requires use of
-64-bit mode.
+@end table
-@item -mupper-regs-df
-@itemx -mno-upper-regs-df
-@opindex mupper-regs-df
-@opindex mno-upper-regs-df
-Generate code that uses (does not use) the scalar double precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.06 of the
-PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you
-use any of the @option{-mcpu=power7}, @option{-mcpu=power8}, or
-@option{-mvsx} options.
+@node Nios II Options
+@subsection Nios II Options
+@cindex Nios II options
+@cindex Altera Nios II options
-@item -mupper-regs-sf
-@itemx -mno-upper-regs-sf
-@opindex mupper-regs-sf
-@opindex mno-upper-regs-sf
-Generate code that uses (does not use) the scalar single precision
-instructions that target all 64 registers in the vector/scalar
-floating point register set that were added in version 2.07 of the
-PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
-use either of the @option{-mcpu=power8} or @option{-mpower8-vector}
-options.
+These are the options defined for the Altera Nios II processor.
-@item -mupper-regs
-@itemx -mno-upper-regs
-@opindex mupper-regs
-@opindex mno-upper-regs
-Generate code that uses (does not use) the scalar
-instructions that target all 64 registers in the vector/scalar
-floating point register set, depending on the model of the machine.
+@table @gcctabopt
-If the @option{-mno-upper-regs} option is used, it turns off both
-@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
+@item -G @var{num}
+@opindex G
+@cindex smaller data references
+Put global and static objects less than or equal to @var{num} bytes
+into the small data or BSS sections instead of the normal data or BSS
+sections. The default value of @var{num} is 8.
-@item -mfloat128
-@itemx -mno-float128
-@opindex mfloat128
-@opindex mno-float128
-Enable/disable the @var{__float128} keyword for IEEE 128-bit floating point
-and use either software emulation for IEEE 128-bit floating point or
-hardware instructions.
+@item -mgpopt=@var{option}
+@item -mgpopt
+@itemx -mno-gpopt
+@opindex mgpopt
+@opindex mno-gpopt
+Generate (do not generate) GP-relative accesses. The following
+@var{option} names are recognized:
-The VSX instruction set (@option{-mvsx}, @option{-mcpu=power7}, or
-@option{-mcpu=power8}) must be enabled to use the @option{-mfloat128}
-option. The @code{-mfloat128} option only works on PowerPC 64-bit
-Linux systems.
+@table @samp
-@item -mfloat128-hardware
-@itemx -mno-float128-hardware
-@opindex mfloat128-hardware
-@opindex mno-float128-hardware
-Enable/disable using ISA 3.0 hardware instructions to support the
-@var{__float128} data type.
+@item none
+Do not generate GP-relative accesses.
-@item -mmodulo
-@itemx -mno-modulo
-@opindex mmodulo
-@opindex mno-module
-Generate code that uses (does not use) the ISA 3.0 integer modulo
-instructions. The @option{-mmodulo} option is enabled by default
-with the @option{-mcpu=power9} option.
+@item local
+Generate GP-relative accesses for small data objects that are not
+external, weak, or uninitialized common symbols.
+Also use GP-relative addressing for objects that
+have been explicitly placed in a small data section via a @code{section}
+attribute.
-@item -mpower9-fusion
-@itemx -mno-power9-fusion
-@opindex mpower9-fusion
-@opindex mno-power9-fusion
-Generate code that keeps (does not keeps) some operations adjacent so
-that the instructions can be fused together on power9 and later
-processors.
+@item global
+As for @samp{local}, but also generate GP-relative accesses for
+small data objects that are external, weak, or common. If you use this option,
+you must ensure that all parts of your program (including libraries) are
+compiled with the same @option{-G} setting.
-@item -mpower9-vector
-@itemx -mno-power9-vector
-@opindex mpower9-vector
-@opindex mno-power9-vector
-Generate code that uses (does not use) the vector and scalar
-instructions that were added in version 2.07 of the PowerPC ISA. Also
-enable the use of built-in functions that allow more direct access to
-the vector instructions.
+@item data
+Generate GP-relative accesses for all data objects in the program. If you
+use this option, the entire data and BSS segments
+of your program must fit in 64K of memory and you must use an appropriate
+linker script to allocate them within the addressible range of the
+global pointer.
-@item -mfloat-gprs=@var{yes/single/double/no}
-@itemx -mfloat-gprs
-@opindex mfloat-gprs
-This switch enables or disables the generation of floating-point
-operations on the general-purpose registers for architectures that
-support it.
+@item all
+Generate GP-relative addresses for function pointers as well as data
+pointers. If you use this option, the entire text, data, and BSS segments
+of your program must fit in 64K of memory and you must use an appropriate
+linker script to allocate them within the addressible range of the
+global pointer.
-The argument @samp{yes} or @samp{single} enables the use of
-single-precision floating-point operations.
+@end table
-The argument @samp{double} enables the use of single and
-double-precision floating-point operations.
+@option{-mgpopt} is equivalent to @option{-mgpopt=local}, and
+@option{-mno-gpopt} is equivalent to @option{-mgpopt=none}.
-The argument @samp{no} disables floating-point operations on the
-general-purpose registers.
+The default is @option{-mgpopt} except when @option{-fpic} or
+@option{-fPIC} is specified to generate position-independent code.
+Note that the Nios II ABI does not permit GP-relative accesses from
+shared libraries.
-This option is currently only available on the MPC854x.
+You may need to specify @option{-mno-gpopt} explicitly when building
+programs that include large amounts of small data, including large
+GOT data sections. In this case, the 16-bit offset for GP-relative
+addressing may not be large enough to allow access to the entire
+small data section.
-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for 32-bit or 64-bit environments of Darwin and SVR4
-targets (including GNU/Linux). The 32-bit environment sets int, long
-and pointer to 32 bits and generates code that runs on any PowerPC
-variant. The 64-bit environment sets int to 32 bits and long and
-pointer to 64 bits, and generates code for PowerPC64, as for
-@option{-mpowerpc64}.
+@item -mel
+@itemx -meb
+@opindex mel
+@opindex meb
+Generate little-endian (default) or big-endian (experimental) code,
+respectively.
-@item -mfull-toc
-@itemx -mno-fp-in-toc
-@itemx -mno-sum-in-toc
-@itemx -mminimal-toc
-@opindex mfull-toc
-@opindex mno-fp-in-toc
-@opindex mno-sum-in-toc
-@opindex mminimal-toc
-Modify generation of the TOC (Table Of Contents), which is created for
-every executable file. The @option{-mfull-toc} option is selected by
-default. In that case, GCC allocates at least one TOC entry for
-each unique non-automatic variable reference in your program. GCC
-also places floating-point constants in the TOC@. However, only
-16,384 entries are available in the TOC@.
+@item -march=@var{arch}
+@opindex march
+This specifies the name of the target Nios II architecture. GCC uses this
+name to determine what kind of instructions it can emit when generating
+assembly code. Permissible names are: @samp{r1}, @samp{r2}.
-If you receive a linker error message that saying you have overflowed
-the available TOC space, you can reduce the amount of TOC space used
-with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
-@option{-mno-fp-in-toc} prevents GCC from putting floating-point
-constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
-generate code to calculate the sum of an address and a constant at
-run time instead of putting that sum into the TOC@. You may specify one
-or both of these options. Each causes GCC to produce very slightly
-slower and larger code at the expense of conserving TOC space.
+The preprocessor macro @code{__nios2_arch__} is available to programs,
+with value 1 or 2, indicating the targeted ISA level.
-If you still run out of space in the TOC even when you specify both of
-these options, specify @option{-mminimal-toc} instead. This option causes
-GCC to make only one TOC entry for every file. When you specify this
-option, GCC produces code that is slower and larger but which
-uses extremely little TOC space. You may wish to use this option
-only on files that contain less frequently-executed code.
+@item -mbypass-cache
+@itemx -mno-bypass-cache
+@opindex mno-bypass-cache
+@opindex mbypass-cache
+Force all load and store instructions to always bypass cache by
+using I/O variants of the instructions. The default is not to
+bypass the cache.
-@item -maix64
-@itemx -maix32
-@opindex maix64
-@opindex maix32
-Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
-@code{long} type, and the infrastructure needed to support them.
-Specifying @option{-maix64} implies @option{-mpowerpc64},
-while @option{-maix32} disables the 64-bit ABI and
-implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
+@item -mno-cache-volatile
+@itemx -mcache-volatile
+@opindex mcache-volatile
+@opindex mno-cache-volatile
+Volatile memory access bypass the cache using the I/O variants of
+the load and store instructions. The default is not to bypass the cache.
-@item -mxl-compat
-@itemx -mno-xl-compat
-@opindex mxl-compat
-@opindex mno-xl-compat
-Produce code that conforms more closely to IBM XL compiler semantics
-when using AIX-compatible ABI@. Pass floating-point arguments to
-prototyped functions beyond the register save area (RSA) on the stack
-in addition to argument FPRs. Do not assume that most significant
-double in 128-bit long double value is properly rounded when comparing
-values and converting to double. Use XL symbol names for long double
-support routines.
+@item -mno-fast-sw-div
+@itemx -mfast-sw-div
+@opindex mno-fast-sw-div
+@opindex mfast-sw-div
+Do not use table-based fast divide for small numbers. The default
+is to use the fast divide at @option{-O3} and above.
-The AIX calling convention was extended but not initially documented to
-handle an obscure K&R C case of calling a function that takes the
-address of its arguments with fewer arguments than declared. IBM XL
-compilers access floating-point arguments that do not fit in the
-RSA from the stack when a subroutine is compiled without
-optimization. Because always storing floating-point arguments on the
-stack is inefficient and rarely needed, this option is not enabled by
-default and only is necessary when calling subroutines compiled by IBM
-XL compilers without optimization.
+@item -mno-hw-mul
+@itemx -mhw-mul
+@itemx -mno-hw-mulx
+@itemx -mhw-mulx
+@itemx -mno-hw-div
+@itemx -mhw-div
+@opindex mno-hw-mul
+@opindex mhw-mul
+@opindex mno-hw-mulx
+@opindex mhw-mulx
+@opindex mno-hw-div
+@opindex mhw-div
+Enable or disable emitting @code{mul}, @code{mulx} and @code{div} family of
+instructions by the compiler. The default is to emit @code{mul}
+and not emit @code{div} and @code{mulx}.
-@item -mpe
-@opindex mpe
-Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
-application written to use message passing with special startup code to
-enable the application to run. The system must have PE installed in the
-standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
-must be overridden with the @option{-specs=} option to specify the
-appropriate directory location. The Parallel Environment does not
-support threads, so the @option{-mpe} option and the @option{-pthread}
-option are incompatible.
+@item -mbmx
+@itemx -mno-bmx
+@itemx -mcdx
+@itemx -mno-cdx
+Enable or disable generation of Nios II R2 BMX (bit manipulation) and
+CDX (code density) instructions. Enabling these instructions also
+requires @option{-march=r2}. Since these instructions are optional
+extensions to the R2 architecture, the default is not to emit them.
-@item -malign-natural
-@itemx -malign-power
-@opindex malign-natural
-@opindex malign-power
-On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option
-@option{-malign-natural} overrides the ABI-defined alignment of larger
-types, such as floating-point doubles, on their natural size-based boundary.
-The option @option{-malign-power} instructs GCC to follow the ABI-specified
-alignment rules. GCC defaults to the standard alignment defined in the ABI@.
+@item -mcustom-@var{insn}=@var{N}
+@itemx -mno-custom-@var{insn}
+@opindex mcustom-@var{insn}
+@opindex mno-custom-@var{insn}
+Each @option{-mcustom-@var{insn}=@var{N}} option enables use of a
+custom instruction with encoding @var{N} when generating code that uses
+@var{insn}. For example, @option{-mcustom-fadds=253} generates custom
+instruction 253 for single-precision floating-point add operations instead
+of the default behavior of using a library call.
-On 64-bit Darwin, natural alignment is the default, and @option{-malign-power}
-is not supported.
+The following values of @var{insn} are supported. Except as otherwise
+noted, floating-point operations are expected to be implemented with
+normal IEEE 754 semantics and correspond directly to the C operators or the
+equivalent GCC built-in functions (@pxref{Other Builtins}).
-@item -msoft-float
-@itemx -mhard-float
-@opindex msoft-float
-@opindex mhard-float
-Generate code that does not use (uses) the floating-point register set.
-Software floating-point emulation is provided if you use the
-@option{-msoft-float} option, and pass the option to GCC when linking.
+Single-precision floating point:
+@table @asis
-@item -msingle-float
-@itemx -mdouble-float
-@opindex msingle-float
-@opindex mdouble-float
-Generate code for single- or double-precision floating-point operations.
-@option{-mdouble-float} implies @option{-msingle-float}.
+@item @samp{fadds}, @samp{fsubs}, @samp{fdivs}, @samp{fmuls}
+Binary arithmetic operations.
-@item -msimple-fpu
-@opindex msimple-fpu
-Do not generate @code{sqrt} and @code{div} instructions for hardware
-floating-point unit.
+@item @samp{fnegs}
+Unary negation.
-@item -mfpu=@var{name}
-@opindex mfpu
-Specify type of floating-point unit. Valid values for @var{name} are
-@samp{sp_lite} (equivalent to @option{-msingle-float -msimple-fpu}),
-@samp{dp_lite} (equivalent to @option{-mdouble-float -msimple-fpu}),
-@samp{sp_full} (equivalent to @option{-msingle-float}),
-and @samp{dp_full} (equivalent to @option{-mdouble-float}).
+@item @samp{fabss}
+Unary absolute value.
-@item -mxilinx-fpu
-@opindex mxilinx-fpu
-Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
+@item @samp{fcmpeqs}, @samp{fcmpges}, @samp{fcmpgts}, @samp{fcmples}, @samp{fcmplts}, @samp{fcmpnes}
+Comparison operations.
-@item -mmultiple
-@itemx -mno-multiple
-@opindex mmultiple
-@opindex mno-multiple
-Generate code that uses (does not use) the load multiple word
-instructions and the store multiple word instructions. These
-instructions are generated by default on POWER systems, and not
-generated on PowerPC systems. Do not use @option{-mmultiple} on little-endian
-PowerPC systems, since those instructions do not work when the
-processor is in little-endian mode. The exceptions are PPC740 and
-PPC750 which permit these instructions in little-endian mode.
+@item @samp{fmins}, @samp{fmaxs}
+Floating-point minimum and maximum. These instructions are only
+generated if @option{-ffinite-math-only} is specified.
-@item -mstring
-@itemx -mno-string
-@opindex mstring
-@opindex mno-string
-Generate code that uses (does not use) the load string instructions
-and the store string word instructions to save multiple registers and
-do small block moves. These instructions are generated by default on
-POWER systems, and not generated on PowerPC systems. Do not use
-@option{-mstring} on little-endian PowerPC systems, since those
-instructions do not work when the processor is in little-endian mode.
-The exceptions are PPC740 and PPC750 which permit these instructions
-in little-endian mode.
+@item @samp{fsqrts}
+Unary square root operation.
-@item -mupdate
-@itemx -mno-update
-@opindex mupdate
-@opindex mno-update
-Generate code that uses (does not use) the load or store instructions
-that update the base register to the address of the calculated memory
-location. These instructions are generated by default. If you use
-@option{-mno-update}, there is a small window between the time that the
-stack pointer is updated and the address of the previous frame is
-stored, which means code that walks the stack frame across interrupts or
-signals may get corrupted data.
+@item @samp{fcoss}, @samp{fsins}, @samp{ftans}, @samp{fatans}, @samp{fexps}, @samp{flogs}
+Floating-point trigonometric and exponential functions. These instructions
+are only generated if @option{-funsafe-math-optimizations} is also specified.
-@item -mavoid-indexed-addresses
-@itemx -mno-avoid-indexed-addresses
-@opindex mavoid-indexed-addresses
-@opindex mno-avoid-indexed-addresses
-Generate code that tries to avoid (not avoid) the use of indexed load
-or store instructions. These instructions can incur a performance
-penalty on Power6 processors in certain situations, such as when
-stepping through large arrays that cross a 16M boundary. This option
-is enabled by default when targeting Power6 and disabled otherwise.
+@end table
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Generate code that uses (does not use) the floating-point multiply and
-accumulate instructions. These instructions are generated by default
-if hardware floating point is used. The machine-dependent
-@option{-mfused-madd} option is now mapped to the machine-independent
-@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
-mapped to @option{-ffp-contract=off}.
+Double-precision floating point:
+@table @asis
-@item -mmulhw
-@itemx -mno-mulhw
-@opindex mmulhw
-@opindex mno-mulhw
-Generate code that uses (does not use) the half-word multiply and
-multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
-These instructions are generated by default when targeting those
-processors.
+@item @samp{faddd}, @samp{fsubd}, @samp{fdivd}, @samp{fmuld}
+Binary arithmetic operations.
-@item -mdlmzb
-@itemx -mno-dlmzb
-@opindex mdlmzb
-@opindex mno-dlmzb
-Generate code that uses (does not use) the string-search @samp{dlmzb}
-instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
-generated by default when targeting those processors.
+@item @samp{fnegd}
+Unary negation.
-@item -mno-bit-align
-@itemx -mbit-align
-@opindex mno-bit-align
-@opindex mbit-align
-On System V.4 and embedded PowerPC systems do not (do) force structures
-and unions that contain bit-fields to be aligned to the base type of the
-bit-field.
+@item @samp{fabsd}
+Unary absolute value.
-For example, by default a structure containing nothing but 8
-@code{unsigned} bit-fields of length 1 is aligned to a 4-byte
-boundary and has a size of 4 bytes. By using @option{-mno-bit-align},
-the structure is aligned to a 1-byte boundary and is 1 byte in
-size.
+@item @samp{fcmpeqd}, @samp{fcmpged}, @samp{fcmpgtd}, @samp{fcmpled}, @samp{fcmpltd}, @samp{fcmpned}
+Comparison operations.
-@item -mno-strict-align
-@itemx -mstrict-align
-@opindex mno-strict-align
-@opindex mstrict-align
-On System V.4 and embedded PowerPC systems do not (do) assume that
-unaligned memory references are handled by the system.
+@item @samp{fmind}, @samp{fmaxd}
+Double-precision minimum and maximum. These instructions are only
+generated if @option{-ffinite-math-only} is specified.
-@item -mrelocatable
-@itemx -mno-relocatable
-@opindex mrelocatable
-@opindex mno-relocatable
-Generate code that allows (does not allow) a static executable to be
-relocated to a different address at run time. A simple embedded
-PowerPC system loader should relocate the entire contents of
-@code{.got2} and 4-byte locations listed in the @code{.fixup} section,
-a table of 32-bit addresses generated by this option. For this to
-work, all objects linked together must be compiled with
-@option{-mrelocatable} or @option{-mrelocatable-lib}.
-@option{-mrelocatable} code aligns the stack to an 8-byte boundary.
+@item @samp{fsqrtd}
+Unary square root operation.
-@item -mrelocatable-lib
-@itemx -mno-relocatable-lib
-@opindex mrelocatable-lib
-@opindex mno-relocatable-lib
-Like @option{-mrelocatable}, @option{-mrelocatable-lib} generates a
-@code{.fixup} section to allow static executables to be relocated at
-run time, but @option{-mrelocatable-lib} does not use the smaller stack
-alignment of @option{-mrelocatable}. Objects compiled with
-@option{-mrelocatable-lib} may be linked with objects compiled with
-any combination of the @option{-mrelocatable} options.
+@item @samp{fcosd}, @samp{fsind}, @samp{ftand}, @samp{fatand}, @samp{fexpd}, @samp{flogd}
+Double-precision trigonometric and exponential functions. These instructions
+are only generated if @option{-funsafe-math-optimizations} is also specified.
-@item -mno-toc
-@itemx -mtoc
-@opindex mno-toc
-@opindex mtoc
-On System V.4 and embedded PowerPC systems do not (do) assume that
-register 2 contains a pointer to a global area pointing to the addresses
-used in the program.
+@end table
-@item -mlittle
-@itemx -mlittle-endian
-@opindex mlittle
-@opindex mlittle-endian
-On System V.4 and embedded PowerPC systems compile code for the
-processor in little-endian mode. The @option{-mlittle-endian} option is
-the same as @option{-mlittle}.
+Conversions:
+@table @asis
+@item @samp{fextsd}
+Conversion from single precision to double precision.
-@item -mbig
-@itemx -mbig-endian
-@opindex mbig
-@opindex mbig-endian
-On System V.4 and embedded PowerPC systems compile code for the
-processor in big-endian mode. The @option{-mbig-endian} option is
-the same as @option{-mbig}.
+@item @samp{ftruncds}
+Conversion from double precision to single precision.
-@item -mdynamic-no-pic
-@opindex mdynamic-no-pic
-On Darwin and Mac OS X systems, compile code so that it is not
-relocatable, but that its external references are relocatable. The
-resulting code is suitable for applications, but not shared
-libraries.
+@item @samp{fixsi}, @samp{fixsu}, @samp{fixdi}, @samp{fixdu}
+Conversion from floating point to signed or unsigned integer types, with
+truncation towards zero.
-@item -msingle-pic-base
-@opindex msingle-pic-base
-Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The runtime system is
-responsible for initializing this register with an appropriate value
-before execution begins.
+@item @samp{round}
+Conversion from single-precision floating point to signed integer,
+rounding to the nearest integer and ties away from zero.
+This corresponds to the @code{__builtin_lroundf} function when
+@option{-fno-math-errno} is used.
-@item -mprioritize-restricted-insns=@var{priority}
-@opindex mprioritize-restricted-insns
-This option controls the priority that is assigned to
-dispatch-slot restricted instructions during the second scheduling
-pass. The argument @var{priority} takes the value @samp{0}, @samp{1},
-or @samp{2} to assign no, highest, or second-highest (respectively)
-priority to dispatch-slot restricted
-instructions.
+@item @samp{floatis}, @samp{floatus}, @samp{floatid}, @samp{floatud}
+Conversion from signed or unsigned integer types to floating-point types.
-@item -msched-costly-dep=@var{dependence_type}
-@opindex msched-costly-dep
-This option controls which dependences are considered costly
-by the target during instruction scheduling. The argument
-@var{dependence_type} takes one of the following values:
+@end table
+
+In addition, all of the following transfer instructions for internal
+registers X and Y must be provided to use any of the double-precision
+floating-point instructions. Custom instructions taking two
+double-precision source operands expect the first operand in the
+64-bit register X. The other operand (or only operand of a unary
+operation) is given to the custom arithmetic instruction with the
+least significant half in source register @var{src1} and the most
+significant half in @var{src2}. A custom instruction that returns a
+double-precision result returns the most significant 32 bits in the
+destination register and the other half in 32-bit register Y.
+GCC automatically generates the necessary code sequences to write
+register X and/or read register Y when double-precision floating-point
+instructions are used.
@table @asis
-@item @samp{no}
-No dependence is costly.
-@item @samp{all}
-All dependences are costly.
+@item @samp{fwrx}
+Write @var{src1} into the least significant half of X and @var{src2} into
+the most significant half of X.
-@item @samp{true_store_to_load}
-A true dependence from store to load is costly.
+@item @samp{fwry}
+Write @var{src1} into Y.
-@item @samp{store_to_load}
-Any dependence from store to load is costly.
+@item @samp{frdxhi}, @samp{frdxlo}
+Read the most or least (respectively) significant half of X and store it in
+@var{dest}.
-@item @var{number}
-Any dependence for which the latency is greater than or equal to
-@var{number} is costly.
+@item @samp{frdy}
+Read the value of Y and store it into @var{dest}.
@end table
-@item -minsert-sched-nops=@var{scheme}
-@opindex minsert-sched-nops
-This option controls which NOP insertion scheme is used during
-the second scheduling pass. The argument @var{scheme} takes one of the
-following values:
+Note that you can gain more local control over generation of Nios II custom
+instructions by using the @code{target("custom-@var{insn}=@var{N}")}
+and @code{target("no-custom-@var{insn}")} function attributes
+(@pxref{Function Attributes})
+or pragmas (@pxref{Function Specific Option Pragmas}).
-@table @asis
-@item @samp{no}
-Don't insert NOPs.
+@item -mcustom-fpu-cfg=@var{name}
+@opindex mcustom-fpu-cfg
-@item @samp{pad}
-Pad with NOPs any dispatch group that has vacant issue slots,
-according to the scheduler's grouping.
+This option enables a predefined, named set of custom instruction encodings
+(see @option{-mcustom-@var{insn}} above).
+Currently, the following sets are defined:
-@item @samp{regroup_exact}
-Insert NOPs to force costly dependent insns into
-separate groups. Insert exactly as many NOPs as needed to force an insn
-to a new group, according to the estimated processor grouping.
+@option{-mcustom-fpu-cfg=60-1} is equivalent to:
+@gccoptlist{-mcustom-fmuls=252 @gol
+-mcustom-fadds=253 @gol
+-mcustom-fsubs=254 @gol
+-fsingle-precision-constant}
-@item @var{number}
-Insert NOPs to force costly dependent insns into
-separate groups. Insert @var{number} NOPs to force an insn to a new group.
-@end table
+@option{-mcustom-fpu-cfg=60-2} is equivalent to:
+@gccoptlist{-mcustom-fmuls=252 @gol
+-mcustom-fadds=253 @gol
+-mcustom-fsubs=254 @gol
+-mcustom-fdivs=255 @gol
+-fsingle-precision-constant}
-@item -mcall-sysv
-@opindex mcall-sysv
-On System V.4 and embedded PowerPC systems compile code using calling
-conventions that adhere to the March 1995 draft of the System V
-Application Binary Interface, PowerPC processor supplement. This is the
-default unless you configured GCC using @samp{powerpc-*-eabiaix}.
+@option{-mcustom-fpu-cfg=72-3} is equivalent to:
+@gccoptlist{-mcustom-floatus=243 @gol
+-mcustom-fixsi=244 @gol
+-mcustom-floatis=245 @gol
+-mcustom-fcmpgts=246 @gol
+-mcustom-fcmples=249 @gol
+-mcustom-fcmpeqs=250 @gol
+-mcustom-fcmpnes=251 @gol
+-mcustom-fmuls=252 @gol
+-mcustom-fadds=253 @gol
+-mcustom-fsubs=254 @gol
+-mcustom-fdivs=255 @gol
+-fsingle-precision-constant}
-@item -mcall-sysv-eabi
-@itemx -mcall-eabi
-@opindex mcall-sysv-eabi
-@opindex mcall-eabi
-Specify both @option{-mcall-sysv} and @option{-meabi} options.
+Custom instruction assignments given by individual
+@option{-mcustom-@var{insn}=} options override those given by
+@option{-mcustom-fpu-cfg=}, regardless of the
+order of the options on the command line.
-@item -mcall-sysv-noeabi
-@opindex mcall-sysv-noeabi
-Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
+Note that you can gain more local control over selection of a FPU
+configuration by using the @code{target("custom-fpu-cfg=@var{name}")}
+function attribute (@pxref{Function Attributes})
+or pragma (@pxref{Function Specific Option Pragmas}).
-@item -mcall-aixdesc
-@opindex m
-On System V.4 and embedded PowerPC systems compile code for the AIX
-operating system.
+@end table
-@item -mcall-linux
-@opindex mcall-linux
-On System V.4 and embedded PowerPC systems compile code for the
-Linux-based GNU system.
+These additional @samp{-m} options are available for the Altera Nios II
+ELF (bare-metal) target:
-@item -mcall-freebsd
-@opindex mcall-freebsd
-On System V.4 and embedded PowerPC systems compile code for the
-FreeBSD operating system.
+@table @gcctabopt
-@item -mcall-netbsd
-@opindex mcall-netbsd
-On System V.4 and embedded PowerPC systems compile code for the
-NetBSD operating system.
+@item -mhal
+@opindex mhal
+Link with HAL BSP. This suppresses linking with the GCC-provided C runtime
+startup and termination code, and is typically used in conjunction with
+@option{-msys-crt0=} to specify the location of the alternate startup code
+provided by the HAL BSP.
-@item -mcall-openbsd
-@opindex mcall-netbsd
-On System V.4 and embedded PowerPC systems compile code for the
-OpenBSD operating system.
+@item -msmallc
+@opindex msmallc
+Link with a limited version of the C library, @option{-lsmallc}, rather than
+Newlib.
-@item -maix-struct-return
-@opindex maix-struct-return
-Return all structures in memory (as specified by the AIX ABI)@.
+@item -msys-crt0=@var{startfile}
+@opindex msys-crt0
+@var{startfile} is the file name of the startfile (crt0) to use
+when linking. This option is only useful in conjunction with @option{-mhal}.
-@item -msvr4-struct-return
-@opindex msvr4-struct-return
-Return structures smaller than 8 bytes in registers (as specified by the
-SVR4 ABI)@.
+@item -msys-lib=@var{systemlib}
+@opindex msys-lib
+@var{systemlib} is the library name of the library that provides
+low-level system calls required by the C library,
+e.g. @code{read} and @code{write}.
+This option is typically used to link with a library provided by a HAL BSP.
-@item -mabi=@var{abi-type}
-@opindex mabi
-Extend the current ABI with a particular extension, or remove such extension.
-Valid values are @samp{altivec}, @samp{no-altivec}, @samp{spe},
-@samp{no-spe}, @samp{ibmlongdouble}, @samp{ieeelongdouble},
-@samp{elfv1}, @samp{elfv2}@.
+@end table
-@item -mabi=spe
-@opindex mabi=spe
-Extend the current ABI with SPE ABI extensions. This does not change
-the default ABI, instead it adds the SPE ABI extensions to the current
-ABI@.
+@node Nvidia PTX Options
+@subsection Nvidia PTX Options
+@cindex Nvidia PTX options
+@cindex nvptx options
-@item -mabi=no-spe
-@opindex mabi=no-spe
-Disable Book-E SPE ABI extensions for the current ABI@.
+These options are defined for Nvidia PTX:
-@item -mabi=ibmlongdouble
-@opindex mabi=ibmlongdouble
-Change the current ABI to use IBM extended-precision long double.
-This is a PowerPC 32-bit SYSV ABI option.
+@table @gcctabopt
-@item -mabi=ieeelongdouble
-@opindex mabi=ieeelongdouble
-Change the current ABI to use IEEE extended-precision long double.
-This is a PowerPC 32-bit Linux ABI option.
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for 32-bit or 64-bit ABI.
-@item -mabi=elfv1
-@opindex mabi=elfv1
-Change the current ABI to use the ELFv1 ABI.
-This is the default ABI for big-endian PowerPC 64-bit Linux.
-Overriding the default ABI requires special system support and is
-likely to fail in spectacular ways.
+@item -mmainkernel
+@opindex mmainkernel
+Link in code for a __main kernel. This is for stand-alone instead of
+offloading execution.
-@item -mabi=elfv2
-@opindex mabi=elfv2
-Change the current ABI to use the ELFv2 ABI.
-This is the default ABI for little-endian PowerPC 64-bit Linux.
-Overriding the default ABI requires special system support and is
-likely to fail in spectacular ways.
+@item -moptimize
+@opindex moptimize
+Apply partitioned execution optimizations. This is the default when any
+level of optimization is selected.
-@item -mprototype
-@itemx -mno-prototype
-@opindex mprototype
-@opindex mno-prototype
-On System V.4 and embedded PowerPC systems assume that all calls to
-variable argument functions are properly prototyped. Otherwise, the
-compiler must insert an instruction before every non-prototyped call to
-set or clear bit 6 of the condition code register (@code{CR}) to
-indicate whether floating-point values are passed in the floating-point
-registers in case the function takes variable arguments. With
-@option{-mprototype}, only calls to prototyped variable argument functions
-set or clear the bit.
+@end table
-@item -msim
-@opindex msim
-On embedded PowerPC systems, assume that the startup module is called
-@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
-@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}
-configurations.
+@node PDP-11 Options
+@subsection PDP-11 Options
+@cindex PDP-11 Options
-@item -mmvme
-@opindex mmvme
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libmvme.a} and
-@file{libc.a}.
+These options are defined for the PDP-11:
-@item -mads
-@opindex mads
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libads.a} and
-@file{libc.a}.
+@table @gcctabopt
+@item -mfpu
+@opindex mfpu
+Use hardware FPP floating point. This is the default. (FIS floating
+point on the PDP-11/40 is not supported.)
-@item -myellowknife
-@opindex myellowknife
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libyk.a} and
-@file{libc.a}.
+@item -msoft-float
+@opindex msoft-float
+Do not use hardware floating point.
-@item -mvxworks
-@opindex mvxworks
-On System V.4 and embedded PowerPC systems, specify that you are
-compiling for a VxWorks system.
+@item -mac0
+@opindex mac0
+Return floating-point results in ac0 (fr0 in Unix assembler syntax).
-@item -memb
-@opindex memb
-On embedded PowerPC systems, set the @code{PPC_EMB} bit in the ELF flags
-header to indicate that @samp{eabi} extended relocations are used.
+@item -mno-ac0
+@opindex mno-ac0
+Return floating-point results in memory. This is the default.
-@item -meabi
-@itemx -mno-eabi
-@opindex meabi
-@opindex mno-eabi
-On System V.4 and embedded PowerPC systems do (do not) adhere to the
-Embedded Applications Binary Interface (EABI), which is a set of
-modifications to the System V.4 specifications. Selecting @option{-meabi}
-means that the stack is aligned to an 8-byte boundary, a function
-@code{__eabi} is called from @code{main} to set up the EABI
-environment, and the @option{-msdata} option can use both @code{r2} and
-@code{r13} to point to two separate small data areas. Selecting
-@option{-mno-eabi} means that the stack is aligned to a 16-byte boundary,
-no EABI initialization function is called from @code{main}, and the
-@option{-msdata} option only uses @code{r13} to point to a single
-small data area. The @option{-meabi} option is on by default if you
-configured GCC using one of the @samp{powerpc*-*-eabi*} options.
+@item -m40
+@opindex m40
+Generate code for a PDP-11/40.
-@item -msdata=eabi
-@opindex msdata=eabi
-On System V.4 and embedded PowerPC systems, put small initialized
-@code{const} global and static data in the @code{.sdata2} section, which
-is pointed to by register @code{r2}. Put small initialized
-non-@code{const} global and static data in the @code{.sdata} section,
-which is pointed to by register @code{r13}. Put small uninitialized
-global and static data in the @code{.sbss} section, which is adjacent to
-the @code{.sdata} section. The @option{-msdata=eabi} option is
-incompatible with the @option{-mrelocatable} option. The
-@option{-msdata=eabi} option also sets the @option{-memb} option.
+@item -m45
+@opindex m45
+Generate code for a PDP-11/45. This is the default.
-@item -msdata=sysv
-@opindex msdata=sysv
-On System V.4 and embedded PowerPC systems, put small global and static
-data in the @code{.sdata} section, which is pointed to by register
-@code{r13}. Put small uninitialized global and static data in the
-@code{.sbss} section, which is adjacent to the @code{.sdata} section.
-The @option{-msdata=sysv} option is incompatible with the
-@option{-mrelocatable} option.
+@item -m10
+@opindex m10
+Generate code for a PDP-11/10.
-@item -msdata=default
-@itemx -msdata
-@opindex msdata=default
-@opindex msdata
-On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
-compile code the same as @option{-msdata=eabi}, otherwise compile code the
-same as @option{-msdata=sysv}.
+@item -mbcopy-builtin
+@opindex mbcopy-builtin
+Use inline @code{movmemhi} patterns for copying memory. This is the
+default.
-@item -msdata=data
-@opindex msdata=data
-On System V.4 and embedded PowerPC systems, put small global
-data in the @code{.sdata} section. Put small uninitialized global
-data in the @code{.sbss} section. Do not use register @code{r13}
-to address small data however. This is the default behavior unless
-other @option{-msdata} options are used.
+@item -mbcopy
+@opindex mbcopy
+Do not use inline @code{movmemhi} patterns for copying memory.
-@item -msdata=none
-@itemx -mno-sdata
-@opindex msdata=none
-@opindex mno-sdata
-On embedded PowerPC systems, put all initialized global and static data
-in the @code{.data} section, and all uninitialized data in the
-@code{.bss} section.
+@item -mint16
+@itemx -mno-int32
+@opindex mint16
+@opindex mno-int32
+Use 16-bit @code{int}. This is the default.
-@item -mblock-move-inline-limit=@var{num}
-@opindex mblock-move-inline-limit
-Inline all block moves (such as calls to @code{memcpy} or structure
-copies) less than or equal to @var{num} bytes. The minimum value for
-@var{num} is 32 bytes on 32-bit targets and 64 bytes on 64-bit
-targets. The default value is target-specific.
+@item -mint32
+@itemx -mno-int16
+@opindex mint32
+@opindex mno-int16
+Use 32-bit @code{int}.
-@item -G @var{num}
-@opindex G
-@cindex smaller data references (PowerPC)
-@cindex .sdata/.sdata2 references (PowerPC)
-On embedded PowerPC systems, put global and static items less than or
-equal to @var{num} bytes into the small data or BSS sections instead of
-the normal data or BSS section. By default, @var{num} is 8. The
-@option{-G @var{num}} switch is also passed to the linker.
-All modules should be compiled with the same @option{-G @var{num}} value.
+@item -mfloat64
+@itemx -mno-float32
+@opindex mfloat64
+@opindex mno-float32
+Use 64-bit @code{float}. This is the default.
-@item -mregnames
-@itemx -mno-regnames
-@opindex mregnames
-@opindex mno-regnames
-On System V.4 and embedded PowerPC systems do (do not) emit register
-names in the assembly language output using symbolic forms.
+@item -mfloat32
+@itemx -mno-float64
+@opindex mfloat32
+@opindex mno-float64
+Use 32-bit @code{float}.
-@item -mlongcall
-@itemx -mno-longcall
-@opindex mlongcall
-@opindex mno-longcall
-By default assume that all calls are far away so that a longer and more
-expensive calling sequence is required. This is required for calls
-farther than 32 megabytes (33,554,432 bytes) from the current location.
-A short call is generated if the compiler knows
-the call cannot be that far away. This setting can be overridden by
-the @code{shortcall} function attribute, or by @code{#pragma
-longcall(0)}.
+@item -mabshi
+@opindex mabshi
+Use @code{abshi2} pattern. This is the default.
-Some linkers are capable of detecting out-of-range calls and generating
-glue code on the fly. On these systems, long calls are unnecessary and
-generate slower code. As of this writing, the AIX linker can do this,
-as can the GNU linker for PowerPC/64. It is planned to add this feature
-to the GNU linker for 32-bit PowerPC systems as well.
+@item -mno-abshi
+@opindex mno-abshi
+Do not use @code{abshi2} pattern.
-On Darwin/PPC systems, @code{#pragma longcall} generates @code{jbsr
-callee, L42}, plus a @dfn{branch island} (glue code). The two target
-addresses represent the callee and the branch island. The
-Darwin/PPC linker prefers the first address and generates a @code{bl
-callee} if the PPC @code{bl} instruction reaches the callee directly;
-otherwise, the linker generates @code{bl L42} to call the branch
-island. The branch island is appended to the body of the
-calling function; it computes the full 32-bit address of the callee
-and jumps to it.
+@item -mbranch-expensive
+@opindex mbranch-expensive
+Pretend that branches are expensive. This is for experimenting with
+code generation only.
-On Mach-O (Darwin) systems, this option directs the compiler emit to
-the glue for every direct call, and the Darwin linker decides whether
-to use or discard it.
+@item -mbranch-cheap
+@opindex mbranch-cheap
+Do not pretend that branches are expensive. This is the default.
-In the future, GCC may ignore all longcall specifications
-when the linker is known to generate glue.
+@item -munix-asm
+@opindex munix-asm
+Use Unix assembler syntax. This is the default when configured for
+@samp{pdp11-*-bsd}.
-@item -mtls-markers
-@itemx -mno-tls-markers
-@opindex mtls-markers
-@opindex mno-tls-markers
-Mark (do not mark) calls to @code{__tls_get_addr} with a relocation
-specifying the function argument. The relocation allows the linker to
-reliably associate function call with argument setup instructions for
-TLS optimization, which in turn allows GCC to better schedule the
-sequence.
+@item -mdec-asm
+@opindex mdec-asm
+Use DEC assembler syntax. This is the default when configured for any
+PDP-11 target other than @samp{pdp11-*-bsd}.
+@end table
-@item -pthread
-@opindex pthread
-Adds support for multithreading with the @dfn{pthreads} library.
-This option sets flags for both the preprocessor and linker.
+@node picoChip Options
+@subsection picoChip Options
+@cindex picoChip options
-@item -mrecip
-@itemx -mno-recip
-@opindex mrecip
-This option enables use of the reciprocal estimate and
-reciprocal square root estimate instructions with additional
-Newton-Raphson steps to increase precision instead of doing a divide or
-square root and divide for floating-point arguments. You should use
-the @option{-ffast-math} option when using @option{-mrecip} (or at
-least @option{-funsafe-math-optimizations},
-@option{-ffinite-math-only}, @option{-freciprocal-math} and
-@option{-fno-trapping-math}). Note that while the throughput of the
-sequence is generally higher than the throughput of the non-reciprocal
-instruction, the precision of the sequence can be decreased by up to 2
-ulp (i.e.@: the inverse of 1.0 equals 0.99999994) for reciprocal square
-roots.
-
-@item -mrecip=@var{opt}
-@opindex mrecip=opt
-This option controls which reciprocal estimate instructions
-may be used. @var{opt} is a comma-separated list of options, which may
-be preceded by a @code{!} to invert the option:
-
-@table @samp
+These @samp{-m} options are defined for picoChip implementations:
-@item all
-Enable all estimate instructions.
+@table @gcctabopt
-@item default
-Enable the default instructions, equivalent to @option{-mrecip}.
+@item -mae=@var{ae_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling
+parameters for array element type @var{ae_type}. Supported values
+for @var{ae_type} are @samp{ANY}, @samp{MUL}, and @samp{MAC}.
-@item none
-Disable all estimate instructions, equivalent to @option{-mno-recip}.
+@option{-mae=ANY} selects a completely generic AE type. Code
+generated with this option runs on any of the other AE types. The
+code is not as efficient as it would be if compiled for a specific
+AE type, and some types of operation (e.g., multiplication) do not
+work properly on all types of AE.
-@item div
-Enable the reciprocal approximation instructions for both
-single and double precision.
+@option{-mae=MUL} selects a MUL AE type. This is the most useful AE type
+for compiled code, and is the default.
-@item divf
-Enable the single-precision reciprocal approximation instructions.
+@option{-mae=MAC} selects a DSP-style MAC AE. Code compiled with this
+option may suffer from poor performance of byte (char) manipulation,
+since the DSP AE does not provide hardware support for byte load/stores.
-@item divd
-Enable the double-precision reciprocal approximation instructions.
+@item -msymbol-as-address
+Enable the compiler to directly use a symbol name as an address in a
+load/store instruction, without first loading it into a
+register. Typically, the use of this option generates larger
+programs, which run faster than when the option isn't used. However, the
+results vary from program to program, so it is left as a user option,
+rather than being permanently enabled.
-@item rsqrt
-Enable the reciprocal square root approximation instructions for both
-single and double precision.
+@item -mno-inefficient-warnings
+Disables warnings about the generation of inefficient code. These
+warnings can be generated, for example, when compiling code that
+performs byte-level memory operations on the MAC AE type. The MAC AE has
+no hardware support for byte-level memory operations, so all byte
+load/stores must be synthesized from word load/store operations. This is
+inefficient and a warning is generated to indicate
+that you should rewrite the code to avoid byte operations, or to target
+an AE type that has the necessary hardware support. This option disables
+these warnings.
-@item rsqrtf
-Enable the single-precision reciprocal square root approximation instructions.
+@end table
-@item rsqrtd
-Enable the double-precision reciprocal square root approximation instructions.
+@node PowerPC Options
+@subsection PowerPC Options
+@cindex PowerPC options
-@end table
+These are listed under @xref{RS/6000 and PowerPC Options}.
-So, for example, @option{-mrecip=all,!rsqrtd} enables
-all of the reciprocal estimate instructions, except for the
-@code{FRSQRTE}, @code{XSRSQRTEDP}, and @code{XVRSQRTEDP} instructions
-which handle the double-precision reciprocal square root calculations.
+@node RL78 Options
+@subsection RL78 Options
+@cindex RL78 Options
-@item -mrecip-precision
-@itemx -mno-recip-precision
-@opindex mrecip-precision
-Assume (do not assume) that the reciprocal estimate instructions
-provide higher-precision estimates than is mandated by the PowerPC
-ABI. Selecting @option{-mcpu=power6}, @option{-mcpu=power7} or
-@option{-mcpu=power8} automatically selects @option{-mrecip-precision}.
-The double-precision square root estimate instructions are not generated by
-default on low-precision machines, since they do not provide an
-estimate that converges after three steps.
+@table @gcctabopt
-@item -mveclibabi=@var{type}
-@opindex mveclibabi
-Specifies the ABI type to use for vectorizing intrinsics using an
-external library. The only type supported at present is @samp{mass},
-which specifies to use IBM's Mathematical Acceleration Subsystem
-(MASS) libraries for vectorizing intrinsics using external libraries.
-GCC currently emits calls to @code{acosd2}, @code{acosf4},
-@code{acoshd2}, @code{acoshf4}, @code{asind2}, @code{asinf4},
-@code{asinhd2}, @code{asinhf4}, @code{atan2d2}, @code{atan2f4},
-@code{atand2}, @code{atanf4}, @code{atanhd2}, @code{atanhf4},
-@code{cbrtd2}, @code{cbrtf4}, @code{cosd2}, @code{cosf4},
-@code{coshd2}, @code{coshf4}, @code{erfcd2}, @code{erfcf4},
-@code{erfd2}, @code{erff4}, @code{exp2d2}, @code{exp2f4},
-@code{expd2}, @code{expf4}, @code{expm1d2}, @code{expm1f4},
-@code{hypotd2}, @code{hypotf4}, @code{lgammad2}, @code{lgammaf4},
-@code{log10d2}, @code{log10f4}, @code{log1pd2}, @code{log1pf4},
-@code{log2d2}, @code{log2f4}, @code{logd2}, @code{logf4},
-@code{powd2}, @code{powf4}, @code{sind2}, @code{sinf4}, @code{sinhd2},
-@code{sinhf4}, @code{sqrtd2}, @code{sqrtf4}, @code{tand2},
-@code{tanf4}, @code{tanhd2}, and @code{tanhf4} when generating code
-for power7. Both @option{-ftree-vectorize} and
-@option{-funsafe-math-optimizations} must also be enabled. The MASS
-libraries must be specified at link time.
+@item -msim
+@opindex msim
+Links in additional target libraries to support operation within a
+simulator.
-@item -mfriz
-@itemx -mno-friz
-@opindex mfriz
-Generate (do not generate) the @code{friz} instruction when the
-@option{-funsafe-math-optimizations} option is used to optimize
-rounding of floating-point values to 64-bit integer and back to floating
-point. The @code{friz} instruction does not return the same value if
-the floating-point number is too large to fit in an integer.
+@item -mmul=none
+@itemx -mmul=g10
+@itemx -mmul=g13
+@itemx -mmul=g14
+@itemx -mmul=rl78
+@opindex mmul
+Specifies the type of hardware multiplication and division support to
+be used. The simplest is @code{none}, which uses software for both
+multiplication and division. This is the default. The @code{g13}
+value is for the hardware multiply/divide peripheral found on the
+RL78/G13 (S2 core) targets. The @code{g14} value selects the use of
+the multiplication and division instructions supported by the RL78/G14
+(S3 core) parts. The value @code{rl78} is an alias for @code{g14} and
+the value @code{mg10} is an alias for @code{none}.
-@item -mpointers-to-nested-functions
-@itemx -mno-pointers-to-nested-functions
-@opindex mpointers-to-nested-functions
-Generate (do not generate) code to load up the static chain register
-(@code{r11}) when calling through a pointer on AIX and 64-bit Linux
-systems where a function pointer points to a 3-word descriptor giving
-the function address, TOC value to be loaded in register @code{r2}, and
-static chain value to be loaded in register @code{r11}. The
-@option{-mpointers-to-nested-functions} is on by default. You cannot
-call through pointers to nested functions or pointers
-to functions compiled in other languages that use the static chain if
-you use @option{-mno-pointers-to-nested-functions}.
+In addition a C preprocessor macro is defined, based upon the setting
+of this option. Possible values are: @code{__RL78_MUL_NONE__},
+@code{__RL78_MUL_G13__} or @code{__RL78_MUL_G14__}.
-@item -msave-toc-indirect
-@itemx -mno-save-toc-indirect
-@opindex msave-toc-indirect
-Generate (do not generate) code to save the TOC value in the reserved
-stack location in the function prologue if the function calls through
-a pointer on AIX and 64-bit Linux systems. If the TOC value is not
-saved in the prologue, it is saved just before the call through the
-pointer. The @option{-mno-save-toc-indirect} option is the default.
+@item -mcpu=g10
+@itemx -mcpu=g13
+@itemx -mcpu=g14
+@itemx -mcpu=rl78
+@opindex mcpu
+Specifies the RL78 core to target. The default is the G14 core, also
+known as an S3 core or just RL78. The G13 or S2 core does not have
+multiply or divide instructions, instead it uses a hardware peripheral
+for these operations. The G10 or S1 core does not have register
+banks, so it uses a different calling convention.
-@item -mcompat-align-parm
-@itemx -mno-compat-align-parm
-@opindex mcompat-align-parm
-Generate (do not generate) code to pass structure parameters with a
-maximum alignment of 64 bits, for compatibility with older versions
-of GCC.
+If this option is set it also selects the type of hardware multiply
+support to use, unless this is overridden by an explicit
+@option{-mmul=none} option on the command line. Thus specifying
+@option{-mcpu=g13} enables the use of the G13 hardware multiply
+peripheral and specifying @option{-mcpu=g10} disables the use of
+hardware multipications altogether.
-Older versions of GCC (prior to 4.9.0) incorrectly did not align a
-structure parameter on a 128-bit boundary when that structure contained
-a member requiring 128-bit alignment. This is corrected in more
-recent versions of GCC. This option may be used to generate code
-that is compatible with functions compiled with older versions of
-GCC.
+Note, although the RL78/G14 core is the default target, specifying
+@option{-mcpu=g14} or @option{-mcpu=rl78} on the command line does
+change the behaviour of the toolchain since it also enables G14
+hardware multiply support. If these options are not specified on the
+command line then software multiplication routines will be used even
+though the code targets the RL78 core. This is for backwards
+compatibility with older toolchains which did not have hardware
+multiply and divide support.
-The @option{-mno-compat-align-parm} option is the default.
-@end table
+In addition a C preprocessor macro is defined, based upon the setting
+of this option. Possible values are: @code{__RL78_G10__},
+@code{__RL78_G13__} or @code{__RL78_G14__}.
-@node RX Options
-@subsection RX Options
-@cindex RX Options
+@item -mg10
+@itemx -mg13
+@itemx -mg14
+@itemx -mrl78
+@opindex mg10
+@opindex mg13
+@opindex mg14
+@opindex mrl78
+These are aliases for the corresponding @option{-mcpu=} option. They
+are provided for backwards compatibility.
-These command-line options are defined for RX targets:
+@item -mallregs
+@opindex mallregs
+Allow the compiler to use all of the available registers. By default
+registers @code{r24..r31} are reserved for use in interrupt handlers.
+With this option enabled these registers can be used in ordinary
+functions as well.
-@table @gcctabopt
@item -m64bit-doubles
@itemx -m32bit-doubles
@opindex m64bit-doubles
@opindex m32bit-doubles
Make the @code{double} data type be 64 bits (@option{-m64bit-doubles})
or 32 bits (@option{-m32bit-doubles}) in size. The default is
-@option{-m32bit-doubles}. @emph{Note} RX floating-point hardware only
-works on 32-bit values, which is why the default is
@option{-m32bit-doubles}.
-@item -fpu
-@itemx -nofpu
-@opindex fpu
-@opindex nofpu
-Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX
-floating-point hardware. The default is enabled for the RX600
-series and disabled for the RX200 series.
-
-Floating-point instructions are only generated for 32-bit floating-point
-values, however, so the FPU hardware is not used for doubles if the
-@option{-m64bit-doubles} option is used.
-
-@emph{Note} If the @option{-fpu} option is enabled then
-@option{-funsafe-math-optimizations} is also enabled automatically.
-This is because the RX FPU instructions are themselves unsafe.
-
-@item -mcpu=@var{name}
-@opindex mcpu
-Selects the type of RX CPU to be targeted. Currently three types are
-supported, the generic @samp{RX600} and @samp{RX200} series hardware and
-the specific @samp{RX610} CPU. The default is @samp{RX600}.
+@end table
-The only difference between @samp{RX600} and @samp{RX610} is that the
-@samp{RX610} does not support the @code{MVTIPL} instruction.
+@node RS/6000 and PowerPC Options
+@subsection IBM RS/6000 and PowerPC Options
+@cindex RS/6000 and PowerPC Options
+@cindex IBM RS/6000 and PowerPC Options
-The @samp{RX200} series does not have a hardware floating-point unit
-and so @option{-nofpu} is enabled by default when this type is
-selected.
-
-@item -mbig-endian-data
-@itemx -mlittle-endian-data
-@opindex mbig-endian-data
-@opindex mlittle-endian-data
-Store data (but not code) in the big-endian format. The default is
-@option{-mlittle-endian-data}, i.e.@: to store data in the little-endian
-format.
+These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
+@table @gcctabopt
+@item -mpowerpc-gpopt
+@itemx -mno-powerpc-gpopt
+@itemx -mpowerpc-gfxopt
+@itemx -mno-powerpc-gfxopt
+@need 800
+@itemx -mpowerpc64
+@itemx -mno-powerpc64
+@itemx -mmfcrf
+@itemx -mno-mfcrf
+@itemx -mpopcntb
+@itemx -mno-popcntb
+@itemx -mpopcntd
+@itemx -mno-popcntd
+@itemx -mfprnd
+@itemx -mno-fprnd
+@need 800
+@itemx -mcmpb
+@itemx -mno-cmpb
+@itemx -mmfpgpr
+@itemx -mno-mfpgpr
+@itemx -mhard-dfp
+@itemx -mno-hard-dfp
+@opindex mpowerpc-gpopt
+@opindex mno-powerpc-gpopt
+@opindex mpowerpc-gfxopt
+@opindex mno-powerpc-gfxopt
+@opindex mpowerpc64
+@opindex mno-powerpc64
+@opindex mmfcrf
+@opindex mno-mfcrf
+@opindex mpopcntb
+@opindex mno-popcntb
+@opindex mpopcntd
+@opindex mno-popcntd
+@opindex mfprnd
+@opindex mno-fprnd
+@opindex mcmpb
+@opindex mno-cmpb
+@opindex mmfpgpr
+@opindex mno-mfpgpr
+@opindex mhard-dfp
+@opindex mno-hard-dfp
+You use these options to specify which instructions are available on the
+processor you are using. The default value of these options is
+determined when configuring GCC@. Specifying the
+@option{-mcpu=@var{cpu_type}} overrides the specification of these
+options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
+rather than the options listed above.
-@item -msmall-data-limit=@var{N}
-@opindex msmall-data-limit
-Specifies the maximum size in bytes of global and static variables
-which can be placed into the small data area. Using the small data
-area can lead to smaller and faster code, but the size of area is
-limited and it is up to the programmer to ensure that the area does
-not overflow. Also when the small data area is used one of the RX's
-registers (usually @code{r13}) is reserved for use pointing to this
-area, so it is no longer available for use by the compiler. This
-could result in slower and/or larger code if variables are pushed onto
-the stack instead of being held in this register.
+Specifying @option{-mpowerpc-gpopt} allows
+GCC to use the optional PowerPC architecture instructions in the
+General Purpose group, including floating-point square root. Specifying
+@option{-mpowerpc-gfxopt} allows GCC to
+use the optional PowerPC architecture instructions in the Graphics
+group, including floating-point select.
-Note, common variables (variables that have not been initialized) and
-constants are not placed into the small data area as they are assigned
-to other sections in the output executable.
+The @option{-mmfcrf} option allows GCC to generate the move from
+condition register field instruction implemented on the POWER4
+processor and other processors that support the PowerPC V2.01
+architecture.
+The @option{-mpopcntb} option allows GCC to generate the popcount and
+double-precision FP reciprocal estimate instruction implemented on the
+POWER5 processor and other processors that support the PowerPC V2.02
+architecture.
+The @option{-mpopcntd} option allows GCC to generate the popcount
+instruction implemented on the POWER7 processor and other processors
+that support the PowerPC V2.06 architecture.
+The @option{-mfprnd} option allows GCC to generate the FP round to
+integer instructions implemented on the POWER5+ processor and other
+processors that support the PowerPC V2.03 architecture.
+The @option{-mcmpb} option allows GCC to generate the compare bytes
+instruction implemented on the POWER6 processor and other processors
+that support the PowerPC V2.05 architecture.
+The @option{-mmfpgpr} option allows GCC to generate the FP move to/from
+general-purpose register instructions implemented on the POWER6X
+processor and other processors that support the extended PowerPC V2.05
+architecture.
+The @option{-mhard-dfp} option allows GCC to generate the decimal
+floating-point instructions implemented on some POWER processors.
-The default value is zero, which disables this feature. Note, this
-feature is not enabled by default with higher optimization levels
-(@option{-O2} etc) because of the potentially detrimental effects of
-reserving a register. It is up to the programmer to experiment and
-discover whether this feature is of benefit to their program. See the
-description of the @option{-mpid} option for a description of how the
-actual register to hold the small data area pointer is chosen.
+The @option{-mpowerpc64} option allows GCC to generate the additional
+64-bit instructions that are found in the full PowerPC64 architecture
+and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
+@option{-mno-powerpc64}.
-@item -msim
-@itemx -mno-sim
-@opindex msim
-@opindex mno-sim
-Use the simulator runtime. The default is to use the libgloss
-board-specific runtime.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set architecture type, register usage, and
+instruction scheduling parameters for machine type @var{cpu_type}.
+Supported values for @var{cpu_type} are @samp{401}, @samp{403},
+@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{464}, @samp{464fp},
+@samp{476}, @samp{476fp}, @samp{505}, @samp{601}, @samp{602}, @samp{603},
+@samp{603e}, @samp{604}, @samp{604e}, @samp{620}, @samp{630}, @samp{740},
+@samp{7400}, @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
+@samp{860}, @samp{970}, @samp{8540}, @samp{a2}, @samp{e300c2},
+@samp{e300c3}, @samp{e500mc}, @samp{e500mc64}, @samp{e5500},
+@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
+@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
+@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
+@samp{power9}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
+and @samp{rs64}.
-@item -mas100-syntax
-@itemx -mno-as100-syntax
-@opindex mas100-syntax
-@opindex mno-as100-syntax
-When generating assembler output use a syntax that is compatible with
-Renesas's AS100 assembler. This syntax can also be handled by the GAS
-assembler, but it has some restrictions so it is not generated by default.
+@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
+@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
+endian), 64-bit big endian PowerPC and 64-bit little endian PowerPC
+architecture machine types, with an appropriate, generic processor
+model assumed for scheduling purposes.
-@item -mmax-constant-size=@var{N}
-@opindex mmax-constant-size
-Specifies the maximum size, in bytes, of a constant that can be used as
-an operand in a RX instruction. Although the RX instruction set does
-allow constants of up to 4 bytes in length to be used in instructions,
-a longer value equates to a longer instruction. Thus in some
-circumstances it can be beneficial to restrict the size of constants
-that are used in instructions. Constants that are too big are instead
-placed into a constant pool and referenced via register indirection.
+The other options specify a specific processor. Code generated under
+those options runs best on that processor, and may not run at all on
+others.
-The value @var{N} can be between 0 and 4. A value of 0 (the default)
-or 4 means that constants of any size are allowed.
+The @option{-mcpu} options automatically enable or disable the
+following options:
-@item -mrelax
-@opindex mrelax
-Enable linker relaxation. Linker relaxation is a process whereby the
-linker attempts to reduce the size of a program by finding shorter
-versions of various instructions. Disabled by default.
+@gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol
+-mpopcntb -mpopcntd -mpowerpc64 @gol
+-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
+-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
+-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol
+-mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
+-mpower9-fusion -mpower9-vector}
-@item -mint-register=@var{N}
-@opindex mint-register
-Specify the number of registers to reserve for fast interrupt handler
-functions. The value @var{N} can be between 0 and 4. A value of 1
-means that register @code{r13} is reserved for the exclusive use
-of fast interrupt handlers. A value of 2 reserves @code{r13} and
-@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
-@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
-A value of 0, the default, does not reserve any registers.
+The particular options set for any particular CPU varies between
+compiler versions, depending on what setting seems to produce optimal
+code for that CPU; it doesn't necessarily reflect the actual hardware's
+capabilities. If you wish to set an individual option to a particular
+value, you may specify it after the @option{-mcpu} option, like
+@option{-mcpu=970 -mno-altivec}.
-@item -msave-acc-in-interrupts
-@opindex msave-acc-in-interrupts
-Specifies that interrupt handler functions should preserve the
-accumulator register. This is only necessary if normal code might use
-the accumulator register, for example because it performs 64-bit
-multiplications. The default is to ignore the accumulator as this
-makes the interrupt handlers faster.
+On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
+not enabled or disabled by the @option{-mcpu} option at present because
+AIX does not have full support for these options. You may still
+enable or disable them individually if you're sure it'll work in your
+environment.
-@item -mpid
-@itemx -mno-pid
-@opindex mpid
-@opindex mno-pid
-Enables the generation of position independent data. When enabled any
-access to constant data is done via an offset from a base address
-held in a register. This allows the location of constant data to be
-determined at run time without requiring the executable to be
-relocated, which is a benefit to embedded applications with tight
-memory constraints. Data that can be modified is not affected by this
-option.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type
+@var{cpu_type}, but do not set the architecture type or register usage,
+as @option{-mcpu=@var{cpu_type}} does. The same
+values for @var{cpu_type} are used for @option{-mtune} as for
+@option{-mcpu}. If both are specified, the code generated uses the
+architecture and registers set by @option{-mcpu}, but the
+scheduling parameters set by @option{-mtune}.
-Note, using this feature reserves a register, usually @code{r13}, for
-the constant data base address. This can result in slower and/or
-larger code, especially in complicated functions.
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate PowerPC64 code for the small model: The TOC is limited to
+64k.
-The actual register chosen to hold the constant data base address
-depends upon whether the @option{-msmall-data-limit} and/or the
-@option{-mint-register} command-line options are enabled. Starting
-with register @code{r13} and proceeding downwards, registers are
-allocated first to satisfy the requirements of @option{-mint-register},
-then @option{-mpid} and finally @option{-msmall-data-limit}. Thus it
-is possible for the small data area register to be @code{r8} if both
-@option{-mint-register=4} and @option{-mpid} are specified on the
-command line.
+@item -mcmodel=medium
+@opindex mcmodel=medium
+Generate PowerPC64 code for the medium model: The TOC and other static
+data may be up to a total of 4G in size.
-By default this feature is not enabled. The default can be restored
-via the @option{-mno-pid} command-line option.
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate PowerPC64 code for the large model: The TOC may be up to 4G
+in size. Other data and code is only limited by the 64-bit address
+space.
-@item -mno-warn-multiple-fast-interrupts
-@itemx -mwarn-multiple-fast-interrupts
-@opindex mno-warn-multiple-fast-interrupts
-@opindex mwarn-multiple-fast-interrupts
-Prevents GCC from issuing a warning message if it finds more than one
-fast interrupt handler when it is compiling a file. The default is to
-issue a warning for each extra fast interrupt handler found, as the RX
-only supports one such interrupt.
+@item -maltivec
+@itemx -mno-altivec
+@opindex maltivec
+@opindex mno-altivec
+Generate code that uses (does not use) AltiVec instructions, and also
+enable the use of built-in functions that allow more direct access to
+the AltiVec instruction set. You may also need to set
+@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
+enhancements.
-@item -mallow-string-insns
-@itemx -mno-allow-string-insns
-@opindex mallow-string-insns
-@opindex mno-allow-string-insns
-Enables or disables the use of the string manipulation instructions
-@code{SMOVF}, @code{SCMPU}, @code{SMOVB}, @code{SMOVU}, @code{SUNTIL}
-@code{SWHILE} and also the @code{RMPA} instruction. These
-instructions may prefetch data, which is not safe to do if accessing
-an I/O register. (See section 12.2.7 of the RX62N Group User's Manual
-for more information).
+When @option{-maltivec} is used, rather than @option{-maltivec=le} or
+@option{-maltivec=be}, the element order for Altivec intrinsics such
+as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert}
+match array element order corresponding to the endianness of the
+target. That is, element zero identifies the leftmost element in a
+vector register when targeting a big-endian platform, and identifies
+the rightmost element in a vector register when targeting a
+little-endian platform.
-The default is to allow these instructions, but it is not possible for
-GCC to reliably detect all circumstances where a string instruction
-might be used to access an I/O register, so their use cannot be
-disabled automatically. Instead it is reliant upon the programmer to
-use the @option{-mno-allow-string-insns} option if their program
-accesses I/O space.
+@item -maltivec=be
+@opindex maltivec=be
+Generate Altivec instructions using big-endian element order,
+regardless of whether the target is big- or little-endian. This is
+the default when targeting a big-endian platform.
-When the instructions are enabled GCC defines the C preprocessor
-symbol @code{__RX_ALLOW_STRING_INSNS__}, otherwise it defines the
-symbol @code{__RX_DISALLOW_STRING_INSNS__}.
+The element order is used to interpret element numbers in Altivec
+intrinsics such as @code{vec_splat}, @code{vec_extract}, and
+@code{vec_insert}. By default, these match array element order
+corresponding to the endianness for the target.
-@item -mjsr
-@itemx -mno-jsr
-@opindex mjsr
-@opindex mno-jsr
-Use only (or not only) @code{JSR} instructions to access functions.
-This option can be used when code size exceeds the range of @code{BSR}
-instructions. Note that @option{-mno-jsr} does not mean to not use
-@code{JSR} but instead means that any type of branch may be used.
-@end table
+@item -maltivec=le
+@opindex maltivec=le
+Generate Altivec instructions using little-endian element order,
+regardless of whether the target is big- or little-endian. This is
+the default when targeting a little-endian platform. This option is
+currently ignored when targeting a big-endian platform.
-@emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}}
-has special significance to the RX port when used with the
-@code{interrupt} function attribute. This attribute indicates a
-function intended to process fast interrupts. GCC ensures
-that it only uses the registers @code{r10}, @code{r11}, @code{r12}
-and/or @code{r13} and only provided that the normal use of the
-corresponding registers have been restricted via the
-@option{-ffixed-@var{reg}} or @option{-mint-register} command-line
-options.
+The element order is used to interpret element numbers in Altivec
+intrinsics such as @code{vec_splat}, @code{vec_extract}, and
+@code{vec_insert}. By default, these match array element order
+corresponding to the endianness for the target.
-@node S/390 and zSeries Options
-@subsection S/390 and zSeries Options
-@cindex S/390 and zSeries Options
+@item -mvrsave
+@itemx -mno-vrsave
+@opindex mvrsave
+@opindex mno-vrsave
+Generate VRSAVE instructions when generating AltiVec code.
-These are the @samp{-m} options defined for the S/390 and zSeries architecture.
+@item -mgen-cell-microcode
+@opindex mgen-cell-microcode
+Generate Cell microcode instructions.
-@table @gcctabopt
-@item -mhard-float
-@itemx -msoft-float
-@opindex mhard-float
-@opindex msoft-float
-Use (do not use) the hardware floating-point instructions and registers
-for floating-point operations. When @option{-msoft-float} is specified,
-functions in @file{libgcc.a} are used to perform floating-point
-operations. When @option{-mhard-float} is specified, the compiler
-generates IEEE floating-point instructions. This is the default.
+@item -mwarn-cell-microcode
+@opindex mwarn-cell-microcode
+Warn when a Cell microcode instruction is emitted. An example
+of a Cell microcode instruction is a variable shift.
-@item -mhard-dfp
-@itemx -mno-hard-dfp
-@opindex mhard-dfp
-@opindex mno-hard-dfp
-Use (do not use) the hardware decimal-floating-point instructions for
-decimal-floating-point operations. When @option{-mno-hard-dfp} is
-specified, functions in @file{libgcc.a} are used to perform
-decimal-floating-point operations. When @option{-mhard-dfp} is
-specified, the compiler generates decimal-floating-point hardware
-instructions. This is the default for @option{-march=z9-ec} or higher.
+@item -msecure-plt
+@opindex msecure-plt
+Generate code that allows @command{ld} and @command{ld.so}
+to build executables and shared
+libraries with non-executable @code{.plt} and @code{.got} sections.
+This is a PowerPC
+32-bit SYSV ABI option.
-@item -mlong-double-64
-@itemx -mlong-double-128
-@opindex mlong-double-64
-@opindex mlong-double-128
-These switches control the size of @code{long double} type. A size
-of 64 bits makes the @code{long double} type equivalent to the @code{double}
-type. This is the default.
+@item -mbss-plt
+@opindex mbss-plt
+Generate code that uses a BSS @code{.plt} section that @command{ld.so}
+fills in, and
+requires @code{.plt} and @code{.got}
+sections that are both writable and executable.
+This is a PowerPC 32-bit SYSV ABI option.
-@item -mbackchain
-@itemx -mno-backchain
-@opindex mbackchain
-@opindex mno-backchain
-Store (do not store) the address of the caller's frame as backchain pointer
-into the callee's stack frame.
-A backchain may be needed to allow debugging using tools that do not understand
-DWARF 2 call frame information.
-When @option{-mno-packed-stack} is in effect, the backchain pointer is stored
-at the bottom of the stack frame; when @option{-mpacked-stack} is in effect,
-the backchain is placed into the topmost word of the 96/160 byte register
-save area.
+@item -misel
+@itemx -mno-isel
+@opindex misel
+@opindex mno-isel
+This switch enables or disables the generation of ISEL instructions.
-In general, code compiled with @option{-mbackchain} is call-compatible with
-code compiled with @option{-mmo-backchain}; however, use of the backchain
-for debugging purposes usually requires that the whole binary is built with
-@option{-mbackchain}. Note that the combination of @option{-mbackchain},
-@option{-mpacked-stack} and @option{-mhard-float} is not supported. In order
-to build a linux kernel use @option{-msoft-float}.
+@item -misel=@var{yes/no}
+This switch has been deprecated. Use @option{-misel} and
+@option{-mno-isel} instead.
-The default is to not maintain the backchain.
+@item -mspe
+@itemx -mno-spe
+@opindex mspe
+@opindex mno-spe
+This switch enables or disables the generation of SPE simd
+instructions.
-@item -mpacked-stack
-@itemx -mno-packed-stack
-@opindex mpacked-stack
-@opindex mno-packed-stack
-Use (do not use) the packed stack layout. When @option{-mno-packed-stack} is
-specified, the compiler uses the all fields of the 96/160 byte register save
-area only for their default purpose; unused fields still take up stack space.
-When @option{-mpacked-stack} is specified, register save slots are densely
-packed at the top of the register save area; unused space is reused for other
-purposes, allowing for more efficient use of the available stack space.
-However, when @option{-mbackchain} is also in effect, the topmost word of
-the save area is always used to store the backchain, and the return address
-register is always saved two words below the backchain.
+@item -mpaired
+@itemx -mno-paired
+@opindex mpaired
+@opindex mno-paired
+This switch enables or disables the generation of PAIRED simd
+instructions.
-As long as the stack frame backchain is not used, code generated with
-@option{-mpacked-stack} is call-compatible with code generated with
-@option{-mno-packed-stack}. Note that some non-FSF releases of GCC 2.95 for
-S/390 or zSeries generated code that uses the stack frame backchain at run
-time, not just for debugging purposes. Such code is not call-compatible
-with code compiled with @option{-mpacked-stack}. Also, note that the
-combination of @option{-mbackchain},
-@option{-mpacked-stack} and @option{-mhard-float} is not supported. In order
-to build a linux kernel use @option{-msoft-float}.
+@item -mspe=@var{yes/no}
+This option has been deprecated. Use @option{-mspe} and
+@option{-mno-spe} instead.
-The default is to not use the packed stack layout.
+@item -mvsx
+@itemx -mno-vsx
+@opindex mvsx
+@opindex mno-vsx
+Generate code that uses (does not use) vector/scalar (VSX)
+instructions, and also enable the use of built-in functions that allow
+more direct access to the VSX instruction set.
-@item -msmall-exec
-@itemx -mno-small-exec
-@opindex msmall-exec
-@opindex mno-small-exec
-Generate (or do not generate) code using the @code{bras} instruction
-to do subroutine calls.
-This only works reliably if the total executable size does not
-exceed 64k. The default is to use the @code{basr} instruction instead,
-which does not have this limitation.
+@item -mcrypto
+@itemx -mno-crypto
+@opindex mcrypto
+@opindex mno-crypto
+Enable the use (disable) of the built-in functions that allow direct
+access to the cryptographic instructions that were added in version
+2.07 of the PowerPC ISA.
-@item -m64
-@itemx -m31
-@opindex m64
-@opindex m31
-When @option{-m31} is specified, generate code compliant to the
-GNU/Linux for S/390 ABI@. When @option{-m64} is specified, generate
-code compliant to the GNU/Linux for zSeries ABI@. This allows GCC in
-particular to generate 64-bit instructions. For the @samp{s390}
-targets, the default is @option{-m31}, while the @samp{s390x}
-targets default to @option{-m64}.
+@item -mdirect-move
+@itemx -mno-direct-move
+@opindex mdirect-move
+@opindex mno-direct-move
+Generate code that uses (does not use) the instructions to move data
+between the general purpose registers and the vector/scalar (VSX)
+registers that were added in version 2.07 of the PowerPC ISA.
-@item -mzarch
-@itemx -mesa
-@opindex mzarch
-@opindex mesa
-When @option{-mzarch} is specified, generate code using the
-instructions available on z/Architecture.
-When @option{-mesa} is specified, generate code using the
-instructions available on ESA/390. Note that @option{-mesa} is
-not possible with @option{-m64}.
-When generating code compliant to the GNU/Linux for S/390 ABI,
-the default is @option{-mesa}. When generating code compliant
-to the GNU/Linux for zSeries ABI, the default is @option{-mzarch}.
+@item -mpower8-fusion
+@itemx -mno-power8-fusion
+@opindex mpower8-fusion
+@opindex mno-power8-fusion
+Generate code that keeps (does not keeps) some integer operations
+adjacent so that the instructions can be fused together on power8 and
+later processors.
-@item -mhtm
-@itemx -mno-htm
-@opindex mhtm
-@opindex mno-htm
-The @option{-mhtm} option enables a set of builtins making use of
-instructions available with the transactional execution facility
-introduced with the IBM zEnterprise EC12 machine generation
-@ref{S/390 System z Built-in Functions}.
-@option{-mhtm} is enabled by default when using @option{-march=zEC12}.
-
-@item -mvx
-@itemx -mno-vx
-@opindex mvx
-@opindex mno-vx
-When @option{-mvx} is specified, generate code using the instructions
-available with the vector extension facility introduced with the IBM
-z13 machine generation.
-This option changes the ABI for some vector type values with regard to
-alignment and calling conventions. In case vector type values are
-being used in an ABI-relevant context a GAS @samp{.gnu_attribute}
-command will be added to mark the resulting binary with the ABI used.
-@option{-mvx} is enabled by default when using @option{-march=z13}.
-
-@item -mzvector
-@itemx -mno-zvector
-@opindex mzvector
-@opindex mno-zvector
-The @option{-mzvector} option enables vector language extensions and
-builtins using instructions available with the vector extension
-facility introduced with the IBM z13 machine generation.
-This option adds support for @samp{vector} to be used as a keyword to
-define vector type variables and arguments. @samp{vector} is only
-available when GNU extensions are enabled. It will not be expanded
-when requesting strict standard compliance e.g. with @option{-std=c99}.
-In addition to the GCC low-level builtins @option{-mzvector} enables
-a set of builtins added for compatibility with Altivec-style
-implementations like Power and Cell. In order to make use of these
-builtins the header file @file{vecintrin.h} needs to be included.
-@option{-mzvector} is disabled by default.
-
-@item -mmvcle
-@itemx -mno-mvcle
-@opindex mmvcle
-@opindex mno-mvcle
-Generate (or do not generate) code using the @code{mvcle} instruction
-to perform block moves. When @option{-mno-mvcle} is specified,
-use a @code{mvc} loop instead. This is the default unless optimizing for
-size.
+@item -mpower8-vector
+@itemx -mno-power8-vector
+@opindex mpower8-vector
+@opindex mno-power8-vector
+Generate code that uses (does not use) the vector and scalar
+instructions that were added in version 2.07 of the PowerPC ISA. Also
+enable the use of built-in functions that allow more direct access to
+the vector instructions.
-@item -mdebug
-@itemx -mno-debug
-@opindex mdebug
-@opindex mno-debug
-Print (or do not print) additional debug information when compiling.
-The default is to not print debug information.
+@item -mquad-memory
+@itemx -mno-quad-memory
+@opindex mquad-memory
+@opindex mno-quad-memory
+Generate code that uses (does not use) the non-atomic quad word memory
+instructions. The @option{-mquad-memory} option requires use of
+64-bit mode.
-@item -march=@var{cpu-type}
-@opindex march
-Generate code that runs on @var{cpu-type}, which is the name of a
-system representing a certain processor type. Possible values for
-@var{cpu-type} are @samp{z900}, @samp{z990}, @samp{z9-109},
-@samp{z9-ec}, @samp{z10}, @samp{z196}, @samp{zEC12}, and @samp{z13}.
-The default is @option{-march=z900}. @samp{g5} and @samp{g6} are
-deprecated and will be removed with future releases.
+@item -mquad-memory-atomic
+@itemx -mno-quad-memory-atomic
+@opindex mquad-memory-atomic
+@opindex mno-quad-memory-atomic
+Generate code that uses (does not use) the atomic quad word memory
+instructions. The @option{-mquad-memory-atomic} option requires use of
+64-bit mode.
-@item -mtune=@var{cpu-type}
-@opindex mtune
-Tune to @var{cpu-type} everything applicable about the generated code,
-except for the ABI and the set of available instructions.
-The list of @var{cpu-type} values is the same as for @option{-march}.
-The default is the value used for @option{-march}.
+@item -mupper-regs-df
+@itemx -mno-upper-regs-df
+@opindex mupper-regs-df
+@opindex mno-upper-regs-df
+Generate code that uses (does not use) the scalar double precision
+instructions that target all 64 registers in the vector/scalar
+floating point register set that were added in version 2.06 of the
+PowerPC ISA. @option{-mupper-regs-df} is turned on by default if you
+use any of the @option{-mcpu=power7}, @option{-mcpu=power8}, or
+@option{-mvsx} options.
-@item -mtpf-trace
-@itemx -mno-tpf-trace
-@opindex mtpf-trace
-@opindex mno-tpf-trace
-Generate code that adds (does not add) in TPF OS specific branches to trace
-routines in the operating system. This option is off by default, even
-when compiling for the TPF OS@.
+@item -mupper-regs-sf
+@itemx -mno-upper-regs-sf
+@opindex mupper-regs-sf
+@opindex mno-upper-regs-sf
+Generate code that uses (does not use) the scalar single precision
+instructions that target all 64 registers in the vector/scalar
+floating point register set that were added in version 2.07 of the
+PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
+use either of the @option{-mcpu=power8} or @option{-mpower8-vector}
+options.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Generate code that uses (does not use) the floating-point multiply and
-accumulate instructions. These instructions are generated by default if
-hardware floating point is used.
+@item -mupper-regs
+@itemx -mno-upper-regs
+@opindex mupper-regs
+@opindex mno-upper-regs
+Generate code that uses (does not use) the scalar
+instructions that target all 64 registers in the vector/scalar
+floating point register set, depending on the model of the machine.
-@item -mwarn-framesize=@var{framesize}
-@opindex mwarn-framesize
-Emit a warning if the current function exceeds the given frame size. Because
-this is a compile-time check it doesn't need to be a real problem when the program
-runs. It is intended to identify functions that most probably cause
-a stack overflow. It is useful to be used in an environment with limited stack
-size e.g.@: the linux kernel.
+If the @option{-mno-upper-regs} option is used, it turns off both
+@option{-mupper-regs-sf} and @option{-mupper-regs-df} options.
-@item -mwarn-dynamicstack
-@opindex mwarn-dynamicstack
-Emit a warning if the function calls @code{alloca} or uses dynamically-sized
-arrays. This is generally a bad idea with a limited stack size.
+@item -mfloat128
+@itemx -mno-float128
+@opindex mfloat128
+@opindex mno-float128
+Enable/disable the @var{__float128} keyword for IEEE 128-bit floating point
+and use either software emulation for IEEE 128-bit floating point or
+hardware instructions.
-@item -mstack-guard=@var{stack-guard}
-@itemx -mstack-size=@var{stack-size}
-@opindex mstack-guard
-@opindex mstack-size
-If these options are provided the S/390 back end emits additional instructions in
-the function prologue that trigger a trap if the stack size is @var{stack-guard}
-bytes above the @var{stack-size} (remember that the stack on S/390 grows downward).
-If the @var{stack-guard} option is omitted the smallest power of 2 larger than
-the frame size of the compiled function is chosen.
-These options are intended to be used to help debugging stack overflow problems.
-The additionally emitted code causes only little overhead and hence can also be
-used in production-like systems without greater performance degradation. The given
-values have to be exact powers of 2 and @var{stack-size} has to be greater than
-@var{stack-guard} without exceeding 64k.
-In order to be efficient the extra code makes the assumption that the stack starts
-at an address aligned to the value given by @var{stack-size}.
-The @var{stack-guard} option can only be used in conjunction with @var{stack-size}.
+The VSX instruction set (@option{-mvsx}, @option{-mcpu=power7}, or
+@option{-mcpu=power8}) must be enabled to use the @option{-mfloat128}
+option. The @code{-mfloat128} option only works on PowerPC 64-bit
+Linux systems.
-@item -mhotpatch=@var{pre-halfwords},@var{post-halfwords}
-@opindex mhotpatch
-If the hotpatch option is enabled, a ``hot-patching'' function
-prologue is generated for all functions in the compilation unit.
-The funtion label is prepended with the given number of two-byte
-NOP instructions (@var{pre-halfwords}, maximum 1000000). After
-the label, 2 * @var{post-halfwords} bytes are appended, using the
-largest NOP like instructions the architecture allows (maximum
-1000000).
+@item -mfloat128-hardware
+@itemx -mno-float128-hardware
+@opindex mfloat128-hardware
+@opindex mno-float128-hardware
+Enable/disable using ISA 3.0 hardware instructions to support the
+@var{__float128} data type.
-If both arguments are zero, hotpatching is disabled.
+@item -mmodulo
+@itemx -mno-modulo
+@opindex mmodulo
+@opindex mno-module
+Generate code that uses (does not use) the ISA 3.0 integer modulo
+instructions. The @option{-mmodulo} option is enabled by default
+with the @option{-mcpu=power9} option.
-This option can be overridden for individual functions with the
-@code{hotpatch} attribute.
-@end table
+@item -mpower9-fusion
+@itemx -mno-power9-fusion
+@opindex mpower9-fusion
+@opindex mno-power9-fusion
+Generate code that keeps (does not keeps) some operations adjacent so
+that the instructions can be fused together on power9 and later
+processors.
-@node Score Options
-@subsection Score Options
-@cindex Score Options
+@item -mpower9-vector
+@itemx -mno-power9-vector
+@opindex mpower9-vector
+@opindex mno-power9-vector
+Generate code that uses (does not use) the vector and scalar
+instructions that were added in version 2.07 of the PowerPC ISA. Also
+enable the use of built-in functions that allow more direct access to
+the vector instructions.
-These options are defined for Score implementations:
+@item -mfloat-gprs=@var{yes/single/double/no}
+@itemx -mfloat-gprs
+@opindex mfloat-gprs
+This switch enables or disables the generation of floating-point
+operations on the general-purpose registers for architectures that
+support it.
-@table @gcctabopt
-@item -meb
-@opindex meb
-Compile code for big-endian mode. This is the default.
+The argument @samp{yes} or @samp{single} enables the use of
+single-precision floating-point operations.
-@item -mel
-@opindex mel
-Compile code for little-endian mode.
+The argument @samp{double} enables the use of single and
+double-precision floating-point operations.
-@item -mnhwloop
-@opindex mnhwloop
-Disable generation of @code{bcnz} instructions.
+The argument @samp{no} disables floating-point operations on the
+general-purpose registers.
-@item -muls
-@opindex muls
-Enable generation of unaligned load and store instructions.
+This option is currently only available on the MPC854x.
-@item -mmac
-@opindex mmac
-Enable the use of multiply-accumulate instructions. Disabled by default.
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for 32-bit or 64-bit environments of Darwin and SVR4
+targets (including GNU/Linux). The 32-bit environment sets int, long
+and pointer to 32 bits and generates code that runs on any PowerPC
+variant. The 64-bit environment sets int to 32 bits and long and
+pointer to 64 bits, and generates code for PowerPC64, as for
+@option{-mpowerpc64}.
-@item -mscore5
-@opindex mscore5
-Specify the SCORE5 as the target architecture.
+@item -mfull-toc
+@itemx -mno-fp-in-toc
+@itemx -mno-sum-in-toc
+@itemx -mminimal-toc
+@opindex mfull-toc
+@opindex mno-fp-in-toc
+@opindex mno-sum-in-toc
+@opindex mminimal-toc
+Modify generation of the TOC (Table Of Contents), which is created for
+every executable file. The @option{-mfull-toc} option is selected by
+default. In that case, GCC allocates at least one TOC entry for
+each unique non-automatic variable reference in your program. GCC
+also places floating-point constants in the TOC@. However, only
+16,384 entries are available in the TOC@.
-@item -mscore5u
-@opindex mscore5u
-Specify the SCORE5U of the target architecture.
+If you receive a linker error message that saying you have overflowed
+the available TOC space, you can reduce the amount of TOC space used
+with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
+@option{-mno-fp-in-toc} prevents GCC from putting floating-point
+constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
+generate code to calculate the sum of an address and a constant at
+run time instead of putting that sum into the TOC@. You may specify one
+or both of these options. Each causes GCC to produce very slightly
+slower and larger code at the expense of conserving TOC space.
-@item -mscore7
-@opindex mscore7
-Specify the SCORE7 as the target architecture. This is the default.
+If you still run out of space in the TOC even when you specify both of
+these options, specify @option{-mminimal-toc} instead. This option causes
+GCC to make only one TOC entry for every file. When you specify this
+option, GCC produces code that is slower and larger but which
+uses extremely little TOC space. You may wish to use this option
+only on files that contain less frequently-executed code.
-@item -mscore7d
-@opindex mscore7d
-Specify the SCORE7D as the target architecture.
-@end table
+@item -maix64
+@itemx -maix32
+@opindex maix64
+@opindex maix32
+Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
+@code{long} type, and the infrastructure needed to support them.
+Specifying @option{-maix64} implies @option{-mpowerpc64},
+while @option{-maix32} disables the 64-bit ABI and
+implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
-@node SH Options
-@subsection SH Options
+@item -mxl-compat
+@itemx -mno-xl-compat
+@opindex mxl-compat
+@opindex mno-xl-compat
+Produce code that conforms more closely to IBM XL compiler semantics
+when using AIX-compatible ABI@. Pass floating-point arguments to
+prototyped functions beyond the register save area (RSA) on the stack
+in addition to argument FPRs. Do not assume that most significant
+double in 128-bit long double value is properly rounded when comparing
+values and converting to double. Use XL symbol names for long double
+support routines.
-These @samp{-m} options are defined for the SH implementations:
+The AIX calling convention was extended but not initially documented to
+handle an obscure K&R C case of calling a function that takes the
+address of its arguments with fewer arguments than declared. IBM XL
+compilers access floating-point arguments that do not fit in the
+RSA from the stack when a subroutine is compiled without
+optimization. Because always storing floating-point arguments on the
+stack is inefficient and rarely needed, this option is not enabled by
+default and only is necessary when calling subroutines compiled by IBM
+XL compilers without optimization.
-@table @gcctabopt
-@item -m1
-@opindex m1
-Generate code for the SH1.
+@item -mpe
+@opindex mpe
+Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
+application written to use message passing with special startup code to
+enable the application to run. The system must have PE installed in the
+standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
+must be overridden with the @option{-specs=} option to specify the
+appropriate directory location. The Parallel Environment does not
+support threads, so the @option{-mpe} option and the @option{-pthread}
+option are incompatible.
-@item -m2
-@opindex m2
-Generate code for the SH2.
+@item -malign-natural
+@itemx -malign-power
+@opindex malign-natural
+@opindex malign-power
+On AIX, 32-bit Darwin, and 64-bit PowerPC GNU/Linux, the option
+@option{-malign-natural} overrides the ABI-defined alignment of larger
+types, such as floating-point doubles, on their natural size-based boundary.
+The option @option{-malign-power} instructs GCC to follow the ABI-specified
+alignment rules. GCC defaults to the standard alignment defined in the ABI@.
-@item -m2e
-Generate code for the SH2e.
+On 64-bit Darwin, natural alignment is the default, and @option{-malign-power}
+is not supported.
-@item -m2a-nofpu
-@opindex m2a-nofpu
-Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way
-that the floating-point unit is not used.
+@item -msoft-float
+@itemx -mhard-float
+@opindex msoft-float
+@opindex mhard-float
+Generate code that does not use (uses) the floating-point register set.
+Software floating-point emulation is provided if you use the
+@option{-msoft-float} option, and pass the option to GCC when linking.
-@item -m2a-single-only
-@opindex m2a-single-only
-Generate code for the SH2a-FPU, in such a way that no double-precision
-floating-point operations are used.
+@item -msingle-float
+@itemx -mdouble-float
+@opindex msingle-float
+@opindex mdouble-float
+Generate code for single- or double-precision floating-point operations.
+@option{-mdouble-float} implies @option{-msingle-float}.
-@item -m2a-single
-@opindex m2a-single
-Generate code for the SH2a-FPU assuming the floating-point unit is in
-single-precision mode by default.
+@item -msimple-fpu
+@opindex msimple-fpu
+Do not generate @code{sqrt} and @code{div} instructions for hardware
+floating-point unit.
-@item -m2a
-@opindex m2a
-Generate code for the SH2a-FPU assuming the floating-point unit is in
-double-precision mode by default.
+@item -mfpu=@var{name}
+@opindex mfpu
+Specify type of floating-point unit. Valid values for @var{name} are
+@samp{sp_lite} (equivalent to @option{-msingle-float -msimple-fpu}),
+@samp{dp_lite} (equivalent to @option{-mdouble-float -msimple-fpu}),
+@samp{sp_full} (equivalent to @option{-msingle-float}),
+and @samp{dp_full} (equivalent to @option{-mdouble-float}).
-@item -m3
-@opindex m3
-Generate code for the SH3.
+@item -mxilinx-fpu
+@opindex mxilinx-fpu
+Perform optimizations for the floating-point unit on Xilinx PPC 405/440.
-@item -m3e
-@opindex m3e
-Generate code for the SH3e.
+@item -mmultiple
+@itemx -mno-multiple
+@opindex mmultiple
+@opindex mno-multiple
+Generate code that uses (does not use) the load multiple word
+instructions and the store multiple word instructions. These
+instructions are generated by default on POWER systems, and not
+generated on PowerPC systems. Do not use @option{-mmultiple} on little-endian
+PowerPC systems, since those instructions do not work when the
+processor is in little-endian mode. The exceptions are PPC740 and
+PPC750 which permit these instructions in little-endian mode.
-@item -m4-nofpu
-@opindex m4-nofpu
-Generate code for the SH4 without a floating-point unit.
+@item -mstring
+@itemx -mno-string
+@opindex mstring
+@opindex mno-string
+Generate code that uses (does not use) the load string instructions
+and the store string word instructions to save multiple registers and
+do small block moves. These instructions are generated by default on
+POWER systems, and not generated on PowerPC systems. Do not use
+@option{-mstring} on little-endian PowerPC systems, since those
+instructions do not work when the processor is in little-endian mode.
+The exceptions are PPC740 and PPC750 which permit these instructions
+in little-endian mode.
-@item -m4-single-only
-@opindex m4-single-only
-Generate code for the SH4 with a floating-point unit that only
-supports single-precision arithmetic.
+@item -mupdate
+@itemx -mno-update
+@opindex mupdate
+@opindex mno-update
+Generate code that uses (does not use) the load or store instructions
+that update the base register to the address of the calculated memory
+location. These instructions are generated by default. If you use
+@option{-mno-update}, there is a small window between the time that the
+stack pointer is updated and the address of the previous frame is
+stored, which means code that walks the stack frame across interrupts or
+signals may get corrupted data.
-@item -m4-single
-@opindex m4-single
-Generate code for the SH4 assuming the floating-point unit is in
-single-precision mode by default.
+@item -mavoid-indexed-addresses
+@itemx -mno-avoid-indexed-addresses
+@opindex mavoid-indexed-addresses
+@opindex mno-avoid-indexed-addresses
+Generate code that tries to avoid (not avoid) the use of indexed load
+or store instructions. These instructions can incur a performance
+penalty on Power6 processors in certain situations, such as when
+stepping through large arrays that cross a 16M boundary. This option
+is enabled by default when targeting Power6 and disabled otherwise.
-@item -m4
-@opindex m4
-Generate code for the SH4.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating-point multiply and
+accumulate instructions. These instructions are generated by default
+if hardware floating point is used. The machine-dependent
+@option{-mfused-madd} option is now mapped to the machine-independent
+@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
+mapped to @option{-ffp-contract=off}.
-@item -m4-100
-@opindex m4-100
-Generate code for SH4-100.
+@item -mmulhw
+@itemx -mno-mulhw
+@opindex mmulhw
+@opindex mno-mulhw
+Generate code that uses (does not use) the half-word multiply and
+multiply-accumulate instructions on the IBM 405, 440, 464 and 476 processors.
+These instructions are generated by default when targeting those
+processors.
-@item -m4-100-nofpu
-@opindex m4-100-nofpu
-Generate code for SH4-100 in such a way that the
-floating-point unit is not used.
+@item -mdlmzb
+@itemx -mno-dlmzb
+@opindex mdlmzb
+@opindex mno-dlmzb
+Generate code that uses (does not use) the string-search @samp{dlmzb}
+instruction on the IBM 405, 440, 464 and 476 processors. This instruction is
+generated by default when targeting those processors.
-@item -m4-100-single
-@opindex m4-100-single
-Generate code for SH4-100 assuming the floating-point unit is in
-single-precision mode by default.
+@item -mno-bit-align
+@itemx -mbit-align
+@opindex mno-bit-align
+@opindex mbit-align
+On System V.4 and embedded PowerPC systems do not (do) force structures
+and unions that contain bit-fields to be aligned to the base type of the
+bit-field.
-@item -m4-100-single-only
-@opindex m4-100-single-only
-Generate code for SH4-100 in such a way that no double-precision
-floating-point operations are used.
-
-@item -m4-200
-@opindex m4-200
-Generate code for SH4-200.
+For example, by default a structure containing nothing but 8
+@code{unsigned} bit-fields of length 1 is aligned to a 4-byte
+boundary and has a size of 4 bytes. By using @option{-mno-bit-align},
+the structure is aligned to a 1-byte boundary and is 1 byte in
+size.
-@item -m4-200-nofpu
-@opindex m4-200-nofpu
-Generate code for SH4-200 without in such a way that the
-floating-point unit is not used.
+@item -mno-strict-align
+@itemx -mstrict-align
+@opindex mno-strict-align
+@opindex mstrict-align
+On System V.4 and embedded PowerPC systems do not (do) assume that
+unaligned memory references are handled by the system.
-@item -m4-200-single
-@opindex m4-200-single
-Generate code for SH4-200 assuming the floating-point unit is in
-single-precision mode by default.
+@item -mrelocatable
+@itemx -mno-relocatable
+@opindex mrelocatable
+@opindex mno-relocatable
+Generate code that allows (does not allow) a static executable to be
+relocated to a different address at run time. A simple embedded
+PowerPC system loader should relocate the entire contents of
+@code{.got2} and 4-byte locations listed in the @code{.fixup} section,
+a table of 32-bit addresses generated by this option. For this to
+work, all objects linked together must be compiled with
+@option{-mrelocatable} or @option{-mrelocatable-lib}.
+@option{-mrelocatable} code aligns the stack to an 8-byte boundary.
-@item -m4-200-single-only
-@opindex m4-200-single-only
-Generate code for SH4-200 in such a way that no double-precision
-floating-point operations are used.
+@item -mrelocatable-lib
+@itemx -mno-relocatable-lib
+@opindex mrelocatable-lib
+@opindex mno-relocatable-lib
+Like @option{-mrelocatable}, @option{-mrelocatable-lib} generates a
+@code{.fixup} section to allow static executables to be relocated at
+run time, but @option{-mrelocatable-lib} does not use the smaller stack
+alignment of @option{-mrelocatable}. Objects compiled with
+@option{-mrelocatable-lib} may be linked with objects compiled with
+any combination of the @option{-mrelocatable} options.
-@item -m4-300
-@opindex m4-300
-Generate code for SH4-300.
+@item -mno-toc
+@itemx -mtoc
+@opindex mno-toc
+@opindex mtoc
+On System V.4 and embedded PowerPC systems do not (do) assume that
+register 2 contains a pointer to a global area pointing to the addresses
+used in the program.
-@item -m4-300-nofpu
-@opindex m4-300-nofpu
-Generate code for SH4-300 without in such a way that the
-floating-point unit is not used.
+@item -mlittle
+@itemx -mlittle-endian
+@opindex mlittle
+@opindex mlittle-endian
+On System V.4 and embedded PowerPC systems compile code for the
+processor in little-endian mode. The @option{-mlittle-endian} option is
+the same as @option{-mlittle}.
-@item -m4-300-single
-@opindex m4-300-single
-Generate code for SH4-300 in such a way that no double-precision
-floating-point operations are used.
+@item -mbig
+@itemx -mbig-endian
+@opindex mbig
+@opindex mbig-endian
+On System V.4 and embedded PowerPC systems compile code for the
+processor in big-endian mode. The @option{-mbig-endian} option is
+the same as @option{-mbig}.
-@item -m4-300-single-only
-@opindex m4-300-single-only
-Generate code for SH4-300 in such a way that no double-precision
-floating-point operations are used.
+@item -mdynamic-no-pic
+@opindex mdynamic-no-pic
+On Darwin and Mac OS X systems, compile code so that it is not
+relocatable, but that its external references are relocatable. The
+resulting code is suitable for applications, but not shared
+libraries.
-@item -m4-340
-@opindex m4-340
-Generate code for SH4-340 (no MMU, no FPU).
+@item -msingle-pic-base
+@opindex msingle-pic-base
+Treat the register used for PIC addressing as read-only, rather than
+loading it in the prologue for each function. The runtime system is
+responsible for initializing this register with an appropriate value
+before execution begins.
-@item -m4-500
-@opindex m4-500
-Generate code for SH4-500 (no FPU). Passes @option{-isa=sh4-nofpu} to the
-assembler.
+@item -mprioritize-restricted-insns=@var{priority}
+@opindex mprioritize-restricted-insns
+This option controls the priority that is assigned to
+dispatch-slot restricted instructions during the second scheduling
+pass. The argument @var{priority} takes the value @samp{0}, @samp{1},
+or @samp{2} to assign no, highest, or second-highest (respectively)
+priority to dispatch-slot restricted
+instructions.
-@item -m4a-nofpu
-@opindex m4a-nofpu
-Generate code for the SH4al-dsp, or for a SH4a in such a way that the
-floating-point unit is not used.
+@item -msched-costly-dep=@var{dependence_type}
+@opindex msched-costly-dep
+This option controls which dependences are considered costly
+by the target during instruction scheduling. The argument
+@var{dependence_type} takes one of the following values:
-@item -m4a-single-only
-@opindex m4a-single-only
-Generate code for the SH4a, in such a way that no double-precision
-floating-point operations are used.
+@table @asis
+@item @samp{no}
+No dependence is costly.
-@item -m4a-single
-@opindex m4a-single
-Generate code for the SH4a assuming the floating-point unit is in
-single-precision mode by default.
+@item @samp{all}
+All dependences are costly.
-@item -m4a
-@opindex m4a
-Generate code for the SH4a.
+@item @samp{true_store_to_load}
+A true dependence from store to load is costly.
-@item -m4al
-@opindex m4al
-Same as @option{-m4a-nofpu}, except that it implicitly passes
-@option{-dsp} to the assembler. GCC doesn't generate any DSP
-instructions at the moment.
+@item @samp{store_to_load}
+Any dependence from store to load is costly.
-@item -mb
-@opindex mb
-Compile code for the processor in big-endian mode.
+@item @var{number}
+Any dependence for which the latency is greater than or equal to
+@var{number} is costly.
+@end table
-@item -ml
-@opindex ml
-Compile code for the processor in little-endian mode.
+@item -minsert-sched-nops=@var{scheme}
+@opindex minsert-sched-nops
+This option controls which NOP insertion scheme is used during
+the second scheduling pass. The argument @var{scheme} takes one of the
+following values:
-@item -mdalign
-@opindex mdalign
-Align doubles at 64-bit boundaries. Note that this changes the calling
-conventions, and thus some functions from the standard C library do
-not work unless you recompile it first with @option{-mdalign}.
+@table @asis
+@item @samp{no}
+Don't insert NOPs.
-@item -mrelax
-@opindex mrelax
-Shorten some address references at link time, when possible; uses the
-linker option @option{-relax}.
+@item @samp{pad}
+Pad with NOPs any dispatch group that has vacant issue slots,
+according to the scheduler's grouping.
-@item -mbigtable
-@opindex mbigtable
-Use 32-bit offsets in @code{switch} tables. The default is to use
-16-bit offsets.
+@item @samp{regroup_exact}
+Insert NOPs to force costly dependent insns into
+separate groups. Insert exactly as many NOPs as needed to force an insn
+to a new group, according to the estimated processor grouping.
-@item -mbitops
-@opindex mbitops
-Enable the use of bit manipulation instructions on SH2A.
+@item @var{number}
+Insert NOPs to force costly dependent insns into
+separate groups. Insert @var{number} NOPs to force an insn to a new group.
+@end table
-@item -mfmovd
-@opindex mfmovd
-Enable the use of the instruction @code{fmovd}. Check @option{-mdalign} for
-alignment constraints.
+@item -mcall-sysv
+@opindex mcall-sysv
+On System V.4 and embedded PowerPC systems compile code using calling
+conventions that adhere to the March 1995 draft of the System V
+Application Binary Interface, PowerPC processor supplement. This is the
+default unless you configured GCC using @samp{powerpc-*-eabiaix}.
-@item -mrenesas
-@opindex mrenesas
-Comply with the calling conventions defined by Renesas.
+@item -mcall-sysv-eabi
+@itemx -mcall-eabi
+@opindex mcall-sysv-eabi
+@opindex mcall-eabi
+Specify both @option{-mcall-sysv} and @option{-meabi} options.
-@item -mno-renesas
-@opindex mno-renesas
-Comply with the calling conventions defined for GCC before the Renesas
-conventions were available. This option is the default for all
-targets of the SH toolchain.
+@item -mcall-sysv-noeabi
+@opindex mcall-sysv-noeabi
+Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
-@item -mnomacsave
-@opindex mnomacsave
-Mark the @code{MAC} register as call-clobbered, even if
-@option{-mrenesas} is given.
+@item -mcall-aixdesc
+@opindex m
+On System V.4 and embedded PowerPC systems compile code for the AIX
+operating system.
-@item -mieee
-@itemx -mno-ieee
-@opindex mieee
-@opindex mno-ieee
-Control the IEEE compliance of floating-point comparisons, which affects the
-handling of cases where the result of a comparison is unordered. By default
-@option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is
-enabled @option{-mno-ieee} is implicitly set, which results in faster
-floating-point greater-equal and less-equal comparisons. The implcit settings
-can be overridden by specifying either @option{-mieee} or @option{-mno-ieee}.
+@item -mcall-linux
+@opindex mcall-linux
+On System V.4 and embedded PowerPC systems compile code for the
+Linux-based GNU system.
-@item -minline-ic_invalidate
-@opindex minline-ic_invalidate
-Inline code to invalidate instruction cache entries after setting up
-nested function trampolines.
-This option has no effect if @option{-musermode} is in effect and the selected
-code generation option (e.g. @option{-m4}) does not allow the use of the @code{icbi}
-instruction.
-If the selected code generation option does not allow the use of the @code{icbi}
-instruction, and @option{-musermode} is not in effect, the inlined code
-manipulates the instruction cache address array directly with an associative
-write. This not only requires privileged mode at run time, but it also
-fails if the cache line had been mapped via the TLB and has become unmapped.
+@item -mcall-freebsd
+@opindex mcall-freebsd
+On System V.4 and embedded PowerPC systems compile code for the
+FreeBSD operating system.
-@item -misize
-@opindex misize
-Dump instruction size and location in the assembly code.
-
-@item -mpadstruct
-@opindex mpadstruct
-This option is deprecated. It pads structures to multiple of 4 bytes,
-which is incompatible with the SH ABI@.
+@item -mcall-netbsd
+@opindex mcall-netbsd
+On System V.4 and embedded PowerPC systems compile code for the
+NetBSD operating system.
-@item -matomic-model=@var{model}
-@opindex matomic-model=@var{model}
-Sets the model of atomic operations and additional parameters as a comma
-separated list. For details on the atomic built-in functions see
-@ref{__atomic Builtins}. The following models and parameters are supported:
+@item -mcall-openbsd
+@opindex mcall-netbsd
+On System V.4 and embedded PowerPC systems compile code for the
+OpenBSD operating system.
-@table @samp
+@item -maix-struct-return
+@opindex maix-struct-return
+Return all structures in memory (as specified by the AIX ABI)@.
-@item none
-Disable compiler generated atomic sequences and emit library calls for atomic
-operations. This is the default if the target is not @code{sh*-*-linux*}.
+@item -msvr4-struct-return
+@opindex msvr4-struct-return
+Return structures smaller than 8 bytes in registers (as specified by the
+SVR4 ABI)@.
-@item soft-gusa
-Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
-built-in functions. The generated atomic sequences require additional support
-from the interrupt/exception handling code of the system and are only suitable
-for SH3* and SH4* single-core systems. This option is enabled by default when
-the target is @code{sh*-*-linux*} and SH3* or SH4*. When the target is SH4A,
-this option also partially utilizes the hardware atomic instructions
-@code{movli.l} and @code{movco.l} to create more efficient code, unless
-@samp{strict} is specified.
+@item -mabi=@var{abi-type}
+@opindex mabi
+Extend the current ABI with a particular extension, or remove such extension.
+Valid values are @samp{altivec}, @samp{no-altivec}, @samp{spe},
+@samp{no-spe}, @samp{ibmlongdouble}, @samp{ieeelongdouble},
+@samp{elfv1}, @samp{elfv2}@.
-@item soft-tcb
-Generate software atomic sequences that use a variable in the thread control
-block. This is a variation of the gUSA sequences which can also be used on
-SH1* and SH2* targets. The generated atomic sequences require additional
-support from the interrupt/exception handling code of the system and are only
-suitable for single-core systems. When using this model, the @samp{gbr-offset=}
-parameter has to be specified as well.
+@item -mabi=spe
+@opindex mabi=spe
+Extend the current ABI with SPE ABI extensions. This does not change
+the default ABI, instead it adds the SPE ABI extensions to the current
+ABI@.
-@item soft-imask
-Generate software atomic sequences that temporarily disable interrupts by
-setting @code{SR.IMASK = 1111}. This model works only when the program runs
-in privileged mode and is only suitable for single-core systems. Additional
-support from the interrupt/exception handling code of the system is not
-required. This model is enabled by default when the target is
-@code{sh*-*-linux*} and SH1* or SH2*.
+@item -mabi=no-spe
+@opindex mabi=no-spe
+Disable Book-E SPE ABI extensions for the current ABI@.
-@item hard-llcs
-Generate hardware atomic sequences using the @code{movli.l} and @code{movco.l}
-instructions only. This is only available on SH4A and is suitable for
-multi-core systems. Since the hardware instructions support only 32 bit atomic
-variables access to 8 or 16 bit variables is emulated with 32 bit accesses.
-Code compiled with this option is also compatible with other software
-atomic model interrupt/exception handling systems if executed on an SH4A
-system. Additional support from the interrupt/exception handling code of the
-system is not required for this model.
+@item -mabi=ibmlongdouble
+@opindex mabi=ibmlongdouble
+Change the current ABI to use IBM extended-precision long double.
+This is a PowerPC 32-bit SYSV ABI option.
-@item gbr-offset=
-This parameter specifies the offset in bytes of the variable in the thread
-control block structure that should be used by the generated atomic sequences
-when the @samp{soft-tcb} model has been selected. For other models this
-parameter is ignored. The specified value must be an integer multiple of four
-and in the range 0-1020.
+@item -mabi=ieeelongdouble
+@opindex mabi=ieeelongdouble
+Change the current ABI to use IEEE extended-precision long double.
+This is a PowerPC 32-bit Linux ABI option.
-@item strict
-This parameter prevents mixed usage of multiple atomic models, even if they
-are compatible, and makes the compiler generate atomic sequences of the
-specified model only.
+@item -mabi=elfv1
+@opindex mabi=elfv1
+Change the current ABI to use the ELFv1 ABI.
+This is the default ABI for big-endian PowerPC 64-bit Linux.
+Overriding the default ABI requires special system support and is
+likely to fail in spectacular ways.
-@end table
+@item -mabi=elfv2
+@opindex mabi=elfv2
+Change the current ABI to use the ELFv2 ABI.
+This is the default ABI for little-endian PowerPC 64-bit Linux.
+Overriding the default ABI requires special system support and is
+likely to fail in spectacular ways.
-@item -mtas
-@opindex mtas
-Generate the @code{tas.b} opcode for @code{__atomic_test_and_set}.
-Notice that depending on the particular hardware and software configuration
-this can degrade overall performance due to the operand cache line flushes
-that are implied by the @code{tas.b} instruction. On multi-core SH4A
-processors the @code{tas.b} instruction must be used with caution since it
-can result in data corruption for certain cache configurations.
+@item -mprototype
+@itemx -mno-prototype
+@opindex mprototype
+@opindex mno-prototype
+On System V.4 and embedded PowerPC systems assume that all calls to
+variable argument functions are properly prototyped. Otherwise, the
+compiler must insert an instruction before every non-prototyped call to
+set or clear bit 6 of the condition code register (@code{CR}) to
+indicate whether floating-point values are passed in the floating-point
+registers in case the function takes variable arguments. With
+@option{-mprototype}, only calls to prototyped variable argument functions
+set or clear the bit.
-@item -mprefergot
-@opindex mprefergot
-When generating position-independent code, emit function calls using
-the Global Offset Table instead of the Procedure Linkage Table.
+@item -msim
+@opindex msim
+On embedded PowerPC systems, assume that the startup module is called
+@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
+@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}
+configurations.
-@item -musermode
-@itemx -mno-usermode
-@opindex musermode
-@opindex mno-usermode
-Don't allow (allow) the compiler generating privileged mode code. Specifying
-@option{-musermode} also implies @option{-mno-inline-ic_invalidate} if the
-inlined code would not work in user mode. @option{-musermode} is the default
-when the target is @code{sh*-*-linux*}. If the target is SH1* or SH2*
-@option{-musermode} has no effect, since there is no user mode.
+@item -mmvme
+@opindex mmvme
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libmvme.a} and
+@file{libc.a}.
-@item -multcost=@var{number}
-@opindex multcost=@var{number}
-Set the cost to assume for a multiply insn.
+@item -mads
+@opindex mads
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libads.a} and
+@file{libc.a}.
-@item -mdiv=@var{strategy}
-@opindex mdiv=@var{strategy}
-Set the division strategy to be used for integer division operations.
-@var{strategy} can be one of:
+@item -myellowknife
+@opindex myellowknife
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libyk.a} and
+@file{libc.a}.
-@table @samp
+@item -mvxworks
+@opindex mvxworks
+On System V.4 and embedded PowerPC systems, specify that you are
+compiling for a VxWorks system.
-@item call-div1
-Calls a library function that uses the single-step division instruction
-@code{div1} to perform the operation. Division by zero calculates an
-unspecified result and does not trap. This is the default except for SH4,
-SH2A and SHcompact.
+@item -memb
+@opindex memb
+On embedded PowerPC systems, set the @code{PPC_EMB} bit in the ELF flags
+header to indicate that @samp{eabi} extended relocations are used.
-@item call-fp
-Calls a library function that performs the operation in double precision
-floating point. Division by zero causes a floating-point exception. This is
-the default for SHcompact with FPU. Specifying this for targets that do not
-have a double precision FPU defaults to @code{call-div1}.
+@item -meabi
+@itemx -mno-eabi
+@opindex meabi
+@opindex mno-eabi
+On System V.4 and embedded PowerPC systems do (do not) adhere to the
+Embedded Applications Binary Interface (EABI), which is a set of
+modifications to the System V.4 specifications. Selecting @option{-meabi}
+means that the stack is aligned to an 8-byte boundary, a function
+@code{__eabi} is called from @code{main} to set up the EABI
+environment, and the @option{-msdata} option can use both @code{r2} and
+@code{r13} to point to two separate small data areas. Selecting
+@option{-mno-eabi} means that the stack is aligned to a 16-byte boundary,
+no EABI initialization function is called from @code{main}, and the
+@option{-msdata} option only uses @code{r13} to point to a single
+small data area. The @option{-meabi} option is on by default if you
+configured GCC using one of the @samp{powerpc*-*-eabi*} options.
-@item call-table
-Calls a library function that uses a lookup table for small divisors and
-the @code{div1} instruction with case distinction for larger divisors. Division
-by zero calculates an unspecified result and does not trap. This is the default
-for SH4. Specifying this for targets that do not have dynamic shift
-instructions defaults to @code{call-div1}.
+@item -msdata=eabi
+@opindex msdata=eabi
+On System V.4 and embedded PowerPC systems, put small initialized
+@code{const} global and static data in the @code{.sdata2} section, which
+is pointed to by register @code{r2}. Put small initialized
+non-@code{const} global and static data in the @code{.sdata} section,
+which is pointed to by register @code{r13}. Put small uninitialized
+global and static data in the @code{.sbss} section, which is adjacent to
+the @code{.sdata} section. The @option{-msdata=eabi} option is
+incompatible with the @option{-mrelocatable} option. The
+@option{-msdata=eabi} option also sets the @option{-memb} option.
-@end table
+@item -msdata=sysv
+@opindex msdata=sysv
+On System V.4 and embedded PowerPC systems, put small global and static
+data in the @code{.sdata} section, which is pointed to by register
+@code{r13}. Put small uninitialized global and static data in the
+@code{.sbss} section, which is adjacent to the @code{.sdata} section.
+The @option{-msdata=sysv} option is incompatible with the
+@option{-mrelocatable} option.
-When a division strategy has not been specified the default strategy is
-selected based on the current target. For SH2A the default strategy is to
-use the @code{divs} and @code{divu} instructions instead of library function
-calls.
+@item -msdata=default
+@itemx -msdata
+@opindex msdata=default
+@opindex msdata
+On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
+compile code the same as @option{-msdata=eabi}, otherwise compile code the
+same as @option{-msdata=sysv}.
-@item -maccumulate-outgoing-args
-@opindex maccumulate-outgoing-args
-Reserve space once for outgoing arguments in the function prologue rather
-than around each call. Generally beneficial for performance and size. Also
-needed for unwinding to avoid changing the stack frame around conditional code.
+@item -msdata=data
+@opindex msdata=data
+On System V.4 and embedded PowerPC systems, put small global
+data in the @code{.sdata} section. Put small uninitialized global
+data in the @code{.sbss} section. Do not use register @code{r13}
+to address small data however. This is the default behavior unless
+other @option{-msdata} options are used.
-@item -mdivsi3_libfunc=@var{name}
-@opindex mdivsi3_libfunc=@var{name}
-Set the name of the library function used for 32-bit signed division to
-@var{name}.
-This only affects the name used in the @samp{call} division strategies, and
-the compiler still expects the same sets of input/output/clobbered registers as
-if this option were not present.
-
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
+@item -msdata=none
+@itemx -mno-sdata
+@opindex msdata=none
+@opindex mno-sdata
+On embedded PowerPC systems, put all initialized global and static data
+in the @code{.data} section, and all uninitialized data in the
+@code{.bss} section.
-@item -mbranch-cost=@var{num}
-@opindex mbranch-cost=@var{num}
-Assume @var{num} to be the cost for a branch instruction. Higher numbers
-make the compiler try to generate more branch-free code if possible.
-If not specified the value is selected depending on the processor type that
-is being compiled for.
+@item -mblock-move-inline-limit=@var{num}
+@opindex mblock-move-inline-limit
+Inline all block moves (such as calls to @code{memcpy} or structure
+copies) less than or equal to @var{num} bytes. The minimum value for
+@var{num} is 32 bytes on 32-bit targets and 64 bytes on 64-bit
+targets. The default value is target-specific.
-@item -mzdcbranch
-@itemx -mno-zdcbranch
-@opindex mzdcbranch
-@opindex mno-zdcbranch
-Assume (do not assume) that zero displacement conditional branch instructions
-@code{bt} and @code{bf} are fast. If @option{-mzdcbranch} is specified, the
-compiler prefers zero displacement branch code sequences. This is
-enabled by default when generating code for SH4 and SH4A. It can be explicitly
-disabled by specifying @option{-mno-zdcbranch}.
+@item -G @var{num}
+@opindex G
+@cindex smaller data references (PowerPC)
+@cindex .sdata/.sdata2 references (PowerPC)
+On embedded PowerPC systems, put global and static items less than or
+equal to @var{num} bytes into the small data or BSS sections instead of
+the normal data or BSS section. By default, @var{num} is 8. The
+@option{-G @var{num}} switch is also passed to the linker.
+All modules should be compiled with the same @option{-G @var{num}} value.
-@item -mcbranch-force-delay-slot
-@opindex mcbranch-force-delay-slot
-Force the usage of delay slots for conditional branches, which stuffs the delay
-slot with a @code{nop} if a suitable instruction can't be found. By default
-this option is disabled. It can be enabled to work around hardware bugs as
-found in the original SH7055.
+@item -mregnames
+@itemx -mno-regnames
+@opindex mregnames
+@opindex mno-regnames
+On System V.4 and embedded PowerPC systems do (do not) emit register
+names in the assembly language output using symbolic forms.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Generate code that uses (does not use) the floating-point multiply and
-accumulate instructions. These instructions are generated by default
-if hardware floating point is used. The machine-dependent
-@option{-mfused-madd} option is now mapped to the machine-independent
-@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
-mapped to @option{-ffp-contract=off}.
+@item -mlongcall
+@itemx -mno-longcall
+@opindex mlongcall
+@opindex mno-longcall
+By default assume that all calls are far away so that a longer and more
+expensive calling sequence is required. This is required for calls
+farther than 32 megabytes (33,554,432 bytes) from the current location.
+A short call is generated if the compiler knows
+the call cannot be that far away. This setting can be overridden by
+the @code{shortcall} function attribute, or by @code{#pragma
+longcall(0)}.
-@item -mfsca
-@itemx -mno-fsca
-@opindex mfsca
-@opindex mno-fsca
-Allow or disallow the compiler to emit the @code{fsca} instruction for sine
-and cosine approximations. The option @option{-mfsca} must be used in
-combination with @option{-funsafe-math-optimizations}. It is enabled by default
-when generating code for SH4A. Using @option{-mno-fsca} disables sine and cosine
-approximations even if @option{-funsafe-math-optimizations} is in effect.
+Some linkers are capable of detecting out-of-range calls and generating
+glue code on the fly. On these systems, long calls are unnecessary and
+generate slower code. As of this writing, the AIX linker can do this,
+as can the GNU linker for PowerPC/64. It is planned to add this feature
+to the GNU linker for 32-bit PowerPC systems as well.
-@item -mfsrra
-@itemx -mno-fsrra
-@opindex mfsrra
-@opindex mno-fsrra
-Allow or disallow the compiler to emit the @code{fsrra} instruction for
-reciprocal square root approximations. The option @option{-mfsrra} must be used
-in combination with @option{-funsafe-math-optimizations} and
-@option{-ffinite-math-only}. It is enabled by default when generating code for
-SH4A. Using @option{-mno-fsrra} disables reciprocal square root approximations
-even if @option{-funsafe-math-optimizations} and @option{-ffinite-math-only} are
-in effect.
+On Darwin/PPC systems, @code{#pragma longcall} generates @code{jbsr
+callee, L42}, plus a @dfn{branch island} (glue code). The two target
+addresses represent the callee and the branch island. The
+Darwin/PPC linker prefers the first address and generates a @code{bl
+callee} if the PPC @code{bl} instruction reaches the callee directly;
+otherwise, the linker generates @code{bl L42} to call the branch
+island. The branch island is appended to the body of the
+calling function; it computes the full 32-bit address of the callee
+and jumps to it.
-@item -mpretend-cmove
-@opindex mpretend-cmove
-Prefer zero-displacement conditional branches for conditional move instruction
-patterns. This can result in faster code on the SH4 processor.
+On Mach-O (Darwin) systems, this option directs the compiler emit to
+the glue for every direct call, and the Darwin linker decides whether
+to use or discard it.
-@item -mfdpic
-@opindex fdpic
-Generate code using the FDPIC ABI.
+In the future, GCC may ignore all longcall specifications
+when the linker is known to generate glue.
-@end table
+@item -mtls-markers
+@itemx -mno-tls-markers
+@opindex mtls-markers
+@opindex mno-tls-markers
+Mark (do not mark) calls to @code{__tls_get_addr} with a relocation
+specifying the function argument. The relocation allows the linker to
+reliably associate function call with argument setup instructions for
+TLS optimization, which in turn allows GCC to better schedule the
+sequence.
-@node Solaris 2 Options
-@subsection Solaris 2 Options
-@cindex Solaris 2 options
+@item -pthread
+@opindex pthread
+Adds support for multithreading with the @dfn{pthreads} library.
+This option sets flags for both the preprocessor and linker.
-These @samp{-m} options are supported on Solaris 2:
+@item -mrecip
+@itemx -mno-recip
+@opindex mrecip
+This option enables use of the reciprocal estimate and
+reciprocal square root estimate instructions with additional
+Newton-Raphson steps to increase precision instead of doing a divide or
+square root and divide for floating-point arguments. You should use
+the @option{-ffast-math} option when using @option{-mrecip} (or at
+least @option{-funsafe-math-optimizations},
+@option{-ffinite-math-only}, @option{-freciprocal-math} and
+@option{-fno-trapping-math}). Note that while the throughput of the
+sequence is generally higher than the throughput of the non-reciprocal
+instruction, the precision of the sequence can be decreased by up to 2
+ulp (i.e.@: the inverse of 1.0 equals 0.99999994) for reciprocal square
+roots.
-@table @gcctabopt
-@item -mclear-hwcap
-@opindex mclear-hwcap
-@option{-mclear-hwcap} tells the compiler to remove the hardware
-capabilities generated by the Solaris assembler. This is only necessary
-when object files use ISA extensions not supported by the current
-machine, but check at runtime whether or not to use them.
+@item -mrecip=@var{opt}
+@opindex mrecip=opt
+This option controls which reciprocal estimate instructions
+may be used. @var{opt} is a comma-separated list of options, which may
+be preceded by a @code{!} to invert the option:
-@item -mimpure-text
-@opindex mimpure-text
-@option{-mimpure-text}, used in addition to @option{-shared}, tells
-the compiler to not pass @option{-z text} to the linker when linking a
-shared object. Using this option, you can link position-dependent
-code into a shared object.
+@table @samp
-@option{-mimpure-text} suppresses the ``relocations remain against
-allocatable but non-writable sections'' linker error message.
-However, the necessary relocations trigger copy-on-write, and the
-shared object is not actually shared across processes. Instead of
-using @option{-mimpure-text}, you should compile all source code with
-@option{-fpic} or @option{-fPIC}.
+@item all
+Enable all estimate instructions.
-@end table
+@item default
+Enable the default instructions, equivalent to @option{-mrecip}.
-These switches are supported in addition to the above on Solaris 2:
+@item none
+Disable all estimate instructions, equivalent to @option{-mno-recip}.
-@table @gcctabopt
-@item -pthreads
-@opindex pthreads
-Add support for multithreading using the POSIX threads library. This
-option sets flags for both the preprocessor and linker. This option does
-not affect the thread safety of object code produced by the compiler or
-that of libraries supplied with it.
+@item div
+Enable the reciprocal approximation instructions for both
+single and double precision.
-@item -pthread
-@opindex pthread
-This is a synonym for @option{-pthreads}.
-@end table
+@item divf
+Enable the single-precision reciprocal approximation instructions.
-@node SPARC Options
-@subsection SPARC Options
-@cindex SPARC options
+@item divd
+Enable the double-precision reciprocal approximation instructions.
-These @samp{-m} options are supported on the SPARC:
+@item rsqrt
+Enable the reciprocal square root approximation instructions for both
+single and double precision.
-@table @gcctabopt
-@item -mno-app-regs
-@itemx -mapp-regs
-@opindex mno-app-regs
-@opindex mapp-regs
-Specify @option{-mapp-regs} to generate output using the global registers
-2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the
-global register 1, each global register 2 through 4 is then treated as an
-allocable register that is clobbered by function calls. This is the default.
+@item rsqrtf
+Enable the single-precision reciprocal square root approximation instructions.
-To be fully SVR4 ABI-compliant at the cost of some performance loss,
-specify @option{-mno-app-regs}. You should compile libraries and system
-software with this option.
+@item rsqrtd
+Enable the double-precision reciprocal square root approximation instructions.
-@item -mflat
-@itemx -mno-flat
-@opindex mflat
-@opindex mno-flat
-With @option{-mflat}, the compiler does not generate save/restore instructions
-and uses a ``flat'' or single register window model. This model is compatible
-with the regular register window model. The local registers and the input
-registers (0--5) are still treated as ``call-saved'' registers and are
-saved on the stack as needed.
+@end table
-With @option{-mno-flat} (the default), the compiler generates save/restore
-instructions (except for leaf functions). This is the normal operating mode.
+So, for example, @option{-mrecip=all,!rsqrtd} enables
+all of the reciprocal estimate instructions, except for the
+@code{FRSQRTE}, @code{XSRSQRTEDP}, and @code{XVRSQRTEDP} instructions
+which handle the double-precision reciprocal square root calculations.
-@item -mfpu
-@itemx -mhard-float
-@opindex mfpu
-@opindex mhard-float
-Generate output containing floating-point instructions. This is the
-default.
+@item -mrecip-precision
+@itemx -mno-recip-precision
+@opindex mrecip-precision
+Assume (do not assume) that the reciprocal estimate instructions
+provide higher-precision estimates than is mandated by the PowerPC
+ABI. Selecting @option{-mcpu=power6}, @option{-mcpu=power7} or
+@option{-mcpu=power8} automatically selects @option{-mrecip-precision}.
+The double-precision square root estimate instructions are not generated by
+default on low-precision machines, since they do not provide an
+estimate that converges after three steps.
-@item -mno-fpu
-@itemx -msoft-float
-@opindex mno-fpu
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all SPARC
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation. The embedded targets @samp{sparc-*-aout} and
-@samp{sparclite-*-*} do provide software floating-point support.
+@item -mveclibabi=@var{type}
+@opindex mveclibabi
+Specifies the ABI type to use for vectorizing intrinsics using an
+external library. The only type supported at present is @samp{mass},
+which specifies to use IBM's Mathematical Acceleration Subsystem
+(MASS) libraries for vectorizing intrinsics using external libraries.
+GCC currently emits calls to @code{acosd2}, @code{acosf4},
+@code{acoshd2}, @code{acoshf4}, @code{asind2}, @code{asinf4},
+@code{asinhd2}, @code{asinhf4}, @code{atan2d2}, @code{atan2f4},
+@code{atand2}, @code{atanf4}, @code{atanhd2}, @code{atanhf4},
+@code{cbrtd2}, @code{cbrtf4}, @code{cosd2}, @code{cosf4},
+@code{coshd2}, @code{coshf4}, @code{erfcd2}, @code{erfcf4},
+@code{erfd2}, @code{erff4}, @code{exp2d2}, @code{exp2f4},
+@code{expd2}, @code{expf4}, @code{expm1d2}, @code{expm1f4},
+@code{hypotd2}, @code{hypotf4}, @code{lgammad2}, @code{lgammaf4},
+@code{log10d2}, @code{log10f4}, @code{log1pd2}, @code{log1pf4},
+@code{log2d2}, @code{log2f4}, @code{logd2}, @code{logf4},
+@code{powd2}, @code{powf4}, @code{sind2}, @code{sinf4}, @code{sinhd2},
+@code{sinhf4}, @code{sqrtd2}, @code{sqrtf4}, @code{tand2},
+@code{tanf4}, @code{tanhd2}, and @code{tanhf4} when generating code
+for power7. Both @option{-ftree-vectorize} and
+@option{-funsafe-math-optimizations} must also be enabled. The MASS
+libraries must be specified at link time.
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
+@item -mfriz
+@itemx -mno-friz
+@opindex mfriz
+Generate (do not generate) the @code{friz} instruction when the
+@option{-funsafe-math-optimizations} option is used to optimize
+rounding of floating-point values to 64-bit integer and back to floating
+point. The @code{friz} instruction does not return the same value if
+the floating-point number is too large to fit in an integer.
-@item -mhard-quad-float
-@opindex mhard-quad-float
-Generate output containing quad-word (long double) floating-point
-instructions.
+@item -mpointers-to-nested-functions
+@itemx -mno-pointers-to-nested-functions
+@opindex mpointers-to-nested-functions
+Generate (do not generate) code to load up the static chain register
+(@code{r11}) when calling through a pointer on AIX and 64-bit Linux
+systems where a function pointer points to a 3-word descriptor giving
+the function address, TOC value to be loaded in register @code{r2}, and
+static chain value to be loaded in register @code{r11}. The
+@option{-mpointers-to-nested-functions} is on by default. You cannot
+call through pointers to nested functions or pointers
+to functions compiled in other languages that use the static chain if
+you use @option{-mno-pointers-to-nested-functions}.
-@item -msoft-quad-float
-@opindex msoft-quad-float
-Generate output containing library calls for quad-word (long double)
-floating-point instructions. The functions called are those specified
-in the SPARC ABI@. This is the default.
+@item -msave-toc-indirect
+@itemx -mno-save-toc-indirect
+@opindex msave-toc-indirect
+Generate (do not generate) code to save the TOC value in the reserved
+stack location in the function prologue if the function calls through
+a pointer on AIX and 64-bit Linux systems. If the TOC value is not
+saved in the prologue, it is saved just before the call through the
+pointer. The @option{-mno-save-toc-indirect} option is the default.
-As of this writing, there are no SPARC implementations that have hardware
-support for the quad-word floating-point instructions. They all invoke
-a trap handler for one of these instructions, and then the trap handler
-emulates the effect of the instruction. Because of the trap handler overhead,
-this is much slower than calling the ABI library routines. Thus the
-@option{-msoft-quad-float} option is the default.
+@item -mcompat-align-parm
+@itemx -mno-compat-align-parm
+@opindex mcompat-align-parm
+Generate (do not generate) code to pass structure parameters with a
+maximum alignment of 64 bits, for compatibility with older versions
+of GCC.
-@item -mno-unaligned-doubles
-@itemx -munaligned-doubles
-@opindex mno-unaligned-doubles
-@opindex munaligned-doubles
-Assume that doubles have 8-byte alignment. This is the default.
+Older versions of GCC (prior to 4.9.0) incorrectly did not align a
+structure parameter on a 128-bit boundary when that structure contained
+a member requiring 128-bit alignment. This is corrected in more
+recent versions of GCC. This option may be used to generate code
+that is compatible with functions compiled with older versions of
+GCC.
-With @option{-munaligned-doubles}, GCC assumes that doubles have 8-byte
-alignment only if they are contained in another type, or if they have an
-absolute address. Otherwise, it assumes they have 4-byte alignment.
-Specifying this option avoids some rare compatibility problems with code
-generated by other compilers. It is not the default because it results
-in a performance loss, especially for floating-point code.
+The @option{-mno-compat-align-parm} option is the default.
+@end table
-@item -muser-mode
-@itemx -mno-user-mode
-@opindex muser-mode
-@opindex mno-user-mode
-Do not generate code that can only run in supervisor mode. This is relevant
-only for the @code{casa} instruction emitted for the LEON3 processor. This
-is the default.
+@node RX Options
+@subsection RX Options
+@cindex RX Options
-@item -mfaster-structs
-@itemx -mno-faster-structs
-@opindex mfaster-structs
-@opindex mno-faster-structs
-With @option{-mfaster-structs}, the compiler assumes that structures
-should have 8-byte alignment. This enables the use of pairs of
-@code{ldd} and @code{std} instructions for copies in structure
-assignment, in place of twice as many @code{ld} and @code{st} pairs.
-However, the use of this changed alignment directly violates the SPARC
-ABI@. Thus, it's intended only for use on targets where the developer
-acknowledges that their resulting code is not directly in line with
-the rules of the ABI@.
+These command-line options are defined for RX targets:
-@item -mstd-struct-return
-@itemx -mno-std-struct-return
-@opindex mstd-struct-return
-@opindex mno-std-struct-return
-With @option{-mstd-struct-return}, the compiler generates checking code
-in functions returning structures or unions to detect size mismatches
-between the two sides of function calls, as per the 32-bit ABI@.
+@table @gcctabopt
+@item -m64bit-doubles
+@itemx -m32bit-doubles
+@opindex m64bit-doubles
+@opindex m32bit-doubles
+Make the @code{double} data type be 64 bits (@option{-m64bit-doubles})
+or 32 bits (@option{-m32bit-doubles}) in size. The default is
+@option{-m32bit-doubles}. @emph{Note} RX floating-point hardware only
+works on 32-bit values, which is why the default is
+@option{-m32bit-doubles}.
-The default is @option{-mno-std-struct-return}. This option has no effect
-in 64-bit mode.
+@item -fpu
+@itemx -nofpu
+@opindex fpu
+@opindex nofpu
+Enables (@option{-fpu}) or disables (@option{-nofpu}) the use of RX
+floating-point hardware. The default is enabled for the RX600
+series and disabled for the RX200 series.
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set, register set, and instruction scheduling parameters
-for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
-@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
-@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930},
-@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
-@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
-@samp{niagara3} and @samp{niagara4}.
+Floating-point instructions are only generated for 32-bit floating-point
+values, however, so the FPU hardware is not used for doubles if the
+@option{-m64bit-doubles} option is used.
-Native Solaris and GNU/Linux toolchains also support the value @samp{native},
-which selects the best architecture option for the host processor.
-@option{-mcpu=native} has no effect if GCC does not recognize
-the processor.
+@emph{Note} If the @option{-fpu} option is enabled then
+@option{-funsafe-math-optimizations} is also enabled automatically.
+This is because the RX FPU instructions are themselves unsafe.
-Default instruction scheduling parameters are used for values that select
-an architecture and not an implementation. These are @samp{v7}, @samp{v8},
-@samp{sparclite}, @samp{sparclet}, @samp{v9}.
+@item -mcpu=@var{name}
+@opindex mcpu
+Selects the type of RX CPU to be targeted. Currently three types are
+supported, the generic @samp{RX600} and @samp{RX200} series hardware and
+the specific @samp{RX610} CPU. The default is @samp{RX600}.
-Here is a list of each supported architecture and their supported
-implementations.
+The only difference between @samp{RX600} and @samp{RX610} is that the
+@samp{RX610} does not support the @code{MVTIPL} instruction.
-@table @asis
-@item v7
-cypress, leon3v7
+The @samp{RX200} series does not have a hardware floating-point unit
+and so @option{-nofpu} is enabled by default when this type is
+selected.
-@item v8
-supersparc, hypersparc, leon, leon3
+@item -mbig-endian-data
+@itemx -mlittle-endian-data
+@opindex mbig-endian-data
+@opindex mlittle-endian-data
+Store data (but not code) in the big-endian format. The default is
+@option{-mlittle-endian-data}, i.e.@: to store data in the little-endian
+format.
-@item sparclite
-f930, f934, sparclite86x
+@item -msmall-data-limit=@var{N}
+@opindex msmall-data-limit
+Specifies the maximum size in bytes of global and static variables
+which can be placed into the small data area. Using the small data
+area can lead to smaller and faster code, but the size of area is
+limited and it is up to the programmer to ensure that the area does
+not overflow. Also when the small data area is used one of the RX's
+registers (usually @code{r13}) is reserved for use pointing to this
+area, so it is no longer available for use by the compiler. This
+could result in slower and/or larger code if variables are pushed onto
+the stack instead of being held in this register.
-@item sparclet
-tsc701
+Note, common variables (variables that have not been initialized) and
+constants are not placed into the small data area as they are assigned
+to other sections in the output executable.
-@item v9
-ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
-@end table
+The default value is zero, which disables this feature. Note, this
+feature is not enabled by default with higher optimization levels
+(@option{-O2} etc) because of the potentially detrimental effects of
+reserving a register. It is up to the programmer to experiment and
+discover whether this feature is of benefit to their program. See the
+description of the @option{-mpid} option for a description of how the
+actual register to hold the small data area pointer is chosen.
-By default (unless configured otherwise), GCC generates code for the V7
-variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
-additionally optimizes it for the Cypress CY7C602 chip, as used in the
-SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
-SPARCStation 1, 2, IPX etc.
+@item -msim
+@itemx -mno-sim
+@opindex msim
+@opindex mno-sim
+Use the simulator runtime. The default is to use the libgloss
+board-specific runtime.
-With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
-architecture. The only difference from V7 code is that the compiler emits
-the integer multiply and integer divide instructions which exist in SPARC-V8
-but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
-optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
-2000 series.
+@item -mas100-syntax
+@itemx -mno-as100-syntax
+@opindex mas100-syntax
+@opindex mno-as100-syntax
+When generating assembler output use a syntax that is compatible with
+Renesas's AS100 assembler. This syntax can also be handled by the GAS
+assembler, but it has some restrictions so it is not generated by default.
-With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
-the SPARC architecture. This adds the integer multiply, integer divide step
-and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
-With @option{-mcpu=f930}, the compiler additionally optimizes it for the
-Fujitsu MB86930 chip, which is the original SPARClite, with no FPU@. With
-@option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
-MB86934 chip, which is the more recent SPARClite with FPU@.
+@item -mmax-constant-size=@var{N}
+@opindex mmax-constant-size
+Specifies the maximum size, in bytes, of a constant that can be used as
+an operand in a RX instruction. Although the RX instruction set does
+allow constants of up to 4 bytes in length to be used in instructions,
+a longer value equates to a longer instruction. Thus in some
+circumstances it can be beneficial to restrict the size of constants
+that are used in instructions. Constants that are too big are instead
+placed into a constant pool and referenced via register indirection.
-With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
-the SPARC architecture. This adds the integer multiply, multiply/accumulate,
-integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
-but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
-optimizes it for the TEMIC SPARClet chip.
+The value @var{N} can be between 0 and 4. A value of 0 (the default)
+or 4 means that constants of any size are allowed.
-With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
-architecture. This adds 64-bit integer and floating-point move instructions,
-3 additional floating-point condition code registers and conditional move
-instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
-optimizes it for the Sun UltraSPARC I/II/IIi chips. With
-@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
-Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
-@option{-mcpu=niagara}, the compiler additionally optimizes it for
-Sun UltraSPARC T1 chips. With @option{-mcpu=niagara2}, the compiler
-additionally optimizes it for Sun UltraSPARC T2 chips. With
-@option{-mcpu=niagara3}, the compiler additionally optimizes it for Sun
-UltraSPARC T3 chips. With @option{-mcpu=niagara4}, the compiler
-additionally optimizes it for Sun UltraSPARC T4 chips.
+@item -mrelax
+@opindex mrelax
+Enable linker relaxation. Linker relaxation is a process whereby the
+linker attempts to reduce the size of a program by finding shorter
+versions of various instructions. Disabled by default.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set the instruction scheduling parameters for machine type
-@var{cpu_type}, but do not set the instruction set or register set that the
-option @option{-mcpu=@var{cpu_type}} does.
+@item -mint-register=@var{N}
+@opindex mint-register
+Specify the number of registers to reserve for fast interrupt handler
+functions. The value @var{N} can be between 0 and 4. A value of 1
+means that register @code{r13} is reserved for the exclusive use
+of fast interrupt handlers. A value of 2 reserves @code{r13} and
+@code{r12}. A value of 3 reserves @code{r13}, @code{r12} and
+@code{r11}, and a value of 4 reserves @code{r13} through @code{r10}.
+A value of 0, the default, does not reserve any registers.
-The same values for @option{-mcpu=@var{cpu_type}} can be used for
-@option{-mtune=@var{cpu_type}}, but the only useful values are those
-that select a particular CPU implementation. Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3},
-@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701},
-@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
-@samp{niagara3} and @samp{niagara4}. With native Solaris and GNU/Linux
-toolchains, @samp{native} can also be used.
+@item -msave-acc-in-interrupts
+@opindex msave-acc-in-interrupts
+Specifies that interrupt handler functions should preserve the
+accumulator register. This is only necessary if normal code might use
+the accumulator register, for example because it performs 64-bit
+multiplications. The default is to ignore the accumulator as this
+makes the interrupt handlers faster.
-@item -mv8plus
-@itemx -mno-v8plus
-@opindex mv8plus
-@opindex mno-v8plus
-With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI@. The
-difference from the V8 ABI is that the global and out registers are
-considered 64 bits wide. This is enabled by default on Solaris in 32-bit
-mode for all SPARC-V9 processors.
+@item -mpid
+@itemx -mno-pid
+@opindex mpid
+@opindex mno-pid
+Enables the generation of position independent data. When enabled any
+access to constant data is done via an offset from a base address
+held in a register. This allows the location of constant data to be
+determined at run time without requiring the executable to be
+relocated, which is a benefit to embedded applications with tight
+memory constraints. Data that can be modified is not affected by this
+option.
-@item -mvis
-@itemx -mno-vis
-@opindex mvis
-@opindex mno-vis
-With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
-Visual Instruction Set extensions. The default is @option{-mno-vis}.
+Note, using this feature reserves a register, usually @code{r13}, for
+the constant data base address. This can result in slower and/or
+larger code, especially in complicated functions.
-@item -mvis2
-@itemx -mno-vis2
-@opindex mvis2
-@opindex mno-vis2
-With @option{-mvis2}, GCC generates code that takes advantage of
-version 2.0 of the UltraSPARC Visual Instruction Set extensions. The
-default is @option{-mvis2} when targeting a cpu that supports such
-instructions, such as UltraSPARC-III and later. Setting @option{-mvis2}
-also sets @option{-mvis}.
+The actual register chosen to hold the constant data base address
+depends upon whether the @option{-msmall-data-limit} and/or the
+@option{-mint-register} command-line options are enabled. Starting
+with register @code{r13} and proceeding downwards, registers are
+allocated first to satisfy the requirements of @option{-mint-register},
+then @option{-mpid} and finally @option{-msmall-data-limit}. Thus it
+is possible for the small data area register to be @code{r8} if both
+@option{-mint-register=4} and @option{-mpid} are specified on the
+command line.
-@item -mvis3
-@itemx -mno-vis3
-@opindex mvis3
-@opindex mno-vis3
-With @option{-mvis3}, GCC generates code that takes advantage of
-version 3.0 of the UltraSPARC Visual Instruction Set extensions. The
-default is @option{-mvis3} when targeting a cpu that supports such
-instructions, such as niagara-3 and later. Setting @option{-mvis3}
-also sets @option{-mvis2} and @option{-mvis}.
+By default this feature is not enabled. The default can be restored
+via the @option{-mno-pid} command-line option.
-@item -mcbcond
-@itemx -mno-cbcond
-@opindex mcbcond
-@opindex mno-cbcond
-With @option{-mcbcond}, GCC generates code that takes advantage of
-compare-and-branch instructions, as defined in the Sparc Architecture 2011.
-The default is @option{-mcbcond} when targeting a cpu that supports such
-instructions, such as niagara-4 and later.
+@item -mno-warn-multiple-fast-interrupts
+@itemx -mwarn-multiple-fast-interrupts
+@opindex mno-warn-multiple-fast-interrupts
+@opindex mwarn-multiple-fast-interrupts
+Prevents GCC from issuing a warning message if it finds more than one
+fast interrupt handler when it is compiling a file. The default is to
+issue a warning for each extra fast interrupt handler found, as the RX
+only supports one such interrupt.
-@item -mpopc
-@itemx -mno-popc
-@opindex mpopc
-@opindex mno-popc
-With @option{-mpopc}, GCC generates code that takes advantage of the UltraSPARC
-population count instruction. The default is @option{-mpopc}
-when targeting a cpu that supports such instructions, such as Niagara-2 and
-later.
+@item -mallow-string-insns
+@itemx -mno-allow-string-insns
+@opindex mallow-string-insns
+@opindex mno-allow-string-insns
+Enables or disables the use of the string manipulation instructions
+@code{SMOVF}, @code{SCMPU}, @code{SMOVB}, @code{SMOVU}, @code{SUNTIL}
+@code{SWHILE} and also the @code{RMPA} instruction. These
+instructions may prefetch data, which is not safe to do if accessing
+an I/O register. (See section 12.2.7 of the RX62N Group User's Manual
+for more information).
-@item -mfmaf
-@itemx -mno-fmaf
-@opindex mfmaf
-@opindex mno-fmaf
-With @option{-mfmaf}, GCC generates code that takes advantage of the UltraSPARC
-Fused Multiply-Add Floating-point extensions. The default is @option{-mfmaf}
-when targeting a cpu that supports such instructions, such as Niagara-3 and
-later.
+The default is to allow these instructions, but it is not possible for
+GCC to reliably detect all circumstances where a string instruction
+might be used to access an I/O register, so their use cannot be
+disabled automatically. Instead it is reliant upon the programmer to
+use the @option{-mno-allow-string-insns} option if their program
+accesses I/O space.
-@item -mfix-at697f
-@opindex mfix-at697f
-Enable the documented workaround for the single erratum of the Atmel AT697F
-processor (which corresponds to erratum #13 of the AT697E processor).
+When the instructions are enabled GCC defines the C preprocessor
+symbol @code{__RX_ALLOW_STRING_INSNS__}, otherwise it defines the
+symbol @code{__RX_DISALLOW_STRING_INSNS__}.
-@item -mfix-ut699
-@opindex mfix-ut699
-Enable the documented workarounds for the floating-point errata and the data
-cache nullify errata of the UT699 processor.
+@item -mjsr
+@itemx -mno-jsr
+@opindex mjsr
+@opindex mno-jsr
+Use only (or not only) @code{JSR} instructions to access functions.
+This option can be used when code size exceeds the range of @code{BSR}
+instructions. Note that @option{-mno-jsr} does not mean to not use
+@code{JSR} but instead means that any type of branch may be used.
@end table
-These @samp{-m} options are supported in addition to the above
-on SPARC-V9 processors in 64-bit environments:
-
-@table @gcctabopt
-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for a 32-bit or 64-bit environment.
-The 32-bit environment sets int, long and pointer to 32 bits.
-The 64-bit environment sets int to 32 bits and long and pointer
-to 64 bits.
+@emph{Note:} The generic GCC command-line option @option{-ffixed-@var{reg}}
+has special significance to the RX port when used with the
+@code{interrupt} function attribute. This attribute indicates a
+function intended to process fast interrupts. GCC ensures
+that it only uses the registers @code{r10}, @code{r11}, @code{r12}
+and/or @code{r13} and only provided that the normal use of the
+corresponding registers have been restricted via the
+@option{-ffixed-@var{reg}} or @option{-mint-register} command-line
+options.
-@item -mcmodel=@var{which}
-@opindex mcmodel
-Set the code model to one of
+@node S/390 and zSeries Options
+@subsection S/390 and zSeries Options
+@cindex S/390 and zSeries Options
-@table @samp
-@item medlow
-The Medium/Low code model: 64-bit addresses, programs
-must be linked in the low 32 bits of memory. Programs can be statically
-or dynamically linked.
+These are the @samp{-m} options defined for the S/390 and zSeries architecture.
-@item medmid
-The Medium/Middle code model: 64-bit addresses, programs
-must be linked in the low 44 bits of memory, the text and data segments must
-be less than 2GB in size and the data segment must be located within 2GB of
-the text segment.
+@table @gcctabopt
+@item -mhard-float
+@itemx -msoft-float
+@opindex mhard-float
+@opindex msoft-float
+Use (do not use) the hardware floating-point instructions and registers
+for floating-point operations. When @option{-msoft-float} is specified,
+functions in @file{libgcc.a} are used to perform floating-point
+operations. When @option{-mhard-float} is specified, the compiler
+generates IEEE floating-point instructions. This is the default.
-@item medany
-The Medium/Anywhere code model: 64-bit addresses, programs
-may be linked anywhere in memory, the text and data segments must be less
-than 2GB in size and the data segment must be located within 2GB of the
-text segment.
-
-@item embmedany
-The Medium/Anywhere code model for embedded systems:
-64-bit addresses, the text and data segments must be less than 2GB in
-size, both starting anywhere in memory (determined at link time). The
-global register %g4 points to the base of the data segment. Programs
-are statically linked and PIC is not supported.
-@end table
+@item -mhard-dfp
+@itemx -mno-hard-dfp
+@opindex mhard-dfp
+@opindex mno-hard-dfp
+Use (do not use) the hardware decimal-floating-point instructions for
+decimal-floating-point operations. When @option{-mno-hard-dfp} is
+specified, functions in @file{libgcc.a} are used to perform
+decimal-floating-point operations. When @option{-mhard-dfp} is
+specified, the compiler generates decimal-floating-point hardware
+instructions. This is the default for @option{-march=z9-ec} or higher.
-@item -mmemory-model=@var{mem-model}
-@opindex mmemory-model
-Set the memory model in force on the processor to one of
+@item -mlong-double-64
+@itemx -mlong-double-128
+@opindex mlong-double-64
+@opindex mlong-double-128
+These switches control the size of @code{long double} type. A size
+of 64 bits makes the @code{long double} type equivalent to the @code{double}
+type. This is the default.
-@table @samp
-@item default
-The default memory model for the processor and operating system.
+@item -mbackchain
+@itemx -mno-backchain
+@opindex mbackchain
+@opindex mno-backchain
+Store (do not store) the address of the caller's frame as backchain pointer
+into the callee's stack frame.
+A backchain may be needed to allow debugging using tools that do not understand
+DWARF 2 call frame information.
+When @option{-mno-packed-stack} is in effect, the backchain pointer is stored
+at the bottom of the stack frame; when @option{-mpacked-stack} is in effect,
+the backchain is placed into the topmost word of the 96/160 byte register
+save area.
-@item rmo
-Relaxed Memory Order
+In general, code compiled with @option{-mbackchain} is call-compatible with
+code compiled with @option{-mmo-backchain}; however, use of the backchain
+for debugging purposes usually requires that the whole binary is built with
+@option{-mbackchain}. Note that the combination of @option{-mbackchain},
+@option{-mpacked-stack} and @option{-mhard-float} is not supported. In order
+to build a linux kernel use @option{-msoft-float}.
-@item pso
-Partial Store Order
+The default is to not maintain the backchain.
-@item tso
-Total Store Order
+@item -mpacked-stack
+@itemx -mno-packed-stack
+@opindex mpacked-stack
+@opindex mno-packed-stack
+Use (do not use) the packed stack layout. When @option{-mno-packed-stack} is
+specified, the compiler uses the all fields of the 96/160 byte register save
+area only for their default purpose; unused fields still take up stack space.
+When @option{-mpacked-stack} is specified, register save slots are densely
+packed at the top of the register save area; unused space is reused for other
+purposes, allowing for more efficient use of the available stack space.
+However, when @option{-mbackchain} is also in effect, the topmost word of
+the save area is always used to store the backchain, and the return address
+register is always saved two words below the backchain.
-@item sc
-Sequential Consistency
-@end table
+As long as the stack frame backchain is not used, code generated with
+@option{-mpacked-stack} is call-compatible with code generated with
+@option{-mno-packed-stack}. Note that some non-FSF releases of GCC 2.95 for
+S/390 or zSeries generated code that uses the stack frame backchain at run
+time, not just for debugging purposes. Such code is not call-compatible
+with code compiled with @option{-mpacked-stack}. Also, note that the
+combination of @option{-mbackchain},
+@option{-mpacked-stack} and @option{-mhard-float} is not supported. In order
+to build a linux kernel use @option{-msoft-float}.
-These memory models are formally defined in Appendix D of the Sparc V9
-architecture manual, as set in the processor's @code{PSTATE.MM} field.
+The default is to not use the packed stack layout.
-@item -mstack-bias
-@itemx -mno-stack-bias
-@opindex mstack-bias
-@opindex mno-stack-bias
-With @option{-mstack-bias}, GCC assumes that the stack pointer, and
-frame pointer if present, are offset by @minus{}2047 which must be added back
-when making stack frame references. This is the default in 64-bit mode.
-Otherwise, assume no such offset is present.
-@end table
+@item -msmall-exec
+@itemx -mno-small-exec
+@opindex msmall-exec
+@opindex mno-small-exec
+Generate (or do not generate) code using the @code{bras} instruction
+to do subroutine calls.
+This only works reliably if the total executable size does not
+exceed 64k. The default is to use the @code{basr} instruction instead,
+which does not have this limitation.
-@node SPU Options
-@subsection SPU Options
-@cindex SPU options
+@item -m64
+@itemx -m31
+@opindex m64
+@opindex m31
+When @option{-m31} is specified, generate code compliant to the
+GNU/Linux for S/390 ABI@. When @option{-m64} is specified, generate
+code compliant to the GNU/Linux for zSeries ABI@. This allows GCC in
+particular to generate 64-bit instructions. For the @samp{s390}
+targets, the default is @option{-m31}, while the @samp{s390x}
+targets default to @option{-m64}.
-These @samp{-m} options are supported on the SPU:
+@item -mzarch
+@itemx -mesa
+@opindex mzarch
+@opindex mesa
+When @option{-mzarch} is specified, generate code using the
+instructions available on z/Architecture.
+When @option{-mesa} is specified, generate code using the
+instructions available on ESA/390. Note that @option{-mesa} is
+not possible with @option{-m64}.
+When generating code compliant to the GNU/Linux for S/390 ABI,
+the default is @option{-mesa}. When generating code compliant
+to the GNU/Linux for zSeries ABI, the default is @option{-mzarch}.
-@table @gcctabopt
-@item -mwarn-reloc
-@itemx -merror-reloc
-@opindex mwarn-reloc
-@opindex merror-reloc
+@item -mhtm
+@itemx -mno-htm
+@opindex mhtm
+@opindex mno-htm
+The @option{-mhtm} option enables a set of builtins making use of
+instructions available with the transactional execution facility
+introduced with the IBM zEnterprise EC12 machine generation
+@ref{S/390 System z Built-in Functions}.
+@option{-mhtm} is enabled by default when using @option{-march=zEC12}.
-The loader for SPU does not handle dynamic relocations. By default, GCC
-gives an error when it generates code that requires a dynamic
-relocation. @option{-mno-error-reloc} disables the error,
-@option{-mwarn-reloc} generates a warning instead.
+@item -mvx
+@itemx -mno-vx
+@opindex mvx
+@opindex mno-vx
+When @option{-mvx} is specified, generate code using the instructions
+available with the vector extension facility introduced with the IBM
+z13 machine generation.
+This option changes the ABI for some vector type values with regard to
+alignment and calling conventions. In case vector type values are
+being used in an ABI-relevant context a GAS @samp{.gnu_attribute}
+command will be added to mark the resulting binary with the ABI used.
+@option{-mvx} is enabled by default when using @option{-march=z13}.
-@item -msafe-dma
-@itemx -munsafe-dma
-@opindex msafe-dma
-@opindex munsafe-dma
+@item -mzvector
+@itemx -mno-zvector
+@opindex mzvector
+@opindex mno-zvector
+The @option{-mzvector} option enables vector language extensions and
+builtins using instructions available with the vector extension
+facility introduced with the IBM z13 machine generation.
+This option adds support for @samp{vector} to be used as a keyword to
+define vector type variables and arguments. @samp{vector} is only
+available when GNU extensions are enabled. It will not be expanded
+when requesting strict standard compliance e.g. with @option{-std=c99}.
+In addition to the GCC low-level builtins @option{-mzvector} enables
+a set of builtins added for compatibility with Altivec-style
+implementations like Power and Cell. In order to make use of these
+builtins the header file @file{vecintrin.h} needs to be included.
+@option{-mzvector} is disabled by default.
-Instructions that initiate or test completion of DMA must not be
-reordered with respect to loads and stores of the memory that is being
-accessed.
-With @option{-munsafe-dma} you must use the @code{volatile} keyword to protect
-memory accesses, but that can lead to inefficient code in places where the
-memory is known to not change. Rather than mark the memory as volatile,
-you can use @option{-msafe-dma} to tell the compiler to treat
-the DMA instructions as potentially affecting all memory.
+@item -mmvcle
+@itemx -mno-mvcle
+@opindex mmvcle
+@opindex mno-mvcle
+Generate (or do not generate) code using the @code{mvcle} instruction
+to perform block moves. When @option{-mno-mvcle} is specified,
+use a @code{mvc} loop instead. This is the default unless optimizing for
+size.
-@item -mbranch-hints
-@opindex mbranch-hints
+@item -mdebug
+@itemx -mno-debug
+@opindex mdebug
+@opindex mno-debug
+Print (or do not print) additional debug information when compiling.
+The default is to not print debug information.
-By default, GCC generates a branch hint instruction to avoid
-pipeline stalls for always-taken or probably-taken branches. A hint
-is not generated closer than 8 instructions away from its branch.
-There is little reason to disable them, except for debugging purposes,
-or to make an object a little bit smaller.
+@item -march=@var{cpu-type}
+@opindex march
+Generate code that runs on @var{cpu-type}, which is the name of a
+system representing a certain processor type. Possible values for
+@var{cpu-type} are @samp{z900}, @samp{z990}, @samp{z9-109},
+@samp{z9-ec}, @samp{z10}, @samp{z196}, @samp{zEC12}, and @samp{z13}.
+The default is @option{-march=z900}. @samp{g5} and @samp{g6} are
+deprecated and will be removed with future releases.
-@item -msmall-mem
-@itemx -mlarge-mem
-@opindex msmall-mem
-@opindex mlarge-mem
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune to @var{cpu-type} everything applicable about the generated code,
+except for the ABI and the set of available instructions.
+The list of @var{cpu-type} values is the same as for @option{-march}.
+The default is the value used for @option{-march}.
-By default, GCC generates code assuming that addresses are never larger
-than 18 bits. With @option{-mlarge-mem} code is generated that assumes
-a full 32-bit address.
+@item -mtpf-trace
+@itemx -mno-tpf-trace
+@opindex mtpf-trace
+@opindex mno-tpf-trace
+Generate code that adds (does not add) in TPF OS specific branches to trace
+routines in the operating system. This option is off by default, even
+when compiling for the TPF OS@.
-@item -mstdmain
-@opindex mstdmain
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating-point multiply and
+accumulate instructions. These instructions are generated by default if
+hardware floating point is used.
-By default, GCC links against startup code that assumes the SPU-style
-main function interface (which has an unconventional parameter list).
-With @option{-mstdmain}, GCC links your program against startup
-code that assumes a C99-style interface to @code{main}, including a
-local copy of @code{argv} strings.
+@item -mwarn-framesize=@var{framesize}
+@opindex mwarn-framesize
+Emit a warning if the current function exceeds the given frame size. Because
+this is a compile-time check it doesn't need to be a real problem when the program
+runs. It is intended to identify functions that most probably cause
+a stack overflow. It is useful to be used in an environment with limited stack
+size e.g.@: the linux kernel.
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator cannot use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
-
-@item -mea32
-@itemx -mea64
-@opindex mea32
-@opindex mea64
-Compile code assuming that pointers to the PPU address space accessed
-via the @code{__ea} named address space qualifier are either 32 or 64
-bits wide. The default is 32 bits. As this is an ABI-changing option,
-all object code in an executable must be compiled with the same setting.
+@item -mwarn-dynamicstack
+@opindex mwarn-dynamicstack
+Emit a warning if the function calls @code{alloca} or uses dynamically-sized
+arrays. This is generally a bad idea with a limited stack size.
-@item -maddress-space-conversion
-@itemx -mno-address-space-conversion
-@opindex maddress-space-conversion
-@opindex mno-address-space-conversion
-Allow/disallow treating the @code{__ea} address space as superset
-of the generic address space. This enables explicit type casts
-between @code{__ea} and generic pointer as well as implicit
-conversions of generic pointers to @code{__ea} pointers. The
-default is to allow address space pointer conversions.
+@item -mstack-guard=@var{stack-guard}
+@itemx -mstack-size=@var{stack-size}
+@opindex mstack-guard
+@opindex mstack-size
+If these options are provided the S/390 back end emits additional instructions in
+the function prologue that trigger a trap if the stack size is @var{stack-guard}
+bytes above the @var{stack-size} (remember that the stack on S/390 grows downward).
+If the @var{stack-guard} option is omitted the smallest power of 2 larger than
+the frame size of the compiled function is chosen.
+These options are intended to be used to help debugging stack overflow problems.
+The additionally emitted code causes only little overhead and hence can also be
+used in production-like systems without greater performance degradation. The given
+values have to be exact powers of 2 and @var{stack-size} has to be greater than
+@var{stack-guard} without exceeding 64k.
+In order to be efficient the extra code makes the assumption that the stack starts
+at an address aligned to the value given by @var{stack-size}.
+The @var{stack-guard} option can only be used in conjunction with @var{stack-size}.
-@item -mcache-size=@var{cache-size}
-@opindex mcache-size
-This option controls the version of libgcc that the compiler links to an
-executable and selects a software-managed cache for accessing variables
-in the @code{__ea} address space with a particular cache size. Possible
-options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
-and @samp{128}. The default cache size is 64KB.
+@item -mhotpatch=@var{pre-halfwords},@var{post-halfwords}
+@opindex mhotpatch
+If the hotpatch option is enabled, a ``hot-patching'' function
+prologue is generated for all functions in the compilation unit.
+The funtion label is prepended with the given number of two-byte
+NOP instructions (@var{pre-halfwords}, maximum 1000000). After
+the label, 2 * @var{post-halfwords} bytes are appended, using the
+largest NOP like instructions the architecture allows (maximum
+1000000).
-@item -matomic-updates
-@itemx -mno-atomic-updates
-@opindex matomic-updates
-@opindex mno-atomic-updates
-This option controls the version of libgcc that the compiler links to an
-executable and selects whether atomic updates to the software-managed
-cache of PPU-side variables are used. If you use atomic updates, changes
-to a PPU variable from SPU code using the @code{__ea} named address space
-qualifier do not interfere with changes to other PPU variables residing
-in the same cache line from PPU code. If you do not use atomic updates,
-such interference may occur; however, writing back cache lines is
-more efficient. The default behavior is to use atomic updates.
+If both arguments are zero, hotpatching is disabled.
-@item -mdual-nops
-@itemx -mdual-nops=@var{n}
-@opindex mdual-nops
-By default, GCC inserts nops to increase dual issue when it expects
-it to increase performance. @var{n} can be a value from 0 to 10. A
-smaller @var{n} inserts fewer nops. 10 is the default, 0 is the
-same as @option{-mno-dual-nops}. Disabled with @option{-Os}.
+This option can be overridden for individual functions with the
+@code{hotpatch} attribute.
+@end table
-@item -mhint-max-nops=@var{n}
-@opindex mhint-max-nops
-Maximum number of nops to insert for a branch hint. A branch hint must
-be at least 8 instructions away from the branch it is affecting. GCC
-inserts up to @var{n} nops to enforce this, otherwise it does not
-generate the branch hint.
+@node Score Options
+@subsection Score Options
+@cindex Score Options
-@item -mhint-max-distance=@var{n}
-@opindex mhint-max-distance
-The encoding of the branch hint instruction limits the hint to be within
-256 instructions of the branch it is affecting. By default, GCC makes
-sure it is within 125.
+These options are defined for Score implementations:
-@item -msafe-hints
-@opindex msafe-hints
-Work around a hardware bug that causes the SPU to stall indefinitely.
-By default, GCC inserts the @code{hbrp} instruction to make sure
-this stall won't happen.
+@table @gcctabopt
+@item -meb
+@opindex meb
+Compile code for big-endian mode. This is the default.
-@end table
+@item -mel
+@opindex mel
+Compile code for little-endian mode.
-@node System V Options
-@subsection Options for System V
+@item -mnhwloop
+@opindex mnhwloop
+Disable generation of @code{bcnz} instructions.
-These additional options are available on System V Release 4 for
-compatibility with other compilers on those systems:
+@item -muls
+@opindex muls
+Enable generation of unaligned load and store instructions.
-@table @gcctabopt
-@item -G
-@opindex G
-Create a shared object.
-It is recommended that @option{-symbolic} or @option{-shared} be used instead.
+@item -mmac
+@opindex mmac
+Enable the use of multiply-accumulate instructions. Disabled by default.
-@item -Qy
-@opindex Qy
-Identify the versions of each tool used by the compiler, in a
-@code{.ident} assembler directive in the output.
+@item -mscore5
+@opindex mscore5
+Specify the SCORE5 as the target architecture.
-@item -Qn
-@opindex Qn
-Refrain from adding @code{.ident} directives to the output file (this is
-the default).
+@item -mscore5u
+@opindex mscore5u
+Specify the SCORE5U of the target architecture.
-@item -YP,@var{dirs}
-@opindex YP
-Search the directories @var{dirs}, and no others, for libraries
-specified with @option{-l}.
+@item -mscore7
+@opindex mscore7
+Specify the SCORE7 as the target architecture. This is the default.
-@item -Ym,@var{dir}
-@opindex Ym
-Look in the directory @var{dir} to find the M4 preprocessor.
-The assembler uses this option.
-@c This is supposed to go with a -Yd for predefined M4 macro files, but
-@c the generic assembler that comes with Solaris takes just -Ym.
+@item -mscore7d
+@opindex mscore7d
+Specify the SCORE7D as the target architecture.
@end table
-@node TILE-Gx Options
-@subsection TILE-Gx Options
-@cindex TILE-Gx options
+@node SH Options
+@subsection SH Options
-These @samp{-m} options are supported on the TILE-Gx:
+These @samp{-m} options are defined for the SH implementations:
@table @gcctabopt
-@item -mcmodel=small
-@opindex mcmodel=small
-Generate code for the small model. The distance for direct calls is
-limited to 500M in either direction. PC-relative addresses are 32
-bits. Absolute addresses support the full address range.
+@item -m1
+@opindex m1
+Generate code for the SH1.
-@item -mcmodel=large
-@opindex mcmodel=large
-Generate code for the large model. There is no limitation on call
-distance, pc-relative addresses, or absolute addresses.
+@item -m2
+@opindex m2
+Generate code for the SH2.
-@item -mcpu=@var{name}
-@opindex mcpu
-Selects the type of CPU to be targeted. Currently the only supported
-type is @samp{tilegx}.
+@item -m2e
+Generate code for the SH2e.
-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for a 32-bit or 64-bit environment. The 32-bit
-environment sets int, long, and pointer to 32 bits. The 64-bit
-environment sets int to 32 bits and long and pointer to 64 bits.
+@item -m2a-nofpu
+@opindex m2a-nofpu
+Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way
+that the floating-point unit is not used.
-@item -mbig-endian
-@itemx -mlittle-endian
-@opindex mbig-endian
-@opindex mlittle-endian
-Generate code in big/little endian mode, respectively.
-@end table
+@item -m2a-single-only
+@opindex m2a-single-only
+Generate code for the SH2a-FPU, in such a way that no double-precision
+floating-point operations are used.
-@node TILEPro Options
-@subsection TILEPro Options
-@cindex TILEPro options
+@item -m2a-single
+@opindex m2a-single
+Generate code for the SH2a-FPU assuming the floating-point unit is in
+single-precision mode by default.
-These @samp{-m} options are supported on the TILEPro:
+@item -m2a
+@opindex m2a
+Generate code for the SH2a-FPU assuming the floating-point unit is in
+double-precision mode by default.
-@table @gcctabopt
-@item -mcpu=@var{name}
-@opindex mcpu
-Selects the type of CPU to be targeted. Currently the only supported
-type is @samp{tilepro}.
+@item -m3
+@opindex m3
+Generate code for the SH3.
-@item -m32
-@opindex m32
-Generate code for a 32-bit environment, which sets int, long, and
-pointer to 32 bits. This is the only supported behavior so the flag
-is essentially ignored.
-@end table
+@item -m3e
+@opindex m3e
+Generate code for the SH3e.
-@node V850 Options
-@subsection V850 Options
-@cindex V850 Options
+@item -m4-nofpu
+@opindex m4-nofpu
+Generate code for the SH4 without a floating-point unit.
-These @samp{-m} options are defined for V850 implementations:
+@item -m4-single-only
+@opindex m4-single-only
+Generate code for the SH4 with a floating-point unit that only
+supports single-precision arithmetic.
-@table @gcctabopt
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Treat all calls as being far away (near). If calls are assumed to be
-far away, the compiler always loads the function's address into a
-register, and calls indirect through the pointer.
-
-@item -mno-ep
-@itemx -mep
-@opindex mno-ep
-@opindex mep
-Do not optimize (do optimize) basic blocks that use the same index
-pointer 4 or more times to copy pointer into the @code{ep} register, and
-use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
-option is on by default if you optimize.
+@item -m4-single
+@opindex m4-single
+Generate code for the SH4 assuming the floating-point unit is in
+single-precision mode by default.
-@item -mno-prolog-function
-@itemx -mprolog-function
-@opindex mno-prolog-function
-@opindex mprolog-function
-Do not use (do use) external functions to save and restore registers
-at the prologue and epilogue of a function. The external functions
-are slower, but use less code space if more than one function saves
-the same number of registers. The @option{-mprolog-function} option
-is on by default if you optimize.
+@item -m4
+@opindex m4
+Generate code for the SH4.
-@item -mspace
-@opindex mspace
-Try to make the code as small as possible. At present, this just turns
-on the @option{-mep} and @option{-mprolog-function} options.
+@item -m4-100
+@opindex m4-100
+Generate code for SH4-100.
-@item -mtda=@var{n}
-@opindex mtda
-Put static or global variables whose size is @var{n} bytes or less into
-the tiny data area that register @code{ep} points to. The tiny data
-area can hold up to 256 bytes in total (128 bytes for byte references).
+@item -m4-100-nofpu
+@opindex m4-100-nofpu
+Generate code for SH4-100 in such a way that the
+floating-point unit is not used.
-@item -msda=@var{n}
-@opindex msda
-Put static or global variables whose size is @var{n} bytes or less into
-the small data area that register @code{gp} points to. The small data
-area can hold up to 64 kilobytes.
+@item -m4-100-single
+@opindex m4-100-single
+Generate code for SH4-100 assuming the floating-point unit is in
+single-precision mode by default.
-@item -mzda=@var{n}
-@opindex mzda
-Put static or global variables whose size is @var{n} bytes or less into
-the first 32 kilobytes of memory.
+@item -m4-100-single-only
+@opindex m4-100-single-only
+Generate code for SH4-100 in such a way that no double-precision
+floating-point operations are used.
-@item -mv850
-@opindex mv850
-Specify that the target processor is the V850.
+@item -m4-200
+@opindex m4-200
+Generate code for SH4-200.
-@item -mv850e3v5
-@opindex mv850e3v5
-Specify that the target processor is the V850E3V5. The preprocessor
-constant @code{__v850e3v5__} is defined if this option is used.
+@item -m4-200-nofpu
+@opindex m4-200-nofpu
+Generate code for SH4-200 without in such a way that the
+floating-point unit is not used.
-@item -mv850e2v4
-@opindex mv850e2v4
-Specify that the target processor is the V850E3V5. This is an alias for
-the @option{-mv850e3v5} option.
+@item -m4-200-single
+@opindex m4-200-single
+Generate code for SH4-200 assuming the floating-point unit is in
+single-precision mode by default.
-@item -mv850e2v3
-@opindex mv850e2v3
-Specify that the target processor is the V850E2V3. The preprocessor
-constant @code{__v850e2v3__} is defined if this option is used.
+@item -m4-200-single-only
+@opindex m4-200-single-only
+Generate code for SH4-200 in such a way that no double-precision
+floating-point operations are used.
-@item -mv850e2
-@opindex mv850e2
-Specify that the target processor is the V850E2. The preprocessor
-constant @code{__v850e2__} is defined if this option is used.
+@item -m4-300
+@opindex m4-300
+Generate code for SH4-300.
-@item -mv850e1
-@opindex mv850e1
-Specify that the target processor is the V850E1. The preprocessor
-constants @code{__v850e1__} and @code{__v850e__} are defined if
-this option is used.
+@item -m4-300-nofpu
+@opindex m4-300-nofpu
+Generate code for SH4-300 without in such a way that the
+floating-point unit is not used.
-@item -mv850es
-@opindex mv850es
-Specify that the target processor is the V850ES. This is an alias for
-the @option{-mv850e1} option.
+@item -m4-300-single
+@opindex m4-300-single
+Generate code for SH4-300 in such a way that no double-precision
+floating-point operations are used.
-@item -mv850e
-@opindex mv850e
-Specify that the target processor is the V850E@. The preprocessor
-constant @code{__v850e__} is defined if this option is used.
+@item -m4-300-single-only
+@opindex m4-300-single-only
+Generate code for SH4-300 in such a way that no double-precision
+floating-point operations are used.
-If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
-nor @option{-mv850e2} nor @option{-mv850e2v3} nor @option{-mv850e3v5}
-are defined then a default target processor is chosen and the
-relevant @samp{__v850*__} preprocessor constant is defined.
+@item -m4-340
+@opindex m4-340
+Generate code for SH4-340 (no MMU, no FPU).
-The preprocessor constants @code{__v850} and @code{__v851__} are always
-defined, regardless of which processor variant is the target.
+@item -m4-500
+@opindex m4-500
+Generate code for SH4-500 (no FPU). Passes @option{-isa=sh4-nofpu} to the
+assembler.
-@item -mdisable-callt
-@itemx -mno-disable-callt
-@opindex mdisable-callt
-@opindex mno-disable-callt
-This option suppresses generation of the @code{CALLT} instruction for the
-v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850
-architecture.
+@item -m4a-nofpu
+@opindex m4a-nofpu
+Generate code for the SH4al-dsp, or for a SH4a in such a way that the
+floating-point unit is not used.
-This option is enabled by default when the RH850 ABI is
-in use (see @option{-mrh850-abi}), and disabled by default when the
-GCC ABI is in use. If @code{CALLT} instructions are being generated
-then the C preprocessor symbol @code{__V850_CALLT__} is defined.
+@item -m4a-single-only
+@opindex m4a-single-only
+Generate code for the SH4a, in such a way that no double-precision
+floating-point operations are used.
-@item -mrelax
-@itemx -mno-relax
-@opindex mrelax
-@opindex mno-relax
-Pass on (or do not pass on) the @option{-mrelax} command-line option
-to the assembler.
+@item -m4a-single
+@opindex m4a-single
+Generate code for the SH4a assuming the floating-point unit is in
+single-precision mode by default.
-@item -mlong-jumps
-@itemx -mno-long-jumps
-@opindex mlong-jumps
-@opindex mno-long-jumps
-Disable (or re-enable) the generation of PC-relative jump instructions.
+@item -m4a
+@opindex m4a
+Generate code for the SH4a.
-@item -msoft-float
-@itemx -mhard-float
-@opindex msoft-float
-@opindex mhard-float
-Disable (or re-enable) the generation of hardware floating point
-instructions. This option is only significant when the target
-architecture is @samp{V850E2V3} or higher. If hardware floating point
-instructions are being generated then the C preprocessor symbol
-@code{__FPU_OK__} is defined, otherwise the symbol
-@code{__NO_FPU__} is defined.
+@item -m4al
+@opindex m4al
+Same as @option{-m4a-nofpu}, except that it implicitly passes
+@option{-dsp} to the assembler. GCC doesn't generate any DSP
+instructions at the moment.
-@item -mloop
-@opindex mloop
-Enables the use of the e3v5 LOOP instruction. The use of this
-instruction is not enabled by default when the e3v5 architecture is
-selected because its use is still experimental.
+@item -mb
+@opindex mb
+Compile code for the processor in big-endian mode.
-@item -mrh850-abi
-@itemx -mghs
-@opindex mrh850-abi
-@opindex mghs
-Enables support for the RH850 version of the V850 ABI. This is the
-default. With this version of the ABI the following rules apply:
+@item -ml
+@opindex ml
+Compile code for the processor in little-endian mode.
-@itemize
-@item
-Integer sized structures and unions are returned via a memory pointer
-rather than a register.
+@item -mdalign
+@opindex mdalign
+Align doubles at 64-bit boundaries. Note that this changes the calling
+conventions, and thus some functions from the standard C library do
+not work unless you recompile it first with @option{-mdalign}.
-@item
-Large structures and unions (more than 8 bytes in size) are passed by
-value.
+@item -mrelax
+@opindex mrelax
+Shorten some address references at link time, when possible; uses the
+linker option @option{-relax}.
-@item
-Functions are aligned to 16-bit boundaries.
+@item -mbigtable
+@opindex mbigtable
+Use 32-bit offsets in @code{switch} tables. The default is to use
+16-bit offsets.
-@item
-The @option{-m8byte-align} command-line option is supported.
+@item -mbitops
+@opindex mbitops
+Enable the use of bit manipulation instructions on SH2A.
-@item
-The @option{-mdisable-callt} command-line option is enabled by
-default. The @option{-mno-disable-callt} command-line option is not
-supported.
-@end itemize
+@item -mfmovd
+@opindex mfmovd
+Enable the use of the instruction @code{fmovd}. Check @option{-mdalign} for
+alignment constraints.
-When this version of the ABI is enabled the C preprocessor symbol
-@code{__V850_RH850_ABI__} is defined.
+@item -mrenesas
+@opindex mrenesas
+Comply with the calling conventions defined by Renesas.
-@item -mgcc-abi
-@opindex mgcc-abi
-Enables support for the old GCC version of the V850 ABI. With this
-version of the ABI the following rules apply:
+@item -mno-renesas
+@opindex mno-renesas
+Comply with the calling conventions defined for GCC before the Renesas
+conventions were available. This option is the default for all
+targets of the SH toolchain.
-@itemize
-@item
-Integer sized structures and unions are returned in register @code{r10}.
-
-@item
-Large structures and unions (more than 8 bytes in size) are passed by
-reference.
+@item -mnomacsave
+@opindex mnomacsave
+Mark the @code{MAC} register as call-clobbered, even if
+@option{-mrenesas} is given.
-@item
-Functions are aligned to 32-bit boundaries, unless optimizing for
-size.
+@item -mieee
+@itemx -mno-ieee
+@opindex mieee
+@opindex mno-ieee
+Control the IEEE compliance of floating-point comparisons, which affects the
+handling of cases where the result of a comparison is unordered. By default
+@option{-mieee} is implicitly enabled. If @option{-ffinite-math-only} is
+enabled @option{-mno-ieee} is implicitly set, which results in faster
+floating-point greater-equal and less-equal comparisons. The implcit settings
+can be overridden by specifying either @option{-mieee} or @option{-mno-ieee}.
-@item
-The @option{-m8byte-align} command-line option is not supported.
+@item -minline-ic_invalidate
+@opindex minline-ic_invalidate
+Inline code to invalidate instruction cache entries after setting up
+nested function trampolines.
+This option has no effect if @option{-musermode} is in effect and the selected
+code generation option (e.g. @option{-m4}) does not allow the use of the @code{icbi}
+instruction.
+If the selected code generation option does not allow the use of the @code{icbi}
+instruction, and @option{-musermode} is not in effect, the inlined code
+manipulates the instruction cache address array directly with an associative
+write. This not only requires privileged mode at run time, but it also
+fails if the cache line had been mapped via the TLB and has become unmapped.
-@item
-The @option{-mdisable-callt} command-line option is supported but not
-enabled by default.
-@end itemize
+@item -misize
+@opindex misize
+Dump instruction size and location in the assembly code.
-When this version of the ABI is enabled the C preprocessor symbol
-@code{__V850_GCC_ABI__} is defined.
+@item -mpadstruct
+@opindex mpadstruct
+This option is deprecated. It pads structures to multiple of 4 bytes,
+which is incompatible with the SH ABI@.
-@item -m8byte-align
-@itemx -mno-8byte-align
-@opindex m8byte-align
-@opindex mno-8byte-align
-Enables support for @code{double} and @code{long long} types to be
-aligned on 8-byte boundaries. The default is to restrict the
-alignment of all objects to at most 4-bytes. When
-@option{-m8byte-align} is in effect the C preprocessor symbol
-@code{__V850_8BYTE_ALIGN__} is defined.
+@item -matomic-model=@var{model}
+@opindex matomic-model=@var{model}
+Sets the model of atomic operations and additional parameters as a comma
+separated list. For details on the atomic built-in functions see
+@ref{__atomic Builtins}. The following models and parameters are supported:
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
+@table @samp
-@item -mapp-regs
-@opindex mapp-regs
-This option causes r2 and r5 to be used in the code generated by
-the compiler. This setting is the default.
+@item none
+Disable compiler generated atomic sequences and emit library calls for atomic
+operations. This is the default if the target is not @code{sh*-*-linux*}.
-@item -mno-app-regs
-@opindex mno-app-regs
-This option causes r2 and r5 to be treated as fixed registers.
+@item soft-gusa
+Generate GNU/Linux compatible gUSA software atomic sequences for the atomic
+built-in functions. The generated atomic sequences require additional support
+from the interrupt/exception handling code of the system and are only suitable
+for SH3* and SH4* single-core systems. This option is enabled by default when
+the target is @code{sh*-*-linux*} and SH3* or SH4*. When the target is SH4A,
+this option also partially utilizes the hardware atomic instructions
+@code{movli.l} and @code{movco.l} to create more efficient code, unless
+@samp{strict} is specified.
-@end table
+@item soft-tcb
+Generate software atomic sequences that use a variable in the thread control
+block. This is a variation of the gUSA sequences which can also be used on
+SH1* and SH2* targets. The generated atomic sequences require additional
+support from the interrupt/exception handling code of the system and are only
+suitable for single-core systems. When using this model, the @samp{gbr-offset=}
+parameter has to be specified as well.
-@node VAX Options
-@subsection VAX Options
-@cindex VAX options
+@item soft-imask
+Generate software atomic sequences that temporarily disable interrupts by
+setting @code{SR.IMASK = 1111}. This model works only when the program runs
+in privileged mode and is only suitable for single-core systems. Additional
+support from the interrupt/exception handling code of the system is not
+required. This model is enabled by default when the target is
+@code{sh*-*-linux*} and SH1* or SH2*.
-These @samp{-m} options are defined for the VAX:
+@item hard-llcs
+Generate hardware atomic sequences using the @code{movli.l} and @code{movco.l}
+instructions only. This is only available on SH4A and is suitable for
+multi-core systems. Since the hardware instructions support only 32 bit atomic
+variables access to 8 or 16 bit variables is emulated with 32 bit accesses.
+Code compiled with this option is also compatible with other software
+atomic model interrupt/exception handling systems if executed on an SH4A
+system. Additional support from the interrupt/exception handling code of the
+system is not required for this model.
-@table @gcctabopt
-@item -munix
-@opindex munix
-Do not output certain jump instructions (@code{aobleq} and so on)
-that the Unix assembler for the VAX cannot handle across long
-ranges.
+@item gbr-offset=
+This parameter specifies the offset in bytes of the variable in the thread
+control block structure that should be used by the generated atomic sequences
+when the @samp{soft-tcb} model has been selected. For other models this
+parameter is ignored. The specified value must be an integer multiple of four
+and in the range 0-1020.
-@item -mgnu
-@opindex mgnu
-Do output those jump instructions, on the assumption that the
-GNU assembler is being used.
+@item strict
+This parameter prevents mixed usage of multiple atomic models, even if they
+are compatible, and makes the compiler generate atomic sequences of the
+specified model only.
-@item -mg
-@opindex mg
-Output code for G-format floating-point numbers instead of D-format.
@end table
-@node Visium Options
-@subsection Visium Options
-@cindex Visium options
-
-@table @gcctabopt
-
-@item -mdebug
-@opindex mdebug
-A program which performs file I/O and is destined to run on an MCM target
-should be linked with this option. It causes the libraries libc.a and
-libdebug.a to be linked. The program should be run on the target under
-the control of the GDB remote debugging stub.
-
-@item -msim
-@opindex msim
-A program which performs file I/O and is destined to run on the simulator
-should be linked with option. This causes libraries libc.a and libsim.a to
-be linked.
-
-@item -mfpu
-@itemx -mhard-float
-@opindex mfpu
-@opindex mhard-float
-Generate code containing floating-point instructions. This is the
-default.
+@item -mtas
+@opindex mtas
+Generate the @code{tas.b} opcode for @code{__atomic_test_and_set}.
+Notice that depending on the particular hardware and software configuration
+this can degrade overall performance due to the operand cache line flushes
+that are implied by the @code{tas.b} instruction. On multi-core SH4A
+processors the @code{tas.b} instruction must be used with caution since it
+can result in data corruption for certain cache configurations.
-@item -mno-fpu
-@itemx -msoft-float
-@opindex mno-fpu
-@opindex msoft-float
-Generate code containing library calls for floating-point.
+@item -mprefergot
+@opindex mprefergot
+When generating position-independent code, emit function calls using
+the Global Offset Table instead of the Procedure Linkage Table.
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
+@item -musermode
+@itemx -mno-usermode
+@opindex musermode
+@opindex mno-usermode
+Don't allow (allow) the compiler generating privileged mode code. Specifying
+@option{-musermode} also implies @option{-mno-inline-ic_invalidate} if the
+inlined code would not work in user mode. @option{-musermode} is the default
+when the target is @code{sh*-*-linux*}. If the target is SH1* or SH2*
+@option{-musermode} has no effect, since there is no user mode.
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set, register set, and instruction scheduling parameters
-for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
-@samp{mcm}, @samp{gr5} and @samp{gr6}.
+@item -multcost=@var{number}
+@opindex multcost=@var{number}
+Set the cost to assume for a multiply insn.
-@samp{mcm} is a synonym of @samp{gr5} present for backward compatibility.
+@item -mdiv=@var{strategy}
+@opindex mdiv=@var{strategy}
+Set the division strategy to be used for integer division operations.
+@var{strategy} can be one of:
-By default (unless configured otherwise), GCC generates code for the GR5
-variant of the Visium architecture.
+@table @samp
-With @option{-mcpu=gr6}, GCC generates code for the GR6 variant of the Visium
-architecture. The only difference from GR5 code is that the compiler will
-generate block move instructions.
+@item call-div1
+Calls a library function that uses the single-step division instruction
+@code{div1} to perform the operation. Division by zero calculates an
+unspecified result and does not trap. This is the default except for SH4,
+SH2A and SHcompact.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set the instruction scheduling parameters for machine type @var{cpu_type},
-but do not set the instruction set or register set that the option
-@option{-mcpu=@var{cpu_type}} would.
+@item call-fp
+Calls a library function that performs the operation in double precision
+floating point. Division by zero causes a floating-point exception. This is
+the default for SHcompact with FPU. Specifying this for targets that do not
+have a double precision FPU defaults to @code{call-div1}.
-@item -msv-mode
-@opindex msv-mode
-Generate code for the supervisor mode, where there are no restrictions on
-the access to general registers. This is the default.
+@item call-table
+Calls a library function that uses a lookup table for small divisors and
+the @code{div1} instruction with case distinction for larger divisors. Division
+by zero calculates an unspecified result and does not trap. This is the default
+for SH4. Specifying this for targets that do not have dynamic shift
+instructions defaults to @code{call-div1}.
-@item -muser-mode
-@opindex muser-mode
-Generate code for the user mode, where the access to some general registers
-is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
-mode; on the GR6, only registers r29 to r31 are affected.
@end table
-@node VMS Options
-@subsection VMS Options
+When a division strategy has not been specified the default strategy is
+selected based on the current target. For SH2A the default strategy is to
+use the @code{divs} and @code{divu} instructions instead of library function
+calls.
-These @samp{-m} options are defined for the VMS implementations:
+@item -maccumulate-outgoing-args
+@opindex maccumulate-outgoing-args
+Reserve space once for outgoing arguments in the function prologue rather
+than around each call. Generally beneficial for performance and size. Also
+needed for unwinding to avoid changing the stack frame around conditional code.
-@table @gcctabopt
-@item -mvms-return-codes
-@opindex mvms-return-codes
-Return VMS condition codes from @code{main}. The default is to return POSIX-style
-condition (e.g.@ error) codes.
+@item -mdivsi3_libfunc=@var{name}
+@opindex mdivsi3_libfunc=@var{name}
+Set the name of the library function used for 32-bit signed division to
+@var{name}.
+This only affects the name used in the @samp{call} division strategies, and
+the compiler still expects the same sets of input/output/clobbered registers as
+if this option were not present.
-@item -mdebug-main=@var{prefix}
-@opindex mdebug-main=@var{prefix}
-Flag the first routine whose name starts with @var{prefix} as the main
-routine for the debugger.
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
-@item -mmalloc64
-@opindex mmalloc64
-Default to 64-bit memory allocation routines.
+@item -mbranch-cost=@var{num}
+@opindex mbranch-cost=@var{num}
+Assume @var{num} to be the cost for a branch instruction. Higher numbers
+make the compiler try to generate more branch-free code if possible.
+If not specified the value is selected depending on the processor type that
+is being compiled for.
-@item -mpointer-size=@var{size}
-@opindex mpointer-size=@var{size}
-Set the default size of pointers. Possible options for @var{size} are
-@samp{32} or @samp{short} for 32 bit pointers, @samp{64} or @samp{long}
-for 64 bit pointers, and @samp{no} for supporting only 32 bit pointers.
-The later option disables @code{pragma pointer_size}.
-@end table
+@item -mzdcbranch
+@itemx -mno-zdcbranch
+@opindex mzdcbranch
+@opindex mno-zdcbranch
+Assume (do not assume) that zero displacement conditional branch instructions
+@code{bt} and @code{bf} are fast. If @option{-mzdcbranch} is specified, the
+compiler prefers zero displacement branch code sequences. This is
+enabled by default when generating code for SH4 and SH4A. It can be explicitly
+disabled by specifying @option{-mno-zdcbranch}.
-@node VxWorks Options
-@subsection VxWorks Options
-@cindex VxWorks Options
+@item -mcbranch-force-delay-slot
+@opindex mcbranch-force-delay-slot
+Force the usage of delay slots for conditional branches, which stuffs the delay
+slot with a @code{nop} if a suitable instruction can't be found. By default
+this option is disabled. It can be enabled to work around hardware bugs as
+found in the original SH7055.
-The options in this section are defined for all VxWorks targets.
-Options specific to the target hardware are listed with the other
-options for that target.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating-point multiply and
+accumulate instructions. These instructions are generated by default
+if hardware floating point is used. The machine-dependent
+@option{-mfused-madd} option is now mapped to the machine-independent
+@option{-ffp-contract=fast} option, and @option{-mno-fused-madd} is
+mapped to @option{-ffp-contract=off}.
-@table @gcctabopt
-@item -mrtp
-@opindex mrtp
-GCC can generate code for both VxWorks kernels and real time processes
-(RTPs). This option switches from the former to the latter. It also
-defines the preprocessor macro @code{__RTP__}.
+@item -mfsca
+@itemx -mno-fsca
+@opindex mfsca
+@opindex mno-fsca
+Allow or disallow the compiler to emit the @code{fsca} instruction for sine
+and cosine approximations. The option @option{-mfsca} must be used in
+combination with @option{-funsafe-math-optimizations}. It is enabled by default
+when generating code for SH4A. Using @option{-mno-fsca} disables sine and cosine
+approximations even if @option{-funsafe-math-optimizations} is in effect.
-@item -non-static
-@opindex non-static
-Link an RTP executable against shared libraries rather than static
-libraries. The options @option{-static} and @option{-shared} can
-also be used for RTPs (@pxref{Link Options}); @option{-static}
-is the default.
+@item -mfsrra
+@itemx -mno-fsrra
+@opindex mfsrra
+@opindex mno-fsrra
+Allow or disallow the compiler to emit the @code{fsrra} instruction for
+reciprocal square root approximations. The option @option{-mfsrra} must be used
+in combination with @option{-funsafe-math-optimizations} and
+@option{-ffinite-math-only}. It is enabled by default when generating code for
+SH4A. Using @option{-mno-fsrra} disables reciprocal square root approximations
+even if @option{-funsafe-math-optimizations} and @option{-ffinite-math-only} are
+in effect.
-@item -Bstatic
-@itemx -Bdynamic
-@opindex Bstatic
-@opindex Bdynamic
-These options are passed down to the linker. They are defined for
-compatibility with Diab.
+@item -mpretend-cmove
+@opindex mpretend-cmove
+Prefer zero-displacement conditional branches for conditional move instruction
+patterns. This can result in faster code on the SH4 processor.
-@item -Xbind-lazy
-@opindex Xbind-lazy
-Enable lazy binding of function calls. This option is equivalent to
-@option{-Wl,-z,now} and is defined for compatibility with Diab.
+@item -mfdpic
+@opindex fdpic
+Generate code using the FDPIC ABI.
-@item -Xbind-now
-@opindex Xbind-now
-Disable lazy binding of function calls. This option is the default and
-is defined for compatibility with Diab.
@end table
-@node x86 Options
-@subsection x86 Options
-@cindex x86 Options
+@node Solaris 2 Options
+@subsection Solaris 2 Options
+@cindex Solaris 2 options
-These @samp{-m} options are defined for the x86 family of computers.
+These @samp{-m} options are supported on Solaris 2:
@table @gcctabopt
+@item -mclear-hwcap
+@opindex mclear-hwcap
+@option{-mclear-hwcap} tells the compiler to remove the hardware
+capabilities generated by the Solaris assembler. This is only necessary
+when object files use ISA extensions not supported by the current
+machine, but check at runtime whether or not to use them.
-@item -march=@var{cpu-type}
-@opindex march
-Generate instructions for the machine type @var{cpu-type}. In contrast to
-@option{-mtune=@var{cpu-type}}, which merely tunes the generated code
-for the specified @var{cpu-type}, @option{-march=@var{cpu-type}} allows GCC
-to generate code that may not run at all on processors other than the one
-indicated. Specifying @option{-march=@var{cpu-type}} implies
-@option{-mtune=@var{cpu-type}}.
+@item -mimpure-text
+@opindex mimpure-text
+@option{-mimpure-text}, used in addition to @option{-shared}, tells
+the compiler to not pass @option{-z text} to the linker when linking a
+shared object. Using this option, you can link position-dependent
+code into a shared object.
-The choices for @var{cpu-type} are:
+@option{-mimpure-text} suppresses the ``relocations remain against
+allocatable but non-writable sections'' linker error message.
+However, the necessary relocations trigger copy-on-write, and the
+shared object is not actually shared across processes. Instead of
+using @option{-mimpure-text}, you should compile all source code with
+@option{-fpic} or @option{-fPIC}.
-@table @samp
-@item native
-This selects the CPU to generate code for at compilation time by determining
-the processor type of the compiling machine. Using @option{-march=native}
-enables all instruction subsets supported by the local machine (hence
-the result might not run on different machines). Using @option{-mtune=native}
-produces code optimized for the local machine under the constraints
-of the selected instruction set.
+@end table
-@item i386
-Original Intel i386 CPU@.
+These switches are supported in addition to the above on Solaris 2:
-@item i486
-Intel i486 CPU@. (No scheduling is implemented for this chip.)
+@table @gcctabopt
+@item -pthreads
+@opindex pthreads
+Add support for multithreading using the POSIX threads library. This
+option sets flags for both the preprocessor and linker. This option does
+not affect the thread safety of object code produced by the compiler or
+that of libraries supplied with it.
-@item i586
-@itemx pentium
-Intel Pentium CPU with no MMX support.
+@item -pthread
+@opindex pthread
+This is a synonym for @option{-pthreads}.
+@end table
-@item lakemont
-Intel Lakemont MCU, based on Intel Pentium CPU.
+@node SPARC Options
+@subsection SPARC Options
+@cindex SPARC options
-@item pentium-mmx
-Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
+These @samp{-m} options are supported on the SPARC:
-@item pentiumpro
-Intel Pentium Pro CPU@.
+@table @gcctabopt
+@item -mno-app-regs
+@itemx -mapp-regs
+@opindex mno-app-regs
+@opindex mapp-regs
+Specify @option{-mapp-regs} to generate output using the global registers
+2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the
+global register 1, each global register 2 through 4 is then treated as an
+allocable register that is clobbered by function calls. This is the default.
-@item i686
-When used with @option{-march}, the Pentium Pro
-instruction set is used, so the code runs on all i686 family chips.
-When used with @option{-mtune}, it has the same meaning as @samp{generic}.
+To be fully SVR4 ABI-compliant at the cost of some performance loss,
+specify @option{-mno-app-regs}. You should compile libraries and system
+software with this option.
-@item pentium2
-Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set
-support.
+@item -mflat
+@itemx -mno-flat
+@opindex mflat
+@opindex mno-flat
+With @option{-mflat}, the compiler does not generate save/restore instructions
+and uses a ``flat'' or single register window model. This model is compatible
+with the regular register window model. The local registers and the input
+registers (0--5) are still treated as ``call-saved'' registers and are
+saved on the stack as needed.
-@item pentium3
-@itemx pentium3m
-Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction
-set support.
+With @option{-mno-flat} (the default), the compiler generates save/restore
+instructions (except for leaf functions). This is the normal operating mode.
-@item pentium-m
-Intel Pentium M; low-power version of Intel Pentium III CPU
-with MMX, SSE and SSE2 instruction set support. Used by Centrino notebooks.
+@item -mfpu
+@itemx -mhard-float
+@opindex mfpu
+@opindex mhard-float
+Generate output containing floating-point instructions. This is the
+default.
-@item pentium4
-@itemx pentium4m
-Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.
+@item -mno-fpu
+@itemx -msoft-float
+@opindex mno-fpu
+@opindex msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries are not available for all SPARC
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross-compilation. The embedded targets @samp{sparc-*-aout} and
+@samp{sparclite-*-*} do provide software floating-point support.
-@item prescott
-Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction
-set support.
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-@item nocona
-Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE,
-SSE2 and SSE3 instruction set support.
+@item -mhard-quad-float
+@opindex mhard-quad-float
+Generate output containing quad-word (long double) floating-point
+instructions.
-@item core2
-Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
-instruction set support.
+@item -msoft-quad-float
+@opindex msoft-quad-float
+Generate output containing library calls for quad-word (long double)
+floating-point instructions. The functions called are those specified
+in the SPARC ABI@. This is the default.
-@item nehalem
-Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2 and POPCNT instruction set support.
+As of this writing, there are no SPARC implementations that have hardware
+support for the quad-word floating-point instructions. They all invoke
+a trap handler for one of these instructions, and then the trap handler
+emulates the effect of the instruction. Because of the trap handler overhead,
+this is much slower than calling the ABI library routines. Thus the
+@option{-msoft-quad-float} option is the default.
-@item westmere
-Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support.
+@item -mno-unaligned-doubles
+@itemx -munaligned-doubles
+@opindex mno-unaligned-doubles
+@opindex munaligned-doubles
+Assume that doubles have 8-byte alignment. This is the default.
-@item sandybridge
-Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
+With @option{-munaligned-doubles}, GCC assumes that doubles have 8-byte
+alignment only if they are contained in another type, or if they have an
+absolute address. Otherwise, it assumes they have 4-byte alignment.
+Specifying this option avoids some rare compatibility problems with code
+generated by other compilers. It is not the default because it results
+in a performance loss, especially for floating-point code.
-@item ivybridge
-Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
-instruction set support.
+@item -muser-mode
+@itemx -mno-user-mode
+@opindex muser-mode
+@opindex mno-user-mode
+Do not generate code that can only run in supervisor mode. This is relevant
+only for the @code{casa} instruction emitted for the LEON3 processor. This
+is the default.
-@item haswell
-Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2 and F16C instruction set support.
+@item -mfaster-structs
+@itemx -mno-faster-structs
+@opindex mfaster-structs
+@opindex mno-faster-structs
+With @option{-mfaster-structs}, the compiler assumes that structures
+should have 8-byte alignment. This enables the use of pairs of
+@code{ldd} and @code{std} instructions for copies in structure
+assignment, in place of twice as many @code{ld} and @code{st} pairs.
+However, the use of this changed alignment directly violates the SPARC
+ABI@. Thus, it's intended only for use on targets where the developer
+acknowledges that their resulting code is not directly in line with
+the rules of the ABI@.
-@item broadwell
-Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
+@item -mstd-struct-return
+@itemx -mno-std-struct-return
+@opindex mstd-struct-return
+@opindex mno-std-struct-return
+With @option{-mstd-struct-return}, the compiler generates checking code
+in functions returning structures or unions to detect size mismatches
+between the two sides of function calls, as per the 32-bit ABI@.
-@item skylake
-Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
-XSAVES instruction set support.
+The default is @option{-mno-std-struct-return}. This option has no effect
+in 64-bit mode.
-@item bonnell
-Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
-instruction set support.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
+@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc},
+@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930},
+@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9},
+@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
+@samp{niagara3} and @samp{niagara4}.
-@item silvermont
-Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
-SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
+Native Solaris and GNU/Linux toolchains also support the value @samp{native},
+which selects the best architecture option for the host processor.
+@option{-mcpu=native} has no effect if GCC does not recognize
+the processor.
-@item knl
-Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
-AVX512CD instruction set support.
+Default instruction scheduling parameters are used for values that select
+an architecture and not an implementation. These are @samp{v7}, @samp{v8},
+@samp{sparclite}, @samp{sparclet}, @samp{v9}.
-@item skylake-avx512
-Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
-SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
-BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
-AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
+Here is a list of each supported architecture and their supported
+implementations.
-@item k6
-AMD K6 CPU with MMX instruction set support.
+@table @asis
+@item v7
+cypress, leon3v7
-@item k6-2
-@itemx k6-3
-Improved versions of AMD K6 CPU with MMX and 3DNow!@: instruction set support.
+@item v8
+supersparc, hypersparc, leon, leon3
-@item athlon
-@itemx athlon-tbird
-AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow!@: and SSE prefetch instructions
-support.
+@item sparclite
+f930, f934, sparclite86x
-@item athlon-4
-@itemx athlon-xp
-@itemx athlon-mp
-Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow!@: and full SSE
-instruction set support.
+@item sparclet
+tsc701
-@item k8
-@itemx opteron
-@itemx athlon64
-@itemx athlon-fx
-Processors based on the AMD K8 core with x86-64 instruction set support,
-including the AMD Opteron, Athlon 64, and Athlon 64 FX processors.
-(This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow!@: and 64-bit
-instruction set extensions.)
+@item v9
+ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
+@end table
-@item k8-sse3
-@itemx opteron-sse3
-@itemx athlon64-sse3
-Improved versions of AMD K8 cores with SSE3 instruction set support.
+By default (unless configured otherwise), GCC generates code for the V7
+variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
+additionally optimizes it for the Cypress CY7C602 chip, as used in the
+SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
+SPARCStation 1, 2, IPX etc.
-@item amdfam10
-@itemx barcelona
-CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This
-supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
-instruction set extensions.)
+With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
+architecture. The only difference from V7 code is that the compiler emits
+the integer multiply and integer divide instructions which exist in SPARC-V8
+but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
+optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
+2000 series.
-@item bdver1
-CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This
-supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
-SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
-@item bdver2
-AMD Family 15h core based CPUs with x86-64 instruction set support. (This
-supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX,
-SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
-extensions.)
-@item bdver3
-AMD Family 15h core based CPUs with x86-64 instruction set support. (This
-supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,
-PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
-64-bit instruction set extensions.
-@item bdver4
-AMD Family 15h core based CPUs with x86-64 instruction set support. (This
-supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,
-AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
-SSE4.2, ABM and 64-bit instruction set extensions.
+With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
+the SPARC architecture. This adds the integer multiply, integer divide step
+and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
+With @option{-mcpu=f930}, the compiler additionally optimizes it for the
+Fujitsu MB86930 chip, which is the original SPARClite, with no FPU@. With
+@option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
+MB86934 chip, which is the more recent SPARClite with FPU@.
-@item znver1
-AMD Family 17h core based CPUs with x86-64 instruction set support. (This
-supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,
-SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,
-SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
-instruction set extensions.
+With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
+the SPARC architecture. This adds the integer multiply, multiply/accumulate,
+integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
+but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
+optimizes it for the TEMIC SPARClet chip.
-@item btver1
-CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
-supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
-instruction set extensions.)
+With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
+architecture. This adds 64-bit integer and floating-point move instructions,
+3 additional floating-point condition code registers and conditional move
+instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
+optimizes it for the Sun UltraSPARC I/II/IIi chips. With
+@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
+Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
+@option{-mcpu=niagara}, the compiler additionally optimizes it for
+Sun UltraSPARC T1 chips. With @option{-mcpu=niagara2}, the compiler
+additionally optimizes it for Sun UltraSPARC T2 chips. With
+@option{-mcpu=niagara3}, the compiler additionally optimizes it for Sun
+UltraSPARC T3 chips. With @option{-mcpu=niagara4}, the compiler
+additionally optimizes it for Sun UltraSPARC T4 chips.
-@item btver2
-CPUs based on AMD Family 16h cores with x86-64 instruction set support. This
-includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM,
-SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type
+@var{cpu_type}, but do not set the instruction set or register set that the
+option @option{-mcpu=@var{cpu_type}} does.
-@item winchip-c6
-IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction
-set support.
+The same values for @option{-mcpu=@var{cpu_type}} can be used for
+@option{-mtune=@var{cpu_type}}, but the only useful values are those
+that select a particular CPU implementation. Those are @samp{cypress},
+@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3},
+@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701},
+@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2},
+@samp{niagara3} and @samp{niagara4}. With native Solaris and GNU/Linux
+toolchains, @samp{native} can also be used.
-@item winchip2
-IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@:
-instruction set support.
-
-@item c3
-VIA C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is
-implemented for this chip.)
-
-@item c3-2
-VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.
-(No scheduling is
-implemented for this chip.)
-
-@item geode
-AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
-@end table
+@item -mv8plus
+@itemx -mno-v8plus
+@opindex mv8plus
+@opindex mno-v8plus
+With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI@. The
+difference from the V8 ABI is that the global and out registers are
+considered 64 bits wide. This is enabled by default on Solaris in 32-bit
+mode for all SPARC-V9 processors.
-@item -mtune=@var{cpu-type}
-@opindex mtune
-Tune to @var{cpu-type} everything applicable about the generated code, except
-for the ABI and the set of available instructions.
-While picking a specific @var{cpu-type} schedules things appropriately
-for that particular chip, the compiler does not generate any code that
-cannot run on the default machine type unless you use a
-@option{-march=@var{cpu-type}} option.
-For example, if GCC is configured for i686-pc-linux-gnu
-then @option{-mtune=pentium4} generates code that is tuned for Pentium 4
-but still runs on i686 machines.
+@item -mvis
+@itemx -mno-vis
+@opindex mvis
+@opindex mno-vis
+With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
+Visual Instruction Set extensions. The default is @option{-mno-vis}.
-The choices for @var{cpu-type} are the same as for @option{-march}.
-In addition, @option{-mtune} supports 2 extra choices for @var{cpu-type}:
+@item -mvis2
+@itemx -mno-vis2
+@opindex mvis2
+@opindex mno-vis2
+With @option{-mvis2}, GCC generates code that takes advantage of
+version 2.0 of the UltraSPARC Visual Instruction Set extensions. The
+default is @option{-mvis2} when targeting a cpu that supports such
+instructions, such as UltraSPARC-III and later. Setting @option{-mvis2}
+also sets @option{-mvis}.
-@table @samp
-@item generic
-Produce code optimized for the most common IA32/@/AMD64/@/EM64T processors.
-If you know the CPU on which your code will run, then you should use
-the corresponding @option{-mtune} or @option{-march} option instead of
-@option{-mtune=generic}. But, if you do not know exactly what CPU users
-of your application will have, then you should use this option.
+@item -mvis3
+@itemx -mno-vis3
+@opindex mvis3
+@opindex mno-vis3
+With @option{-mvis3}, GCC generates code that takes advantage of
+version 3.0 of the UltraSPARC Visual Instruction Set extensions. The
+default is @option{-mvis3} when targeting a cpu that supports such
+instructions, such as niagara-3 and later. Setting @option{-mvis3}
+also sets @option{-mvis2} and @option{-mvis}.
-As new processors are deployed in the marketplace, the behavior of this
-option will change. Therefore, if you upgrade to a newer version of
-GCC, code generation controlled by this option will change to reflect
-the processors
-that are most common at the time that version of GCC is released.
+@item -mcbcond
+@itemx -mno-cbcond
+@opindex mcbcond
+@opindex mno-cbcond
+With @option{-mcbcond}, GCC generates code that takes advantage of
+compare-and-branch instructions, as defined in the Sparc Architecture 2011.
+The default is @option{-mcbcond} when targeting a cpu that supports such
+instructions, such as niagara-4 and later.
-There is no @option{-march=generic} option because @option{-march}
-indicates the instruction set the compiler can use, and there is no
-generic instruction set applicable to all processors. In contrast,
-@option{-mtune} indicates the processor (or, in this case, collection of
-processors) for which the code is optimized.
+@item -mpopc
+@itemx -mno-popc
+@opindex mpopc
+@opindex mno-popc
+With @option{-mpopc}, GCC generates code that takes advantage of the UltraSPARC
+population count instruction. The default is @option{-mpopc}
+when targeting a cpu that supports such instructions, such as Niagara-2 and
+later.
-@item intel
-Produce code optimized for the most current Intel processors, which are
-Haswell and Silvermont for this version of GCC. If you know the CPU
-on which your code will run, then you should use the corresponding
-@option{-mtune} or @option{-march} option instead of @option{-mtune=intel}.
-But, if you want your application performs better on both Haswell and
-Silvermont, then you should use this option.
+@item -mfmaf
+@itemx -mno-fmaf
+@opindex mfmaf
+@opindex mno-fmaf
+With @option{-mfmaf}, GCC generates code that takes advantage of the UltraSPARC
+Fused Multiply-Add Floating-point extensions. The default is @option{-mfmaf}
+when targeting a cpu that supports such instructions, such as Niagara-3 and
+later.
-As new Intel processors are deployed in the marketplace, the behavior of
-this option will change. Therefore, if you upgrade to a newer version of
-GCC, code generation controlled by this option will change to reflect
-the most current Intel processors at the time that version of GCC is
-released.
+@item -mfix-at697f
+@opindex mfix-at697f
+Enable the documented workaround for the single erratum of the Atmel AT697F
+processor (which corresponds to erratum #13 of the AT697E processor).
-There is no @option{-march=intel} option because @option{-march} indicates
-the instruction set the compiler can use, and there is no common
-instruction set applicable to all processors. In contrast,
-@option{-mtune} indicates the processor (or, in this case, collection of
-processors) for which the code is optimized.
+@item -mfix-ut699
+@opindex mfix-ut699
+Enable the documented workarounds for the floating-point errata and the data
+cache nullify errata of the UT699 processor.
@end table
-@item -mcpu=@var{cpu-type}
-@opindex mcpu
-A deprecated synonym for @option{-mtune}.
+These @samp{-m} options are supported in addition to the above
+on SPARC-V9 processors in 64-bit environments:
-@item -mfpmath=@var{unit}
-@opindex mfpmath
-Generate floating-point arithmetic for selected unit @var{unit}. The choices
-for @var{unit} are:
+@table @gcctabopt
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for a 32-bit or 64-bit environment.
+The 32-bit environment sets int, long and pointer to 32 bits.
+The 64-bit environment sets int to 32 bits and long and pointer
+to 64 bits.
+
+@item -mcmodel=@var{which}
+@opindex mcmodel
+Set the code model to one of
@table @samp
-@item 387
-Use the standard 387 floating-point coprocessor present on the majority of chips and
-emulated otherwise. Code compiled with this option runs almost everywhere.
-The temporary results are computed in 80-bit precision instead of the precision
-specified by the type, resulting in slightly different results compared to most
-of other chips. See @option{-ffloat-store} for more detailed description.
+@item medlow
+The Medium/Low code model: 64-bit addresses, programs
+must be linked in the low 32 bits of memory. Programs can be statically
+or dynamically linked.
-This is the default choice for x86-32 targets.
+@item medmid
+The Medium/Middle code model: 64-bit addresses, programs
+must be linked in the low 44 bits of memory, the text and data segments must
+be less than 2GB in size and the data segment must be located within 2GB of
+the text segment.
-@item sse
-Use scalar floating-point instructions present in the SSE instruction set.
-This instruction set is supported by Pentium III and newer chips,
-and in the AMD line
-by Athlon-4, Athlon XP and Athlon MP chips. The earlier version of the SSE
-instruction set supports only single-precision arithmetic, thus the double and
-extended-precision arithmetic are still done using 387. A later version, present
-only in Pentium 4 and AMD x86-64 chips, supports double-precision
-arithmetic too.
+@item medany
+The Medium/Anywhere code model: 64-bit addresses, programs
+may be linked anywhere in memory, the text and data segments must be less
+than 2GB in size and the data segment must be located within 2GB of the
+text segment.
-For the x86-32 compiler, you must use @option{-march=@var{cpu-type}}, @option{-msse}
-or @option{-msse2} switches to enable SSE extensions and make this option
-effective. For the x86-64 compiler, these extensions are enabled by default.
+@item embmedany
+The Medium/Anywhere code model for embedded systems:
+64-bit addresses, the text and data segments must be less than 2GB in
+size, both starting anywhere in memory (determined at link time). The
+global register %g4 points to the base of the data segment. Programs
+are statically linked and PIC is not supported.
+@end table
-The resulting code should be considerably faster in the majority of cases and avoid
-the numerical instability problems of 387 code, but may break some existing
-code that expects temporaries to be 80 bits.
+@item -mmemory-model=@var{mem-model}
+@opindex mmemory-model
+Set the memory model in force on the processor to one of
-This is the default choice for the x86-64 compiler.
+@table @samp
+@item default
+The default memory model for the processor and operating system.
-@item sse,387
-@itemx sse+387
-@itemx both
-Attempt to utilize both instruction sets at once. This effectively doubles the
-amount of available registers, and on chips with separate execution units for
-387 and SSE the execution resources too. Use this option with care, as it is
-still experimental, because the GCC register allocator does not model separate
-functional units well, resulting in unstable performance.
-@end table
+@item rmo
+Relaxed Memory Order
-@item -masm=@var{dialect}
-@opindex masm=@var{dialect}
-Output assembly instructions using selected @var{dialect}. Also affects
-which dialect is used for basic @code{asm} (@pxref{Basic Asm}) and
-extended @code{asm} (@pxref{Extended Asm}). Supported choices (in dialect
-order) are @samp{att} or @samp{intel}. The default is @samp{att}. Darwin does
-not support @samp{intel}.
+@item pso
+Partial Store Order
-@item -mieee-fp
-@itemx -mno-ieee-fp
-@opindex mieee-fp
-@opindex mno-ieee-fp
-Control whether or not the compiler uses IEEE floating-point
-comparisons. These correctly handle the case where the result of a
-comparison is unordered.
+@item tso
+Total Store Order
-@item -msoft-float
-@opindex msoft-float
-Generate output containing library calls for floating point.
+@item sc
+Sequential Consistency
+@end table
-@strong{Warning:} the requisite libraries are not part of GCC@.
-Normally the facilities of the machine's usual C compiler are used, but
-this can't be done directly in cross-compilation. You must make your
-own arrangements to provide suitable library functions for
-cross-compilation.
+These memory models are formally defined in Appendix D of the Sparc V9
+architecture manual, as set in the processor's @code{PSTATE.MM} field.
-On machines where a function returns floating-point results in the 80387
-register stack, some floating-point opcodes may be emitted even if
-@option{-msoft-float} is used.
+@item -mstack-bias
+@itemx -mno-stack-bias
+@opindex mstack-bias
+@opindex mno-stack-bias
+With @option{-mstack-bias}, GCC assumes that the stack pointer, and
+frame pointer if present, are offset by @minus{}2047 which must be added back
+when making stack frame references. This is the default in 64-bit mode.
+Otherwise, assume no such offset is present.
+@end table
-@item -mno-fp-ret-in-387
-@opindex mno-fp-ret-in-387
-Do not use the FPU registers for return values of functions.
+@node SPU Options
+@subsection SPU Options
+@cindex SPU options
-The usual calling convention has functions return values of types
-@code{float} and @code{double} in an FPU register, even if there
-is no FPU@. The idea is that the operating system should emulate
-an FPU@.
+These @samp{-m} options are supported on the SPU:
-The option @option{-mno-fp-ret-in-387} causes such values to be returned
-in ordinary CPU registers instead.
+@table @gcctabopt
+@item -mwarn-reloc
+@itemx -merror-reloc
+@opindex mwarn-reloc
+@opindex merror-reloc
-@item -mno-fancy-math-387
-@opindex mno-fancy-math-387
-Some 387 emulators do not support the @code{sin}, @code{cos} and
-@code{sqrt} instructions for the 387. Specify this option to avoid
-generating those instructions. This option is the default on
-OpenBSD and NetBSD@. This option is overridden when @option{-march}
-indicates that the target CPU always has an FPU and so the
-instruction does not need emulation. These
-instructions are not generated unless you also use the
-@option{-funsafe-math-optimizations} switch.
+The loader for SPU does not handle dynamic relocations. By default, GCC
+gives an error when it generates code that requires a dynamic
+relocation. @option{-mno-error-reloc} disables the error,
+@option{-mwarn-reloc} generates a warning instead.
-@item -malign-double
-@itemx -mno-align-double
-@opindex malign-double
-@opindex mno-align-double
-Control whether GCC aligns @code{double}, @code{long double}, and
-@code{long long} variables on a two-word boundary or a one-word
-boundary. Aligning @code{double} variables on a two-word boundary
-produces code that runs somewhat faster on a Pentium at the
-expense of more memory.
+@item -msafe-dma
+@itemx -munsafe-dma
+@opindex msafe-dma
+@opindex munsafe-dma
-On x86-64, @option{-malign-double} is enabled by default.
+Instructions that initiate or test completion of DMA must not be
+reordered with respect to loads and stores of the memory that is being
+accessed.
+With @option{-munsafe-dma} you must use the @code{volatile} keyword to protect
+memory accesses, but that can lead to inefficient code in places where the
+memory is known to not change. Rather than mark the memory as volatile,
+you can use @option{-msafe-dma} to tell the compiler to treat
+the DMA instructions as potentially affecting all memory.
-@strong{Warning:} if you use the @option{-malign-double} switch,
-structures containing the above types are aligned differently than
-the published application binary interface specifications for the x86-32
-and are not binary compatible with structures in code compiled
-without that switch.
+@item -mbranch-hints
+@opindex mbranch-hints
-@item -m96bit-long-double
-@itemx -m128bit-long-double
-@opindex m96bit-long-double
-@opindex m128bit-long-double
-These switches control the size of @code{long double} type. The x86-32
-application binary interface specifies the size to be 96 bits,
-so @option{-m96bit-long-double} is the default in 32-bit mode.
+By default, GCC generates a branch hint instruction to avoid
+pipeline stalls for always-taken or probably-taken branches. A hint
+is not generated closer than 8 instructions away from its branch.
+There is little reason to disable them, except for debugging purposes,
+or to make an object a little bit smaller.
-Modern architectures (Pentium and newer) prefer @code{long double}
-to be aligned to an 8- or 16-byte boundary. In arrays or structures
-conforming to the ABI, this is not possible. So specifying
-@option{-m128bit-long-double} aligns @code{long double}
-to a 16-byte boundary by padding the @code{long double} with an additional
-32-bit zero.
+@item -msmall-mem
+@itemx -mlarge-mem
+@opindex msmall-mem
+@opindex mlarge-mem
-In the x86-64 compiler, @option{-m128bit-long-double} is the default choice as
-its ABI specifies that @code{long double} is aligned on 16-byte boundary.
+By default, GCC generates code assuming that addresses are never larger
+than 18 bits. With @option{-mlarge-mem} code is generated that assumes
+a full 32-bit address.
-Notice that neither of these options enable any extra precision over the x87
-standard of 80 bits for a @code{long double}.
+@item -mstdmain
+@opindex mstdmain
-@strong{Warning:} if you override the default value for your target ABI, this
-changes the size of
-structures and arrays containing @code{long double} variables,
-as well as modifying the function calling convention for functions taking
-@code{long double}. Hence they are not binary-compatible
-with code compiled without that switch.
+By default, GCC links against startup code that assumes the SPU-style
+main function interface (which has an unconventional parameter list).
+With @option{-mstdmain}, GCC links your program against startup
+code that assumes a C99-style interface to @code{main}, including a
+local copy of @code{argv} strings.
-@item -mlong-double-64
-@itemx -mlong-double-80
-@itemx -mlong-double-128
-@opindex mlong-double-64
-@opindex mlong-double-80
-@opindex mlong-double-128
-These switches control the size of @code{long double} type. A size
-of 64 bits makes the @code{long double} type equivalent to the @code{double}
-type. This is the default for 32-bit Bionic C library. A size
-of 128 bits makes the @code{long double} type equivalent to the
-@code{__float128} type. This is the default for 64-bit Bionic C library.
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator cannot use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
-@strong{Warning:} if you override the default value for your target ABI, this
-changes the size of
-structures and arrays containing @code{long double} variables,
-as well as modifying the function calling convention for functions taking
-@code{long double}. Hence they are not binary-compatible
-with code compiled without that switch.
+@item -mea32
+@itemx -mea64
+@opindex mea32
+@opindex mea64
+Compile code assuming that pointers to the PPU address space accessed
+via the @code{__ea} named address space qualifier are either 32 or 64
+bits wide. The default is 32 bits. As this is an ABI-changing option,
+all object code in an executable must be compiled with the same setting.
-@item -malign-data=@var{type}
-@opindex malign-data
-Control how GCC aligns variables. Supported values for @var{type} are
-@samp{compat} uses increased alignment value compatible uses GCC 4.8
-and earlier, @samp{abi} uses alignment value as specified by the
-psABI, and @samp{cacheline} uses increased alignment value to match
-the cache line size. @samp{compat} is the default.
+@item -maddress-space-conversion
+@itemx -mno-address-space-conversion
+@opindex maddress-space-conversion
+@opindex mno-address-space-conversion
+Allow/disallow treating the @code{__ea} address space as superset
+of the generic address space. This enables explicit type casts
+between @code{__ea} and generic pointer as well as implicit
+conversions of generic pointers to @code{__ea} pointers. The
+default is to allow address space pointer conversions.
-@item -mlarge-data-threshold=@var{threshold}
-@opindex mlarge-data-threshold
-When @option{-mcmodel=medium} is specified, data objects larger than
-@var{threshold} are placed in the large data section. This value must be the
-same across all objects linked into the binary, and defaults to 65535.
+@item -mcache-size=@var{cache-size}
+@opindex mcache-size
+This option controls the version of libgcc that the compiler links to an
+executable and selects a software-managed cache for accessing variables
+in the @code{__ea} address space with a particular cache size. Possible
+options for @var{cache-size} are @samp{8}, @samp{16}, @samp{32}, @samp{64}
+and @samp{128}. The default cache size is 64KB.
-@item -mrtd
-@opindex mrtd
-Use a different function-calling convention, in which functions that
-take a fixed number of arguments return with the @code{ret @var{num}}
-instruction, which pops their arguments while returning. This saves one
-instruction in the caller since there is no need to pop the arguments
-there.
+@item -matomic-updates
+@itemx -mno-atomic-updates
+@opindex matomic-updates
+@opindex mno-atomic-updates
+This option controls the version of libgcc that the compiler links to an
+executable and selects whether atomic updates to the software-managed
+cache of PPU-side variables are used. If you use atomic updates, changes
+to a PPU variable from SPU code using the @code{__ea} named address space
+qualifier do not interfere with changes to other PPU variables residing
+in the same cache line from PPU code. If you do not use atomic updates,
+such interference may occur; however, writing back cache lines is
+more efficient. The default behavior is to use atomic updates.
-You can specify that an individual function is called with this calling
-sequence with the function attribute @code{stdcall}. You can also
-override the @option{-mrtd} option by using the function attribute
-@code{cdecl}. @xref{Function Attributes}.
+@item -mdual-nops
+@itemx -mdual-nops=@var{n}
+@opindex mdual-nops
+By default, GCC inserts nops to increase dual issue when it expects
+it to increase performance. @var{n} can be a value from 0 to 10. A
+smaller @var{n} inserts fewer nops. 10 is the default, 0 is the
+same as @option{-mno-dual-nops}. Disabled with @option{-Os}.
-@strong{Warning:} this calling convention is incompatible with the one
-normally used on Unix, so you cannot use it if you need to call
-libraries compiled with the Unix compiler.
+@item -mhint-max-nops=@var{n}
+@opindex mhint-max-nops
+Maximum number of nops to insert for a branch hint. A branch hint must
+be at least 8 instructions away from the branch it is affecting. GCC
+inserts up to @var{n} nops to enforce this, otherwise it does not
+generate the branch hint.
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including @code{printf});
-otherwise incorrect code is generated for calls to those
-functions.
+@item -mhint-max-distance=@var{n}
+@opindex mhint-max-distance
+The encoding of the branch hint instruction limits the hint to be within
+256 instructions of the branch it is affecting. By default, GCC makes
+sure it is within 125.
-In addition, seriously incorrect code results if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
+@item -msafe-hints
+@opindex msafe-hints
+Work around a hardware bug that causes the SPU to stall indefinitely.
+By default, GCC inserts the @code{hbrp} instruction to make sure
+this stall won't happen.
-@item -mregparm=@var{num}
-@opindex mregparm
-Control how many registers are used to pass integer arguments. By
-default, no registers are used to pass arguments, and at most 3
-registers can be used. You can control this behavior for a specific
-function by using the function attribute @code{regparm}.
-@xref{Function Attributes}.
+@end table
-@strong{Warning:} if you use this switch, and
-@var{num} is nonzero, then you must build all modules with the same
-value, including any libraries. This includes the system libraries and
-startup modules.
+@node System V Options
+@subsection Options for System V
-@item -msseregparm
-@opindex msseregparm
-Use SSE register passing conventions for float and double arguments
-and return values. You can control this behavior for a specific
-function by using the function attribute @code{sseregparm}.
-@xref{Function Attributes}.
+These additional options are available on System V Release 4 for
+compatibility with other compilers on those systems:
-@strong{Warning:} if you use this switch then you must build all
-modules with the same value, including any libraries. This includes
-the system libraries and startup modules.
+@table @gcctabopt
+@item -G
+@opindex G
+Create a shared object.
+It is recommended that @option{-symbolic} or @option{-shared} be used instead.
-@item -mvect8-ret-in-mem
-@opindex mvect8-ret-in-mem
-Return 8-byte vectors in memory instead of MMX registers. This is the
-default on Solaris@tie{}8 and 9 and VxWorks to match the ABI of the Sun
-Studio compilers until version 12. Later compiler versions (starting
-with Studio 12 Update@tie{}1) follow the ABI used by other x86 targets, which
-is the default on Solaris@tie{}10 and later. @emph{Only} use this option if
-you need to remain compatible with existing code produced by those
-previous compiler versions or older versions of GCC@.
+@item -Qy
+@opindex Qy
+Identify the versions of each tool used by the compiler, in a
+@code{.ident} assembler directive in the output.
-@item -mpc32
-@itemx -mpc64
-@itemx -mpc80
-@opindex mpc32
-@opindex mpc64
-@opindex mpc80
+@item -Qn
+@opindex Qn
+Refrain from adding @code{.ident} directives to the output file (this is
+the default).
-Set 80387 floating-point precision to 32, 64 or 80 bits. When @option{-mpc32}
-is specified, the significands of results of floating-point operations are
-rounded to 24 bits (single precision); @option{-mpc64} rounds the
-significands of results of floating-point operations to 53 bits (double
-precision) and @option{-mpc80} rounds the significands of results of
-floating-point operations to 64 bits (extended double precision), which is
-the default. When this option is used, floating-point operations in higher
-precisions are not available to the programmer without setting the FPU
-control word explicitly.
+@item -YP,@var{dirs}
+@opindex YP
+Search the directories @var{dirs}, and no others, for libraries
+specified with @option{-l}.
-Setting the rounding of floating-point operations to less than the default
-80 bits can speed some programs by 2% or more. Note that some mathematical
-libraries assume that extended-precision (80-bit) floating-point operations
-are enabled by default; routines in such libraries could suffer significant
-loss of accuracy, typically through so-called ``catastrophic cancellation'',
-when this option is used to set the precision to less than extended precision.
+@item -Ym,@var{dir}
+@opindex Ym
+Look in the directory @var{dir} to find the M4 preprocessor.
+The assembler uses this option.
+@c This is supposed to go with a -Yd for predefined M4 macro files, but
+@c the generic assembler that comes with Solaris takes just -Ym.
+@end table
-@item -mstackrealign
-@opindex mstackrealign
-Realign the stack at entry. On the x86, the @option{-mstackrealign}
-option generates an alternate prologue and epilogue that realigns the
-run-time stack if necessary. This supports mixing legacy codes that keep
-4-byte stack alignment with modern codes that keep 16-byte stack alignment for
-SSE compatibility. See also the attribute @code{force_align_arg_pointer},
-applicable to individual functions.
+@node TILE-Gx Options
+@subsection TILE-Gx Options
+@cindex TILE-Gx options
-@item -mpreferred-stack-boundary=@var{num}
-@opindex mpreferred-stack-boundary
-Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
-byte boundary. If @option{-mpreferred-stack-boundary} is not specified,
-the default is 4 (16 bytes or 128 bits).
+These @samp{-m} options are supported on the TILE-Gx:
-@strong{Warning:} When generating code for the x86-64 architecture with
-SSE extensions disabled, @option{-mpreferred-stack-boundary=3} can be
-used to keep the stack boundary aligned to 8 byte boundary. Since
-x86-64 ABI require 16 byte stack alignment, this is ABI incompatible and
-intended to be used in controlled environment where stack space is
-important limitation. This option leads to wrong code when functions
-compiled with 16 byte stack alignment (such as functions from a standard
-library) are called with misaligned stack. In this case, SSE
-instructions may lead to misaligned memory access traps. In addition,
-variable arguments are handled incorrectly for 16 byte aligned
-objects (including x87 long double and __int128), leading to wrong
-results. You must build all modules with
-@option{-mpreferred-stack-boundary=3}, including any libraries. This
-includes the system libraries and startup modules.
+@table @gcctabopt
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small model. The distance for direct calls is
+limited to 500M in either direction. PC-relative addresses are 32
+bits. Absolute addresses support the full address range.
-@item -mincoming-stack-boundary=@var{num}
-@opindex mincoming-stack-boundary
-Assume the incoming stack is aligned to a 2 raised to @var{num} byte
-boundary. If @option{-mincoming-stack-boundary} is not specified,
-the one specified by @option{-mpreferred-stack-boundary} is used.
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large model. There is no limitation on call
+distance, pc-relative addresses, or absolute addresses.
-On Pentium and Pentium Pro, @code{double} and @code{long double} values
-should be aligned to an 8-byte boundary (see @option{-malign-double}) or
-suffer significant run time performance penalties. On Pentium III, the
-Streaming SIMD Extension (SSE) data type @code{__m128} may not work
-properly if it is not 16-byte aligned.
+@item -mcpu=@var{name}
+@opindex mcpu
+Selects the type of CPU to be targeted. Currently the only supported
+type is @samp{tilegx}.
-To ensure proper alignment of this values on the stack, the stack boundary
-must be as aligned as that required by any value stored on the stack.
-Further, every function must be generated such that it keeps the stack
-aligned. Thus calling a function compiled with a higher preferred
-stack boundary from a function compiled with a lower preferred stack
-boundary most likely misaligns the stack. It is recommended that
-libraries that use callbacks always use the default setting.
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for a 32-bit or 64-bit environment. The 32-bit
+environment sets int, long, and pointer to 32 bits. The 64-bit
+environment sets int to 32 bits and long and pointer to 64 bits.
-This extra alignment does consume extra stack space, and generally
-increases code size. Code that is sensitive to stack space usage, such
-as embedded systems and operating system kernels, may want to reduce the
-preferred alignment to @option{-mpreferred-stack-boundary=2}.
+@item -mbig-endian
+@itemx -mlittle-endian
+@opindex mbig-endian
+@opindex mlittle-endian
+Generate code in big/little endian mode, respectively.
+@end table
-@need 200
-@item -mmmx
-@opindex mmmx
-@need 200
-@itemx -msse
-@opindex msse
-@need 200
-@itemx -msse2
-@opindex msse2
-@need 200
-@itemx -msse3
-@opindex msse3
-@need 200
-@itemx -mssse3
-@opindex mssse3
-@need 200
-@itemx -msse4
-@opindex msse4
-@need 200
-@itemx -msse4a
-@opindex msse4a
-@need 200
-@itemx -msse4.1
-@opindex msse4.1
-@need 200
-@itemx -msse4.2
-@opindex msse4.2
-@need 200
-@itemx -mavx
-@opindex mavx
-@need 200
-@itemx -mavx2
-@opindex mavx2
-@need 200
-@itemx -mavx512f
-@opindex mavx512f
-@need 200
-@itemx -mavx512pf
-@opindex mavx512pf
-@need 200
-@itemx -mavx512er
-@opindex mavx512er
-@need 200
-@itemx -mavx512cd
-@opindex mavx512cd
-@need 200
-@itemx -mavx512vl
-@opindex mavx512vl
-@need 200
-@itemx -mavx512bw
-@opindex mavx512bw
-@need 200
-@itemx -mavx512dq
-@opindex mavx512dq
-@need 200
-@itemx -mavx512ifma
-@opindex mavx512ifma
-@need 200
-@itemx -mavx512vbmi
-@opindex mavx512vbmi
-@need 200
-@itemx -msha
-@opindex msha
-@need 200
-@itemx -maes
-@opindex maes
-@need 200
-@itemx -mpclmul
-@opindex mpclmul
-@need 200
-@itemx -mclfushopt
-@opindex mclfushopt
-@need 200
-@itemx -mfsgsbase
-@opindex mfsgsbase
-@need 200
-@itemx -mrdrnd
-@opindex mrdrnd
-@need 200
-@itemx -mf16c
-@opindex mf16c
-@need 200
-@itemx -mfma
-@opindex mfma
-@need 200
-@itemx -mfma4
-@opindex mfma4
-@need 200
-@itemx -mno-fma4
-@opindex mno-fma4
-@need 200
-@itemx -mprefetchwt1
-@opindex mprefetchwt1
-@need 200
-@itemx -mxop
-@opindex mxop
-@need 200
-@itemx -mlwp
-@opindex mlwp
-@need 200
-@itemx -m3dnow
-@opindex m3dnow
-@need 200
-@itemx -mpopcnt
-@opindex mpopcnt
-@need 200
-@itemx -mabm
-@opindex mabm
-@need 200
-@itemx -mbmi
-@opindex mbmi
-@need 200
-@itemx -mbmi2
-@need 200
-@itemx -mlzcnt
-@opindex mlzcnt
-@need 200
-@itemx -mfxsr
-@opindex mfxsr
-@need 200
-@itemx -mxsave
-@opindex mxsave
-@need 200
-@itemx -mxsaveopt
-@opindex mxsaveopt
-@need 200
-@itemx -mxsavec
-@opindex mxsavec
-@need 200
-@itemx -mxsaves
-@opindex mxsaves
-@need 200
-@itemx -mrtm
-@opindex mrtm
-@need 200
-@itemx -mtbm
-@opindex mtbm
-@need 200
-@itemx -mmpx
-@opindex mmpx
-@need 200
-@itemx -mmwaitx
-@opindex mmwaitx
-@need 200
-@itemx -mclzero
-@opindex mclzero
-@itemx -mpku
-@opindex mpku
-These switches enable the use of instructions in the MMX, SSE,
-SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
-SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
-AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
-XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@:
-extended instruction sets. Each has a corresponding @option{-mno-} option
-to disable use of these instructions.
+@node TILEPro Options
+@subsection TILEPro Options
+@cindex TILEPro options
-These extensions are also available as built-in functions: see
-@ref{x86 Built-in Functions}, for details of the functions enabled and
-disabled by these switches.
+These @samp{-m} options are supported on the TILEPro:
-To generate SSE/SSE2 instructions automatically from floating-point
-code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
+@table @gcctabopt
+@item -mcpu=@var{name}
+@opindex mcpu
+Selects the type of CPU to be targeted. Currently the only supported
+type is @samp{tilepro}.
-GCC depresses SSEx instructions when @option{-mavx} is used. Instead, it
-generates new AVX instructions or AVX equivalence for all SSEx instructions
-when needed.
+@item -m32
+@opindex m32
+Generate code for a 32-bit environment, which sets int, long, and
+pointer to 32 bits. This is the only supported behavior so the flag
+is essentially ignored.
+@end table
-These options enable GCC to use these extended instructions in
-generated code, even without @option{-mfpmath=sse}. Applications that
-perform run-time CPU detection must compile separate files for each
-supported architecture, using the appropriate flags. In particular,
-the file containing the CPU detection code should be compiled without
-these options.
+@node V850 Options
+@subsection V850 Options
+@cindex V850 Options
-@item -mdump-tune-features
-@opindex mdump-tune-features
-This option instructs GCC to dump the names of the x86 performance
-tuning features and default settings. The names can be used in
-@option{-mtune-ctrl=@var{feature-list}}.
+These @samp{-m} options are defined for V850 implementations:
-@item -mtune-ctrl=@var{feature-list}
-@opindex mtune-ctrl=@var{feature-list}
-This option is used to do fine grain control of x86 code generation features.
-@var{feature-list} is a comma separated list of @var{feature} names. See also
-@option{-mdump-tune-features}. When specified, the @var{feature} is turned
-on if it is not preceded with @samp{^}, otherwise, it is turned off.
-@option{-mtune-ctrl=@var{feature-list}} is intended to be used by GCC
-developers. Using it may lead to code paths not covered by testing and can
-potentially result in compiler ICEs or runtime errors.
+@table @gcctabopt
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Treat all calls as being far away (near). If calls are assumed to be
+far away, the compiler always loads the function's address into a
+register, and calls indirect through the pointer.
-@item -mno-default
-@opindex mno-default
-This option instructs GCC to turn off all tunable features. See also
-@option{-mtune-ctrl=@var{feature-list}} and @option{-mdump-tune-features}.
+@item -mno-ep
+@itemx -mep
+@opindex mno-ep
+@opindex mep
+Do not optimize (do optimize) basic blocks that use the same index
+pointer 4 or more times to copy pointer into the @code{ep} register, and
+use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
+option is on by default if you optimize.
-@item -mcld
-@opindex mcld
-This option instructs GCC to emit a @code{cld} instruction in the prologue
-of functions that use string instructions. String instructions depend on
-the DF flag to select between autoincrement or autodecrement mode. While the
-ABI specifies the DF flag to be cleared on function entry, some operating
-systems violate this specification by not clearing the DF flag in their
-exception dispatchers. The exception handler can be invoked with the DF flag
-set, which leads to wrong direction mode when string instructions are used.
-This option can be enabled by default on 32-bit x86 targets by configuring
-GCC with the @option{--enable-cld} configure option. Generation of @code{cld}
-instructions can be suppressed with the @option{-mno-cld} compiler option
-in this case.
+@item -mno-prolog-function
+@itemx -mprolog-function
+@opindex mno-prolog-function
+@opindex mprolog-function
+Do not use (do use) external functions to save and restore registers
+at the prologue and epilogue of a function. The external functions
+are slower, but use less code space if more than one function saves
+the same number of registers. The @option{-mprolog-function} option
+is on by default if you optimize.
-@item -mvzeroupper
-@opindex mvzeroupper
-This option instructs GCC to emit a @code{vzeroupper} instruction
-before a transfer of control flow out of the function to minimize
-the AVX to SSE transition penalty as well as remove unnecessary @code{zeroupper}
-intrinsics.
+@item -mspace
+@opindex mspace
+Try to make the code as small as possible. At present, this just turns
+on the @option{-mep} and @option{-mprolog-function} options.
-@item -mprefer-avx128
-@opindex mprefer-avx128
-This option instructs GCC to use 128-bit AVX instructions instead of
-256-bit AVX instructions in the auto-vectorizer.
+@item -mtda=@var{n}
+@opindex mtda
+Put static or global variables whose size is @var{n} bytes or less into
+the tiny data area that register @code{ep} points to. The tiny data
+area can hold up to 256 bytes in total (128 bytes for byte references).
-@item -mcx16
-@opindex mcx16
-This option enables GCC to generate @code{CMPXCHG16B} instructions.
-@code{CMPXCHG16B} allows for atomic operations on 128-bit double quadword
-(or oword) data types.
-This is useful for high-resolution counters that can be updated
-by multiple processors (or cores). This instruction is generated as part of
-atomic built-in functions: see @ref{__sync Builtins} or
-@ref{__atomic Builtins} for details.
+@item -msda=@var{n}
+@opindex msda
+Put static or global variables whose size is @var{n} bytes or less into
+the small data area that register @code{gp} points to. The small data
+area can hold up to 64 kilobytes.
-@item -msahf
-@opindex msahf
-This option enables generation of @code{SAHF} instructions in 64-bit code.
-Early Intel Pentium 4 CPUs with Intel 64 support,
-prior to the introduction of Pentium 4 G1 step in December 2005,
-lacked the @code{LAHF} and @code{SAHF} instructions
-which are supported by AMD64.
-These are load and store instructions, respectively, for certain status flags.
-In 64-bit mode, the @code{SAHF} instruction is used to optimize @code{fmod},
-@code{drem}, and @code{remainder} built-in functions;
-see @ref{Other Builtins} for details.
+@item -mzda=@var{n}
+@opindex mzda
+Put static or global variables whose size is @var{n} bytes or less into
+the first 32 kilobytes of memory.
-@item -mmovbe
-@opindex mmovbe
-This option enables use of the @code{movbe} instruction to implement
-@code{__builtin_bswap32} and @code{__builtin_bswap64}.
+@item -mv850
+@opindex mv850
+Specify that the target processor is the V850.
-@item -mcrc32
-@opindex mcrc32
-This option enables built-in functions @code{__builtin_ia32_crc32qi},
-@code{__builtin_ia32_crc32hi}, @code{__builtin_ia32_crc32si} and
-@code{__builtin_ia32_crc32di} to generate the @code{crc32} machine instruction.
+@item -mv850e3v5
+@opindex mv850e3v5
+Specify that the target processor is the V850E3V5. The preprocessor
+constant @code{__v850e3v5__} is defined if this option is used.
-@item -mrecip
-@opindex mrecip
-This option enables use of @code{RCPSS} and @code{RSQRTSS} instructions
-(and their vectorized variants @code{RCPPS} and @code{RSQRTPS})
-with an additional Newton-Raphson step
-to increase precision instead of @code{DIVSS} and @code{SQRTSS}
-(and their vectorized
-variants) for single-precision floating-point arguments. These instructions
-are generated only when @option{-funsafe-math-optimizations} is enabled
-together with @option{-ffinite-math-only} and @option{-fno-trapping-math}.
-Note that while the throughput of the sequence is higher than the throughput
-of the non-reciprocal instruction, the precision of the sequence can be
-decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
+@item -mv850e2v4
+@opindex mv850e2v4
+Specify that the target processor is the V850E3V5. This is an alias for
+the @option{-mv850e3v5} option.
-Note that GCC implements @code{1.0f/sqrtf(@var{x})} in terms of @code{RSQRTSS}
-(or @code{RSQRTPS}) already with @option{-ffast-math} (or the above option
-combination), and doesn't need @option{-mrecip}.
+@item -mv850e2v3
+@opindex mv850e2v3
+Specify that the target processor is the V850E2V3. The preprocessor
+constant @code{__v850e2v3__} is defined if this option is used.
-Also note that GCC emits the above sequence with additional Newton-Raphson step
-for vectorized single-float division and vectorized @code{sqrtf(@var{x})}
-already with @option{-ffast-math} (or the above option combination), and
-doesn't need @option{-mrecip}.
+@item -mv850e2
+@opindex mv850e2
+Specify that the target processor is the V850E2. The preprocessor
+constant @code{__v850e2__} is defined if this option is used.
-@item -mrecip=@var{opt}
-@opindex mrecip=opt
-This option controls which reciprocal estimate instructions
-may be used. @var{opt} is a comma-separated list of options, which may
-be preceded by a @samp{!} to invert the option:
+@item -mv850e1
+@opindex mv850e1
+Specify that the target processor is the V850E1. The preprocessor
+constants @code{__v850e1__} and @code{__v850e__} are defined if
+this option is used.
-@table @samp
-@item all
-Enable all estimate instructions.
+@item -mv850es
+@opindex mv850es
+Specify that the target processor is the V850ES. This is an alias for
+the @option{-mv850e1} option.
-@item default
-Enable the default instructions, equivalent to @option{-mrecip}.
+@item -mv850e
+@opindex mv850e
+Specify that the target processor is the V850E@. The preprocessor
+constant @code{__v850e__} is defined if this option is used.
-@item none
-Disable all estimate instructions, equivalent to @option{-mno-recip}.
+If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
+nor @option{-mv850e2} nor @option{-mv850e2v3} nor @option{-mv850e3v5}
+are defined then a default target processor is chosen and the
+relevant @samp{__v850*__} preprocessor constant is defined.
-@item div
-Enable the approximation for scalar division.
+The preprocessor constants @code{__v850} and @code{__v851__} are always
+defined, regardless of which processor variant is the target.
-@item vec-div
-Enable the approximation for vectorized division.
+@item -mdisable-callt
+@itemx -mno-disable-callt
+@opindex mdisable-callt
+@opindex mno-disable-callt
+This option suppresses generation of the @code{CALLT} instruction for the
+v850e, v850e1, v850e2, v850e2v3 and v850e3v5 flavors of the v850
+architecture.
-@item sqrt
-Enable the approximation for scalar square root.
+This option is enabled by default when the RH850 ABI is
+in use (see @option{-mrh850-abi}), and disabled by default when the
+GCC ABI is in use. If @code{CALLT} instructions are being generated
+then the C preprocessor symbol @code{__V850_CALLT__} is defined.
-@item vec-sqrt
-Enable the approximation for vectorized square root.
-@end table
+@item -mrelax
+@itemx -mno-relax
+@opindex mrelax
+@opindex mno-relax
+Pass on (or do not pass on) the @option{-mrelax} command-line option
+to the assembler.
-So, for example, @option{-mrecip=all,!sqrt} enables
-all of the reciprocal approximations, except for square root.
+@item -mlong-jumps
+@itemx -mno-long-jumps
+@opindex mlong-jumps
+@opindex mno-long-jumps
+Disable (or re-enable) the generation of PC-relative jump instructions.
-@item -mveclibabi=@var{type}
-@opindex mveclibabi
-Specifies the ABI type to use for vectorizing intrinsics using an
-external library. Supported values for @var{type} are @samp{svml}
-for the Intel short
-vector math library and @samp{acml} for the AMD math core library.
-To use this option, both @option{-ftree-vectorize} and
-@option{-funsafe-math-optimizations} have to be enabled, and an SVML or ACML
-ABI-compatible library must be specified at link time.
+@item -msoft-float
+@itemx -mhard-float
+@opindex msoft-float
+@opindex mhard-float
+Disable (or re-enable) the generation of hardware floating point
+instructions. This option is only significant when the target
+architecture is @samp{V850E2V3} or higher. If hardware floating point
+instructions are being generated then the C preprocessor symbol
+@code{__FPU_OK__} is defined, otherwise the symbol
+@code{__NO_FPU__} is defined.
-GCC currently emits calls to @code{vmldExp2},
-@code{vmldLn2}, @code{vmldLog102}, @code{vmldLog102}, @code{vmldPow2},
-@code{vmldTanh2}, @code{vmldTan2}, @code{vmldAtan2}, @code{vmldAtanh2},
-@code{vmldCbrt2}, @code{vmldSinh2}, @code{vmldSin2}, @code{vmldAsinh2},
-@code{vmldAsin2}, @code{vmldCosh2}, @code{vmldCos2}, @code{vmldAcosh2},
-@code{vmldAcos2}, @code{vmlsExp4}, @code{vmlsLn4}, @code{vmlsLog104},
-@code{vmlsLog104}, @code{vmlsPow4}, @code{vmlsTanh4}, @code{vmlsTan4},
-@code{vmlsAtan4}, @code{vmlsAtanh4}, @code{vmlsCbrt4}, @code{vmlsSinh4},
-@code{vmlsSin4}, @code{vmlsAsinh4}, @code{vmlsAsin4}, @code{vmlsCosh4},
-@code{vmlsCos4}, @code{vmlsAcosh4} and @code{vmlsAcos4} for corresponding
-function type when @option{-mveclibabi=svml} is used, and @code{__vrd2_sin},
-@code{__vrd2_cos}, @code{__vrd2_exp}, @code{__vrd2_log}, @code{__vrd2_log2},
-@code{__vrd2_log10}, @code{__vrs4_sinf}, @code{__vrs4_cosf},
-@code{__vrs4_expf}, @code{__vrs4_logf}, @code{__vrs4_log2f},
-@code{__vrs4_log10f} and @code{__vrs4_powf} for the corresponding function type
-when @option{-mveclibabi=acml} is used.
+@item -mloop
+@opindex mloop
+Enables the use of the e3v5 LOOP instruction. The use of this
+instruction is not enabled by default when the e3v5 architecture is
+selected because its use is still experimental.
-@item -mabi=@var{name}
-@opindex mabi
-Generate code for the specified calling convention. Permissible values
-are @samp{sysv} for the ABI used on GNU/Linux and other systems, and
-@samp{ms} for the Microsoft ABI. The default is to use the Microsoft
-ABI when targeting Microsoft Windows and the SysV ABI on all other systems.
-You can control this behavior for specific functions by
-using the function attributes @code{ms_abi} and @code{sysv_abi}.
-@xref{Function Attributes}.
+@item -mrh850-abi
+@itemx -mghs
+@opindex mrh850-abi
+@opindex mghs
+Enables support for the RH850 version of the V850 ABI. This is the
+default. With this version of the ABI the following rules apply:
-@item -mtls-dialect=@var{type}
-@opindex mtls-dialect
-Generate code to access thread-local storage using the @samp{gnu} or
-@samp{gnu2} conventions. @samp{gnu} is the conservative default;
-@samp{gnu2} is more efficient, but it may add compile- and run-time
-requirements that cannot be satisfied on all systems.
+@itemize
+@item
+Integer sized structures and unions are returned via a memory pointer
+rather than a register.
-@item -mpush-args
-@itemx -mno-push-args
-@opindex mpush-args
-@opindex mno-push-args
-Use PUSH operations to store outgoing parameters. This method is shorter
-and usually equally fast as method using SUB/MOV operations and is enabled
-by default. In some cases disabling it may improve performance because of
-improved scheduling and reduced dependencies.
+@item
+Large structures and unions (more than 8 bytes in size) are passed by
+value.
-@item -maccumulate-outgoing-args
-@opindex maccumulate-outgoing-args
-If enabled, the maximum amount of space required for outgoing arguments is
-computed in the function prologue. This is faster on most modern CPUs
-because of reduced dependencies, improved scheduling and reduced stack usage
-when the preferred stack boundary is not equal to 2. The drawback is a notable
-increase in code size. This switch implies @option{-mno-push-args}.
+@item
+Functions are aligned to 16-bit boundaries.
-@item -mthreads
-@opindex mthreads
-Support thread-safe exception handling on MinGW. Programs that rely
-on thread-safe exception handling must compile and link all code with the
-@option{-mthreads} option. When compiling, @option{-mthreads} defines
-@option{-D_MT}; when linking, it links in a special thread helper library
-@option{-lmingwthrd} which cleans up per-thread exception-handling data.
+@item
+The @option{-m8byte-align} command-line option is supported.
-@item -mms-bitfields
-@itemx -mno-ms-bitfields
-@opindex mms-bitfields
-@opindex mno-ms-bitfields
+@item
+The @option{-mdisable-callt} command-line option is enabled by
+default. The @option{-mno-disable-callt} command-line option is not
+supported.
+@end itemize
-Enable/disable bit-field layout compatible with the native Microsoft
-Windows compiler.
+When this version of the ABI is enabled the C preprocessor symbol
+@code{__V850_RH850_ABI__} is defined.
-If @code{packed} is used on a structure, or if bit-fields are used,
-it may be that the Microsoft ABI lays out the structure differently
-than the way GCC normally does. Particularly when moving packed
-data between functions compiled with GCC and the native Microsoft compiler
-(either via function call or as data in a file), it may be necessary to access
-either format.
+@item -mgcc-abi
+@opindex mgcc-abi
+Enables support for the old GCC version of the V850 ABI. With this
+version of the ABI the following rules apply:
-This option is enabled by default for Microsoft Windows
-targets. This behavior can also be controlled locally by use of variable
-or type attributes. For more information, see @ref{x86 Variable Attributes}
-and @ref{x86 Type Attributes}.
+@itemize
+@item
+Integer sized structures and unions are returned in register @code{r10}.
-The Microsoft structure layout algorithm is fairly simple with the exception
-of the bit-field packing.
-The padding and alignment of members of structures and whether a bit-field
-can straddle a storage-unit boundary are determine by these rules:
+@item
+Large structures and unions (more than 8 bytes in size) are passed by
+reference.
-@enumerate
-@item Structure members are stored sequentially in the order in which they are
-declared: the first member has the lowest memory address and the last member
-the highest.
+@item
+Functions are aligned to 32-bit boundaries, unless optimizing for
+size.
-@item Every data object has an alignment requirement. The alignment requirement
-for all data except structures, unions, and arrays is either the size of the
-object or the current packing size (specified with either the
-@code{aligned} attribute or the @code{pack} pragma),
-whichever is less. For structures, unions, and arrays,
-the alignment requirement is the largest alignment requirement of its members.
-Every object is allocated an offset so that:
+@item
+The @option{-m8byte-align} command-line option is not supported.
-@smallexample
-offset % alignment_requirement == 0
-@end smallexample
+@item
+The @option{-mdisable-callt} command-line option is supported but not
+enabled by default.
+@end itemize
-@item Adjacent bit-fields are packed into the same 1-, 2-, or 4-byte allocation
-unit if the integral types are the same size and if the next bit-field fits
-into the current allocation unit without crossing the boundary imposed by the
-common alignment requirements of the bit-fields.
-@end enumerate
+When this version of the ABI is enabled the C preprocessor symbol
+@code{__V850_GCC_ABI__} is defined.
-MSVC interprets zero-length bit-fields in the following ways:
+@item -m8byte-align
+@itemx -mno-8byte-align
+@opindex m8byte-align
+@opindex mno-8byte-align
+Enables support for @code{double} and @code{long long} types to be
+aligned on 8-byte boundaries. The default is to restrict the
+alignment of all objects to at most 4-bytes. When
+@option{-m8byte-align} is in effect the C preprocessor symbol
+@code{__V850_8BYTE_ALIGN__} is defined.
-@enumerate
-@item If a zero-length bit-field is inserted between two bit-fields that
-are normally coalesced, the bit-fields are not coalesced.
+@item -mbig-switch
+@opindex mbig-switch
+Generate code suitable for big switch tables. Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
-For example:
+@item -mapp-regs
+@opindex mapp-regs
+This option causes r2 and r5 to be used in the code generated by
+the compiler. This setting is the default.
-@smallexample
-struct
- @{
- unsigned long bf_1 : 12;
- unsigned long : 0;
- unsigned long bf_2 : 12;
- @} t1;
-@end smallexample
+@item -mno-app-regs
+@opindex mno-app-regs
+This option causes r2 and r5 to be treated as fixed registers.
-@noindent
-The size of @code{t1} is 8 bytes with the zero-length bit-field. If the
-zero-length bit-field were removed, @code{t1}'s size would be 4 bytes.
+@end table
-@item If a zero-length bit-field is inserted after a bit-field, @code{foo}, and the
-alignment of the zero-length bit-field is greater than the member that follows it,
-@code{bar}, @code{bar} is aligned as the type of the zero-length bit-field.
+@node VAX Options
+@subsection VAX Options
+@cindex VAX options
-For example:
+These @samp{-m} options are defined for the VAX:
-@smallexample
-struct
- @{
- char foo : 4;
- short : 0;
- char bar;
- @} t2;
+@table @gcctabopt
+@item -munix
+@opindex munix
+Do not output certain jump instructions (@code{aobleq} and so on)
+that the Unix assembler for the VAX cannot handle across long
+ranges.
-struct
- @{
- char foo : 4;
- short : 0;
- double bar;
- @} t3;
-@end smallexample
+@item -mgnu
+@opindex mgnu
+Do output those jump instructions, on the assumption that the
+GNU assembler is being used.
-@noindent
-For @code{t2}, @code{bar} is placed at offset 2, rather than offset 1.
-Accordingly, the size of @code{t2} is 4. For @code{t3}, the zero-length
-bit-field does not affect the alignment of @code{bar} or, as a result, the size
-of the structure.
+@item -mg
+@opindex mg
+Output code for G-format floating-point numbers instead of D-format.
+@end table
-Taking this into account, it is important to note the following:
+@node Visium Options
+@subsection Visium Options
+@cindex Visium options
-@enumerate
-@item If a zero-length bit-field follows a normal bit-field, the type of the
-zero-length bit-field may affect the alignment of the structure as whole. For
-example, @code{t2} has a size of 4 bytes, since the zero-length bit-field follows a
-normal bit-field, and is of type short.
-
-@item Even if a zero-length bit-field is not followed by a normal bit-field, it may
-still affect the alignment of the structure:
-
-@smallexample
-struct
- @{
- char foo : 6;
- long : 0;
- @} t4;
-@end smallexample
+@table @gcctabopt
-@noindent
-Here, @code{t4} takes up 4 bytes.
-@end enumerate
+@item -mdebug
+@opindex mdebug
+A program which performs file I/O and is destined to run on an MCM target
+should be linked with this option. It causes the libraries libc.a and
+libdebug.a to be linked. The program should be run on the target under
+the control of the GDB remote debugging stub.
-@item Zero-length bit-fields following non-bit-field members are ignored:
+@item -msim
+@opindex msim
+A program which performs file I/O and is destined to run on the simulator
+should be linked with option. This causes libraries libc.a and libsim.a to
+be linked.
-@smallexample
-struct
- @{
- char foo;
- long : 0;
- char bar;
- @} t5;
-@end smallexample
+@item -mfpu
+@itemx -mhard-float
+@opindex mfpu
+@opindex mhard-float
+Generate code containing floating-point instructions. This is the
+default.
-@noindent
-Here, @code{t5} takes up 2 bytes.
-@end enumerate
+@item -mno-fpu
+@itemx -msoft-float
+@opindex mno-fpu
+@opindex msoft-float
+Generate code containing library calls for floating-point.
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-@item -mno-align-stringops
-@opindex mno-align-stringops
-Do not align the destination of inlined string operations. This switch reduces
-code size and improves performance in case the destination is already aligned,
-but GCC doesn't know about it.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
+@samp{mcm}, @samp{gr5} and @samp{gr6}.
-@item -minline-all-stringops
-@opindex minline-all-stringops
-By default GCC inlines string operations only when the destination is
-known to be aligned to least a 4-byte boundary.
-This enables more inlining and increases code
-size, but may improve performance of code that depends on fast
-@code{memcpy}, @code{strlen},
-and @code{memset} for short lengths.
+@samp{mcm} is a synonym of @samp{gr5} present for backward compatibility.
-@item -minline-stringops-dynamically
-@opindex minline-stringops-dynamically
-For string operations of unknown size, use run-time checks with
-inline code for small blocks and a library call for large blocks.
+By default (unless configured otherwise), GCC generates code for the GR5
+variant of the Visium architecture.
-@item -mstringop-strategy=@var{alg}
-@opindex mstringop-strategy=@var{alg}
-Override the internal decision heuristic for the particular algorithm to use
-for inlining string operations. The allowed values for @var{alg} are:
+With @option{-mcpu=gr6}, GCC generates code for the GR6 variant of the Visium
+architecture. The only difference from GR5 code is that the compiler will
+generate block move instructions.
-@table @samp
-@item rep_byte
-@itemx rep_4byte
-@itemx rep_8byte
-Expand using i386 @code{rep} prefix of the specified size.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type @var{cpu_type},
+but do not set the instruction set or register set that the option
+@option{-mcpu=@var{cpu_type}} would.
-@item byte_loop
-@itemx loop
-@itemx unrolled_loop
-Expand into an inline loop.
+@item -msv-mode
+@opindex msv-mode
+Generate code for the supervisor mode, where there are no restrictions on
+the access to general registers. This is the default.
-@item libcall
-Always use a library call.
+@item -muser-mode
+@opindex muser-mode
+Generate code for the user mode, where the access to some general registers
+is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this
+mode; on the GR6, only registers r29 to r31 are affected.
@end table
-@item -mmemcpy-strategy=@var{strategy}
-@opindex mmemcpy-strategy=@var{strategy}
-Override the internal decision heuristic to decide if @code{__builtin_memcpy}
-should be inlined and what inline algorithm to use when the expected size
-of the copy operation is known. @var{strategy}
-is a comma-separated list of @var{alg}:@var{max_size}:@var{dest_align} triplets.
-@var{alg} is specified in @option{-mstringop-strategy}, @var{max_size} specifies
-the max byte size with which inline algorithm @var{alg} is allowed. For the last
-triplet, the @var{max_size} must be @code{-1}. The @var{max_size} of the triplets
-in the list must be specified in increasing order. The minimal byte size for
-@var{alg} is @code{0} for the first triplet and @code{@var{max_size} + 1} of the
-preceding range.
+@node VMS Options
+@subsection VMS Options
-@item -mmemset-strategy=@var{strategy}
-@opindex mmemset-strategy=@var{strategy}
-The option is similar to @option{-mmemcpy-strategy=} except that it is to control
-@code{__builtin_memset} expansion.
+These @samp{-m} options are defined for the VMS implementations:
-@item -momit-leaf-frame-pointer
-@opindex momit-leaf-frame-pointer
-Don't keep the frame pointer in a register for leaf functions. This
-avoids the instructions to save, set up, and restore frame pointers and
-makes an extra register available in leaf functions. The option
-@option{-fomit-leaf-frame-pointer} removes the frame pointer for leaf functions,
-which might make debugging harder.
+@table @gcctabopt
+@item -mvms-return-codes
+@opindex mvms-return-codes
+Return VMS condition codes from @code{main}. The default is to return POSIX-style
+condition (e.g.@ error) codes.
-@item -mtls-direct-seg-refs
-@itemx -mno-tls-direct-seg-refs
-@opindex mtls-direct-seg-refs
-Controls whether TLS variables may be accessed with offsets from the
-TLS segment register (@code{%gs} for 32-bit, @code{%fs} for 64-bit),
-or whether the thread base pointer must be added. Whether or not this
-is valid depends on the operating system, and whether it maps the
-segment to cover the entire TLS area.
+@item -mdebug-main=@var{prefix}
+@opindex mdebug-main=@var{prefix}
+Flag the first routine whose name starts with @var{prefix} as the main
+routine for the debugger.
-For systems that use the GNU C Library, the default is on.
+@item -mmalloc64
+@opindex mmalloc64
+Default to 64-bit memory allocation routines.
-@item -msse2avx
-@itemx -mno-sse2avx
-@opindex msse2avx
-Specify that the assembler should encode SSE instructions with VEX
-prefix. The option @option{-mavx} turns this on by default.
+@item -mpointer-size=@var{size}
+@opindex mpointer-size=@var{size}
+Set the default size of pointers. Possible options for @var{size} are
+@samp{32} or @samp{short} for 32 bit pointers, @samp{64} or @samp{long}
+for 64 bit pointers, and @samp{no} for supporting only 32 bit pointers.
+The later option disables @code{pragma pointer_size}.
+@end table
-@item -mfentry
-@itemx -mno-fentry
-@opindex mfentry
-If profiling is active (@option{-pg}), put the profiling
-counter call before the prologue.
-Note: On x86 architectures the attribute @code{ms_hook_prologue}
-isn't possible at the moment for @option{-mfentry} and @option{-pg}.
+@node VxWorks Options
+@subsection VxWorks Options
+@cindex VxWorks Options
-@item -mrecord-mcount
-@itemx -mno-record-mcount
-@opindex mrecord-mcount
-If profiling is active (@option{-pg}), generate a __mcount_loc section
-that contains pointers to each profiling call. This is useful for
-automatically patching and out calls.
+The options in this section are defined for all VxWorks targets.
+Options specific to the target hardware are listed with the other
+options for that target.
-@item -mnop-mcount
-@itemx -mno-nop-mcount
-@opindex mnop-mcount
-If profiling is active (@option{-pg}), generate the calls to
-the profiling functions as nops. This is useful when they
-should be patched in later dynamically. This is likely only
-useful together with @option{-mrecord-mcount}.
+@table @gcctabopt
+@item -mrtp
+@opindex mrtp
+GCC can generate code for both VxWorks kernels and real time processes
+(RTPs). This option switches from the former to the latter. It also
+defines the preprocessor macro @code{__RTP__}.
-@item -mskip-rax-setup
-@itemx -mno-skip-rax-setup
-@opindex mskip-rax-setup
-When generating code for the x86-64 architecture with SSE extensions
-disabled, @option{-skip-rax-setup} can be used to skip setting up RAX
-register when there are no variable arguments passed in vector registers.
+@item -non-static
+@opindex non-static
+Link an RTP executable against shared libraries rather than static
+libraries. The options @option{-static} and @option{-shared} can
+also be used for RTPs (@pxref{Link Options}); @option{-static}
+is the default.
-@strong{Warning:} Since RAX register is used to avoid unnecessarily
-saving vector registers on stack when passing variable arguments, the
-impacts of this option are callees may waste some stack space,
-misbehave or jump to a random location. GCC 4.4 or newer don't have
-those issues, regardless the RAX register value.
+@item -Bstatic
+@itemx -Bdynamic
+@opindex Bstatic
+@opindex Bdynamic
+These options are passed down to the linker. They are defined for
+compatibility with Diab.
-@item -m8bit-idiv
-@itemx -mno-8bit-idiv
-@opindex m8bit-idiv
-On some processors, like Intel Atom, 8-bit unsigned integer divide is
-much faster than 32-bit/64-bit integer divide. This option generates a
-run-time check. If both dividend and divisor are within range of 0
-to 255, 8-bit unsigned integer divide is used instead of
-32-bit/64-bit integer divide.
+@item -Xbind-lazy
+@opindex Xbind-lazy
+Enable lazy binding of function calls. This option is equivalent to
+@option{-Wl,-z,now} and is defined for compatibility with Diab.
-@item -mavx256-split-unaligned-load
-@itemx -mavx256-split-unaligned-store
-@opindex mavx256-split-unaligned-load
-@opindex mavx256-split-unaligned-store
-Split 32-byte AVX unaligned load and store.
+@item -Xbind-now
+@opindex Xbind-now
+Disable lazy binding of function calls. This option is the default and
+is defined for compatibility with Diab.
+@end table
-@item -mstack-protector-guard=@var{guard}
-@opindex mstack-protector-guard=@var{guard}
-Generate stack protection code using canary at @var{guard}. Supported
-locations are @samp{global} for global canary or @samp{tls} for per-thread
-canary in the TLS block (the default). This option has effect only when
-@option{-fstack-protector} or @option{-fstack-protector-all} is specified.
+@node x86 Options
+@subsection x86 Options
+@cindex x86 Options
-@item -mmitigate-rop
-@opindex mmitigate-rop
-Try to avoid generating code sequences that contain unintended return
-opcodes, to mitigate against certain forms of attack. At the moment,
-this option is limited in what it can do and should not be relied
-on to provide serious protection.
-
-@end table
-
-These @samp{-m} switches are supported in addition to the above
-on x86-64 processors in 64-bit environments.
+These @samp{-m} options are defined for the x86 family of computers.
@table @gcctabopt
-@item -m32
-@itemx -m64
-@itemx -mx32
-@itemx -m16
-@itemx -miamcu
-@opindex m32
-@opindex m64
-@opindex mx32
-@opindex m16
-@opindex miamcu
-Generate code for a 16-bit, 32-bit or 64-bit environment.
-The @option{-m32} option sets @code{int}, @code{long}, and pointer types
-to 32 bits, and
-generates code that runs on any i386 system.
-The @option{-m64} option sets @code{int} to 32 bits and @code{long} and pointer
-types to 64 bits, and generates code for the x86-64 architecture.
-For Darwin only the @option{-m64} option also turns off the @option{-fno-pic}
-and @option{-mdynamic-no-pic} options.
+@item -march=@var{cpu-type}
+@opindex march
+Generate instructions for the machine type @var{cpu-type}. In contrast to
+@option{-mtune=@var{cpu-type}}, which merely tunes the generated code
+for the specified @var{cpu-type}, @option{-march=@var{cpu-type}} allows GCC
+to generate code that may not run at all on processors other than the one
+indicated. Specifying @option{-march=@var{cpu-type}} implies
+@option{-mtune=@var{cpu-type}}.
-The @option{-mx32} option sets @code{int}, @code{long}, and pointer types
-to 32 bits, and
-generates code for the x86-64 architecture.
+The choices for @var{cpu-type} are:
-The @option{-m16} option is the same as @option{-m32}, except for that
-it outputs the @code{.code16gcc} assembly directive at the beginning of
-the assembly output so that the binary can run in 16-bit mode.
+@table @samp
+@item native
+This selects the CPU to generate code for at compilation time by determining
+the processor type of the compiling machine. Using @option{-march=native}
+enables all instruction subsets supported by the local machine (hence
+the result might not run on different machines). Using @option{-mtune=native}
+produces code optimized for the local machine under the constraints
+of the selected instruction set.
-The @option{-miamcu} option generates code which conforms to Intel MCU
-psABI. It requires the @option{-m32} option to be turned on.
+@item i386
+Original Intel i386 CPU@.
-@item -mno-red-zone
-@opindex mno-red-zone
-Do not use a so-called ``red zone'' for x86-64 code. The red zone is mandated
-by the x86-64 ABI; it is a 128-byte area beyond the location of the
-stack pointer that is not modified by signal or interrupt handlers
-and therefore can be used for temporary data without adjusting the stack
-pointer. The flag @option{-mno-red-zone} disables this red zone.
+@item i486
+Intel i486 CPU@. (No scheduling is implemented for this chip.)
-@item -mcmodel=small
-@opindex mcmodel=small
-Generate code for the small code model: the program and its symbols must
-be linked in the lower 2 GB of the address space. Pointers are 64 bits.
-Programs can be statically or dynamically linked. This is the default
-code model.
+@item i586
+@itemx pentium
+Intel Pentium CPU with no MMX support.
-@item -mcmodel=kernel
-@opindex mcmodel=kernel
-Generate code for the kernel code model. The kernel runs in the
-negative 2 GB of the address space.
-This model has to be used for Linux kernel code.
+@item lakemont
+Intel Lakemont MCU, based on Intel Pentium CPU.
-@item -mcmodel=medium
-@opindex mcmodel=medium
-Generate code for the medium model: the program is linked in the lower 2
-GB of the address space. Small symbols are also placed there. Symbols
-with sizes larger than @option{-mlarge-data-threshold} are put into
-large data or BSS sections and can be located above 2GB. Programs can
-be statically or dynamically linked.
+@item pentium-mmx
+Intel Pentium MMX CPU, based on Pentium core with MMX instruction set support.
-@item -mcmodel=large
-@opindex mcmodel=large
-Generate code for the large model. This model makes no assumptions
-about addresses and sizes of sections.
+@item pentiumpro
+Intel Pentium Pro CPU@.
-@item -maddress-mode=long
-@opindex maddress-mode=long
-Generate code for long address mode. This is only supported for 64-bit
-and x32 environments. It is the default address mode for 64-bit
-environments.
+@item i686
+When used with @option{-march}, the Pentium Pro
+instruction set is used, so the code runs on all i686 family chips.
+When used with @option{-mtune}, it has the same meaning as @samp{generic}.
-@item -maddress-mode=short
-@opindex maddress-mode=short
-Generate code for short address mode. This is only supported for 32-bit
-and x32 environments. It is the default address mode for 32-bit and
-x32 environments.
-@end table
+@item pentium2
+Intel Pentium II CPU, based on Pentium Pro core with MMX instruction set
+support.
-@node x86 Windows Options
-@subsection x86 Windows Options
-@cindex x86 Windows Options
-@cindex Windows Options for x86
+@item pentium3
+@itemx pentium3m
+Intel Pentium III CPU, based on Pentium Pro core with MMX and SSE instruction
+set support.
-These additional options are available for Microsoft Windows targets:
+@item pentium-m
+Intel Pentium M; low-power version of Intel Pentium III CPU
+with MMX, SSE and SSE2 instruction set support. Used by Centrino notebooks.
-@table @gcctabopt
-@item -mconsole
-@opindex mconsole
-This option
-specifies that a console application is to be generated, by
-instructing the linker to set the PE header subsystem type
-required for console applications.
-This option is available for Cygwin and MinGW targets and is
-enabled by default on those targets.
+@item pentium4
+@itemx pentium4m
+Intel Pentium 4 CPU with MMX, SSE and SSE2 instruction set support.
-@item -mdll
-@opindex mdll
-This option is available for Cygwin and MinGW targets. It
-specifies that a DLL---a dynamic link library---is to be
-generated, enabling the selection of the required runtime
-startup object and entry point.
+@item prescott
+Improved version of Intel Pentium 4 CPU with MMX, SSE, SSE2 and SSE3 instruction
+set support.
-@item -mnop-fun-dllimport
-@opindex mnop-fun-dllimport
-This option is available for Cygwin and MinGW targets. It
-specifies that the @code{dllimport} attribute should be ignored.
+@item nocona
+Improved version of Intel Pentium 4 CPU with 64-bit extensions, MMX, SSE,
+SSE2 and SSE3 instruction set support.
-@item -mthread
-@opindex mthread
-This option is available for MinGW targets. It specifies
-that MinGW-specific thread support is to be used.
+@item core2
+Intel Core 2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
+instruction set support.
-@item -municode
-@opindex municode
-This option is available for MinGW-w64 targets. It causes
-the @code{UNICODE} preprocessor macro to be predefined, and
-chooses Unicode-capable runtime startup code.
+@item nehalem
+Intel Nehalem CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2 and POPCNT instruction set support.
-@item -mwin32
-@opindex mwin32
-This option is available for Cygwin and MinGW targets. It
-specifies that the typical Microsoft Windows predefined macros are to
-be set in the pre-processor, but does not influence the choice
-of runtime library/startup code.
+@item westmere
+Intel Westmere CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AES and PCLMUL instruction set support.
-@item -mwindows
-@opindex mwindows
-This option is available for Cygwin and MinGW targets. It
-specifies that a GUI application is to be generated by
-instructing the linker to set the PE header subsystem type
-appropriately.
+@item sandybridge
+Intel Sandy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AES and PCLMUL instruction set support.
-@item -fno-set-stack-executable
-@opindex fno-set-stack-executable
-This option is available for MinGW targets. It specifies that
-the executable flag for the stack used by nested functions isn't
-set. This is necessary for binaries running in kernel mode of
-Microsoft Windows, as there the User32 API, which is used to set executable
-privileges, isn't available.
+@item ivybridge
+Intel Ivy Bridge CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C
+instruction set support.
-@item -fwritable-relocated-rdata
-@opindex fno-writable-relocated-rdata
-This option is available for MinGW and Cygwin targets. It specifies
-that relocated-data in read-only section is put into .data
-section. This is a necessary for older runtimes not supporting
-modification of .rdata sections for pseudo-relocation.
+@item haswell
+Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2 and F16C instruction set support.
-@item -mpe-aligned-commons
-@opindex mpe-aligned-commons
-This option is available for Cygwin and MinGW targets. It
-specifies that the GNU extension to the PE file format that
-permits the correct alignment of COMMON variables should be
-used when generating code. It is enabled by default if
-GCC detects that the target assembler found during configuration
-supports the feature.
-@end table
+@item broadwell
+Intel Broadwell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX and PREFETCHW instruction set support.
-See also under @ref{x86 Options} for standard options.
+@item skylake
+Intel Skylake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC and
+XSAVES instruction set support.
-@node Xstormy16 Options
-@subsection Xstormy16 Options
-@cindex Xstormy16 Options
+@item bonnell
+Intel Bonnell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3 and SSSE3
+instruction set support.
-These options are defined for Xstormy16:
+@item silvermont
+Intel Silvermont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
+SSE4.1, SSE4.2, POPCNT, AES, PCLMUL and RDRND instruction set support.
-@table @gcctabopt
-@item -msim
-@opindex msim
-Choose startup files and linker script suitable for the simulator.
-@end table
+@item knl
+Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, AVX512F, AVX512PF, AVX512ER and
+AVX512CD instruction set support.
-@node Xtensa Options
-@subsection Xtensa Options
-@cindex Xtensa Options
+@item skylake-avx512
+Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
+BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
+AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
-These options are supported for Xtensa targets:
+@item k6
+AMD K6 CPU with MMX instruction set support.
-@table @gcctabopt
-@item -mconst16
-@itemx -mno-const16
-@opindex mconst16
-@opindex mno-const16
-Enable or disable use of @code{CONST16} instructions for loading
-constant values. The @code{CONST16} instruction is currently not a
-standard option from Tensilica. When enabled, @code{CONST16}
-instructions are always used in place of the standard @code{L32R}
-instructions. The use of @code{CONST16} is enabled by default only if
-the @code{L32R} instruction is not available.
+@item k6-2
+@itemx k6-3
+Improved versions of AMD K6 CPU with MMX and 3DNow!@: instruction set support.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Enable or disable use of fused multiply/add and multiply/subtract
-instructions in the floating-point option. This has no effect if the
-floating-point option is not also enabled. Disabling fused multiply/add
-and multiply/subtract instructions forces the compiler to use separate
-instructions for the multiply and add/subtract operations. This may be
-desirable in some cases where strict IEEE 754-compliant results are
-required: the fused multiply add/subtract instructions do not round the
-intermediate result, thereby producing results with @emph{more} bits of
-precision than specified by the IEEE standard. Disabling fused multiply
-add/subtract instructions also ensures that the program output is not
-sensitive to the compiler's ability to combine multiply and add/subtract
-operations.
+@item athlon
+@itemx athlon-tbird
+AMD Athlon CPU with MMX, 3dNOW!, enhanced 3DNow!@: and SSE prefetch instructions
+support.
-@item -mserialize-volatile
-@itemx -mno-serialize-volatile
-@opindex mserialize-volatile
-@opindex mno-serialize-volatile
-When this option is enabled, GCC inserts @code{MEMW} instructions before
-@code{volatile} memory references to guarantee sequential consistency.
-The default is @option{-mserialize-volatile}. Use
-@option{-mno-serialize-volatile} to omit the @code{MEMW} instructions.
+@item athlon-4
+@itemx athlon-xp
+@itemx athlon-mp
+Improved AMD Athlon CPU with MMX, 3DNow!, enhanced 3DNow!@: and full SSE
+instruction set support.
-@item -mforce-no-pic
-@opindex mforce-no-pic
-For targets, like GNU/Linux, where all user-mode Xtensa code must be
-position-independent code (PIC), this option disables PIC for compiling
-kernel code.
+@item k8
+@itemx opteron
+@itemx athlon64
+@itemx athlon-fx
+Processors based on the AMD K8 core with x86-64 instruction set support,
+including the AMD Opteron, Athlon 64, and Athlon 64 FX processors.
+(This supersets MMX, SSE, SSE2, 3DNow!, enhanced 3DNow!@: and 64-bit
+instruction set extensions.)
-@item -mtext-section-literals
-@itemx -mno-text-section-literals
-@opindex mtext-section-literals
-@opindex mno-text-section-literals
-These options control the treatment of literal pools. The default is
-@option{-mno-text-section-literals}, which places literals in a separate
-section in the output file. This allows the literal pool to be placed
-in a data RAM/ROM, and it also allows the linker to combine literal
-pools from separate object files to remove redundant literals and
-improve code size. With @option{-mtext-section-literals}, the literals
-are interspersed in the text section in order to keep them as close as
-possible to their references. This may be necessary for large assembly
-files. Literals for each function are placed right before that function.
+@item k8-sse3
+@itemx opteron-sse3
+@itemx athlon64-sse3
+Improved versions of AMD K8 cores with SSE3 instruction set support.
-@item -mauto-litpools
-@itemx -mno-auto-litpools
-@opindex mauto-litpools
-@opindex mno-auto-litpools
-These options control the treatment of literal pools. The default is
-@option{-mno-auto-litpools}, which places literals in a separate
-section in the output file unless @option{-mtext-section-literals} is
-used. With @option{-mauto-litpools} the literals are interspersed in
-the text section by the assembler. Compiler does not produce explicit
-@code{.literal} directives and loads literals into registers with
-@code{MOVI} instructions instead of @code{L32R} to let the assembler
-do relaxation and place literals as necessary. This option allows
-assembler to create several literal pools per function and assemble
-very big functions, which may not be possible with
-@option{-mtext-section-literals}.
+@item amdfam10
+@itemx barcelona
+CPUs based on AMD Family 10h cores with x86-64 instruction set support. (This
+supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
+instruction set extensions.)
-@item -mtarget-align
-@itemx -mno-target-align
-@opindex mtarget-align
-@opindex mno-target-align
-When this option is enabled, GCC instructs the assembler to
-automatically align instructions to reduce branch penalties at the
-expense of some code density. The assembler attempts to widen density
-instructions to align branch targets and the instructions following call
-instructions. If there are not enough preceding safe density
-instructions to align a target, no widening is performed. The
-default is @option{-mtarget-align}. These options do not affect the
-treatment of auto-aligned instructions like @code{LOOP}, which the
-assembler always aligns, either by widening density instructions or
-by inserting NOP instructions.
+@item bdver1
+CPUs based on AMD Family 15h cores with x86-64 instruction set support. (This
+supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
+SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.)
+@item bdver2
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, TBM, F16C, FMA, FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX,
+SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set
+extensions.)
+@item bdver3
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, XOP, LWP, AES,
+PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and
+64-bit instruction set extensions.
+@item bdver4
+AMD Family 15h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, BMI2, TBM, F16C, FMA, FMA4, FSGSBASE, AVX, AVX2, XOP, LWP,
+AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1,
+SSE4.2, ABM and 64-bit instruction set extensions.
-@item -mlongcalls
-@itemx -mno-longcalls
-@opindex mlongcalls
-@opindex mno-longcalls
-When this option is enabled, GCC instructs the assembler to translate
-direct calls to indirect calls unless it can determine that the target
-of a direct call is in the range allowed by the call instruction. This
-translation typically occurs for calls to functions in other source
-files. Specifically, the assembler translates a direct @code{CALL}
-instruction into an @code{L32R} followed by a @code{CALLX} instruction.
-The default is @option{-mno-longcalls}. This option should be used in
-programs where the call target can potentially be out of range. This
-option is implemented in the assembler, not the compiler, so the
-assembly code generated by GCC still shows direct call
-instructions---look at the disassembled object code to see the actual
-instructions. Note that the assembler uses an indirect call for
-every cross-file call, not just those that really are out of range.
+@item znver1
+AMD Family 17h core based CPUs with x86-64 instruction set support. (This
+supersets BMI, BMI2, F16C, FMA, FSGSBASE, AVX, AVX2, ADCX, RDSEED, MWAITX,
+SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3,
+SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
+instruction set extensions.
+
+@item btver1
+CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
+supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
+instruction set extensions.)
+
+@item btver2
+CPUs based on AMD Family 16h cores with x86-64 instruction set support. This
+includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM,
+SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
+
+@item winchip-c6
+IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction
+set support.
+
+@item winchip2
+IDT WinChip 2 CPU, dealt in same way as i486 with additional MMX and 3DNow!@:
+instruction set support.
+
+@item c3
+VIA C3 CPU with MMX and 3DNow!@: instruction set support. (No scheduling is
+implemented for this chip.)
+
+@item c3-2
+VIA C3-2 (Nehemiah/C5XL) CPU with MMX and SSE instruction set support.
+(No scheduling is
+implemented for this chip.)
+
+@item geode
+AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
+@end table
+
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune to @var{cpu-type} everything applicable about the generated code, except
+for the ABI and the set of available instructions.
+While picking a specific @var{cpu-type} schedules things appropriately
+for that particular chip, the compiler does not generate any code that
+cannot run on the default machine type unless you use a
+@option{-march=@var{cpu-type}} option.
+For example, if GCC is configured for i686-pc-linux-gnu
+then @option{-mtune=pentium4} generates code that is tuned for Pentium 4
+but still runs on i686 machines.
+
+The choices for @var{cpu-type} are the same as for @option{-march}.
+In addition, @option{-mtune} supports 2 extra choices for @var{cpu-type}:
+
+@table @samp
+@item generic
+Produce code optimized for the most common IA32/@/AMD64/@/EM64T processors.
+If you know the CPU on which your code will run, then you should use
+the corresponding @option{-mtune} or @option{-march} option instead of
+@option{-mtune=generic}. But, if you do not know exactly what CPU users
+of your application will have, then you should use this option.
+
+As new processors are deployed in the marketplace, the behavior of this
+option will change. Therefore, if you upgrade to a newer version of
+GCC, code generation controlled by this option will change to reflect
+the processors
+that are most common at the time that version of GCC is released.
+
+There is no @option{-march=generic} option because @option{-march}
+indicates the instruction set the compiler can use, and there is no
+generic instruction set applicable to all processors. In contrast,
+@option{-mtune} indicates the processor (or, in this case, collection of
+processors) for which the code is optimized.
+
+@item intel
+Produce code optimized for the most current Intel processors, which are
+Haswell and Silvermont for this version of GCC. If you know the CPU
+on which your code will run, then you should use the corresponding
+@option{-mtune} or @option{-march} option instead of @option{-mtune=intel}.
+But, if you want your application performs better on both Haswell and
+Silvermont, then you should use this option.
+
+As new Intel processors are deployed in the marketplace, the behavior of
+this option will change. Therefore, if you upgrade to a newer version of
+GCC, code generation controlled by this option will change to reflect
+the most current Intel processors at the time that version of GCC is
+released.
+
+There is no @option{-march=intel} option because @option{-march} indicates
+the instruction set the compiler can use, and there is no common
+instruction set applicable to all processors. In contrast,
+@option{-mtune} indicates the processor (or, in this case, collection of
+processors) for which the code is optimized.
@end table
-@node zSeries Options
-@subsection zSeries Options
-@cindex zSeries options
+@item -mcpu=@var{cpu-type}
+@opindex mcpu
+A deprecated synonym for @option{-mtune}.
+
+@item -mfpmath=@var{unit}
+@opindex mfpmath
+Generate floating-point arithmetic for selected unit @var{unit}. The choices
+for @var{unit} are:
+
+@table @samp
+@item 387
+Use the standard 387 floating-point coprocessor present on the majority of chips and
+emulated otherwise. Code compiled with this option runs almost everywhere.
+The temporary results are computed in 80-bit precision instead of the precision
+specified by the type, resulting in slightly different results compared to most
+of other chips. See @option{-ffloat-store} for more detailed description.
+
+This is the default choice for x86-32 targets.
+
+@item sse
+Use scalar floating-point instructions present in the SSE instruction set.
+This instruction set is supported by Pentium III and newer chips,
+and in the AMD line
+by Athlon-4, Athlon XP and Athlon MP chips. The earlier version of the SSE
+instruction set supports only single-precision arithmetic, thus the double and
+extended-precision arithmetic are still done using 387. A later version, present
+only in Pentium 4 and AMD x86-64 chips, supports double-precision
+arithmetic too.
+
+For the x86-32 compiler, you must use @option{-march=@var{cpu-type}}, @option{-msse}
+or @option{-msse2} switches to enable SSE extensions and make this option
+effective. For the x86-64 compiler, these extensions are enabled by default.
+
+The resulting code should be considerably faster in the majority of cases and avoid
+the numerical instability problems of 387 code, but may break some existing
+code that expects temporaries to be 80 bits.
+
+This is the default choice for the x86-64 compiler.
+
+@item sse,387
+@itemx sse+387
+@itemx both
+Attempt to utilize both instruction sets at once. This effectively doubles the
+amount of available registers, and on chips with separate execution units for
+387 and SSE the execution resources too. Use this option with care, as it is
+still experimental, because the GCC register allocator does not model separate
+functional units well, resulting in unstable performance.
+@end table
+
+@item -masm=@var{dialect}
+@opindex masm=@var{dialect}
+Output assembly instructions using selected @var{dialect}. Also affects
+which dialect is used for basic @code{asm} (@pxref{Basic Asm}) and
+extended @code{asm} (@pxref{Extended Asm}). Supported choices (in dialect
+order) are @samp{att} or @samp{intel}. The default is @samp{att}. Darwin does
+not support @samp{intel}.
+
+@item -mieee-fp
+@itemx -mno-ieee-fp
+@opindex mieee-fp
+@opindex mno-ieee-fp
+Control whether or not the compiler uses IEEE floating-point
+comparisons. These correctly handle the case where the result of a
+comparison is unordered.
+
+@item -msoft-float
+@opindex msoft-float
+Generate output containing library calls for floating point.
+
+@strong{Warning:} the requisite libraries are not part of GCC@.
+Normally the facilities of the machine's usual C compiler are used, but
+this can't be done directly in cross-compilation. You must make your
+own arrangements to provide suitable library functions for
+cross-compilation.
+
+On machines where a function returns floating-point results in the 80387
+register stack, some floating-point opcodes may be emitted even if
+@option{-msoft-float} is used.
+
+@item -mno-fp-ret-in-387
+@opindex mno-fp-ret-in-387
+Do not use the FPU registers for return values of functions.
+
+The usual calling convention has functions return values of types
+@code{float} and @code{double} in an FPU register, even if there
+is no FPU@. The idea is that the operating system should emulate
+an FPU@.
+
+The option @option{-mno-fp-ret-in-387} causes such values to be returned
+in ordinary CPU registers instead.
+
+@item -mno-fancy-math-387
+@opindex mno-fancy-math-387
+Some 387 emulators do not support the @code{sin}, @code{cos} and
+@code{sqrt} instructions for the 387. Specify this option to avoid
+generating those instructions. This option is the default on
+OpenBSD and NetBSD@. This option is overridden when @option{-march}
+indicates that the target CPU always has an FPU and so the
+instruction does not need emulation. These
+instructions are not generated unless you also use the
+@option{-funsafe-math-optimizations} switch.
+
+@item -malign-double
+@itemx -mno-align-double
+@opindex malign-double
+@opindex mno-align-double
+Control whether GCC aligns @code{double}, @code{long double}, and
+@code{long long} variables on a two-word boundary or a one-word
+boundary. Aligning @code{double} variables on a two-word boundary
+produces code that runs somewhat faster on a Pentium at the
+expense of more memory.
+
+On x86-64, @option{-malign-double} is enabled by default.
+
+@strong{Warning:} if you use the @option{-malign-double} switch,
+structures containing the above types are aligned differently than
+the published application binary interface specifications for the x86-32
+and are not binary compatible with structures in code compiled
+without that switch.
+
+@item -m96bit-long-double
+@itemx -m128bit-long-double
+@opindex m96bit-long-double
+@opindex m128bit-long-double
+These switches control the size of @code{long double} type. The x86-32
+application binary interface specifies the size to be 96 bits,
+so @option{-m96bit-long-double} is the default in 32-bit mode.
+
+Modern architectures (Pentium and newer) prefer @code{long double}
+to be aligned to an 8- or 16-byte boundary. In arrays or structures
+conforming to the ABI, this is not possible. So specifying
+@option{-m128bit-long-double} aligns @code{long double}
+to a 16-byte boundary by padding the @code{long double} with an additional
+32-bit zero.
+
+In the x86-64 compiler, @option{-m128bit-long-double} is the default choice as
+its ABI specifies that @code{long double} is aligned on 16-byte boundary.
+
+Notice that neither of these options enable any extra precision over the x87
+standard of 80 bits for a @code{long double}.
+
+@strong{Warning:} if you override the default value for your target ABI, this
+changes the size of
+structures and arrays containing @code{long double} variables,
+as well as modifying the function calling convention for functions taking
+@code{long double}. Hence they are not binary-compatible
+with code compiled without that switch.
+
+@item -mlong-double-64
+@itemx -mlong-double-80
+@itemx -mlong-double-128
+@opindex mlong-double-64
+@opindex mlong-double-80
+@opindex mlong-double-128
+These switches control the size of @code{long double} type. A size
+of 64 bits makes the @code{long double} type equivalent to the @code{double}
+type. This is the default for 32-bit Bionic C library. A size
+of 128 bits makes the @code{long double} type equivalent to the
+@code{__float128} type. This is the default for 64-bit Bionic C library.
+
+@strong{Warning:} if you override the default value for your target ABI, this
+changes the size of
+structures and arrays containing @code{long double} variables,
+as well as modifying the function calling convention for functions taking
+@code{long double}. Hence they are not binary-compatible
+with code compiled without that switch.
+
+@item -malign-data=@var{type}
+@opindex malign-data
+Control how GCC aligns variables. Supported values for @var{type} are
+@samp{compat} uses increased alignment value compatible uses GCC 4.8
+and earlier, @samp{abi} uses alignment value as specified by the
+psABI, and @samp{cacheline} uses increased alignment value to match
+the cache line size. @samp{compat} is the default.
+
+@item -mlarge-data-threshold=@var{threshold}
+@opindex mlarge-data-threshold
+When @option{-mcmodel=medium} is specified, data objects larger than
+@var{threshold} are placed in the large data section. This value must be the
+same across all objects linked into the binary, and defaults to 65535.
+
+@item -mrtd
+@opindex mrtd
+Use a different function-calling convention, in which functions that
+take a fixed number of arguments return with the @code{ret @var{num}}
+instruction, which pops their arguments while returning. This saves one
+instruction in the caller since there is no need to pop the arguments
+there.
+
+You can specify that an individual function is called with this calling
+sequence with the function attribute @code{stdcall}. You can also
+override the @option{-mrtd} option by using the function attribute
+@code{cdecl}. @xref{Function Attributes}.
+
+@strong{Warning:} this calling convention is incompatible with the one
+normally used on Unix, so you cannot use it if you need to call
+libraries compiled with the Unix compiler.
+
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including @code{printf});
+otherwise incorrect code is generated for calls to those
+functions.
+
+In addition, seriously incorrect code results if you call a
+function with too many arguments. (Normally, extra arguments are
+harmlessly ignored.)
+
+@item -mregparm=@var{num}
+@opindex mregparm
+Control how many registers are used to pass integer arguments. By
+default, no registers are used to pass arguments, and at most 3
+registers can be used. You can control this behavior for a specific
+function by using the function attribute @code{regparm}.
+@xref{Function Attributes}.
+
+@strong{Warning:} if you use this switch, and
+@var{num} is nonzero, then you must build all modules with the same
+value, including any libraries. This includes the system libraries and
+startup modules.
+
+@item -msseregparm
+@opindex msseregparm
+Use SSE register passing conventions for float and double arguments
+and return values. You can control this behavior for a specific
+function by using the function attribute @code{sseregparm}.
+@xref{Function Attributes}.
+
+@strong{Warning:} if you use this switch then you must build all
+modules with the same value, including any libraries. This includes
+the system libraries and startup modules.
+
+@item -mvect8-ret-in-mem
+@opindex mvect8-ret-in-mem
+Return 8-byte vectors in memory instead of MMX registers. This is the
+default on Solaris@tie{}8 and 9 and VxWorks to match the ABI of the Sun
+Studio compilers until version 12. Later compiler versions (starting
+with Studio 12 Update@tie{}1) follow the ABI used by other x86 targets, which
+is the default on Solaris@tie{}10 and later. @emph{Only} use this option if
+you need to remain compatible with existing code produced by those
+previous compiler versions or older versions of GCC@.
+
+@item -mpc32
+@itemx -mpc64
+@itemx -mpc80
+@opindex mpc32
+@opindex mpc64
+@opindex mpc80
+
+Set 80387 floating-point precision to 32, 64 or 80 bits. When @option{-mpc32}
+is specified, the significands of results of floating-point operations are
+rounded to 24 bits (single precision); @option{-mpc64} rounds the
+significands of results of floating-point operations to 53 bits (double
+precision) and @option{-mpc80} rounds the significands of results of
+floating-point operations to 64 bits (extended double precision), which is
+the default. When this option is used, floating-point operations in higher
+precisions are not available to the programmer without setting the FPU
+control word explicitly.
+
+Setting the rounding of floating-point operations to less than the default
+80 bits can speed some programs by 2% or more. Note that some mathematical
+libraries assume that extended-precision (80-bit) floating-point operations
+are enabled by default; routines in such libraries could suffer significant
+loss of accuracy, typically through so-called ``catastrophic cancellation'',
+when this option is used to set the precision to less than extended precision.
+
+@item -mstackrealign
+@opindex mstackrealign
+Realign the stack at entry. On the x86, the @option{-mstackrealign}
+option generates an alternate prologue and epilogue that realigns the
+run-time stack if necessary. This supports mixing legacy codes that keep
+4-byte stack alignment with modern codes that keep 16-byte stack alignment for
+SSE compatibility. See also the attribute @code{force_align_arg_pointer},
+applicable to individual functions.
+
+@item -mpreferred-stack-boundary=@var{num}
+@opindex mpreferred-stack-boundary
+Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
+byte boundary. If @option{-mpreferred-stack-boundary} is not specified,
+the default is 4 (16 bytes or 128 bits).
+
+@strong{Warning:} When generating code for the x86-64 architecture with
+SSE extensions disabled, @option{-mpreferred-stack-boundary=3} can be
+used to keep the stack boundary aligned to 8 byte boundary. Since
+x86-64 ABI require 16 byte stack alignment, this is ABI incompatible and
+intended to be used in controlled environment where stack space is
+important limitation. This option leads to wrong code when functions
+compiled with 16 byte stack alignment (such as functions from a standard
+library) are called with misaligned stack. In this case, SSE
+instructions may lead to misaligned memory access traps. In addition,
+variable arguments are handled incorrectly for 16 byte aligned
+objects (including x87 long double and __int128), leading to wrong
+results. You must build all modules with
+@option{-mpreferred-stack-boundary=3}, including any libraries. This
+includes the system libraries and startup modules.
+
+@item -mincoming-stack-boundary=@var{num}
+@opindex mincoming-stack-boundary
+Assume the incoming stack is aligned to a 2 raised to @var{num} byte
+boundary. If @option{-mincoming-stack-boundary} is not specified,
+the one specified by @option{-mpreferred-stack-boundary} is used.
+
+On Pentium and Pentium Pro, @code{double} and @code{long double} values
+should be aligned to an 8-byte boundary (see @option{-malign-double}) or
+suffer significant run time performance penalties. On Pentium III, the
+Streaming SIMD Extension (SSE) data type @code{__m128} may not work
+properly if it is not 16-byte aligned.
+
+To ensure proper alignment of this values on the stack, the stack boundary
+must be as aligned as that required by any value stored on the stack.
+Further, every function must be generated such that it keeps the stack
+aligned. Thus calling a function compiled with a higher preferred
+stack boundary from a function compiled with a lower preferred stack
+boundary most likely misaligns the stack. It is recommended that
+libraries that use callbacks always use the default setting.
+
+This extra alignment does consume extra stack space, and generally
+increases code size. Code that is sensitive to stack space usage, such
+as embedded systems and operating system kernels, may want to reduce the
+preferred alignment to @option{-mpreferred-stack-boundary=2}.
+
+@need 200
+@item -mmmx
+@opindex mmmx
+@need 200
+@itemx -msse
+@opindex msse
+@need 200
+@itemx -msse2
+@opindex msse2
+@need 200
+@itemx -msse3
+@opindex msse3
+@need 200
+@itemx -mssse3
+@opindex mssse3
+@need 200
+@itemx -msse4
+@opindex msse4
+@need 200
+@itemx -msse4a
+@opindex msse4a
+@need 200
+@itemx -msse4.1
+@opindex msse4.1
+@need 200
+@itemx -msse4.2
+@opindex msse4.2
+@need 200
+@itemx -mavx
+@opindex mavx
+@need 200
+@itemx -mavx2
+@opindex mavx2
+@need 200
+@itemx -mavx512f
+@opindex mavx512f
+@need 200
+@itemx -mavx512pf
+@opindex mavx512pf
+@need 200
+@itemx -mavx512er
+@opindex mavx512er
+@need 200
+@itemx -mavx512cd
+@opindex mavx512cd
+@need 200
+@itemx -mavx512vl
+@opindex mavx512vl
+@need 200
+@itemx -mavx512bw
+@opindex mavx512bw
+@need 200
+@itemx -mavx512dq
+@opindex mavx512dq
+@need 200
+@itemx -mavx512ifma
+@opindex mavx512ifma
+@need 200
+@itemx -mavx512vbmi
+@opindex mavx512vbmi
+@need 200
+@itemx -msha
+@opindex msha
+@need 200
+@itemx -maes
+@opindex maes
+@need 200
+@itemx -mpclmul
+@opindex mpclmul
+@need 200
+@itemx -mclfushopt
+@opindex mclfushopt
+@need 200
+@itemx -mfsgsbase
+@opindex mfsgsbase
+@need 200
+@itemx -mrdrnd
+@opindex mrdrnd
+@need 200
+@itemx -mf16c
+@opindex mf16c
+@need 200
+@itemx -mfma
+@opindex mfma
+@need 200
+@itemx -mfma4
+@opindex mfma4
+@need 200
+@itemx -mno-fma4
+@opindex mno-fma4
+@need 200
+@itemx -mprefetchwt1
+@opindex mprefetchwt1
+@need 200
+@itemx -mxop
+@opindex mxop
+@need 200
+@itemx -mlwp
+@opindex mlwp
+@need 200
+@itemx -m3dnow
+@opindex m3dnow
+@need 200
+@itemx -mpopcnt
+@opindex mpopcnt
+@need 200
+@itemx -mabm
+@opindex mabm
+@need 200
+@itemx -mbmi
+@opindex mbmi
+@need 200
+@itemx -mbmi2
+@need 200
+@itemx -mlzcnt
+@opindex mlzcnt
+@need 200
+@itemx -mfxsr
+@opindex mfxsr
+@need 200
+@itemx -mxsave
+@opindex mxsave
+@need 200
+@itemx -mxsaveopt
+@opindex mxsaveopt
+@need 200
+@itemx -mxsavec
+@opindex mxsavec
+@need 200
+@itemx -mxsaves
+@opindex mxsaves
+@need 200
+@itemx -mrtm
+@opindex mrtm
+@need 200
+@itemx -mtbm
+@opindex mtbm
+@need 200
+@itemx -mmpx
+@opindex mmpx
+@need 200
+@itemx -mmwaitx
+@opindex mmwaitx
+@need 200
+@itemx -mclzero
+@opindex mclzero
+@itemx -mpku
+@opindex mpku
+These switches enable the use of instructions in the MMX, SSE,
+SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
+SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
+AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
+XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@:
+extended instruction sets. Each has a corresponding @option{-mno-} option
+to disable use of these instructions.
+
+These extensions are also available as built-in functions: see
+@ref{x86 Built-in Functions}, for details of the functions enabled and
+disabled by these switches.
+
+To generate SSE/SSE2 instructions automatically from floating-point
+code (as opposed to 387 instructions), see @option{-mfpmath=sse}.
+
+GCC depresses SSEx instructions when @option{-mavx} is used. Instead, it
+generates new AVX instructions or AVX equivalence for all SSEx instructions
+when needed.
+
+These options enable GCC to use these extended instructions in
+generated code, even without @option{-mfpmath=sse}. Applications that
+perform run-time CPU detection must compile separate files for each
+supported architecture, using the appropriate flags. In particular,
+the file containing the CPU detection code should be compiled without
+these options.
+
+@item -mdump-tune-features
+@opindex mdump-tune-features
+This option instructs GCC to dump the names of the x86 performance
+tuning features and default settings. The names can be used in
+@option{-mtune-ctrl=@var{feature-list}}.
+
+@item -mtune-ctrl=@var{feature-list}
+@opindex mtune-ctrl=@var{feature-list}
+This option is used to do fine grain control of x86 code generation features.
+@var{feature-list} is a comma separated list of @var{feature} names. See also
+@option{-mdump-tune-features}. When specified, the @var{feature} is turned
+on if it is not preceded with @samp{^}, otherwise, it is turned off.
+@option{-mtune-ctrl=@var{feature-list}} is intended to be used by GCC
+developers. Using it may lead to code paths not covered by testing and can
+potentially result in compiler ICEs or runtime errors.
-These are listed under @xref{S/390 and zSeries Options}.
+@item -mno-default
+@opindex mno-default
+This option instructs GCC to turn off all tunable features. See also
+@option{-mtune-ctrl=@var{feature-list}} and @option{-mdump-tune-features}.
-@node Code Gen Options
-@section Options for Code Generation Conventions
-@cindex code generation conventions
-@cindex options, code generation
-@cindex run-time options
+@item -mcld
+@opindex mcld
+This option instructs GCC to emit a @code{cld} instruction in the prologue
+of functions that use string instructions. String instructions depend on
+the DF flag to select between autoincrement or autodecrement mode. While the
+ABI specifies the DF flag to be cleared on function entry, some operating
+systems violate this specification by not clearing the DF flag in their
+exception dispatchers. The exception handler can be invoked with the DF flag
+set, which leads to wrong direction mode when string instructions are used.
+This option can be enabled by default on 32-bit x86 targets by configuring
+GCC with the @option{--enable-cld} configure option. Generation of @code{cld}
+instructions can be suppressed with the @option{-mno-cld} compiler option
+in this case.
-These machine-independent options control the interface conventions
-used in code generation.
+@item -mvzeroupper
+@opindex mvzeroupper
+This option instructs GCC to emit a @code{vzeroupper} instruction
+before a transfer of control flow out of the function to minimize
+the AVX to SSE transition penalty as well as remove unnecessary @code{zeroupper}
+intrinsics.
-Most of them have both positive and negative forms; the negative form
-of @option{-ffoo} is @option{-fno-foo}. In the table below, only
-one of the forms is listed---the one that is not the default. You
-can figure out the other form by either removing @samp{no-} or adding
-it.
+@item -mprefer-avx128
+@opindex mprefer-avx128
+This option instructs GCC to use 128-bit AVX instructions instead of
+256-bit AVX instructions in the auto-vectorizer.
-@table @gcctabopt
-@item -fbounds-check
-@opindex fbounds-check
-For front ends that support it, generate additional code to check that
-indices used to access arrays are within the declared range. This is
-currently only supported by the Java and Fortran front ends, where
-this option defaults to true and false respectively.
+@item -mcx16
+@opindex mcx16
+This option enables GCC to generate @code{CMPXCHG16B} instructions.
+@code{CMPXCHG16B} allows for atomic operations on 128-bit double quadword
+(or oword) data types.
+This is useful for high-resolution counters that can be updated
+by multiple processors (or cores). This instruction is generated as part of
+atomic built-in functions: see @ref{__sync Builtins} or
+@ref{__atomic Builtins} for details.
-@item -fstack-reuse=@var{reuse-level}
-@opindex fstack_reuse
-This option controls stack space reuse for user declared local/auto variables
-and compiler generated temporaries. @var{reuse_level} can be @samp{all},
-@samp{named_vars}, or @samp{none}. @samp{all} enables stack reuse for all
-local variables and temporaries, @samp{named_vars} enables the reuse only for
-user defined local variables with names, and @samp{none} disables stack reuse
-completely. The default value is @samp{all}. The option is needed when the
-program extends the lifetime of a scoped local variable or a compiler generated
-temporary beyond the end point defined by the language. When a lifetime of
-a variable ends, and if the variable lives in memory, the optimizing compiler
-has the freedom to reuse its stack space with other temporaries or scoped
-local variables whose live range does not overlap with it. Legacy code extending
-local lifetime is likely to break with the stack reuse optimization.
+@item -msahf
+@opindex msahf
+This option enables generation of @code{SAHF} instructions in 64-bit code.
+Early Intel Pentium 4 CPUs with Intel 64 support,
+prior to the introduction of Pentium 4 G1 step in December 2005,
+lacked the @code{LAHF} and @code{SAHF} instructions
+which are supported by AMD64.
+These are load and store instructions, respectively, for certain status flags.
+In 64-bit mode, the @code{SAHF} instruction is used to optimize @code{fmod},
+@code{drem}, and @code{remainder} built-in functions;
+see @ref{Other Builtins} for details.
-For example,
+@item -mmovbe
+@opindex mmovbe
+This option enables use of the @code{movbe} instruction to implement
+@code{__builtin_bswap32} and @code{__builtin_bswap64}.
-@smallexample
- int *p;
- @{
- int local1;
+@item -mcrc32
+@opindex mcrc32
+This option enables built-in functions @code{__builtin_ia32_crc32qi},
+@code{__builtin_ia32_crc32hi}, @code{__builtin_ia32_crc32si} and
+@code{__builtin_ia32_crc32di} to generate the @code{crc32} machine instruction.
- p = &local1;
- local1 = 10;
- ....
- @}
- @{
- int local2;
- local2 = 20;
- ...
- @}
+@item -mrecip
+@opindex mrecip
+This option enables use of @code{RCPSS} and @code{RSQRTSS} instructions
+(and their vectorized variants @code{RCPPS} and @code{RSQRTPS})
+with an additional Newton-Raphson step
+to increase precision instead of @code{DIVSS} and @code{SQRTSS}
+(and their vectorized
+variants) for single-precision floating-point arguments. These instructions
+are generated only when @option{-funsafe-math-optimizations} is enabled
+together with @option{-ffinite-math-only} and @option{-fno-trapping-math}.
+Note that while the throughput of the sequence is higher than the throughput
+of the non-reciprocal instruction, the precision of the sequence can be
+decreased by up to 2 ulp (i.e. the inverse of 1.0 equals 0.99999994).
- if (*p == 10) // out of scope use of local1
- @{
+Note that GCC implements @code{1.0f/sqrtf(@var{x})} in terms of @code{RSQRTSS}
+(or @code{RSQRTPS}) already with @option{-ffast-math} (or the above option
+combination), and doesn't need @option{-mrecip}.
- @}
-@end smallexample
+Also note that GCC emits the above sequence with additional Newton-Raphson step
+for vectorized single-float division and vectorized @code{sqrtf(@var{x})}
+already with @option{-ffast-math} (or the above option combination), and
+doesn't need @option{-mrecip}.
-Another example:
-@smallexample
+@item -mrecip=@var{opt}
+@opindex mrecip=opt
+This option controls which reciprocal estimate instructions
+may be used. @var{opt} is a comma-separated list of options, which may
+be preceded by a @samp{!} to invert the option:
- struct A
- @{
- A(int k) : i(k), j(k) @{ @}
- int i;
- int j;
- @};
+@table @samp
+@item all
+Enable all estimate instructions.
- A *ap;
+@item default
+Enable the default instructions, equivalent to @option{-mrecip}.
- void foo(const A& ar)
- @{
- ap = &ar;
- @}
+@item none
+Disable all estimate instructions, equivalent to @option{-mno-recip}.
- void bar()
- @{
- foo(A(10)); // temp object's lifetime ends when foo returns
+@item div
+Enable the approximation for scalar division.
- @{
- A a(20);
- ....
- @}
- ap->i+= 10; // ap references out of scope temp whose space
- // is reused with a. What is the value of ap->i?
- @}
+@item vec-div
+Enable the approximation for vectorized division.
-@end smallexample
+@item sqrt
+Enable the approximation for scalar square root.
-The lifetime of a compiler generated temporary is well defined by the C++
-standard. When a lifetime of a temporary ends, and if the temporary lives
-in memory, the optimizing compiler has the freedom to reuse its stack
-space with other temporaries or scoped local variables whose live range
-does not overlap with it. However some of the legacy code relies on
-the behavior of older compilers in which temporaries' stack space is
-not reused, the aggressive stack reuse can lead to runtime errors. This
-option is used to control the temporary stack reuse optimization.
+@item vec-sqrt
+Enable the approximation for vectorized square root.
+@end table
-@item -ftrapv
-@opindex ftrapv
-This option generates traps for signed overflow on addition, subtraction,
-multiplication operations.
-The options @option{-ftrapv} and @option{-fwrapv} override each other, so using
-@option{-ftrapv} @option{-fwrapv} on the command-line results in
-@option{-fwrapv} being effective. Note that only active options override, so
-using @option{-ftrapv} @option{-fwrapv} @option{-fno-wrapv} on the command-line
-results in @option{-ftrapv} being effective.
+So, for example, @option{-mrecip=all,!sqrt} enables
+all of the reciprocal approximations, except for square root.
-@item -fwrapv
-@opindex fwrapv
-This option instructs the compiler to assume that signed arithmetic
-overflow of addition, subtraction and multiplication wraps around
-using twos-complement representation. This flag enables some optimizations
-and disables others. This option is enabled by default for the Java
-front end, as required by the Java language specification.
-The options @option{-ftrapv} and @option{-fwrapv} override each other, so using
-@option{-ftrapv} @option{-fwrapv} on the command-line results in
-@option{-fwrapv} being effective. Note that only active options override, so
-using @option{-ftrapv} @option{-fwrapv} @option{-fno-wrapv} on the command-line
-results in @option{-ftrapv} being effective.
+@item -mveclibabi=@var{type}
+@opindex mveclibabi
+Specifies the ABI type to use for vectorizing intrinsics using an
+external library. Supported values for @var{type} are @samp{svml}
+for the Intel short
+vector math library and @samp{acml} for the AMD math core library.
+To use this option, both @option{-ftree-vectorize} and
+@option{-funsafe-math-optimizations} have to be enabled, and an SVML or ACML
+ABI-compatible library must be specified at link time.
+
+GCC currently emits calls to @code{vmldExp2},
+@code{vmldLn2}, @code{vmldLog102}, @code{vmldLog102}, @code{vmldPow2},
+@code{vmldTanh2}, @code{vmldTan2}, @code{vmldAtan2}, @code{vmldAtanh2},
+@code{vmldCbrt2}, @code{vmldSinh2}, @code{vmldSin2}, @code{vmldAsinh2},
+@code{vmldAsin2}, @code{vmldCosh2}, @code{vmldCos2}, @code{vmldAcosh2},
+@code{vmldAcos2}, @code{vmlsExp4}, @code{vmlsLn4}, @code{vmlsLog104},
+@code{vmlsLog104}, @code{vmlsPow4}, @code{vmlsTanh4}, @code{vmlsTan4},
+@code{vmlsAtan4}, @code{vmlsAtanh4}, @code{vmlsCbrt4}, @code{vmlsSinh4},
+@code{vmlsSin4}, @code{vmlsAsinh4}, @code{vmlsAsin4}, @code{vmlsCosh4},
+@code{vmlsCos4}, @code{vmlsAcosh4} and @code{vmlsAcos4} for corresponding
+function type when @option{-mveclibabi=svml} is used, and @code{__vrd2_sin},
+@code{__vrd2_cos}, @code{__vrd2_exp}, @code{__vrd2_log}, @code{__vrd2_log2},
+@code{__vrd2_log10}, @code{__vrs4_sinf}, @code{__vrs4_cosf},
+@code{__vrs4_expf}, @code{__vrs4_logf}, @code{__vrs4_log2f},
+@code{__vrs4_log10f} and @code{__vrs4_powf} for the corresponding function type
+when @option{-mveclibabi=acml} is used.
+
+@item -mabi=@var{name}
+@opindex mabi
+Generate code for the specified calling convention. Permissible values
+are @samp{sysv} for the ABI used on GNU/Linux and other systems, and
+@samp{ms} for the Microsoft ABI. The default is to use the Microsoft
+ABI when targeting Microsoft Windows and the SysV ABI on all other systems.
+You can control this behavior for specific functions by
+using the function attributes @code{ms_abi} and @code{sysv_abi}.
+@xref{Function Attributes}.
-@item -fexceptions
-@opindex fexceptions
-Enable exception handling. Generates extra code needed to propagate
-exceptions. For some targets, this implies GCC generates frame
-unwind information for all functions, which can produce significant data
-size overhead, although it does not affect execution. If you do not
-specify this option, GCC enables it by default for languages like
-C++ that normally require exception handling, and disables it for
-languages like C that do not normally require it. However, you may need
-to enable this option when compiling C code that needs to interoperate
-properly with exception handlers written in C++. You may also wish to
-disable this option if you are compiling older C++ programs that don't
-use exception handling.
+@item -mtls-dialect=@var{type}
+@opindex mtls-dialect
+Generate code to access thread-local storage using the @samp{gnu} or
+@samp{gnu2} conventions. @samp{gnu} is the conservative default;
+@samp{gnu2} is more efficient, but it may add compile- and run-time
+requirements that cannot be satisfied on all systems.
-@item -fnon-call-exceptions
-@opindex fnon-call-exceptions
-Generate code that allows trapping instructions to throw exceptions.
-Note that this requires platform-specific runtime support that does
-not exist everywhere. Moreover, it only allows @emph{trapping}
-instructions to throw exceptions, i.e.@: memory references or floating-point
-instructions. It does not allow exceptions to be thrown from
-arbitrary signal handlers such as @code{SIGALRM}.
+@item -mpush-args
+@itemx -mno-push-args
+@opindex mpush-args
+@opindex mno-push-args
+Use PUSH operations to store outgoing parameters. This method is shorter
+and usually equally fast as method using SUB/MOV operations and is enabled
+by default. In some cases disabling it may improve performance because of
+improved scheduling and reduced dependencies.
-@item -fdelete-dead-exceptions
-@opindex fdelete-dead-exceptions
-Consider that instructions that may throw exceptions but don't otherwise
-contribute to the execution of the program can be optimized away.
-This option is enabled by default for the Ada front end, as permitted by
-the Ada language specification.
-Optimization passes that cause dead exceptions to be removed are enabled independently at different optimization levels.
+@item -maccumulate-outgoing-args
+@opindex maccumulate-outgoing-args
+If enabled, the maximum amount of space required for outgoing arguments is
+computed in the function prologue. This is faster on most modern CPUs
+because of reduced dependencies, improved scheduling and reduced stack usage
+when the preferred stack boundary is not equal to 2. The drawback is a notable
+increase in code size. This switch implies @option{-mno-push-args}.
-@item -funwind-tables
-@opindex funwind-tables
-Similar to @option{-fexceptions}, except that it just generates any needed
-static data, but does not affect the generated code in any other way.
-You normally do not need to enable this option; instead, a language processor
-that needs this handling enables it on your behalf.
+@item -mthreads
+@opindex mthreads
+Support thread-safe exception handling on MinGW. Programs that rely
+on thread-safe exception handling must compile and link all code with the
+@option{-mthreads} option. When compiling, @option{-mthreads} defines
+@option{-D_MT}; when linking, it links in a special thread helper library
+@option{-lmingwthrd} which cleans up per-thread exception-handling data.
-@item -fasynchronous-unwind-tables
-@opindex fasynchronous-unwind-tables
-Generate unwind table in DWARF 2 format, if supported by target machine. The
-table is exact at each instruction boundary, so it can be used for stack
-unwinding from asynchronous events (such as debugger or garbage collector).
+@item -mms-bitfields
+@itemx -mno-ms-bitfields
+@opindex mms-bitfields
+@opindex mno-ms-bitfields
-@item -fno-gnu-unique
-@opindex fno-gnu-unique
-On systems with recent GNU assembler and C library, the C++ compiler
-uses the @code{STB_GNU_UNIQUE} binding to make sure that definitions
-of template static data members and static local variables in inline
-functions are unique even in the presence of @code{RTLD_LOCAL}; this
-is necessary to avoid problems with a library used by two different
-@code{RTLD_LOCAL} plugins depending on a definition in one of them and
-therefore disagreeing with the other one about the binding of the
-symbol. But this causes @code{dlclose} to be ignored for affected
-DSOs; if your program relies on reinitialization of a DSO via
-@code{dlclose} and @code{dlopen}, you can use
-@option{-fno-gnu-unique}.
+Enable/disable bit-field layout compatible with the native Microsoft
+Windows compiler.
-@item -fpcc-struct-return
-@opindex fpcc-struct-return
-Return ``short'' @code{struct} and @code{union} values in memory like
-longer ones, rather than in registers. This convention is less
-efficient, but it has the advantage of allowing intercallability between
-GCC-compiled files and files compiled with other compilers, particularly
-the Portable C Compiler (pcc).
+If @code{packed} is used on a structure, or if bit-fields are used,
+it may be that the Microsoft ABI lays out the structure differently
+than the way GCC normally does. Particularly when moving packed
+data between functions compiled with GCC and the native Microsoft compiler
+(either via function call or as data in a file), it may be necessary to access
+either format.
-The precise convention for returning structures in memory depends
-on the target configuration macros.
+This option is enabled by default for Microsoft Windows
+targets. This behavior can also be controlled locally by use of variable
+or type attributes. For more information, see @ref{x86 Variable Attributes}
+and @ref{x86 Type Attributes}.
-Short structures and unions are those whose size and alignment match
-that of some integer type.
+The Microsoft structure layout algorithm is fairly simple with the exception
+of the bit-field packing.
+The padding and alignment of members of structures and whether a bit-field
+can straddle a storage-unit boundary are determine by these rules:
-@strong{Warning:} code compiled with the @option{-fpcc-struct-return}
-switch is not binary compatible with code compiled with the
-@option{-freg-struct-return} switch.
-Use it to conform to a non-default application binary interface.
+@enumerate
+@item Structure members are stored sequentially in the order in which they are
+declared: the first member has the lowest memory address and the last member
+the highest.
-@item -freg-struct-return
-@opindex freg-struct-return
-Return @code{struct} and @code{union} values in registers when possible.
-This is more efficient for small structures than
-@option{-fpcc-struct-return}.
+@item Every data object has an alignment requirement. The alignment requirement
+for all data except structures, unions, and arrays is either the size of the
+object or the current packing size (specified with either the
+@code{aligned} attribute or the @code{pack} pragma),
+whichever is less. For structures, unions, and arrays,
+the alignment requirement is the largest alignment requirement of its members.
+Every object is allocated an offset so that:
-If you specify neither @option{-fpcc-struct-return} nor
-@option{-freg-struct-return}, GCC defaults to whichever convention is
-standard for the target. If there is no standard convention, GCC
-defaults to @option{-fpcc-struct-return}, except on targets where GCC is
-the principal compiler. In those cases, we can choose the standard, and
-we chose the more efficient register return alternative.
+@smallexample
+offset % alignment_requirement == 0
+@end smallexample
-@strong{Warning:} code compiled with the @option{-freg-struct-return}
-switch is not binary compatible with code compiled with the
-@option{-fpcc-struct-return} switch.
-Use it to conform to a non-default application binary interface.
+@item Adjacent bit-fields are packed into the same 1-, 2-, or 4-byte allocation
+unit if the integral types are the same size and if the next bit-field fits
+into the current allocation unit without crossing the boundary imposed by the
+common alignment requirements of the bit-fields.
+@end enumerate
-@item -fshort-enums
-@opindex fshort-enums
-Allocate to an @code{enum} type only as many bytes as it needs for the
-declared range of possible values. Specifically, the @code{enum} type
-is equivalent to the smallest integer type that has enough room.
+MSVC interprets zero-length bit-fields in the following ways:
-@strong{Warning:} the @option{-fshort-enums} switch causes GCC to generate
-code that is not binary compatible with code generated without that switch.
-Use it to conform to a non-default application binary interface.
+@enumerate
+@item If a zero-length bit-field is inserted between two bit-fields that
+are normally coalesced, the bit-fields are not coalesced.
-@item -fshort-double
-@opindex fshort-double
-Use the same size for @code{double} as for @code{float}.
+For example:
-@strong{Warning:} the @option{-fshort-double} switch causes GCC to generate
-code that is not binary compatible with code generated without that switch.
-Use it to conform to a non-default application binary interface.
+@smallexample
+struct
+ @{
+ unsigned long bf_1 : 12;
+ unsigned long : 0;
+ unsigned long bf_2 : 12;
+ @} t1;
+@end smallexample
-@item -fshort-wchar
-@opindex fshort-wchar
-Override the underlying type for @code{wchar_t} to be @code{short
-unsigned int} instead of the default for the target. This option is
-useful for building programs to run under WINE@.
+@noindent
+The size of @code{t1} is 8 bytes with the zero-length bit-field. If the
+zero-length bit-field were removed, @code{t1}'s size would be 4 bytes.
-@strong{Warning:} the @option{-fshort-wchar} switch causes GCC to generate
-code that is not binary compatible with code generated without that switch.
-Use it to conform to a non-default application binary interface.
+@item If a zero-length bit-field is inserted after a bit-field, @code{foo}, and the
+alignment of the zero-length bit-field is greater than the member that follows it,
+@code{bar}, @code{bar} is aligned as the type of the zero-length bit-field.
-@item -fno-common
-@opindex fno-common
-In C code, controls the placement of uninitialized global variables.
-Unix C compilers have traditionally permitted multiple definitions of
-such variables in different compilation units by placing the variables
-in a common block.
-This is the behavior specified by @option{-fcommon}, and is the default
-for GCC on most targets.
-On the other hand, this behavior is not required by ISO C, and on some
-targets may carry a speed or code size penalty on variable references.
-The @option{-fno-common} option specifies that the compiler should place
-uninitialized global variables in the data section of the object file,
-rather than generating them as common blocks.
-This has the effect that if the same variable is declared
-(without @code{extern}) in two different compilations,
-you get a multiple-definition error when you link them.
-In this case, you must compile with @option{-fcommon} instead.
-Compiling with @option{-fno-common} is useful on targets for which
-it provides better performance, or if you wish to verify that the
-program will work on other systems that always treat uninitialized
-variable declarations this way.
+For example:
-@item -fno-ident
-@opindex fno-ident
-Ignore the @code{#ident} directive.
+@smallexample
+struct
+ @{
+ char foo : 4;
+ short : 0;
+ char bar;
+ @} t2;
-@item -finhibit-size-directive
-@opindex finhibit-size-directive
-Don't output a @code{.size} assembler directive, or anything else that
-would cause trouble if the function is split in the middle, and the
-two halves are placed at locations far apart in memory. This option is
-used when compiling @file{crtstuff.c}; you should not need to use it
-for anything else.
+struct
+ @{
+ char foo : 4;
+ short : 0;
+ double bar;
+ @} t3;
+@end smallexample
-@item -fverbose-asm
-@opindex fverbose-asm
-Put extra commentary information in the generated assembly code to
-make it more readable. This option is generally only of use to those
-who actually need to read the generated assembly code (perhaps while
-debugging the compiler itself).
+@noindent
+For @code{t2}, @code{bar} is placed at offset 2, rather than offset 1.
+Accordingly, the size of @code{t2} is 4. For @code{t3}, the zero-length
+bit-field does not affect the alignment of @code{bar} or, as a result, the size
+of the structure.
+
+Taking this into account, it is important to note the following:
+
+@enumerate
+@item If a zero-length bit-field follows a normal bit-field, the type of the
+zero-length bit-field may affect the alignment of the structure as whole. For
+example, @code{t2} has a size of 4 bytes, since the zero-length bit-field follows a
+normal bit-field, and is of type short.
-@option{-fno-verbose-asm}, the default, causes the
-extra information to be omitted and is useful when comparing two assembler
-files.
+@item Even if a zero-length bit-field is not followed by a normal bit-field, it may
+still affect the alignment of the structure:
-@item -frecord-gcc-switches
-@opindex frecord-gcc-switches
-This switch causes the command line used to invoke the
-compiler to be recorded into the object file that is being created.
-This switch is only implemented on some targets and the exact format
-of the recording is target and binary file format dependent, but it
-usually takes the form of a section containing ASCII text. This
-switch is related to the @option{-fverbose-asm} switch, but that
-switch only records information in the assembler output file as
-comments, so it never reaches the object file.
-See also @option{-grecord-gcc-switches} for another
-way of storing compiler options into the object file.
+@smallexample
+struct
+ @{
+ char foo : 6;
+ long : 0;
+ @} t4;
+@end smallexample
-@item -fpic
-@opindex fpic
-@cindex global offset table
-@cindex PIC
-Generate position-independent code (PIC) suitable for use in a shared
-library, if supported for the target machine. Such code accesses all
-constant addresses through a global offset table (GOT)@. The dynamic
-loader resolves the GOT entries when the program starts (the dynamic
-loader is not part of GCC; it is part of the operating system). If
-the GOT size for the linked executable exceeds a machine-specific
-maximum size, you get an error message from the linker indicating that
-@option{-fpic} does not work; in that case, recompile with @option{-fPIC}
-instead. (These maximums are 8k on the SPARC, 28k on AArch64 and 32k
-on the m68k and RS/6000. The x86 has no such limit.)
+@noindent
+Here, @code{t4} takes up 4 bytes.
+@end enumerate
-Position-independent code requires special support, and therefore works
-only on certain machines. For the x86, GCC supports PIC for System V
-but not for the Sun 386i. Code generated for the IBM RS/6000 is always
-position-independent.
+@item Zero-length bit-fields following non-bit-field members are ignored:
-When this flag is set, the macros @code{__pic__} and @code{__PIC__}
-are defined to 1.
+@smallexample
+struct
+ @{
+ char foo;
+ long : 0;
+ char bar;
+ @} t5;
+@end smallexample
-@item -fPIC
-@opindex fPIC
-If supported for the target machine, emit position-independent code,
-suitable for dynamic linking and avoiding any limit on the size of the
-global offset table. This option makes a difference on AArch64, m68k,
-PowerPC and SPARC@.
+@noindent
+Here, @code{t5} takes up 2 bytes.
+@end enumerate
-Position-independent code requires special support, and therefore works
-only on certain machines.
-When this flag is set, the macros @code{__pic__} and @code{__PIC__}
-are defined to 2.
+@item -mno-align-stringops
+@opindex mno-align-stringops
+Do not align the destination of inlined string operations. This switch reduces
+code size and improves performance in case the destination is already aligned,
+but GCC doesn't know about it.
-@item -fpie
-@itemx -fPIE
-@opindex fpie
-@opindex fPIE
-These options are similar to @option{-fpic} and @option{-fPIC}, but
-generated position independent code can be only linked into executables.
-Usually these options are used when @option{-pie} GCC option is
-used during linking.
+@item -minline-all-stringops
+@opindex minline-all-stringops
+By default GCC inlines string operations only when the destination is
+known to be aligned to least a 4-byte boundary.
+This enables more inlining and increases code
+size, but may improve performance of code that depends on fast
+@code{memcpy}, @code{strlen},
+and @code{memset} for short lengths.
-@option{-fpie} and @option{-fPIE} both define the macros
-@code{__pie__} and @code{__PIE__}. The macros have the value 1
-for @option{-fpie} and 2 for @option{-fPIE}.
+@item -minline-stringops-dynamically
+@opindex minline-stringops-dynamically
+For string operations of unknown size, use run-time checks with
+inline code for small blocks and a library call for large blocks.
-@item -fno-plt
-@opindex fno-plt
-Do not use the PLT for external function calls in position-independent code.
-Instead, load the callee address at call sites from the GOT and branch to it.
-This leads to more efficient code by eliminating PLT stubs and exposing
-GOT loads to optimizations. On architectures such as 32-bit x86 where
-PLT stubs expect the GOT pointer in a specific register, this gives more
-register allocation freedom to the compiler.
-Lazy binding requires use of the PLT;
-with @option{-fno-plt} all external symbols are resolved at load time.
+@item -mstringop-strategy=@var{alg}
+@opindex mstringop-strategy=@var{alg}
+Override the internal decision heuristic for the particular algorithm to use
+for inlining string operations. The allowed values for @var{alg} are:
-Alternatively, the function attribute @code{noplt} can be used to avoid calls
-through the PLT for specific external functions.
+@table @samp
+@item rep_byte
+@itemx rep_4byte
+@itemx rep_8byte
+Expand using i386 @code{rep} prefix of the specified size.
-In position-dependent code, a few targets also convert calls to
-functions that are marked to not use the PLT to use the GOT instead.
+@item byte_loop
+@itemx loop
+@itemx unrolled_loop
+Expand into an inline loop.
-@item -fno-jump-tables
-@opindex fno-jump-tables
-Do not use jump tables for switch statements even where it would be
-more efficient than other code generation strategies. This option is
-of use in conjunction with @option{-fpic} or @option{-fPIC} for
-building code that forms part of a dynamic linker and cannot
-reference the address of a jump table. On some targets, jump tables
-do not require a GOT and this option is not needed.
+@item libcall
+Always use a library call.
+@end table
-@item -ffixed-@var{reg}
-@opindex ffixed
-Treat the register named @var{reg} as a fixed register; generated code
-should never refer to it (except perhaps as a stack pointer, frame
-pointer or in some other fixed role).
+@item -mmemcpy-strategy=@var{strategy}
+@opindex mmemcpy-strategy=@var{strategy}
+Override the internal decision heuristic to decide if @code{__builtin_memcpy}
+should be inlined and what inline algorithm to use when the expected size
+of the copy operation is known. @var{strategy}
+is a comma-separated list of @var{alg}:@var{max_size}:@var{dest_align} triplets.
+@var{alg} is specified in @option{-mstringop-strategy}, @var{max_size} specifies
+the max byte size with which inline algorithm @var{alg} is allowed. For the last
+triplet, the @var{max_size} must be @code{-1}. The @var{max_size} of the triplets
+in the list must be specified in increasing order. The minimal byte size for
+@var{alg} is @code{0} for the first triplet and @code{@var{max_size} + 1} of the
+preceding range.
-@var{reg} must be the name of a register. The register names accepted
-are machine-specific and are defined in the @code{REGISTER_NAMES}
-macro in the machine description macro file.
+@item -mmemset-strategy=@var{strategy}
+@opindex mmemset-strategy=@var{strategy}
+The option is similar to @option{-mmemcpy-strategy=} except that it is to control
+@code{__builtin_memset} expansion.
-This flag does not have a negative form, because it specifies a
-three-way choice.
+@item -momit-leaf-frame-pointer
+@opindex momit-leaf-frame-pointer
+Don't keep the frame pointer in a register for leaf functions. This
+avoids the instructions to save, set up, and restore frame pointers and
+makes an extra register available in leaf functions. The option
+@option{-fomit-leaf-frame-pointer} removes the frame pointer for leaf functions,
+which might make debugging harder.
-@item -fcall-used-@var{reg}
-@opindex fcall-used
-Treat the register named @var{reg} as an allocable register that is
-clobbered by function calls. It may be allocated for temporaries or
-variables that do not live across a call. Functions compiled this way
-do not save and restore the register @var{reg}.
+@item -mtls-direct-seg-refs
+@itemx -mno-tls-direct-seg-refs
+@opindex mtls-direct-seg-refs
+Controls whether TLS variables may be accessed with offsets from the
+TLS segment register (@code{%gs} for 32-bit, @code{%fs} for 64-bit),
+or whether the thread base pointer must be added. Whether or not this
+is valid depends on the operating system, and whether it maps the
+segment to cover the entire TLS area.
-It is an error to use this flag with the frame pointer or stack pointer.
-Use of this flag for other registers that have fixed pervasive roles in
-the machine's execution model produces disastrous results.
+For systems that use the GNU C Library, the default is on.
-This flag does not have a negative form, because it specifies a
-three-way choice.
+@item -msse2avx
+@itemx -mno-sse2avx
+@opindex msse2avx
+Specify that the assembler should encode SSE instructions with VEX
+prefix. The option @option{-mavx} turns this on by default.
-@item -fcall-saved-@var{reg}
-@opindex fcall-saved
-Treat the register named @var{reg} as an allocable register saved by
-functions. It may be allocated even for temporaries or variables that
-live across a call. Functions compiled this way save and restore
-the register @var{reg} if they use it.
+@item -mfentry
+@itemx -mno-fentry
+@opindex mfentry
+If profiling is active (@option{-pg}), put the profiling
+counter call before the prologue.
+Note: On x86 architectures the attribute @code{ms_hook_prologue}
+isn't possible at the moment for @option{-mfentry} and @option{-pg}.
-It is an error to use this flag with the frame pointer or stack pointer.
-Use of this flag for other registers that have fixed pervasive roles in
-the machine's execution model produces disastrous results.
+@item -mrecord-mcount
+@itemx -mno-record-mcount
+@opindex mrecord-mcount
+If profiling is active (@option{-pg}), generate a __mcount_loc section
+that contains pointers to each profiling call. This is useful for
+automatically patching and out calls.
-A different sort of disaster results from the use of this flag for
-a register in which function values may be returned.
+@item -mnop-mcount
+@itemx -mno-nop-mcount
+@opindex mnop-mcount
+If profiling is active (@option{-pg}), generate the calls to
+the profiling functions as nops. This is useful when they
+should be patched in later dynamically. This is likely only
+useful together with @option{-mrecord-mcount}.
-This flag does not have a negative form, because it specifies a
-three-way choice.
+@item -mskip-rax-setup
+@itemx -mno-skip-rax-setup
+@opindex mskip-rax-setup
+When generating code for the x86-64 architecture with SSE extensions
+disabled, @option{-skip-rax-setup} can be used to skip setting up RAX
+register when there are no variable arguments passed in vector registers.
-@item -fpack-struct[=@var{n}]
-@opindex fpack-struct
-Without a value specified, pack all structure members together without
-holes. When a value is specified (which must be a small power of two), pack
-structure members according to this value, representing the maximum
-alignment (that is, objects with default alignment requirements larger than
-this are output potentially unaligned at the next fitting location.
+@strong{Warning:} Since RAX register is used to avoid unnecessarily
+saving vector registers on stack when passing variable arguments, the
+impacts of this option are callees may waste some stack space,
+misbehave or jump to a random location. GCC 4.4 or newer don't have
+those issues, regardless the RAX register value.
-@strong{Warning:} the @option{-fpack-struct} switch causes GCC to generate
-code that is not binary compatible with code generated without that switch.
-Additionally, it makes the code suboptimal.
-Use it to conform to a non-default application binary interface.
+@item -m8bit-idiv
+@itemx -mno-8bit-idiv
+@opindex m8bit-idiv
+On some processors, like Intel Atom, 8-bit unsigned integer divide is
+much faster than 32-bit/64-bit integer divide. This option generates a
+run-time check. If both dividend and divisor are within range of 0
+to 255, 8-bit unsigned integer divide is used instead of
+32-bit/64-bit integer divide.
-@item -finstrument-functions
-@opindex finstrument-functions
-Generate instrumentation calls for entry and exit to functions. Just
-after function entry and just before function exit, the following
-profiling functions are called with the address of the current
-function and its call site. (On some platforms,
-@code{__builtin_return_address} does not work beyond the current
-function, so the call site information may not be available to the
-profiling functions otherwise.)
+@item -mavx256-split-unaligned-load
+@itemx -mavx256-split-unaligned-store
+@opindex mavx256-split-unaligned-load
+@opindex mavx256-split-unaligned-store
+Split 32-byte AVX unaligned load and store.
-@smallexample
-void __cyg_profile_func_enter (void *this_fn,
- void *call_site);
-void __cyg_profile_func_exit (void *this_fn,
- void *call_site);
-@end smallexample
+@item -mstack-protector-guard=@var{guard}
+@opindex mstack-protector-guard=@var{guard}
+Generate stack protection code using canary at @var{guard}. Supported
+locations are @samp{global} for global canary or @samp{tls} for per-thread
+canary in the TLS block (the default). This option has effect only when
+@option{-fstack-protector} or @option{-fstack-protector-all} is specified.
-The first argument is the address of the start of the current function,
-which may be looked up exactly in the symbol table.
+@item -mmitigate-rop
+@opindex mmitigate-rop
+Try to avoid generating code sequences that contain unintended return
+opcodes, to mitigate against certain forms of attack. At the moment,
+this option is limited in what it can do and should not be relied
+on to provide serious protection.
-This instrumentation is also done for functions expanded inline in other
-functions. The profiling calls indicate where, conceptually, the
-inline function is entered and exited. This means that addressable
-versions of such functions must be available. If all your uses of a
-function are expanded inline, this may mean an additional expansion of
-code size. If you use @code{extern inline} in your C code, an
-addressable version of such functions must be provided. (This is
-normally the case anyway, but if you get lucky and the optimizer always
-expands the functions inline, you might have gotten away without
-providing static copies.)
+@end table
-A function may be given the attribute @code{no_instrument_function}, in
-which case this instrumentation is not done. This can be used, for
-example, for the profiling functions listed above, high-priority
-interrupt routines, and any functions from which the profiling functions
-cannot safely be called (perhaps signal handlers, if the profiling
-routines generate output or allocate memory).
+These @samp{-m} switches are supported in addition to the above
+on x86-64 processors in 64-bit environments.
-@item -finstrument-functions-exclude-file-list=@var{file},@var{file},@dots{}
-@opindex finstrument-functions-exclude-file-list
+@table @gcctabopt
+@item -m32
+@itemx -m64
+@itemx -mx32
+@itemx -m16
+@itemx -miamcu
+@opindex m32
+@opindex m64
+@opindex mx32
+@opindex m16
+@opindex miamcu
+Generate code for a 16-bit, 32-bit or 64-bit environment.
+The @option{-m32} option sets @code{int}, @code{long}, and pointer types
+to 32 bits, and
+generates code that runs on any i386 system.
-Set the list of functions that are excluded from instrumentation (see
-the description of @option{-finstrument-functions}). If the file that
-contains a function definition matches with one of @var{file}, then
-that function is not instrumented. The match is done on substrings:
-if the @var{file} parameter is a substring of the file name, it is
-considered to be a match.
+The @option{-m64} option sets @code{int} to 32 bits and @code{long} and pointer
+types to 64 bits, and generates code for the x86-64 architecture.
+For Darwin only the @option{-m64} option also turns off the @option{-fno-pic}
+and @option{-mdynamic-no-pic} options.
-For example:
+The @option{-mx32} option sets @code{int}, @code{long}, and pointer types
+to 32 bits, and
+generates code for the x86-64 architecture.
-@smallexample
--finstrument-functions-exclude-file-list=/bits/stl,include/sys
-@end smallexample
+The @option{-m16} option is the same as @option{-m32}, except for that
+it outputs the @code{.code16gcc} assembly directive at the beginning of
+the assembly output so that the binary can run in 16-bit mode.
-@noindent
-excludes any inline function defined in files whose pathnames
-contain @file{/bits/stl} or @file{include/sys}.
+The @option{-miamcu} option generates code which conforms to Intel MCU
+psABI. It requires the @option{-m32} option to be turned on.
-If, for some reason, you want to include letter @samp{,} in one of
-@var{sym}, write @samp{\,}. For example,
-@option{-finstrument-functions-exclude-file-list='\,\,tmp'}
-(note the single quote surrounding the option).
+@item -mno-red-zone
+@opindex mno-red-zone
+Do not use a so-called ``red zone'' for x86-64 code. The red zone is mandated
+by the x86-64 ABI; it is a 128-byte area beyond the location of the
+stack pointer that is not modified by signal or interrupt handlers
+and therefore can be used for temporary data without adjusting the stack
+pointer. The flag @option{-mno-red-zone} disables this red zone.
-@item -finstrument-functions-exclude-function-list=@var{sym},@var{sym},@dots{}
-@opindex finstrument-functions-exclude-function-list
+@item -mcmodel=small
+@opindex mcmodel=small
+Generate code for the small code model: the program and its symbols must
+be linked in the lower 2 GB of the address space. Pointers are 64 bits.
+Programs can be statically or dynamically linked. This is the default
+code model.
-This is similar to @option{-finstrument-functions-exclude-file-list},
-but this option sets the list of function names to be excluded from
-instrumentation. The function name to be matched is its user-visible
-name, such as @code{vector<int> blah(const vector<int> &)}, not the
-internal mangled name (e.g., @code{_Z4blahRSt6vectorIiSaIiEE}). The
-match is done on substrings: if the @var{sym} parameter is a substring
-of the function name, it is considered to be a match. For C99 and C++
-extended identifiers, the function name must be given in UTF-8, not
-using universal character names.
+@item -mcmodel=kernel
+@opindex mcmodel=kernel
+Generate code for the kernel code model. The kernel runs in the
+negative 2 GB of the address space.
+This model has to be used for Linux kernel code.
-@item -fstack-check
-@opindex fstack-check
-Generate code to verify that you do not go beyond the boundary of the
-stack. You should specify this flag if you are running in an
-environment with multiple threads, but you only rarely need to specify it in
-a single-threaded environment since stack overflow is automatically
-detected on nearly all systems if there is only one stack.
+@item -mcmodel=medium
+@opindex mcmodel=medium
+Generate code for the medium model: the program is linked in the lower 2
+GB of the address space. Small symbols are also placed there. Symbols
+with sizes larger than @option{-mlarge-data-threshold} are put into
+large data or BSS sections and can be located above 2GB. Programs can
+be statically or dynamically linked.
-Note that this switch does not actually cause checking to be done; the
-operating system or the language runtime must do that. The switch causes
-generation of code to ensure that they see the stack being extended.
+@item -mcmodel=large
+@opindex mcmodel=large
+Generate code for the large model. This model makes no assumptions
+about addresses and sizes of sections.
-You can additionally specify a string parameter: @samp{no} means no
-checking, @samp{generic} means force the use of old-style checking,
-@samp{specific} means use the best checking method and is equivalent
-to bare @option{-fstack-check}.
+@item -maddress-mode=long
+@opindex maddress-mode=long
+Generate code for long address mode. This is only supported for 64-bit
+and x32 environments. It is the default address mode for 64-bit
+environments.
-Old-style checking is a generic mechanism that requires no specific
-target support in the compiler but comes with the following drawbacks:
+@item -maddress-mode=short
+@opindex maddress-mode=short
+Generate code for short address mode. This is only supported for 32-bit
+and x32 environments. It is the default address mode for 32-bit and
+x32 environments.
+@end table
-@enumerate
-@item
-Modified allocation strategy for large objects: they are always
-allocated dynamically if their size exceeds a fixed threshold.
+@node x86 Windows Options
+@subsection x86 Windows Options
+@cindex x86 Windows Options
+@cindex Windows Options for x86
-@item
-Fixed limit on the size of the static frame of functions: when it is
-topped by a particular function, stack checking is not reliable and
-a warning is issued by the compiler.
+These additional options are available for Microsoft Windows targets:
-@item
-Inefficiency: because of both the modified allocation strategy and the
-generic implementation, code performance is hampered.
-@end enumerate
+@table @gcctabopt
+@item -mconsole
+@opindex mconsole
+This option
+specifies that a console application is to be generated, by
+instructing the linker to set the PE header subsystem type
+required for console applications.
+This option is available for Cygwin and MinGW targets and is
+enabled by default on those targets.
-Note that old-style stack checking is also the fallback method for
-@samp{specific} if no target support has been added in the compiler.
+@item -mdll
+@opindex mdll
+This option is available for Cygwin and MinGW targets. It
+specifies that a DLL---a dynamic link library---is to be
+generated, enabling the selection of the required runtime
+startup object and entry point.
-@item -fstack-limit-register=@var{reg}
-@itemx -fstack-limit-symbol=@var{sym}
-@itemx -fno-stack-limit
-@opindex fstack-limit-register
-@opindex fstack-limit-symbol
-@opindex fno-stack-limit
-Generate code to ensure that the stack does not grow beyond a certain value,
-either the value of a register or the address of a symbol. If a larger
-stack is required, a signal is raised at run time. For most targets,
-the signal is raised before the stack overruns the boundary, so
-it is possible to catch the signal without taking special precautions.
+@item -mnop-fun-dllimport
+@opindex mnop-fun-dllimport
+This option is available for Cygwin and MinGW targets. It
+specifies that the @code{dllimport} attribute should be ignored.
-For instance, if the stack starts at absolute address @samp{0x80000000}
-and grows downwards, you can use the flags
-@option{-fstack-limit-symbol=__stack_limit} and
-@option{-Wl,--defsym,__stack_limit=0x7ffe0000} to enforce a stack limit
-of 128KB@. Note that this may only work with the GNU linker.
+@item -mthread
+@opindex mthread
+This option is available for MinGW targets. It specifies
+that MinGW-specific thread support is to be used.
-You can locally override stack limit checking by using the
-@code{no_stack_limit} function attribute (@pxref{Function Attributes}).
+@item -municode
+@opindex municode
+This option is available for MinGW-w64 targets. It causes
+the @code{UNICODE} preprocessor macro to be predefined, and
+chooses Unicode-capable runtime startup code.
-@item -fsplit-stack
-@opindex fsplit-stack
-Generate code to automatically split the stack before it overflows.
-The resulting program has a discontiguous stack which can only
-overflow if the program is unable to allocate any more memory. This
-is most useful when running threaded programs, as it is no longer
-necessary to calculate a good stack size to use for each thread. This
-is currently only implemented for the x86 targets running
-GNU/Linux.
+@item -mwin32
+@opindex mwin32
+This option is available for Cygwin and MinGW targets. It
+specifies that the typical Microsoft Windows predefined macros are to
+be set in the pre-processor, but does not influence the choice
+of runtime library/startup code.
-When code compiled with @option{-fsplit-stack} calls code compiled
-without @option{-fsplit-stack}, there may not be much stack space
-available for the latter code to run. If compiling all code,
-including library code, with @option{-fsplit-stack} is not an option,
-then the linker can fix up these calls so that the code compiled
-without @option{-fsplit-stack} always has a large stack. Support for
-this is implemented in the gold linker in GNU binutils release 2.21
-and later.
+@item -mwindows
+@opindex mwindows
+This option is available for Cygwin and MinGW targets. It
+specifies that a GUI application is to be generated by
+instructing the linker to set the PE header subsystem type
+appropriately.
-@item -fleading-underscore
-@opindex fleading-underscore
-This option and its counterpart, @option{-fno-leading-underscore}, forcibly
-change the way C symbols are represented in the object file. One use
-is to help link with legacy assembly code.
+@item -fno-set-stack-executable
+@opindex fno-set-stack-executable
+This option is available for MinGW targets. It specifies that
+the executable flag for the stack used by nested functions isn't
+set. This is necessary for binaries running in kernel mode of
+Microsoft Windows, as there the User32 API, which is used to set executable
+privileges, isn't available.
-@strong{Warning:} the @option{-fleading-underscore} switch causes GCC to
-generate code that is not binary compatible with code generated without that
-switch. Use it to conform to a non-default application binary interface.
-Not all targets provide complete support for this switch.
+@item -fwritable-relocated-rdata
+@opindex fno-writable-relocated-rdata
+This option is available for MinGW and Cygwin targets. It specifies
+that relocated-data in read-only section is put into .data
+section. This is a necessary for older runtimes not supporting
+modification of .rdata sections for pseudo-relocation.
-@item -ftls-model=@var{model}
-@opindex ftls-model
-Alter the thread-local storage model to be used (@pxref{Thread-Local}).
-The @var{model} argument should be one of @samp{global-dynamic},
-@samp{local-dynamic}, @samp{initial-exec} or @samp{local-exec}.
-Note that the choice is subject to optimization: the compiler may use
-a more efficient model for symbols not visible outside of the translation
-unit, or if @option{-fpic} is not given on the command line.
+@item -mpe-aligned-commons
+@opindex mpe-aligned-commons
+This option is available for Cygwin and MinGW targets. It
+specifies that the GNU extension to the PE file format that
+permits the correct alignment of COMMON variables should be
+used when generating code. It is enabled by default if
+GCC detects that the target assembler found during configuration
+supports the feature.
+@end table
-The default without @option{-fpic} is @samp{initial-exec}; with
-@option{-fpic} the default is @samp{global-dynamic}.
+See also under @ref{x86 Options} for standard options.
-@item -fvisibility=@r{[}default@r{|}internal@r{|}hidden@r{|}protected@r{]}
-@opindex fvisibility
-Set the default ELF image symbol visibility to the specified option---all
-symbols are marked with this unless overridden within the code.
-Using this feature can very substantially improve linking and
-load times of shared object libraries, produce more optimized
-code, provide near-perfect API export and prevent symbol clashes.
-It is @strong{strongly} recommended that you use this in any shared objects
-you distribute.
+@node Xstormy16 Options
+@subsection Xstormy16 Options
+@cindex Xstormy16 Options
-Despite the nomenclature, @samp{default} always means public; i.e.,
-available to be linked against from outside the shared object.
-@samp{protected} and @samp{internal} are pretty useless in real-world
-usage so the only other commonly used option is @samp{hidden}.
-The default if @option{-fvisibility} isn't specified is
-@samp{default}, i.e., make every symbol public.
+These options are defined for Xstormy16:
-A good explanation of the benefits offered by ensuring ELF
-symbols have the correct visibility is given by ``How To Write
-Shared Libraries'' by Ulrich Drepper (which can be found at
-@w{@uref{http://www.akkadia.org/drepper/}})---however a superior
-solution made possible by this option to marking things hidden when
-the default is public is to make the default hidden and mark things
-public. This is the norm with DLLs on Windows and with @option{-fvisibility=hidden}
-and @code{__attribute__ ((visibility("default")))} instead of
-@code{__declspec(dllexport)} you get almost identical semantics with
-identical syntax. This is a great boon to those working with
-cross-platform projects.
+@table @gcctabopt
+@item -msim
+@opindex msim
+Choose startup files and linker script suitable for the simulator.
+@end table
-For those adding visibility support to existing code, you may find
-@code{#pragma GCC visibility} of use. This works by you enclosing
-the declarations you wish to set visibility for with (for example)
-@code{#pragma GCC visibility push(hidden)} and
-@code{#pragma GCC visibility pop}.
-Bear in mind that symbol visibility should be viewed @strong{as
-part of the API interface contract} and thus all new code should
-always specify visibility when it is not the default; i.e., declarations
-only for use within the local DSO should @strong{always} be marked explicitly
-as hidden as so to avoid PLT indirection overheads---making this
-abundantly clear also aids readability and self-documentation of the code.
-Note that due to ISO C++ specification requirements, @code{operator new} and
-@code{operator delete} must always be of default visibility.
+@node Xtensa Options
+@subsection Xtensa Options
+@cindex Xtensa Options
-Be aware that headers from outside your project, in particular system
-headers and headers from any other library you use, may not be
-expecting to be compiled with visibility other than the default. You
-may need to explicitly say @code{#pragma GCC visibility push(default)}
-before including any such headers.
+These options are supported for Xtensa targets:
-@code{extern} declarations are not affected by @option{-fvisibility}, so
-a lot of code can be recompiled with @option{-fvisibility=hidden} with
-no modifications. However, this means that calls to @code{extern}
-functions with no explicit visibility use the PLT, so it is more
-effective to use @code{__attribute ((visibility))} and/or
-@code{#pragma GCC visibility} to tell the compiler which @code{extern}
-declarations should be treated as hidden.
+@table @gcctabopt
+@item -mconst16
+@itemx -mno-const16
+@opindex mconst16
+@opindex mno-const16
+Enable or disable use of @code{CONST16} instructions for loading
+constant values. The @code{CONST16} instruction is currently not a
+standard option from Tensilica. When enabled, @code{CONST16}
+instructions are always used in place of the standard @code{L32R}
+instructions. The use of @code{CONST16} is enabled by default only if
+the @code{L32R} instruction is not available.
-Note that @option{-fvisibility} does affect C++ vague linkage
-entities. This means that, for instance, an exception class that is
-be thrown between DSOs must be explicitly marked with default
-visibility so that the @samp{type_info} nodes are unified between
-the DSOs.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Enable or disable use of fused multiply/add and multiply/subtract
+instructions in the floating-point option. This has no effect if the
+floating-point option is not also enabled. Disabling fused multiply/add
+and multiply/subtract instructions forces the compiler to use separate
+instructions for the multiply and add/subtract operations. This may be
+desirable in some cases where strict IEEE 754-compliant results are
+required: the fused multiply add/subtract instructions do not round the
+intermediate result, thereby producing results with @emph{more} bits of
+precision than specified by the IEEE standard. Disabling fused multiply
+add/subtract instructions also ensures that the program output is not
+sensitive to the compiler's ability to combine multiply and add/subtract
+operations.
-An overview of these techniques, their benefits and how to use them
-is at @uref{http://gcc.gnu.org/@/wiki/@/Visibility}.
+@item -mserialize-volatile
+@itemx -mno-serialize-volatile
+@opindex mserialize-volatile
+@opindex mno-serialize-volatile
+When this option is enabled, GCC inserts @code{MEMW} instructions before
+@code{volatile} memory references to guarantee sequential consistency.
+The default is @option{-mserialize-volatile}. Use
+@option{-mno-serialize-volatile} to omit the @code{MEMW} instructions.
-@item -fstrict-volatile-bitfields
-@opindex fstrict-volatile-bitfields
-This option should be used if accesses to volatile bit-fields (or other
-structure fields, although the compiler usually honors those types
-anyway) should use a single access of the width of the
-field's type, aligned to a natural alignment if possible. For
-example, targets with memory-mapped peripheral registers might require
-all such accesses to be 16 bits wide; with this flag you can
-declare all peripheral bit-fields as @code{unsigned short} (assuming short
-is 16 bits on these targets) to force GCC to use 16-bit accesses
-instead of, perhaps, a more efficient 32-bit access.
+@item -mforce-no-pic
+@opindex mforce-no-pic
+For targets, like GNU/Linux, where all user-mode Xtensa code must be
+position-independent code (PIC), this option disables PIC for compiling
+kernel code.
-If this option is disabled, the compiler uses the most efficient
-instruction. In the previous example, that might be a 32-bit load
-instruction, even though that accesses bytes that do not contain
-any portion of the bit-field, or memory-mapped registers unrelated to
-the one being updated.
+@item -mtext-section-literals
+@itemx -mno-text-section-literals
+@opindex mtext-section-literals
+@opindex mno-text-section-literals
+These options control the treatment of literal pools. The default is
+@option{-mno-text-section-literals}, which places literals in a separate
+section in the output file. This allows the literal pool to be placed
+in a data RAM/ROM, and it also allows the linker to combine literal
+pools from separate object files to remove redundant literals and
+improve code size. With @option{-mtext-section-literals}, the literals
+are interspersed in the text section in order to keep them as close as
+possible to their references. This may be necessary for large assembly
+files. Literals for each function are placed right before that function.
-In some cases, such as when the @code{packed} attribute is applied to a
-structure field, it may not be possible to access the field with a single
-read or write that is correctly aligned for the target machine. In this
-case GCC falls back to generating multiple accesses rather than code that
-will fault or truncate the result at run time.
+@item -mauto-litpools
+@itemx -mno-auto-litpools
+@opindex mauto-litpools
+@opindex mno-auto-litpools
+These options control the treatment of literal pools. The default is
+@option{-mno-auto-litpools}, which places literals in a separate
+section in the output file unless @option{-mtext-section-literals} is
+used. With @option{-mauto-litpools} the literals are interspersed in
+the text section by the assembler. Compiler does not produce explicit
+@code{.literal} directives and loads literals into registers with
+@code{MOVI} instructions instead of @code{L32R} to let the assembler
+do relaxation and place literals as necessary. This option allows
+assembler to create several literal pools per function and assemble
+very big functions, which may not be possible with
+@option{-mtext-section-literals}.
-Note: Due to restrictions of the C/C++11 memory model, write accesses are
-not allowed to touch non bit-field members. It is therefore recommended
-to define all bits of the field's type as bit-field members.
+@item -mtarget-align
+@itemx -mno-target-align
+@opindex mtarget-align
+@opindex mno-target-align
+When this option is enabled, GCC instructs the assembler to
+automatically align instructions to reduce branch penalties at the
+expense of some code density. The assembler attempts to widen density
+instructions to align branch targets and the instructions following call
+instructions. If there are not enough preceding safe density
+instructions to align a target, no widening is performed. The
+default is @option{-mtarget-align}. These options do not affect the
+treatment of auto-aligned instructions like @code{LOOP}, which the
+assembler always aligns, either by widening density instructions or
+by inserting NOP instructions.
-The default value of this option is determined by the application binary
-interface for the target processor.
+@item -mlongcalls
+@itemx -mno-longcalls
+@opindex mlongcalls
+@opindex mno-longcalls
+When this option is enabled, GCC instructs the assembler to translate
+direct calls to indirect calls unless it can determine that the target
+of a direct call is in the range allowed by the call instruction. This
+translation typically occurs for calls to functions in other source
+files. Specifically, the assembler translates a direct @code{CALL}
+instruction into an @code{L32R} followed by a @code{CALLX} instruction.
+The default is @option{-mno-longcalls}. This option should be used in
+programs where the call target can potentially be out of range. This
+option is implemented in the assembler, not the compiler, so the
+assembly code generated by GCC still shows direct call
+instructions---look at the disassembled object code to see the actual
+instructions. Note that the assembler uses an indirect call for
+every cross-file call, not just those that really are out of range.
+@end table
-@item -fsync-libcalls
-@opindex fsync-libcalls
-This option controls whether any out-of-line instance of the @code{__sync}
-family of functions may be used to implement the C++11 @code{__atomic}
-family of functions.
+@node zSeries Options
+@subsection zSeries Options
+@cindex zSeries options
-The default value of this option is enabled, thus the only useful form
-of the option is @option{-fno-sync-libcalls}. This option is used in
-the implementation of the @file{libatomic} runtime library.
+These are listed under @xref{S/390 and zSeries Options}.
-@end table
@c man end
projects / gcc.git / commitdiff