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Add assertion
author
Eddie Hung
<eddie@fpgeh.com>
Wed, 4 Dec 2019 03:21:42 +0000
(19:21 -0800)
committer
Eddie Hung
<eddie@fpgeh.com>
Wed, 4 Dec 2019 03:21:42 +0000
(19:21 -0800)
passes/techmap/abc9.cc
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diff --git
a/passes/techmap/abc9.cc
b/passes/techmap/abc9.cc
index 5139cb80b620f83df7454cc5e36aa203d241ad5d..5b4100574ba8f8d357b929721ccfa4af07a27964 100644
(file)
--- a/
passes/techmap/abc9.cc
+++ b/
passes/techmap/abc9.cc
@@
-1107,6
+1107,7
@@
struct Abc9Pass : public Pass {
Wire *abc9_clock_wire = module->wire(stringf("%s.$abc9_clock", cell->name.c_str()));
if (abc9_clock_wire == NULL)
log_error("'%s.$abc9_clock' is not a wire present in module '%s'.\n", cell->name.c_str(), log_id(module));
+ log_assert(GetSize(abc9_clock_wire) == 1);
SigBit abc9_clock = sigmap(abc9_clock_wire);
auto r = clocks.insert(abc9_clock.wire);
if (r.second) {