Merge remote-tracking branch 'origin/master' into xaig_arrival

diff --cc README.md
Simple merge

diff --cc techlibs/ecp5/cells_sim.v
index 24de0c3c2bd44ad47b76faa2f7191f504ed68ced,dc8334acba1fae55eae2b6f2114addcb51e2dd21..e2bf3c8544cdbd7338fc1689ce5b89c7639377b5
--- 1/techlibs/ecp5/cells_sim.v
--- 2/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@@ -113,7 -118,8 +115,8 @@@ module TRELLIS_DPR16X4 
        input        WRE,
        input        WCK,
        input  [3:0] RAD,
-       /* (* abc_arrival=<TODO> *) */ output [3:0] DO
 -      output [3:0] DO
++      /* (* abc_arrival=<TODO> *) */
++    output [3:0] DO
  );
        parameter WCKMUX = "WCK";
        parameter WREMUX = "WRE";

diff --cc techlibs/xilinx/cells_sim.v
index 65c59759af120d971a7dc78a336766270529f1fb,3ad96d7fbbeea60c693a5f24866bcb78b4c39ef4..21ac193006ba3b4d08de6fb54116f30a5235eb6d
--- 1/techlibs/xilinx/cells_sim.v
--- 2/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@@ -297,11 -297,13 +299,12 @@@ module FDPE_1 ((* abc_arrival=303 *) ou
    always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
  endmodule
  
 -(* abc_box_id = 5 *)
  module RAM32X1D (
-   (* abc_arrival=1153 *) output DPO, SPO,
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 -  (* abc_scc_break *)
++  (* abc_arrival=1153 *)
+   output DPO, SPO,
    input  D,
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
@@@ -317,11 -319,13 +320,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 6 *)
  module RAM64X1D (
-   (* abc_arrival=1153 *) output DPO, SPO,
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
 -  (* abc_scc_break *)
++  (* abc_arrival=1153 *)
+   output DPO, SPO,
    input  D,
    input  WCLK,
 -  (* abc_scc_break *)
    input  WE,
    input  A0, A1, A2, A3, A4, A5,
    input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@@ -337,11 -341,13 +341,12 @@@
    always @(posedge clk) if (WE) mem[a] <= D;
  endmodule
  
 -(* abc_box_id = 7 *)
  module RAM128X1D (
 -  output       DPO, SPO,
 -  (* abc_scc_break *)
 +  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
-   (* abc_arrival=1153 *) output DPO, SPO,
++  (* abc_arrival=1153 *)
++  output DPO, SPO,
    input        D,
    input        WCLK,
 -  (* abc_scc_break *)
    input        WE,
    input  [6:0] A, DPRA
  );