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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 11:09:43 +0000 (12:09 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 29 Sep 2022 11:09:43 +0000 (12:09 +0100)
src/openpower/decoder/isa/test_caller_svp64_bigint.py patch | blob | history

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bigint.py b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
index e2719666faf11c49494478a25f5baaf61ba2fda6..5ae4d830c72c564093b0d0fd47a51bfee5158520 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bigint.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bigint.py
@@ -64,7 +64,7 @@ class DecoderTestCase(FHDLTestCase):
 
         r3                    r2                    r1                       r4
         0x0000_0000_0000_0002 0x8000_8000_8000_8001 0xffff_ffff_ffff_ffff >> 4
-        0x0000_0000_0000_0002 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff >> 4
+        0x0000_0000_0000_0002 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
         """
         isa = SVP64Asm(['sv.dsrd *0,*1,4,1'
                        ])