mem-cache: Fix bug in handleAtomicReqMiss

"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug
where if an atomic request that fills in using the tempBlock it will
not evict it when it finishes handling the request as it should. This
triggers an assertion. This change fixes this bug.

Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12644
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 4ba256b95dbef1a521abd5a50da54bbe040a9ba8..4ebc52493c27a5a44f6dd33d104ff38c569c4a97 100644 (file)
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -506,7 +506,7 @@ class BaseCache : public MemObject
      * @param writebacks A list with packets for any performed writebacks
      * @return Cycles for handling the request
      */
-    virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+    virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                                        PacketList &writebacks) = 0;
 
     /**

diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 9b161290458313fc5182c2730b058d32f0fafc33..1b5316383d1f38d628b45870fa0671272a2bd7de 100644 (file)
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -560,7 +560,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
 
 
 Cycles
-Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                            PacketList &writebacks)
 {
     // deal with the packets that go through the write path of

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 32752a5e6975dc1a08b57d38542532d72d2b28ea..f8eccfee67b7963138e5ac698c243e097a002551 100644 (file)
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -110,7 +110,7 @@ class Cache : public BaseCache
 
     void recvTimingSnoopResp(PacketPtr pkt) override;
 
-    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                                PacketList &writebacks) override;
 
     Tick recvAtomic(PacketPtr pkt) override;

diff --git a/src/mem/cache/noncoherent_cache.cc b/src/mem/cache/noncoherent_cache.cc
index 50738375e68607b819441ad9e9b7f1c3608126d6..fb8193a9963ada4cc6c7c3db66e3cedcdeb2b977 100644 (file)
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -170,7 +170,7 @@ NoncoherentCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
 
 
 Cycles
-NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+NoncoherentCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                                       PacketList &writebacks)
 {
     PacketPtr bus_pkt = createMissPacket(pkt, blk, true);

diff --git a/src/mem/cache/noncoherent_cache.hh b/src/mem/cache/noncoherent_cache.hh
index 09012ba108b6fe7b6872419498f18b809254a022..2a60f4c5e21f40de602f40583c9fb9285ab4a3ec 100644 (file)
--- a/src/mem/cache/noncoherent_cache.hh
+++ b/src/mem/cache/noncoherent_cache.hh
@@ -98,7 +98,7 @@ class NoncoherentCache : public BaseCache
         panic("Unexpected timing snoop response %s", pkt->print());
     }
 
-    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
+    Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
                                PacketList &writebacks) override;
 
     Tick recvAtomic(PacketPtr pkt) override;