Add riscv64-none-elf triple

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index b58ac1a1d2fa42fc7c551cadf738b28b7825a701..897664892941f86df18fc5e2dd9482331a4179b9 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -48,7 +48,8 @@ class BlackParrotRV64(CPU):
     name                 = "blackparrot"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
+    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
+                            "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
     io_regions           = {0x30000000: 0x20000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 2c3d967cb8d7e21cec32623fb5d935e1d7f6cddb..2edbfe7ee77eaa5225e0669fc6b6d39357e60fe7 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -18,7 +18,7 @@ class Minerva(CPU):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf")
+                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index c918b6d108b25eb81731127709028caf756f9c65..304f6c14d58123ebacfbfdf26a5c59497ed8feae 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -35,7 +35,7 @@ class PicoRV32(CPU):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf")
+                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 3f94cf2dfcf4098638842db200a299524a1b1e31..14bab0f41705ef769b4267ff48d2625a6db101d7 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -67,7 +67,8 @@ class RocketRV64(CPU):
     name                 = "rocket"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
+    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
+                            "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
     io_regions           = {0x10000000: 0x70000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 7c85a3c99877c6d4de1216fbc805b7d3c95815a3..4e0bbc0a0bd24454454484fec24f885628011c93 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -78,7 +78,7 @@ class VexRiscv(CPU, AutoCSR):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf")
+                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length