check: add support for processes.

diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index 54b9b340db1be8d3426adde7785aa68089350e97..36febb98ac61cfedc52e24e743b5970b294a8b27 100644 (file)
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -98,9 +98,6 @@ struct CheckPass : public Pass {
 
                for (auto module : design->selected_whole_modules_warn())
                {
-                       if (module->has_processes_warn())
-                               continue;
-
                        log("Checking module %s...\n", log_id(module));
 
                        SigMap sigmap(module);
@@ -109,6 +106,44 @@ struct CheckPass : public Pass {
                        pool<SigBit> used_wires;
                        TopoSort<string> topo;
 
+                       for (auto &proc_it : module->processes)
+                       {
+                               std::vector<RTLIL::CaseRule*> all_cases = {&proc_it.second->root_case};
+                               for (size_t i = 0; i < all_cases.size(); i++) {
+                                       for (auto action : all_cases[i]->actions) {
+                                               for (auto bit : sigmap(action.first))
+                                                       if (bit.wire) {
+                                                               wire_drivers[bit].push_back(
+                                                                       stringf("action %s <= %s (case rule) in process %s",
+                                                                               log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
+                                                       }
+                                               for (auto bit : sigmap(action.second))
+                                                       if (bit.wire) used_wires.insert(bit);
+                                       }
+                                       for (auto switch_ : all_cases[i]->switches) {
+                                               for (auto case_ : switch_->cases) {
+                                                       all_cases.push_back(case_);
+                                                       for (auto compare : case_->compare)
+                                                               for (auto bit : sigmap(compare))
+                                                                       if (bit.wire) used_wires.insert(bit);
+                                               }
+                                       }
+                               }
+                               for (auto &sync : proc_it.second->syncs) {
+                                       for (auto bit : sigmap(sync->signal))
+                                               if (bit.wire) used_wires.insert(bit);
+                                       for (auto action : sync->actions) {
+                                               for (auto bit : sigmap(action.first))
+                                                       if (bit.wire)
+                                                               wire_drivers[bit].push_back(
+                                                                       stringf("action %s <= %s (sync rule) in process %s",
+                                                                               log_signal(action.first), log_signal(action.second), log_id(proc_it.first)));
+                                               for (auto bit : sigmap(action.second))
+                                                       if (bit.wire) used_wires.insert(bit);
+                                       }
+                               }
+                       }
+
                        for (auto cell : module->cells())
                        {
                                if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {