evergreeng: respect linewidth state, use integer widths only

Discard fractional bits from linewidth.  This matches the nvidia
closed drivers, my reading of the OpenGL SI and current llvmpipe
behaviour.

It looks a lot nicer & avoids ugliness where lines alternate between n
and n+1 pixels in width along their length.

Also fix up r600g to match.

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index ce8e93a1d2555ef68e9ff19cce36da9867846698..7dd261d7e235976ad87004389477dcdd5ab3c390 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -281,7 +281,10 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx,
        tmp = (unsigned)(state->point_size * 8.0);
        r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, 0x00000008, 0xFFFFFFFF, NULL);
+
+       tmp = (unsigned)state->line_width * 8;
+       r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
+
        r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);

diff --git a/src/gallium/drivers/r600/evergreend.h b/src/gallium/drivers/r600/evergreend.h
index 8e96f9355e62a938e9bf37f768b7ba91fc89102c..7e7bd01291d2b32383b22a755c5c9efba761e36c 100644 (file)
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1636,6 +1636,9 @@
 #define R_028980_ALU_CONST_CACHE_VS_0                0x00028980
 #define R_028A04_PA_SU_POINT_MINMAX                  0x00028A04
 #define R_028A08_PA_SU_LINE_CNTL                     0x00028A08
+#define   S_028A08_WIDTH(x)                            (((x) & 0xFFFF) << 0)
+#define   G_028A08_WIDTH(x)                            (((x) >> 0) & 0xFFFF)
+#define   C_028A08_WIDTH                               0xFFFF0000
 #define R_028A10_VGT_OUTPUT_PATH_CNTL                0x00028A10
 #define R_028A14_VGT_HOS_CNTL                        0x00028A14
 #define R_028A18_VGT_HOS_MAX_TESS_LEVEL              0x00028A18

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 17e64b18e97e3dc3a7878973357d41cd616310a2..54cc79b15494f5996071b98ace2faa89a6f1f771 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -469,7 +469,7 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
        r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
        r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 
-       tmp = (unsigned)(state->line_width * 8.0);
+       tmp = (unsigned)state->line_width * 8;
        r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
 
        r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);