RISC-V: Add privileged extensions without instructions/CSRs

Currently, GNU Binutils does not support following privileged extensions:

-   'Smepmp'
-   'Svnapot'
-   'Svpbmt'

as they do not provide new CSRs or new instructions ('Smepmp' extends the
privileged architecture CSRs but does not define the CSR itself).  However,
adding them might be useful as we no longer have to "filter" ISA strings
just for toolchains (if full ISA string is given by a vendor, we can
straightly use it).

And there's a fact that supports this theory: there's already an
(unprivileged) extension which does not provide CSRs or instructions (but
only an architectural guarantee): 'Zkt' (constant timing guarantee for
certain subset of RISC-V instructions).

This simple commit simply adds three privileged extensions listed above.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_supported_std_s_ext): Add 'Smepmp',
	'Svnapot' and 'Svpbmt' extensions.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index fa393c7c427f557edc868bc927c4a36cee194fab..c67d4167232e07a5140082ad33c3480f986f278c 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1211,10 +1211,13 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 
 static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
+  {"smepmp",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"smstateen",                ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sscofpmf",         ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"sstc",             ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {"svinval",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"svnapot",          ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
+  {"svpbmt",           ISA_SPEC_CLASS_DRAFT,           1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };