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add new RC reg to get pywriter to build
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 May 2021 12:41:58 +0000 (13:41 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 17 May 2021 12:41:58 +0000 (13:41 +0100)
src/openpower/decoder/isa/caller.py patch | blob | history

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index c3e2e9a4fff919d13b51abf06af43a864b0ba10f..acbfc9424c35b53c73e697e06fd9d14249806546 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -62,6 +62,7 @@ REG_SORT_ORDER = {
     "RT": 0,
     "RA": 0,
     "RB": 0,
+    "RC": 0,
     "RS": 0,
     "CR": 0,
     "LR": 0,