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gas/testsuite/
authorRoland McGrath <roland@gnu.org>
Tue, 7 Aug 2012 18:22:04 +0000 (18:22 +0000)
committerRoland McGrath <roland@gnu.org>
Tue, 7 Aug 2012 18:22:04 +0000 (18:22 +0000)
* gas/i386/prefetch.s: New file.
* gas/i386/prefetch.d: New file.
* gas/i386/prefetch-intel.d: New file.
* gas/i386/x86-64-prefetch.d: New file.
* gas/i386/x86-64-prefetch-intel.d: New file.
* gas/i386/i386.exp: Run them.

opcodes/
* i386-dis.c (reg_table): Fill out REG_0F0D table with
AMD-reserved cases as "prefetch".
(MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
(MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
(reg_table): Use those under REG_0F18.
(mod_table): Add those cases as "nop/reserved".

gas/testsuite/ChangeLog patch | blob | history
gas/testsuite/gas/i386/i386.exp patch | blob | history
gas/testsuite/gas/i386/prefetch-intel.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/i386/prefetch.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/i386/prefetch.s [new file with mode: 0644] patch | blob
gas/testsuite/gas/i386/x86-64-prefetch-intel.d [new file with mode: 0644] patch | blob
gas/testsuite/gas/i386/x86-64-prefetch.d [new file with mode: 0644] patch | blob
opcodes/ChangeLog patch | blob | history
opcodes/i386-dis.c patch | blob | history

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 56a01d8fd3f50031246f38c1a43af68c13246af3..57b39a39fe25643ae83fa8827c793379d0a9c316 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2012-08-07  Roland McGrath  <mcgrathr@google.com>
+
+       * gas/i386/prefetch.s: New file.
+       * gas/i386/prefetch.d: New file.
+       * gas/i386/prefetch-intel.d: New file.
+       * gas/i386/x86-64-prefetch.d: New file.
+       * gas/i386/x86-64-prefetch-intel.d: New file.
+       * gas/i386/i386.exp: Run them.
+
 2012-08-07  Jan Beulich <jbeulich@suse.com>
 
        * gas/i386/x86-64-segovr.{s,l}: New.
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 82cef63ab9ccf422a3f0910540b0459247cfcd33..7b93babb67de0874779a0717e5ae11d6177e78e6 100644 (file)
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -216,6 +216,8 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "adx-intel"
     run_dump_test "rdseed"
     run_dump_test "rdseed-intel"
+    run_dump_test "prefetch"
+    run_dump_test "prefetch-intel"
 
     # These tests require support for 8 and 16 bit relocs,
     # so we only run them for ELF and COFF targets.
@@ -457,6 +459,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
     run_dump_test "x86-64-adx-intel"
     run_dump_test "x86-64-rdseed"
     run_dump_test "x86-64-rdseed-intel"
+    run_dump_test "x86-64-prefetch"
+    run_dump_test "x86-64-prefetch-intel"
 
     if { ![istarget "*-*-aix*"]
       && ![istarget "*-*-beos*"]
diff --git a/gas/testsuite/gas/i386/prefetch-intel.d b/gas/testsuite/gas/i386/prefetch-intel.d
new file mode 100644 (file)
index 0000000..fbdd2ef
--- /dev/null
+++ b/gas/testsuite/gas/i386/prefetch-intel.d
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: i386 prefetch (Intel disassembly)
+#source: prefetch.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <amd_prefetch>:
+\s*[a-f0-9]+:  0f 0d 00                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 08                prefetchw BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 10                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 18                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 20                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 28                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 30                prefetch BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 0d 38                prefetch BYTE PTR \[eax\]
+
+0+[0-9a-f]+ <intel_prefetch>:
+\s*[a-f0-9]+:  0f 18 00                prefetchnta BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 08                prefetcht0 BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 10                prefetcht1 BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 18                prefetcht2 BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 20                nop/reserved BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 28                nop/reserved BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 30                nop/reserved BYTE PTR \[eax\]
+\s*[a-f0-9]+:  0f 18 38                nop/reserved BYTE PTR \[eax\]
diff --git a/gas/testsuite/gas/i386/prefetch.d b/gas/testsuite/gas/i386/prefetch.d
new file mode 100644 (file)
index 0000000..13980bc
--- /dev/null
+++ b/gas/testsuite/gas/i386/prefetch.d
@@ -0,0 +1,26 @@
+#objdump: -dw
+#name: i386 prefetch
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <amd_prefetch>:
+\s*[a-f0-9]+:  0f 0d 00                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 08                prefetchw \(%eax\)
+\s*[a-f0-9]+:  0f 0d 10                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 18                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 20                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 28                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 30                prefetch \(%eax\)
+\s*[a-f0-9]+:  0f 0d 38                prefetch \(%eax\)
+
+0+[0-9a-f]+ <intel_prefetch>:
+\s*[a-f0-9]+:  0f 18 00                prefetchnta \(%eax\)
+\s*[a-f0-9]+:  0f 18 08                prefetcht0 \(%eax\)
+\s*[a-f0-9]+:  0f 18 10                prefetcht1 \(%eax\)
+\s*[a-f0-9]+:  0f 18 18                prefetcht2 \(%eax\)
+\s*[a-f0-9]+:  0f 18 20                nop/reserved \(%eax\)
+\s*[a-f0-9]+:  0f 18 28                nop/reserved \(%eax\)
+\s*[a-f0-9]+:  0f 18 30                nop/reserved \(%eax\)
+\s*[a-f0-9]+:  0f 18 38                nop/reserved \(%eax\)
diff --git a/gas/testsuite/gas/i386/prefetch.s b/gas/testsuite/gas/i386/prefetch.s
new file mode 100644 (file)
index 0000000..c0f92ae
--- /dev/null
+++ b/gas/testsuite/gas/i386/prefetch.s
@@ -0,0 +1,18 @@
+.macro try opcode:vararg
+       .byte \opcode, 0x00
+       .byte \opcode, 0x08
+       .byte \opcode, 0x10
+       .byte \opcode, 0x18
+       .byte \opcode, 0x20
+       .byte \opcode, 0x28
+       .byte \opcode, 0x30
+       .byte \opcode, 0x38
+.endm
+
+.text
+
+amd_prefetch:
+       try 0x0f, 0x0d
+
+intel_prefetch:
+       try 0x0f, 0x18
diff --git a/gas/testsuite/gas/i386/x86-64-prefetch-intel.d b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d
new file mode 100644 (file)
index 0000000..9941946
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetch-intel.d
@@ -0,0 +1,27 @@
+#objdump: -dw -Mintel
+#name: x86-64 prefetch (Intel disassembly)
+#source: prefetch.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <amd_prefetch>:
+\s*[a-f0-9]+:  0f 0d 00                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 08                prefetchw BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 10                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 18                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 20                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 28                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 30                prefetch BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 0d 38                prefetch BYTE PTR \[rax\]
+
+0+[0-9a-f]+ <intel_prefetch>:
+\s*[a-f0-9]+:  0f 18 00                prefetchnta BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 08                prefetcht0 BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 10                prefetcht1 BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 18                prefetcht2 BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 20                nop/reserved BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 28                nop/reserved BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 30                nop/reserved BYTE PTR \[rax\]
+\s*[a-f0-9]+:  0f 18 38                nop/reserved BYTE PTR \[rax\]
diff --git a/gas/testsuite/gas/i386/x86-64-prefetch.d b/gas/testsuite/gas/i386/x86-64-prefetch.d
new file mode 100644 (file)
index 0000000..476d9f2
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-prefetch.d
@@ -0,0 +1,27 @@
+#objdump: -dw
+#name: x86-64 prefetch
+#source: prefetch.s
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <amd_prefetch>:
+\s*[a-f0-9]+:  0f 0d 00                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 08                prefetchw \(%rax\)
+\s*[a-f0-9]+:  0f 0d 10                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 18                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 20                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 28                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 30                prefetch \(%rax\)
+\s*[a-f0-9]+:  0f 0d 38                prefetch \(%rax\)
+
+0+[0-9a-f]+ <intel_prefetch>:
+\s*[a-f0-9]+:  0f 18 00                prefetchnta \(%rax\)
+\s*[a-f0-9]+:  0f 18 08                prefetcht0 \(%rax\)
+\s*[a-f0-9]+:  0f 18 10                prefetcht1 \(%rax\)
+\s*[a-f0-9]+:  0f 18 18                prefetcht2 \(%rax\)
+\s*[a-f0-9]+:  0f 18 20                nop/reserved \(%rax\)
+\s*[a-f0-9]+:  0f 18 28                nop/reserved \(%rax\)
+\s*[a-f0-9]+:  0f 18 30                nop/reserved \(%rax\)
+\s*[a-f0-9]+:  0f 18 38                nop/reserved \(%rax\)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 77063ce7c612c50ee8093e9a1daed00585cb8a6a..0b55bb80402e96537dabe4e5865c0ecf5c89943b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2012-08-07  Roland McGrath  <mcgrathr@google.com>
+
+       * i386-dis.c (reg_table): Fill out REG_0F0D table with
+       AMD-reserved cases as "prefetch".
+       (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
+       (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
+       (reg_table): Use those under REG_0F18.
+       (mod_table): Add those cases as "nop/reserved".
+
 2012-08-07  Jan Beulich <jbeulich@suse.com>
 
        * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index da5ede57d2ec08ade10947753fd657187b2cd6cb..15c968a5290165d392ffad03972d00191b8c00a9 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -668,6 +668,10 @@ enum
   MOD_0F18_REG_1,
   MOD_0F18_REG_2,
   MOD_0F18_REG_3,
+  MOD_0F18_REG_4,
+  MOD_0F18_REG_5,
+  MOD_0F18_REG_6,
+  MOD_0F18_REG_7,
   MOD_0F20,
   MOD_0F21,
   MOD_0F22,
@@ -2652,6 +2656,12 @@ static const struct dis386 reg_table[][8] = {
   {
     { "prefetch",      { Mb } },
     { "prefetchw",     { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
+    { "prefetch",      { Mb } },
   },
   /* REG_0F18 */
   {
@@ -2659,6 +2669,10 @@ static const struct dis386 reg_table[][8] = {
     { MOD_TABLE (MOD_0F18_REG_1) },
     { MOD_TABLE (MOD_0F18_REG_2) },
     { MOD_TABLE (MOD_0F18_REG_3) },
+    { MOD_TABLE (MOD_0F18_REG_4) },
+    { MOD_TABLE (MOD_0F18_REG_5) },
+    { MOD_TABLE (MOD_0F18_REG_6) },
+    { MOD_TABLE (MOD_0F18_REG_7) },
   },
   /* REG_0F71 */
   {
@@ -10220,6 +10234,22 @@ static const struct dis386 mod_table[][2] = {
     /* MOD_0F18_REG_3 */
     { "prefetcht2",    { Mb } },
   },
+  {
+    /* MOD_0F18_REG_4 */
+    { "nop/reserved",  { Mb } },
+  },
+  {
+    /* MOD_0F18_REG_5 */
+    { "nop/reserved",  { Mb } },
+  },
+  {
+    /* MOD_0F18_REG_6 */
+    { "nop/reserved",  { Mb } },
+  },
+  {
+    /* MOD_0F18_REG_7 */
+    { "nop/reserved",  { Mb } },
+  },
   {
     /* MOD_0F20 */
     { Bad_Opcode },