GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.

diff --git a/src/SConscript b/src/SConscript
index 7c6bcd8462f0270c7bf93378f7e97e3804aa163e..391a832bab3798d5fa5cc4871ca6d6b2ad73a827 100755 (executable)
--- a/src/SConscript
+++ b/src/SConscript
@@ -851,6 +851,8 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
         swig_env.Append(CCFLAGS='-Wno-uninitialized')
         swig_env.Append(CCFLAGS='-Wno-sign-compare')
         swig_env.Append(CCFLAGS='-Wno-parentheses')
+        swig_env.Append(CCFLAGS='-Wno-unused-label')
+        swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
 
     werror_env = new_env.Clone()
     werror_env.Append(CCFLAGS='-Werror')

diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 2bc913f92e0b1ef4045968788d1fedec6964aa85..6259f8fc21dc4d62e24f61342686d534c8ac01b1 100644 (file)
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -209,8 +209,6 @@ int break_ipl = -1;
 void
 ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 {
-    uint64_t old;
-
     if (tc->misspeculating())
         return;
 
@@ -262,12 +260,11 @@ ISA::setIpr(int idx, uint64_t val, ThreadContext *tc)
 
       case IPR_PALtemp23:
         // write entire quad w/ no side-effect
-        old = ipr[idx];
-        ipr[idx] = val;
 #if FULL_SYSTEM
         if (tc->getKernelStats())
-            tc->getKernelStats()->context(old, val, tc);
+            tc->getKernelStats()->context(ipr[idx], val, tc);
 #endif
+        ipr[idx] = val;
         break;
 
       case IPR_DTB_PTE:

diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index ed5128204dd1ccc77458c37caceeac98a9e3ebc1..f286be91cd3624497b3f448461daf52ff99176cf 100644 (file)
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -388,7 +388,7 @@ def template MiscExecute {{
     Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Addr EA;
+        Addr EA M5_VAR_USED;
         Fault fault = NoFault;
 
         %(fp_enable_check)s;

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 812338c301b514f93f317459bb05c9c2756ff1fb..0cb27d7f17396887af7320bfde593803d28e422d 100644 (file)
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -561,20 +561,22 @@ let {{
                 }
             }
           case 0xa:
+            if (q)
+                return new Unknown(machInst);
             if (b) {
-                return decodeNeonUSThreeReg<VpminD, VpminQ>(
-                        q, u, size, machInst, vd, vn, vm);
+                return decodeNeonUSThreeUSReg<VpminD>(
+                        u, size, machInst, vd, vn, vm);
             } else {
-                return decodeNeonUSThreeReg<VpmaxD, VpmaxQ>(
-                        q, u, size, machInst, vd, vn, vm);
+                return decodeNeonUSThreeUSReg<VpmaxD>(
+                        u, size, machInst, vd, vn, vm);
             }
           case 0xb:
             if (b) {
-                if (u) {
+                if (u || q) {
                     return new Unknown(machInst);
                 } else {
-                    return decodeNeonUThreeReg<NVpaddD, NVpaddQ>(
-                            q, size, machInst, vd, vn, vm);
+                    return decodeNeonUThreeUSReg<NVpaddD>(
+                            size, machInst, vd, vn, vm);
                 }
             } else {
                 if (u) {
@@ -1542,7 +1544,7 @@ let {{
                 else
                     return new NVswpD<uint64_t>(machInst, vd, vm);
               case 0x1:
-                return decodeNeonUTwoMiscReg<NVtrnD, NVtrnQ>(
+                return decodeNeonUTwoMiscSReg<NVtrnD, NVtrnQ>(
                         q, size, machInst, vd, vm);
               case 0x2:
                 return decodeNeonUTwoMiscReg<NVuzpD, NVuzpQ>(

diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index f82858bbdaae11e2541c0fcb04f0ae036e3e1ff2..b701995f402e2c41fd366f0c883ea76af631b504 100644 (file)
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -447,7 +447,7 @@ let {{
     exec_output = ""
 
     singleSimpleCode = vfpEnabledCheckCode + '''
-        FPSCR fpscr = (FPSCR) FpscrExc;
+        FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
         FpDest = %(op)s;
     '''
     singleCode = singleSimpleCode + '''
@@ -457,7 +457,7 @@ let {{
                 "%(func)s, fpscr.fz, fpscr.dn, fpscr.rMode)"
     singleUnaryOp = "unaryOp(fpscr, FpOp1, %(func)s, fpscr.fz, fpscr.rMode)"
     doubleCode = vfpEnabledCheckCode + '''
-        FPSCR fpscr = (FPSCR) FpscrExc;
+        FPSCR fpscr M5_VAR_USED = (FPSCR) FpscrExc;
         double dest = %(op)s;
         FpDestP0_uw = dblLow(dest);
         FpDestP1_uw = dblHi(dest);

diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa
index e891a0a91ac12b9f6b064c1f039132d84c201e3f..3b837cba9837c58808c90db7f7b691e498fb0095 100644 (file)
--- a/src/arch/arm/isa/insts/m5ops.isa
+++ b/src/arch/arm/isa/insts/m5ops.isa
@@ -54,9 +54,7 @@ let {{
 
 
     armCode = '''
-#if FULL_SYSTEM
     PseudoInst::arm(xc->tcBase());
-#endif
     '''
     armIop = InstObjParams("arm", "Arm", "PredOp",
                            { "code": armCode,
@@ -67,9 +65,7 @@ let {{
     exec_output += PredOpExecute.subst(armIop)
 
     quiesceCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesce(xc->tcBase());
-#endif
     '''
     quiesceIop = InstObjParams("quiesce", "Quiesce", "PredOp",
                            { "code": quiesceCode,
@@ -80,9 +76,7 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceIop)
 
     quiesceNsCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesceNs(xc->tcBase(), join32to64(R1, R0));
-#endif
     '''
 
     quiesceNsIop = InstObjParams("quiesceNs", "QuiesceNs", "PredOp",
@@ -94,9 +88,7 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceNsIop)
 
     quiesceCyclesCode = '''
-#if FULL_SYSTEM
     PseudoInst::quiesceCycles(xc->tcBase(), join32to64(R1, R0));
-#endif
     '''
 
     quiesceCyclesIop = InstObjParams("quiesceCycles", "QuiesceCycles", "PredOp",
@@ -108,11 +100,9 @@ let {{
     exec_output += QuiescePredOpExecute.subst(quiesceCyclesIop)
 
     quiesceTimeCode = '''
-#if FULL_SYSTEM
     uint64_t qt_val = PseudoInst::quiesceTime(xc->tcBase());
     R0 = bits(qt_val, 31, 0);
     R1 = bits(qt_val, 63, 32);
-#endif
     '''
 
     quiesceTimeIop = InstObjParams("quiesceTime", "QuiesceTime", "PredOp",
@@ -188,9 +178,7 @@ let {{
     exec_output += PredOpExecute.subst(m5exitIop)
 
     loadsymbolCode = '''
-#if FULL_SYSTEM
     PseudoInst::loadsymbol(xc->tcBase());
-#endif
     '''
 
     loadsymbolIop = InstObjParams("loadsymbol", "Loadsymbol", "PredOp",
@@ -204,6 +192,9 @@ let {{
     initparamCode = '''
 #if FULL_SYSTEM
     Rt = PseudoInst::initParam(xc->tcBase());
+#else
+    PseudoInst::panicFsOnlyPseudoInst("initparam");
+    Rt = 0;
 #endif
     '''
 
@@ -260,11 +251,9 @@ let {{
     exec_output += PredOpExecute.subst(m5checkpointIop)
 
     m5readfileCode = '''
-#if FULL_SYSTEM
     int n = 4;
     uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false);
     R0 = PseudoInst::readfile(xc->tcBase(), R0, join32to64(R3,R2), offset);
-#endif
     '''
     m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
                            { "code": m5readfileCode,
@@ -291,9 +280,7 @@ let {{
     exec_output += PredOpExecute.subst(m5switchcpuIop)
 
     m5addsymbolCode = '''
-#if FULL_SYSTEM
     PseudoInst::addsymbol(xc->tcBase(), join32to64(R1, R0), R2);
-#endif
     '''
     m5addsymbolIop = InstObjParams("m5addsymbol", "M5addsymbol", "PredOp",
                            { "code": m5addsymbolCode,

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 815d4c258f4c8e23b96f98bed11a4894c517aab9..db36a3fff8a1ab7a1e6deffee3181bb9e400cc7b 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -563,15 +563,16 @@ let {{
 
 let {{
     exec_output = ''
-    for type in ('uint8_t', 'uint16_t', 'uint32_t'):
+    for typeSize in (8, 16, 32):
         for sRegs in 1, 2:
-            for dRegs in range(sRegs, 5):
+            for dRegs in range(sRegs, min(sRegs * 64 / typeSize + 1, 5)):
                 for format in ("MicroUnpackNeon%(sRegs)dto%(dRegs)dUop",
                                "MicroUnpackAllNeon%(sRegs)dto%(dRegs)dUop",
                                "MicroPackNeon%(dRegs)dto%(sRegs)dUop"):
                     Name = format % { "sRegs" : sRegs * 2,
                                       "dRegs" : dRegs * 2 }
-                    substDict = { "class_name" : Name, "targs" : type }
+                    substDict = { "class_name" : Name,
+                                  "targs" : "uint%d_t" % typeSize }
                     exec_output += MicroNeonExecDeclare.subst(substDict)
 }};
 

diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index fdb6237c0cc0a26d3ab3543d91bb1d1a70188c98..dd0d49a5cf875642add6b248ec62ef03c13d1b3f 100644 (file)
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -1619,10 +1619,8 @@ let {{
     threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode)
     threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode)
 
-    threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", unsignedTypes,
+    threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes,
                       2, vaddCode, pairwise=True)
-    threeEqualRegInst("vpadd", "NVpaddQ", "SimdAddOp", unsignedTypes,
-                      4, vaddCode, pairwise=True)
     vaddlwCode = '''
         destElem = (BigElement)srcElem1 + (BigElement)srcElem2;
     '''
@@ -2113,11 +2111,9 @@ let {{
     '''
     threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode)
 
-    threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", allTypes, 2, vmaxCode, pairwise=True)
-    threeEqualRegInst("vpmax", "VpmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode, pairwise=True)
+    threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True)
 
-    threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", allTypes, 2, vminCode, pairwise=True)
-    threeEqualRegInst("vpmin", "VpminQ", "SimdCmpOp", allTypes, 4, vminCode, pairwise=True)
+    threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True)
 
     vqdmulhCode = '''
         FPSCR fpscr = (FPSCR) FpscrQc;
@@ -3140,8 +3136,10 @@ let {{
             destReg.elements[i + 1] = mid;
         }
     '''
-    twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", unsignedTypes, 2, vtrnCode)
-    twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", unsignedTypes, 4, vtrnCode)
+    twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp",
+            smallUnsignedTypes, 2, vtrnCode)
+    twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp",
+            smallUnsignedTypes, 4, vtrnCode)
 
     vuzpCode = '''
         Element mid[eCount];

diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index a00114409646b577c59170697abd313c85e24e64..a4a740f89ebfd9bbf4640e0e5c6791cdcd6fb59d 100644 (file)
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1112,7 +1112,7 @@ def template LoadRegConstructor {{
                  (IntRegIndex)_index)
     {
         %(constructor)s;
-        bool conditional = false;
+        bool conditional M5_VAR_USED = false;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {
@@ -1166,7 +1166,7 @@ def template LoadImmConstructor {{
                  (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
     {
         %(constructor)s;
-        bool conditional = false;
+        bool conditional M5_VAR_USED = false;
         if (!(condCode == COND_AL || condCode == COND_UC)) {
             conditional = true;
             for (int x = 0; x < _numDestRegs; x++) {

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 7b8dafdba95bf60160132e57607e97d2746aba87..179e409dd5bcb5b3ea026539413fef366484bf83 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() {
                             0x2: mttc1({{
                                 uint64_t data = xc->readRegOtherThread(RD +
                                                                        FP_Base_DepTag);
-                                data = insertBits(data, top_bit,
-                                                  bottom_bit, Rt);
+                                data = insertBits(data, MT_H ? 63 : 31,
+                                                  MT_H ? 32 : 0, Rt);
                                 xc->setRegOtherThread(RD + FP_Base_DepTag,
                                                       data);
                             }});
@@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() {
                                     panic("FP Control Value (%d) "
                                             "Not Available. Ignoring "
                                             "Access to Floating Control "
-                                            "Status Register", FS);
+                                            "S""tatus Register", FS);
                                 }
                                 xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data);
                             }});
@@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        IndexReg index = Index;
                         Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP);
                     }});
                     0x06: tlbwr({{
@@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() {
                             bits(pageGrain, pageGrain.esp) == 1) {
                             SP = 1;
                         }
-                        IndexReg index = Index;
                         Ptr->insertAt(newEntry, Random, SP);
                     }});
 

diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index 1944d69d3c2fc0239a5441c6c6ffb3f4891cce7b..41f94e12979982b17e8e95c889e70a06f277780f 100644 (file)
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -107,7 +107,7 @@ def template ThreadRegisterExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
-            int64_t data;
+            int64_t data M5_VAR_USED;
             %(op_decl)s;
             %(op_rd)s;
 
@@ -126,17 +126,6 @@ def template ThreadRegisterExecute {{
                 } else if (vpeControl.targTC > mvpConf0.ptc) {
                     data = -1;
                 } else {
-                    int top_bit = 0;
-                    int bottom_bit = 0;
-
-                    if (MT_H == 1) {
-                        top_bit = 63;
-                        bottom_bit = 32;
-                    } else {
-                        top_bit = 31;
-                        bottom_bit = 0;
-                    }
-
                     %(code)s;
                 }
             } else {
@@ -203,10 +192,11 @@ def format MT_MFTR(code, *flags) {{
         flags += ('IsNonSpeculative', )
 #        code = 'std::cerr << curTick() << \": T\" << xc->tcBase()->threadId() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
 
-        code += 'if (MT_H == 1) {\n'
-        code += 'data = bits(data, top_bit, bottom_bit);\n'
-        code += '}\n'
-        code += 'Rd = data;\n'
+        code += '''
+            if (MT_H)
+                data = bits(data, 63, 32);
+            Rd = data;
+        '''
 
         iop = InstObjParams(name, Name, 'MTOp', code, flags)
         header_output = BasicDeclare.subst(iop)

diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index c9f5da41d97dee4cb170a2daef46f3019311fac0..4ce03b1c2da93a3d72a6d18cb2cb822c531da56b 100644 (file)
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -52,7 +52,9 @@ output decoder {{
 #include "arch/mips/faults.hh"
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/mt_constants.hh"
+#include "arch/mips/pagetable.hh"
 #include "arch/mips/pra_constants.hh"
+#include "arch/mips/tlb.hh"
 #include "arch/mips/utility.hh"
 #include "base/loader/symtab.hh"
 #include "base/cprintf.hh"

diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index e35ac6d4abdfdf8dbc53c4fa69a31ea4768f5272..57d8849e1d275cc19c796383093058fdff5cd2c8 100644 (file)
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -129,7 +129,6 @@ int
 TLB::probeEntry(Addr vpn, uint8_t asn) const
 {
     // assume not found...
-    PTE *retval = NULL;
     int Ind = -1;
     PageTable::const_iterator i = lookupTable.find(vpn);
     if (i != lookupTable.end()) {
@@ -144,7 +143,6 @@ TLB::probeEntry(Addr vpn, uint8_t asn) const
             if (((vpn & InvMask) == (VPN & InvMask)) &&
                     (pte->G  || (asn == pte->asid))) {
                 // We have a VPN + ASID Match
-                retval = pte;
                 Ind = index;
                 break;
             }

diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 0361ee998be2ebbdd3b9f3f0fcf69485cc19879b..a409eefac756b95b4dbf914c3a5265a621a6ca99 100644 (file)
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -123,7 +123,7 @@ def template LoadCompleteAcc {{
                                       %(CPU_exec_context)s *xc,
                                       Trace::InstRecord *traceData) const
     {
-        Addr EA;
+        Addr M5_VAR_USED EA;
         Fault fault = NoFault;
 
         %(op_decl)s;

diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 8a088032c77b38cb61dfbbf823e39307402d5a21..0b3edd5a2dc910ad1c8c300a4a094d7f838a8a3e 100644 (file)
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -118,7 +118,6 @@ int
 TLB::probeEntry(Addr vpn,uint8_t asn) const
 {
     // assume not found...
-    PowerISA::PTE *retval = NULL;
     int Ind = -1;
     PageTable::const_iterator i = lookupTable.find(vpn);
     if (i != lookupTable.end()) {
@@ -132,7 +131,6 @@ TLB::probeEntry(Addr vpn,uint8_t asn) const
                 && (pte->G  || (asn == pte->asid))) {
 
                 // We have a VPN + ASID Match
-                retval = pte;
                 Ind = index;
                 break;
             }

diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 06206c02bed4cfd8060f897318df5785dbb0b9c5..0ca56252e7d688bfd0b90b412dbcae37db1cde78 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -326,9 +326,8 @@ let {{
     '''
 
     TruncateEA = '''
-#if !FULL_SYSTEM
-                EA = Pstate<3:> ? EA<31:0> : EA;
-#endif
+        if (!FULL_SYSTEM)
+            EA = Pstate<3:> ? EA<31:0> : EA;
     '''
 }};
 

diff --git a/src/arch/x86/isa/microops/base.isa b/src/arch/x86/isa/microops/base.isa
index 664f91860ab6b40acd9256fbcbfbf62f39cb9a75..5798ac4b09e1d8c588cc12602494f5a830cef51e 100644 (file)
--- a/src/arch/x86/isa/microops/base.isa
+++ b/src/arch/x86/isa/microops/base.isa
@@ -59,7 +59,8 @@ let {{
             ''' + generatorNameTemplate + '''(StaticInstPtr curMacroop)
             {
                 static const char *macrocodeBlock = romMnemonic;
-                static const ExtMachInst dummyExtMachInst;
+                static const ExtMachInst dummyExtMachInst = \
+                    X86ISA::NoopMachInst;
                 static const EmulEnv dummyEmulEnv(0, 0, 1, 1, 1);
 
                 Macroop * macroop = dynamic_cast<Macroop *>(curMacroop.get());

diff --git a/src/base/inet.cc b/src/base/inet.cc
index 0fb864dab927f9fc126982976011e14c904ec762..7d7eb3f5abdcb854683df88e587f7d0373727881 100644 (file)
--- a/src/base/inet.cc
+++ b/src/base/inet.cc
@@ -30,6 +30,7 @@
  *          Gabe Black
  */
 
+#include <cstddef>
 #include <cstdio>
 #include <sstream>
 #include <string>

diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 1e25a5982e456f8cc6e45acee2405dfab162a286..76c7c964b19a4cdd4fd9f3f1890386a32e33dde8 100644 (file)
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -240,8 +240,7 @@ BaseCPU::startup()
     if (params()->progress_interval) {
         Tick num_ticks = ticks(params()->progress_interval);
 
-        Event *event;
-        event = new CPUProgressEvent(this, num_ticks);
+        new CPUProgressEvent(this, num_ticks);
     }
 }
 

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 07a013afc71ac2483c94605c3311c70827052d63..232554db2ee1a54bab372af0cb8c912c2d7feb9d 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -211,7 +211,6 @@ InOrderCPU::InOrderCPU(Params *params)
       lastRunningCycle(0),
       instsPerSwitch(0)
 {    
-    ThreadID active_threads;
     cpu_params = params;
 
     resPool = new ResourcePool(this, params);
@@ -219,10 +218,8 @@ InOrderCPU::InOrderCPU(Params *params)
     // Resize for Multithreading CPUs
     thread.resize(numThreads);
 
-#if FULL_SYSTEM
-    active_threads = 1;
-#else
-    active_threads = params->workload.size();
+#if !FULL_SYSTEM
+    ThreadID active_threads = params->workload.size();
 
     if (active_threads > MaxThreads) {
         panic("Workload Size too large. Increase the 'MaxThreads'"
@@ -1124,7 +1121,6 @@ InOrderCPU::updateThreadPriority()
         //DEFAULT TO ROUND ROBIN SCHEME
         //e.g. Move highest priority to end of thread list
         list<ThreadID>::iterator list_begin = activeThreads.begin();
-        list<ThreadID>::iterator list_end   = activeThreads.end();
 
         unsigned high_thread = *list_begin;
 

diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index 484af1008b279be9fe65fd6784b7a76706f55635..aa8e99fd11dfb2d592d4616bcb2059d5969aaf25 100644 (file)
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -167,7 +167,7 @@ Trace::LegionTraceRecord::dump()
     bool diffTnpc = false;
     bool diffTstate = false;
     bool diffTt = false;
-    bool diffTba = false;
+    bool diffTba M5_VAR_USED = false;
     bool diffHpstate = false;
     bool diffHtstate = false;
     bool diffHtba = false;

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 441bd43898dc36b5fd5ed4fd44de98dec91bd822..819495d622cb9b9e7be9adce215bbcf5e2c22b01 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1653,7 +1653,6 @@ FullO3CPU<Impl>::updateThreadPriority()
         //DEFAULT TO ROUND ROBIN SCHEME
         //e.g. Move highest priority to end of thread list
         list<ThreadID>::iterator list_begin = activeThreads.begin();
-        list<ThreadID>::iterator list_end   = activeThreads.end();
 
         unsigned high_thread = *list_begin;
 

diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index ee67c14f9c903f0d74349a6591882ec728cafd21..fc93a51970973956b298f64b2838e3bcf369b269 100644 (file)
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -1215,24 +1215,16 @@ template <class Impl>
 void
 DefaultRename<Impl>::readFreeEntries(ThreadID tid)
 {
-    bool updated = false;
-    if (fromIEW->iewInfo[tid].usedIQ) {
-        freeEntries[tid].iqEntries =
-            fromIEW->iewInfo[tid].freeIQEntries;
-        updated = true;
-    }
+    if (fromIEW->iewInfo[tid].usedIQ)
+        freeEntries[tid].iqEntries = fromIEW->iewInfo[tid].freeIQEntries;
 
-    if (fromIEW->iewInfo[tid].usedLSQ) {
-        freeEntries[tid].lsqEntries =
-            fromIEW->iewInfo[tid].freeLSQEntries;
-        updated = true;
-    }
+    if (fromIEW->iewInfo[tid].usedLSQ)
+        freeEntries[tid].lsqEntries = fromIEW->iewInfo[tid].freeLSQEntries;
 
     if (fromCommit->commitInfo[tid].usedROB) {
         freeEntries[tid].robEntries =
             fromCommit->commitInfo[tid].freeROBEntries;
         emptyROB[tid] = fromCommit->commitInfo[tid].emptyROB;
-        updated = true;
     }
 
     DPRINTF(Rename, "[tid:%i]: Free IQ: %i, Free ROB: %i, Free LSQ: %i\n",

diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 113ad8b4dff24b079fffd6e82b7c0a1aa07ceb1b..71c3ba48ca4d3b9da67f8e2c5e6215102807cfb4 100644 (file)
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -393,10 +393,8 @@ IIC::freeReplacementBlock(PacketList & writebacks)
 unsigned long
 IIC::getFreeDataBlock(PacketList & writebacks)
 {
-    struct IICTag *tag_ptr;
     unsigned long data_ptr;
 
-    tag_ptr = NULL;
     /* find data block */
     while (blkFreelist.empty()) {
         freeReplacementBlock(writebacks);

diff --git a/src/mem/ruby/network/orion/Clock.cc b/src/mem/ruby/network/orion/Clock.cc
index 500d6580b60cd77562d57420a8ed314f2eedc4db..fda18cd641377bed649e1c14a60039cf566406c7 100644 (file)
--- a/src/mem/ruby/network/orion/Clock.cc
+++ b/src/mem/ruby/network/orion/Clock.cc
@@ -137,13 +137,10 @@ void Clock::init()
 
         double router_diagonal = m_orion_cfg_ptr->get<double>("ROUTER_DIAGONAL");
         double Clockwire = m_tech_param_ptr->get_ClockCap();
-        double Reswire = m_tech_param_ptr->get_Reswire();
 
         double htree_clockcap;
-        double htree_res;
         int k;
         double h;
-        double cap_clock_buf = 0;
 
         double BufferNMOSOffCurrent = m_tech_param_ptr->get_BufferNMOSOffCurrent();
         double BufferPMOSOffCurrent = m_tech_param_ptr->get_BufferPMOSOffCurrent();
@@ -151,7 +148,6 @@ void Clock::init()
         if (m_tech_param_ptr->is_trans_type_hvt() || m_tech_param_ptr->is_trans_type_nvt())
         {
             htree_clockcap = (4+4+2+2)*(router_diagonal*1e-6)*Clockwire;
-            htree_res = (4+4+2+2)*(router_diagonal*1e-6)*Reswire;
 
             wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));
             i_static_nmos = BufferNMOSOffCurrent*h*k*15;
@@ -160,15 +156,12 @@ void Clock::init()
         else
         {
             htree_clockcap = (8+4+4+4+4)*(router_diagonal*1e-6)*Clockwire;
-            htree_res = (8+4+4+4+4)*(router_diagonal*1e-6)*Reswire;
 
             wire.calc_opt_buffering(&k, &h, ((4+4+2+2)*router_diagonal*1e-6));  
             i_static_nmos = BufferNMOSOffCurrent*h*k*29;
             i_static_pmos = BufferPMOSOffCurrent*h*k*15;
         }
 
-        cap_clock_buf = ((double)k)*cap_clock*h;
-
         m_e_htree = (htree_clockcap+cap_clock)*e_factor;
     }
     else

diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh
index 356406cbdaebb00823002cd1b872a06774a02ed0..d2f58b0db76a6f4683e1538ed08a1f9198451dda 100644 (file)
--- a/src/mem/ruby/system/PersistentTable.hh
+++ b/src/mem/ruby/system/PersistentTable.hh
@@ -41,6 +41,7 @@
 class PersistentTableEntry
 {
   public:
+    PersistentTableEntry() {}
     void print(std::ostream& out) const {}
 
     NetDest m_starving;

diff --git a/src/mem/ruby/system/PseudoLRUPolicy.hh b/src/mem/ruby/system/PseudoLRUPolicy.hh
index 1e1e681880e902bfc6cfe31fccbde01598d629d2..3cc2a5dfea81c3c4c9373e37df5dc64bb53dd1b7 100644 (file)
--- a/src/mem/ruby/system/PseudoLRUPolicy.hh
+++ b/src/mem/ruby/system/PseudoLRUPolicy.hh
@@ -64,8 +64,6 @@ inline
 PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc)
     : AbstractReplacementPolicy(num_sets, assoc)
 {
-    int num_tree_nodes;
-
     // associativity cannot exceed capacity of tree representation
     assert(num_sets > 0 && assoc > 1 && assoc <= (Index) sizeof(uint64)*4);
 
@@ -84,7 +82,6 @@ PseudoLRUPolicy::PseudoLRUPolicy(Index num_sets, Index assoc)
         m_num_levels++;
     }
     assert(m_num_levels < sizeof(unsigned int)*4);
-    num_tree_nodes = (1 << m_num_levels) - 1;
     m_trees = new uint64[m_num_sets];
     for (unsigned i = 0; i < m_num_sets; i++) {
         m_trees[i] = 0;

diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 4575e677f46c495c6cef648ed9f934a40a7cde06..ee3678dc9b7c8b31b0a38ab529941c162fb3f6f9 100644 (file)
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -164,6 +164,7 @@ class ParamDesc(object):
         return self.ptype(value)
 
     def cxx_predecls(self, code):
+        code('#include <cstddef>')
         self.ptype.cxx_predecls(code)
 
     def swig_predecls(self, code):

diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
index 7847a6f3ad2dfc7e3265e3bf6592506fc20c2bb4..c8555cd3153dec5bf2f78f8e1b3190679b24fb02 100644 (file)
--- a/src/python/swig/pyobject.cc
+++ b/src/python/swig/pyobject.cc
@@ -94,10 +94,6 @@ int
 connectPorts(SimObject *o1, const std::string &name1, int i1,
              SimObject *o2, const std::string &name2, int i2)
 {
-    MemObject *mo1, *mo2;
-    mo1 = dynamic_cast<MemObject*>(o1);
-    mo2 = dynamic_cast<MemObject*>(o2);
-
 #if FULL_SYSTEM
     EtherObject *eo1, *eo2;
     EtherDevice *ed1, *ed2;