soc/cores/pwm: remove debug print(n)

diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py
index 6b28c393d6e10d3a5e5699fc9d2520447ffe04df..f3167de8226cc42b1b75112505b34a1a70f4a4d2 100644 (file)
--- a/litex/soc/cores/pwm.py
+++ b/litex/soc/cores/pwm.py
@@ -54,7 +54,6 @@ class PWM(Module, AutoCSR):
         self._period = CSRStorage(32)
 
         n = 0 if clock_domain == "sys" else 2
-        print(n)
         self.specials += [
             MultiReg(self._enable.storage, self.enable, n=n),
             MultiReg(self._width.storage,  self.width,  n=n),