lasmicon: fix FSM reset state with delayed_enter

diff --git a/milkymist/lasmicon/bankmachine.py b/milkymist/lasmicon/bankmachine.py
index eb6d338d688184dfff02f4175d07cbfc3d073327..1bc5676dcb895717fb1200769baed2533f2ad1bc 100644 (file)
--- a/milkymist/lasmicon/bankmachine.py
+++ b/milkymist/lasmicon/bankmachine.py
@@ -93,8 +93,6 @@ class BankMachine(Module):
                # Control and command generation FSM
                fsm = FSM()
                self.submodules += fsm
-               fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
-               fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)
                fsm.act("REGULAR",
                        If(self.refresh_req,
                                NextState("REFRESH")
@@ -140,3 +138,5 @@ class BankMachine(Module):
                        track_close.eq(1),
                        If(~self.refresh_req, NextState("REGULAR"))
                )
+               fsm.delayed_enter("TRP", "ACTIVATE", timing_settings.tRP-1)
+               fsm.delayed_enter("TRCD", "REGULAR", timing_settings.tRCD-1)

diff --git a/milkymist/lasmicon/multiplexer.py b/milkymist/lasmicon/multiplexer.py
index b19cd65701a0a86904f229c9d084ea7a6b5ebc14..27978f941cd6d6dc3729fda2d239e5649dc3c4ed 100644 (file)
--- a/milkymist/lasmicon/multiplexer.py
+++ b/milkymist/lasmicon/multiplexer.py
@@ -149,8 +149,6 @@ class Multiplexer(Module, AutoCSR):
                # Control FSM
                fsm = FSM()
                self.submodules += fsm
-               fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
-               fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
                fsm.act("READ",
                        read_time_en.eq(1),
                        choose_req.want_reads.eq(1),
@@ -180,6 +178,8 @@ class Multiplexer(Module, AutoCSR):
                        steerer.sel[0].eq(STEER_REFRESH),
                        If(~refresher.req, NextState("READ"))
                )
+               fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
+               fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
                # FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
                fsm.finalize()
                self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])