#include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh"
#include "sim/annotation.hh"
-#include "sim/serialize.hh"
-#include "sim/sim_events.hh"
-#include "sim/sim_stats.hh"
+#include "sim/sim_exit.hh"
#ifdef FULL_SYSTEM
-#include "targetarch/ev5.hh"
+#include "arch/alpha/ev5.hh"
+#include "arch/alpha/pseudo_inst.hh"
#endif
namespace AlphaISA;
}}, No_OpClass);
0x20: m5exit_old({{
if (!xc->misspeculating())
- SimExit(curTick, "m5_exit_old instruction encountered");
+ AlphaPseudo::m5exit_old(xc);
}}, No_OpClass);
0x21: m5exit({{
- if (!xc->misspeculating()) {
- Tick delay = xc->regs.intRegFile[16];
- Tick when = curTick + NS2Ticks(delay);
- SimExit(when, "m5_exit instruction encountered");
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::m5exit(xc);
}}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{
- if (!xc->misspeculating()) {
- using namespace Statistics;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + NS2Ticks(delay);
- Tick repeat = NS2Ticks(period);
-
- SetupEvent(Reset, when, repeat);
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::resetstats(xc);
}});
0x41: dumpstats({{
- if (!xc->misspeculating()) {
- using namespace Statistics;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + NS2Ticks(delay);
- Tick repeat = NS2Ticks(period);
-
- SetupEvent(Dump, when, repeat);
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::dumpstats(xc);
}});
0x42: dumpresetstats({{
- if (!xc->misspeculating()) {
- using namespace Statistics;
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + NS2Ticks(delay);
- Tick repeat = NS2Ticks(period);
-
- SetupEvent(Dump|Reset, when, repeat);
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::dumpresetstats(xc);
}});
0x43: m5checkpoint({{
- if (!xc->misspeculating()) {
- Tick delay = xc->regs.intRegFile[16];
- Tick period = xc->regs.intRegFile[17];
-
- Tick when = curTick + NS2Ticks(delay);
- Tick repeat = NS2Ticks(period);
-
- SetupCheckpoint(when, repeat);
- }
+ if (!xc->misspeculating())
+ AlphaPseudo::m5checkpoint(xc);
}});
}
}
--- /dev/null
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/alpha/pseudo_inst.hh"
+#include "cpu/exec_context.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_exit.hh"
+#include "sim/sim_stats.hh"
+
+using namespace Statistics;
+
+namespace AlphaPseudo
+{
+ void
+ m5exit_old(ExecContext *xc)
+ {
+ SimExit(curTick, "m5_exit_old instruction encountered");
+ }
+
+ void
+ m5exit(ExecContext *xc)
+ {
+ Tick delay = xc->regs.intRegFile[16];
+ Tick when = curTick + NS2Ticks(delay);
+ SimExit(when, "m5_exit instruction encountered");
+ }
+
+ void
+ resetstats(ExecContext *xc)
+ {
+ Tick delay = xc->regs.intRegFile[16];
+ Tick period = xc->regs.intRegFile[17];
+
+ Tick when = curTick + NS2Ticks(delay);
+ Tick repeat = NS2Ticks(period);
+
+ SetupEvent(Reset, when, repeat);
+ }
+
+ void
+ dumpstats(ExecContext *xc)
+ {
+ Tick delay = xc->regs.intRegFile[16];
+ Tick period = xc->regs.intRegFile[17];
+
+ Tick when = curTick + NS2Ticks(delay);
+ Tick repeat = NS2Ticks(period);
+
+ SetupEvent(Dump, when, repeat);
+ }
+
+ void
+ dumpresetstats(ExecContext *xc)
+ {
+ Tick delay = xc->regs.intRegFile[16];
+ Tick period = xc->regs.intRegFile[17];
+
+ Tick when = curTick + NS2Ticks(delay);
+ Tick repeat = NS2Ticks(period);
+
+ SetupEvent(Dump|Reset, when, repeat);
+ }
+
+ void
+ m5checkpoint(ExecContext *xc)
+ {
+ Tick delay = xc->regs.intRegFile[16];
+ Tick period = xc->regs.intRegFile[17];
+
+ Tick when = curTick + NS2Ticks(delay);
+ Tick repeat = NS2Ticks(period);
+
+ SetupCheckpoint(when, repeat);
+ }
+
+}
--- /dev/null
+/*
+ * Copyright (c) 2003 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+class ExecContext;
+
+namespace AlphaPseudo
+{
+ void m5exit(ExecContext *xc);
+ void m5exit_old(ExecContext *xc);
+ void resetstats(ExecContext *xc);
+ void dumpstats(ExecContext *xc);
+ void dumpresetstats(ExecContext *xc);
+ void m5checkpoint(ExecContext *xc);
+}
return "simulation termination";
}
-void
-SimExit(Tick when, const char *message)
-{
- static SimExitEvent event(when, message);
-}
-
//
// constructor: automatically schedules at specified time
//
virtual const char *description();
};
-void SimExit(Tick when, const char *message);
-
//
// Event class to terminate simulation after 'n' related events have
// occurred using a shared counter: used to terminate when *all*
#include <string>
+#include "sim/host.hh"
+
class Callback;
void registerExitCallback(Callback *);
void exitNow(const std::string &cause, int exit_code);
void exitNow(const char *cause, int exit_code);
+void SimExit(Tick when, const char *message);
#endif // __SIM_EXIT_HH__
projects / gem5.git / commitdiff