tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index c8ef182b759247474f6d17d34f1da2787934b64a..8bae6b6b3b2983d1eadfda62726a766b562a9d12 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -124,6 +124,7 @@ class SimSoC(SoCSDRAM):
         # serial
         self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial"))
         self.submodules.uart = uart.UART(self.uart_phy)
+        self.add_csr("uart")
         self.add_interrupt("uart")
 
         # sdram