Fix S/R conflicts

This commit fixes S/R conflicts introduced by commit 6f9be93.

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 1c86c7895716545a595fdf0e96c52fe6398fc882..b9e721415427287aa73aadb948f10a1388ddfd4a 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -742,12 +742,13 @@ module_body:
        module_body module_body_stmt |
        /* the following line makes the generate..endgenrate keywords optional */
        module_body gen_stmt |
+       module_body ';' |
        /* empty */;
 
 module_body_stmt:
        task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt |
        enum_decl | struct_decl |
-       always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';';
+       always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block;
 
 checker_decl:
        TOK_CHECKER TOK_ID ';' {