+2021-03-05 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * riscv-tdep.c (riscv_feature_name_csr): Define.
+ (riscv_feature_name_cpu): Define.
+ (riscv_feature_name_fpu): Define.
+ (riscv_feature_name_virtual): Define.
+ (riscv_xreg_feature): Use riscv_feature_name_cpu.
+ (riscv_freg_feature): Use riscv_feature_name_fpu.
+ (riscv_virtual_feature): Use riscv_feature_name_virtual.
+ (riscv_csr_feature): Use riscv_feature_name_csr.
+ * riscv-tdep.h (riscv_feature_name_csr): Declare.
+
2021-03-05 Andrew Burgess <andrew.burgess@embecosm.com>
Craig Blackmore <craig.blackmore@embecosm.com>
static unsigned int riscv_debug_gdbarch = 0;
+/* The names of the RISC-V target description features. */
+const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr";
+static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu";
+static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu";
+static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual";
+
/* Cached information about a frame. */
struct riscv_unwind_cache
struct riscv_xreg_feature : public riscv_register_feature
{
riscv_xreg_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.cpu")
+ : riscv_register_feature (riscv_feature_name_cpu)
{
m_registers = {
{ RISCV_ZERO_REGNUM + 0, { "zero", "x0" } },
struct riscv_freg_feature : public riscv_register_feature
{
riscv_freg_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.fpu")
+ : riscv_register_feature (riscv_feature_name_fpu)
{
m_registers = {
{ RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } },
struct riscv_virtual_feature : public riscv_register_feature
{
riscv_virtual_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.virtual")
+ : riscv_register_feature (riscv_feature_name_virtual)
{
m_registers = {
{ RISCV_PRIV_REGNUM, { "priv" } }
struct riscv_csr_feature : public riscv_register_feature
{
riscv_csr_feature ()
- : riscv_register_feature ("org.gnu.gdb.riscv.csr")
+ : riscv_register_feature (riscv_feature_name_csr)
{
m_registers = {
#define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \
struct regcache *regcache, int regnum,
const void *regs, size_t len);
+/* The names of the RISC-V target description features. */
+extern const char *riscv_feature_name_csr;
+
#endif /* RISCV_TDEP_H */