None
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
+
+VA-Form
+
+* maddedus RT,RA,RB,RC
+
+Pseudo-code:
+
+ <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+ <!-- bit 8 of EXTRA is set : RS.[s|v]=RT.[s|v]+MAXVL
+ <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+ <!-- no MULUS, so do it manually -->
+ prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
+ if (RB)[0] != 0 then
+ prod[0:XLEN*2-1] <- -((RA) * -(RB))
+ else
+ prod[0:XLEN*2-1] <- (RA) * (RB)
+ <!-- no EXTS2XL, so do it manually -->
+ sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
+ RT <- sum[XLEN:2*XLEN-1]
+ RS <- sum[0:XLEN-1]
+
+Special Registers Altered:
+
+ None
+
# [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
VA-Form
maddhdu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
maddedu,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
maddld,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
+maddedus,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
divmod2du,NORMAL,,1P,EXTRA2,NO,d:RT,s:RA,s:RB,s:RC,RA,RB,RC,RT,0,0,0
absdacs,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
absdacu,NORMAL,,1P,EXTRA2,NO,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0
48,ALU,OP_MADDHD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhd,VA,,,
49,ALU,OP_MADDHDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddhdu,VA,,,
50,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedu,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+57,ALU,OP_MADDEDU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddedus,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
51,ALU,OP_MADDLD,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,maddld,VA,,,
58,ALU,OP_DIVMOD2DU,RA,RB,RC,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,divmod2du,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
56,ALU,OP_PCDEC,RA,RB,RC,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,ONE,0,0,pcdec,VA,,1,unofficial until submitted and approved/renumbered by the opf isa wg
'grev', 'ternlogi', 'bmask', 'cprop',
'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du",
- "dsld", "dsrd",
+ "dsld", "dsrd", "maddedus",
"shadd", "shadduw",
]:
illegal = False
with m.If((major == 4) & xo6.matches(
'111000', # pcdec
'110010', # maddedu
+ '111001', # maddedus
'111010', # divmod2du
'11010-', # dsld
'11011-', # dsrd
"lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
# "lwabr", # load word SVP64 bit-reversed
# "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
- "maddedu",
+ "maddedu", "maddedus",
"maddhd", "maddhdu", "maddld", # INT multiply-and-add
"mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf", # CR mvs
"mfmsr", "mfspr",
@_custom_insns(
_insn("maddedu", XO=50),
+ _insn("maddedus", XO=57),
_insn("divmod2du", XO=58),
_insn("pcdec.", XO=56),
)
from openpower.test.state import ExpectedState
from openpower.simulator.program import Program
from openpower.decoder.isa.caller import SVP64State
+from openpower.decoder.helpers import exts
_SHIFT_TEST_RANGE = list(range(-64, 128, 16)) + [1, 63]
_MASK32 = ((2 ** 32) - 1)
e.intregs[7] = (gprs[5] * gprs[6] + gprs[7]) >> 64
self.add_case(Program(lst, False), gprs, expected=e)
+ def case_maddedus(self):
+ lst = list(SVP64Asm(["maddedus 3,5,6,7"]))
+ gprs = [0] * 32
+ gprs[5] = 0x8123456789ABCDEF
+ gprs[6] = 0xFEDCBA9876543210
+ gprs[7] = 0x82468ACE13579BDF
+ e = ExpectedState(pc=4, int_regs=gprs)
+ v = gprs[5] * exts(gprs[6], 64) + exts(gprs[7], 64)
+ e.intregs[3] = v % 2 ** 64
+ e.intregs[7] = (v >> 64) % 2 ** 64
+ self.add_case(Program(lst, False), gprs, expected=e)
+
def case_divmod2du(self):
lst = list(SVP64Asm(["divmod2du 3,5,6,7"]))
gprs = [0] * 32
e.intregs[4] = 0x1357 # 64-bit carry-out
self.add_case(prog, gprs, expected=e, initial_svstate=svstate)
+ def case_sv_unsigned_bigint_mul_by_signed_scalar(self):
+ """performs a carry-rollover-vector-mul-with-add with a scalar,
+ using "RC" as a 64-bit carry in/out.
+ outputs are negative of sv.maddedu test.
+
+ r18 r17 r16
+ 0x1234_0000_5678_0000 0x9ABC_0000_DEF0_0000 0x1357_0000_9BDF_0000 *
+ r3 (scalar factor) -0x1_0001 +
+ r4 (carry in) -0xFEDC =
+ -0x1234_1234_5678_5678_9ABC_9ABC_DEF0_DEF0_1357_1357_9BDF_9BDF_FEDC =
+ r18 r17 r16
+ 0xEDCB_A987_A987_6543 0x6543_210F_210F_ECA8 0xECA8_6420_6420_0124
+ r4 (carry out) 0xFFFF_FFFF_FFFF_EDCB
+ """
+ prog = Program(list(SVP64Asm(["sv.maddedus *16,*16,3,4"])), False)
+ gprs = [0] * 32
+ gprs[16] = 0x1357_0000_9BDF_0000 # vector...
+ gprs[17] = 0x9ABC_0000_DEF0_0000 # ...
+ gprs[18] = 0x1234_0000_5678_0000 # ... input
+ gprs[3] = -0x1_0001 % 2 ** 64 # scalar multiplier
+ gprs[4] = -0xFEDC % 2 ** 64 # 64-bit carry-in
+ svstate = SVP64State()
+ svstate.vl = 3
+ svstate.maxvl = 3
+ e = ExpectedState(pc=8, int_regs=gprs)
+ e.intregs[16] = 0xECA8_6420_6420_0124 # vector...
+ e.intregs[17] = 0x6543_210F_210F_ECA8 # ...
+ e.intregs[18] = 0xEDCB_A987_A987_6543 # ... result
+ e.intregs[4] = 0xFFFF_FFFF_FFFF_EDCB # 64-bit carry-out
+ self.add_case(prog, gprs, expected=e, initial_svstate=svstate)
+
def case_sv_bigint_div_by_scalar(self):
"""performs a carry-rollover-vector-divmod with a scalar,
using "RC" as a 64-bit carry. matched with the sv.maddedu
projects / openpower-isa.git / commitdiff