clarify comparison table

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 7ce83509e0f84857481ca938134b1d9cbae5a5c1..e4cb8caa8a4a13806b26632cc6f4636b2ee12b98 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -12,9 +12,9 @@
 
 * (1): plus EXT001 24-bit prefixing. See [[sv/svp64]]
 * (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
-* (3): on specific operations.  See [[opcode_regs_deduped]] for full list
+* (3): on specific operations.  See [[opcode_regs_deduped]] for full list. Key: 2P - Twin Predication, 1P - Single-Predicate
 * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries.
-* (5): SVP64 Vectorises Scalar instructions. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector operations.
+* (5): SVP64 Vectorises Scalar ops. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector ops.
 * (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger/analysis]]
 * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
 * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
@@ -27,12 +27,14 @@
 * (14): difficult to exactly ascertain, see ARM Architecture Reference Manual Supplement, DDI 0584.  Critically depends on ARM Scalar instructions.
 * (15): ARM states that the Scalability is a [Silicon-partner choice](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/102340_0001_00_en_introduction-to-sve2.pdf?revision=aae96dd2-5334-4ad3-9a47-393086a20fea).
   Scalability in the ISA is **not available to the programmer**: there is no `setvl` instruction in SVE2, which is already causing assembler programmer difficulties. Effectively this makes SVE2 Predicated SIMD where the SIMD width is chosen by the "Silicon partner".
-  **Note that there does not exist publicly-available SVE2 Hardware. Assessing the non-portability of binaries, acknowledged PRIVATELY by ARM Engineers, requires in-depth knowledge of SVE2. This has NOT yet reached public awareness due to world-wide total lack of SVE2 Hardware**
+  **Assessing binary non-portability, acknowledged PRIVATELY by ARM Engineers, requires in-depth knowledge of SVE2. This has NOT yet reached public awareness due to total world-wide lack of SVE2 Hardware**
 * (16): [AVX512 Wikipedia](https://en.wikipedia.org/wiki/AVX-512), [Lifecycle of an instruction set](https://media.handmade-seattle.com/tom-forsyth/) including full slides
 * (17): difficult to exactly ascertain, contains subsets. Critically depends on ISA support from earlier x86 ISA subsets (several more thousand instructions). See [SIMD ISA listing](https://www.officedaytime.com/simd512e/)
 * (18): [RVV Spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc)
 * (19): RISC-V Vectors are not stand-alone, i.e. like SVE2 and AVX-512 are critically dependent on the Scalar ISA (an additional ~96 instructions for the Scalar RV64GC set (RV64GC is equivalent to the Linux Compliancy Level)
 * (20): Like the original Cray RVV is a truly scalable Vector ISA (Cray setvl instruction).  However, like SVE2, the Maximum Vector length is a Silicon-partner choice, which creates similar limitations that SVP64 does not have.
+  The RISC-V Founders strongly discouraged efforts by programmers to find out the Maximum Vector Length, as an effort to steer programmers towards Silicon-independent assembler. This requires all algorithms to contain a loop construct.
+  MAXVL in SVP64 is a Spec-hard-fixed quantity and consequently such loop constructs are not 100% necessary.
 * (21): like SVP64 it is up to the hardware implementor to choose whether to support 128-bit elements.
 * (22): [NEC SX Aurora](https://ftp.libre-soc.org/NEC_SX_Aurora_TSUBASA_VectorEngine-as-manual-v1.2.pdf) is based on the original Cray Vectors
 * (23): [Aurora ISA guide](https://sxauroratsubasa.sakura.ne.jp/documents/guide/pdfs/Aurora_ISA_guide.pdf) Appendix-3 11.1 p508