S/390: Move vcond-shift.c to vector subdir.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/vcond-shift.c: Move to ...
	* gcc.target/s390/vector/vcond-shift.c: ... here.

From-SVN: r233624

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 85af2342b3bc55a9520888eead14d661778fc671..1eacf121a450835108c41f7a269051111f0e0dc7 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2016-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
+
+       * gcc.target/s390/vcond-shift.c: Move to ...
+       * gcc.target/s390/vector/vcond-shift.c: ... here.
+
 2016-02-23  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 
        * gcc.target/s390/md/movstr-2.c: Move and rename to ...

diff --git a/gcc/testsuite/gcc.target/s390/vcond-shift.c b/gcc/testsuite/gcc.target/s390/vcond-shift.c
deleted file mode 100644 (file)
index f58bd1f..0000000
--- a/gcc/testsuite/gcc.target/s390/vcond-shift.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Check if conditional vector instructions are simplified
-   into shift operations.  */
-/* { dg-do compile { target { s390*-*-* } } } */
-/* { dg-options "-O3 -march=z13 -mzarch" } */
-
-/* { dg-final { scan-assembler "vesraf\t%v.?,%v.?,31" } } */
-/* { dg-final { scan-assembler "vesrah\t%v.?,%v.?,15" } } */
-/* { dg-final { scan-assembler "vesrab\t%v.?,%v.?,7" } } */
-/* { dg-final { scan-assembler-not "vzero\t*" } } */
-/* { dg-final { scan-assembler "vesrlf\t%v.?,%v.?,31" } } */
-/* { dg-final { scan-assembler "vesrlh\t%v.?,%v.?,15" } } */
-/* { dg-final { scan-assembler "vesrlb\t%v.?,%v.?,7" } } */
-
-#define SZ 4
-#define SZ2 8
-#define SZ3 16
-
-void foo(int *w)
-{
-  int i;
-  /* Should expand to (w + (w < 0 ? 1 : 0)) >> 1
-     which in turn should get simplified to (w + (w >> 31)) >> 1.  */
-  for (i = 0; i < SZ; i++)
-    w[i] = w[i] / 2;
-}
-
-void foo2(short *w)
-{
-  int i;
-  for (i = 0; i < SZ2; i++)
-    w[i] = w[i] / 2;
-}
-
-
-void foo3(signed char *w)
-{
-  int i;
-  for (i = 0; i < SZ3; i++)
-    w[i] = w[i] / 2;
-}
-
-int baz(int *x)
-{
-  int i;
-  for (i = 0; i < SZ; i++)
-    x[i] = x[i] < 0 ? -1 : 0;
-}
-
-int baf(short *x)
-{
-  int i;
-  for (i = 0; i < SZ2; i++)
-    x[i] = x[i] >= 0 ? 0 : 1;
-}
-
-int bal(signed char *x)
-{
-  int i;
-  for (i = 0; i < SZ3; i++)
-    x[i] = x[i] >= 0 ? 0 : -1;
-}

diff --git a/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
new file mode 100644 (file)
index 0000000..f58bd1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/vector/vcond-shift.c
@@ -0,0 +1,61 @@
+/* Check if conditional vector instructions are simplified
+   into shift operations.  */
+/* { dg-do compile { target { s390*-*-* } } } */
+/* { dg-options "-O3 -march=z13 -mzarch" } */
+
+/* { dg-final { scan-assembler "vesraf\t%v.?,%v.?,31" } } */
+/* { dg-final { scan-assembler "vesrah\t%v.?,%v.?,15" } } */
+/* { dg-final { scan-assembler "vesrab\t%v.?,%v.?,7" } } */
+/* { dg-final { scan-assembler-not "vzero\t*" } } */
+/* { dg-final { scan-assembler "vesrlf\t%v.?,%v.?,31" } } */
+/* { dg-final { scan-assembler "vesrlh\t%v.?,%v.?,15" } } */
+/* { dg-final { scan-assembler "vesrlb\t%v.?,%v.?,7" } } */
+
+#define SZ 4
+#define SZ2 8
+#define SZ3 16
+
+void foo(int *w)
+{
+  int i;
+  /* Should expand to (w + (w < 0 ? 1 : 0)) >> 1
+     which in turn should get simplified to (w + (w >> 31)) >> 1.  */
+  for (i = 0; i < SZ; i++)
+    w[i] = w[i] / 2;
+}
+
+void foo2(short *w)
+{
+  int i;
+  for (i = 0; i < SZ2; i++)
+    w[i] = w[i] / 2;
+}
+
+
+void foo3(signed char *w)
+{
+  int i;
+  for (i = 0; i < SZ3; i++)
+    w[i] = w[i] / 2;
+}
+
+int baz(int *x)
+{
+  int i;
+  for (i = 0; i < SZ; i++)
+    x[i] = x[i] < 0 ? -1 : 0;
+}
+
+int baf(short *x)
+{
+  int i;
+  for (i = 0; i < SZ2; i++)
+    x[i] = x[i] >= 0 ? 0 : 1;
+}
+
+int bal(signed char *x)
+{
+  int i;
+  for (i = 0; i < SZ3; i++)
+    x[i] = x[i] >= 0 ? 0 : -1;
+}