Add support for memory barriers.

arch/alpha/isa_desc:
    Add cache port bindings for mb & wmb.

--HG--
extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index d4636f60902800715d653c4fc5c3c8c56fe7ec2c..75b2f4138ccd5d082bd1ddf63e2000d198d5a5c7 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2362,8 +2362,8 @@ decode OPCODE default Unknown::unknown() {
            // them the same though.
            0x0000: trapb({{ }}, IsSerializing, No_OpClass);
            0x0400: excb({{ }}, IsSerializing, No_OpClass);
-           0x4000: mb({{ }}, IsMemBarrier);
-           0x4400: wmb({{ }}, IsWriteBarrier);
+           0x4000: mb({{ }}, IsMemBarrier, RdPort);
+           0x4400: wmb({{ }}, IsWriteBarrier, WrPort);
        }
 
 #ifdef FULL_SYSTEM