gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 19:53:43
-gem5 started Mar 15 2016 21:14:27
-gem5 executing on dinar2c11, pid 11560
+gem5 compiled Mar 16 2016 23:07:21
+gem5 started Mar 16 2016 23:48:20
+gem5 executing on dinar2c11, pid 25963
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 233975583000 because target called exit()
+Exiting @ tick 234067145000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.233976 # Number of seconds simulated
-sim_ticks 233975583000 # Number of ticks simulated
-final_tick 233975583000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.234067 # Number of seconds simulated
+sim_ticks 234067145000 # Number of ticks simulated
+final_tick 234067145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86832 # Simulator instruction rate (inst/s)
-host_op_rate 94070 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40212079 # Simulator tick rate (ticks/s)
-host_mem_usage 330216 # Number of bytes of host memory used
-host_seconds 5818.54 # Real time elapsed on the host
-sim_insts 505237724 # Number of instructions simulated
-sim_ops 547350945 # Number of ops (including micro ops) simulated
+host_inst_rate 77703 # Simulator instruction rate (inst/s)
+host_op_rate 84180 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35998538 # Simulator tick rate (ticks/s)
+host_mem_usage 329176 # Number of bytes of host memory used
+host_seconds 6502.13 # Real time elapsed on the host
+sim_insts 505234934 # Number of instructions simulated
+sim_ops 547348155 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 519680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10101184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 16452992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 27073856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 519680 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 519680 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18693440 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18693440 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 8120 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 157831 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 257078 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 423029 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 292085 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 292085 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2221086 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 43171958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 70319269 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 115712313 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2221086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2221086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 79894832 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 79894832 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 79894832 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2221086 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 43171958 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 70319269 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 195607146 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 423029 # Number of read requests accepted
-system.physmem.writeReqs 292085 # Number of write requests accepted
-system.physmem.readBursts 423029 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 292085 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 26921664 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 152192 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18690816 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 27073856 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18693440 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 2378 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 12 # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst 528384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10113344 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 16488320 # Number of bytes read from this memory
+system.physmem.bytes_read::total 27130048 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 528384 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 528384 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18753344 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18753344 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 8256 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 158021 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 257630 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 423907 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293021 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293021 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 2257404 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 43207021 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 70442693 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 115907117 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 2257404 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 2257404 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 80119506 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 80119506 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 80119506 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 2257404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 43207021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 70442693 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 196026623 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 423907 # Number of read requests accepted
+system.physmem.writeReqs 293021 # Number of write requests accepted
+system.physmem.readBursts 423907 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 293021 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 26979584 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 150464 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18751744 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 27130048 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18753344 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 2351 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 26587 # Per bank write bursts
-system.physmem.perBankRdBursts::1 25566 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25266 # Per bank write bursts
-system.physmem.perBankRdBursts::3 32149 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27127 # Per bank write bursts
-system.physmem.perBankRdBursts::5 28227 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25084 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24199 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25413 # Per bank write bursts
-system.physmem.perBankRdBursts::9 25760 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25321 # Per bank write bursts
-system.physmem.perBankRdBursts::11 26053 # Per bank write bursts
-system.physmem.perBankRdBursts::12 27496 # Per bank write bursts
-system.physmem.perBankRdBursts::13 25872 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24848 # Per bank write bursts
-system.physmem.perBankRdBursts::15 25683 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18549 # Per bank write bursts
-system.physmem.perBankWrBursts::1 18359 # Per bank write bursts
-system.physmem.perBankWrBursts::2 17952 # Per bank write bursts
-system.physmem.perBankWrBursts::3 17851 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18559 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18328 # Per bank write bursts
-system.physmem.perBankWrBursts::6 17864 # Per bank write bursts
-system.physmem.perBankWrBursts::7 17725 # Per bank write bursts
-system.physmem.perBankWrBursts::8 17897 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17869 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18218 # Per bank write bursts
-system.physmem.perBankWrBursts::11 18760 # Per bank write bursts
-system.physmem.perBankWrBursts::12 18894 # Per bank write bursts
-system.physmem.perBankWrBursts::13 18283 # Per bank write bursts
-system.physmem.perBankWrBursts::14 18348 # Per bank write bursts
-system.physmem.perBankWrBursts::15 18588 # Per bank write bursts
+system.physmem.perBankRdBursts::0 26590 # Per bank write bursts
+system.physmem.perBankRdBursts::1 25594 # Per bank write bursts
+system.physmem.perBankRdBursts::2 25276 # Per bank write bursts
+system.physmem.perBankRdBursts::3 32211 # Per bank write bursts
+system.physmem.perBankRdBursts::4 27176 # Per bank write bursts
+system.physmem.perBankRdBursts::5 28517 # Per bank write bursts
+system.physmem.perBankRdBursts::6 25342 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24044 # Per bank write bursts
+system.physmem.perBankRdBursts::8 25598 # Per bank write bursts
+system.physmem.perBankRdBursts::9 25550 # Per bank write bursts
+system.physmem.perBankRdBursts::10 25481 # Per bank write bursts
+system.physmem.perBankRdBursts::11 26074 # Per bank write bursts
+system.physmem.perBankRdBursts::12 27377 # Per bank write bursts
+system.physmem.perBankRdBursts::13 26182 # Per bank write bursts
+system.physmem.perBankRdBursts::14 25062 # Per bank write bursts
+system.physmem.perBankRdBursts::15 25482 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18771 # Per bank write bursts
+system.physmem.perBankWrBursts::1 18326 # Per bank write bursts
+system.physmem.perBankWrBursts::2 17966 # Per bank write bursts
+system.physmem.perBankWrBursts::3 17954 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18603 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18522 # Per bank write bursts
+system.physmem.perBankWrBursts::6 18156 # Per bank write bursts
+system.physmem.perBankWrBursts::7 17645 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18039 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17820 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18389 # Per bank write bursts
+system.physmem.perBankWrBursts::11 18735 # Per bank write bursts
+system.physmem.perBankWrBursts::12 18802 # Per bank write bursts
+system.physmem.perBankWrBursts::13 18436 # Per bank write bursts
+system.physmem.perBankWrBursts::14 18499 # Per bank write bursts
+system.physmem.perBankWrBursts::15 18333 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 233975530500 # Total gap between requests
+system.physmem.totGap 234067092500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 423029 # Read request sizes (log2)
+system.physmem.readPktSize::6 423907 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 292085 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 323238 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 49503 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 12846 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 8907 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7169 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6055 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3292 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 36 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 293021 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 324297 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 49438 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 12772 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 8887 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 7182 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 6051 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 4282 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 3308 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 79 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 7196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7667 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12422 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 15020 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 16297 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 16971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17278 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17822 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 18069 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 18331 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 18591 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 18715 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 18832 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 19060 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17612 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17231 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 47 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 7217 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 7709 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 12444 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 14936 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 16344 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 16981 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17377 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17664 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17969 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 18131 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 18327 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 18655 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 18757 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 18967 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 19091 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 321539 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 141.852976 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 99.721857 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 179.991773 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 202400 62.95% 62.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 79393 24.69% 87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 15074 4.69% 92.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7330 2.28% 94.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4928 1.53% 96.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2561 0.80% 96.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1887 0.59% 97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1542 0.48% 98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6424 2.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 321539 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17050 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 24.666979 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 143.647395 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17048 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 323145 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 141.515567 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 99.534760 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 179.780407 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 203801 63.07% 63.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 79524 24.61% 87.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 15124 4.68% 92.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7403 2.29% 94.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4958 1.53% 96.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2458 0.76% 96.94% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1821 0.56% 97.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1542 0.48% 97.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6514 2.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 323145 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17117 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 24.623824 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 142.773249 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17115 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17050 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17050 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.128680 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.068427 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.524733 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 9277 54.41% 54.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 307 1.80% 56.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 5331 31.27% 87.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 1349 7.91% 95.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 375 2.20% 97.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 167 0.98% 98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 95 0.56% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 68 0.40% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 36 0.21% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 15 0.09% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 9 0.05% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 5 0.03% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 3 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 2 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 3 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32 3 0.02% 99.98% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17117 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17117 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.117252 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.059352 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.476775 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 9319 54.44% 54.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 336 1.96% 56.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 5339 31.19% 87.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 1368 7.99% 95.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 375 2.19% 97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 151 0.88% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 90 0.53% 99.19% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 54 0.32% 99.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 43 0.25% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 14 0.08% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 11 0.06% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 3 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 5 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 2 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::30 1 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 1 0.01% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::35 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::49 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::50 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17050 # Writes before turning the bus around for reads
-system.physmem.totQLat 8699002486 # Total ticks spent queuing
-system.physmem.totMemAccLat 16586208736 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2103255000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20679.86 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::36 1 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::37 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::38 2 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17117 # Writes before turning the bus around for reads
+system.physmem.totQLat 8655442270 # Total ticks spent queuing
+system.physmem.totMemAccLat 16559617270 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2107780000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20532.13 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39429.86 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 115.06 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 79.88 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 115.71 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 79.89 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39282.13 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 115.26 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 80.11 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 115.91 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 80.12 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.52 # Data bus utilization in percentage
+system.physmem.busUtil 1.53 # Data bus utilization in percentage
system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.12 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.61 # Average write queue length when enqueuing
-system.physmem.readRowHits 305767 # Number of row buffer hits during reads
-system.physmem.writeRowHits 85381 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 72.69 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 29.23 # Row buffer hit rate for writes
-system.physmem.avgGap 327186.34 # Average gap between requests
-system.physmem.pageHitRate 54.88 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1223691840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 667689000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1670487000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 940811760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 82095857685 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 68367661500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 170247918225 # Total energy per rank (pJ)
-system.physmem_0.averagePower 727.650714 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 113204918849 # Time in different power states
-system.physmem_0.memoryStateTime::REF 7812740000 # Time in different power states
+system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing
+system.physmem.readRowHits 306165 # Number of row buffer hits during reads
+system.physmem.writeRowHits 85234 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 72.63 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 29.09 # Row buffer hit rate for writes
+system.physmem.avgGap 326486.19 # Average gap between requests
+system.physmem.pageHitRate 54.77 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1230881400 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 671611875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1674738000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 945710640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 82093251645 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 68426008500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 170330024220 # Total energy per rank (pJ)
+system.physmem_0.averagePower 727.711031 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 113299566780 # Time in different power states
+system.physmem_0.memoryStateTime::REF 7815860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 112953795651 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 112947723720 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1207044720 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 658605750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1610044800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 951633360 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 15281719440 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 79725813930 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 70446639000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 169881501000 # Total energy per rank (pJ)
-system.physmem_1.averagePower 726.084666 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 116677189668 # Time in different power states
-system.physmem_1.memoryStateTime::REF 7812740000 # Time in different power states
+system.physmem_1.actEnergy 1211996520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 661307625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1612860600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 952903440 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 15287822160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 79567358490 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 70641696000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 169935944835 # Total energy per rank (pJ)
+system.physmem_1.averagePower 726.027425 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 117000888833 # Time in different power states
+system.physmem_1.memoryStateTime::REF 7815860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 109482083332 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 109246895167 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 175127231 # Number of BP lookups
-system.cpu.branchPred.condPredicted 131371482 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7444734 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 90531038 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 83892410 # Number of BTB hits
+system.cpu.branchPred.lookups 175180766 # Number of BP lookups
+system.cpu.branchPred.condPredicted 131398582 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7457767 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 90448674 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 83962981 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 92.667014 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12111505 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104166 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 92.829422 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12120591 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 103810 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 467951167 # number of cpu cycles simulated
+system.cpu.numCycles 468134291 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7807571 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 731933483 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 175127231 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 96003915 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 452021991 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 14942209 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 5420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 243 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 11591 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 236759344 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 34037 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 467317920 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.696233 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.181442 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 7820267 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 732116673 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 175180766 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 96083572 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 452171073 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 14968467 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 4602 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 73 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 11985 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 236801931 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 34000 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 467492233 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.696108 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.181518 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95319924 20.40% 20.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 132721002 28.40% 48.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 57871857 12.38% 61.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 181405137 38.82% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95390302 20.40% 20.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 132755119 28.40% 48.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 57878050 12.38% 61.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 181468762 38.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 467317920 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.374243 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.564124 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32360208 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 118941905 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 286956233 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 22076930 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6982644 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 24050421 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 496163 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 715840292 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 30013840 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6982644 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 63442941 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 55755110 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 40375220 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 276571280 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 24190725 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 686624983 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 13341882 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 9442632 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2386991 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1673870 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1900758 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 831052151 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3019309313 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 723953553 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 176928400 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1535125 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 42420493 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 143531079 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 67984063 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 12865529 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11219958 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 668189770 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2978336 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 610255971 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 5862329 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 123817161 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 319322709 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 704 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 467317920 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.305869 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.102065 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 467492233 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.374210 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.563903 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32386715 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 118994468 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 287021244 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 22094342 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 6995464 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 24069927 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 496423 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 716090334 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 30070891 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 6995464 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 63523233 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 55798726 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 40379426 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 276600311 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 24195073 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 686795271 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 13387267 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 9456751 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 2380300 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1659301 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 1902126 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 831315383 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3020004146 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 724106734 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 177219709 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1544715 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 1534907 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 42449008 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 143548530 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 67987102 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 12901487 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11312004 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 668319179 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2978345 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 610345579 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 5883396 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 123949369 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 319552681 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 467492233 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.305574 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.102144 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 150163836 32.13% 32.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 101159501 21.65% 53.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 145796763 31.20% 84.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 63288828 13.54% 98.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6908500 1.48% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 492 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 150289114 32.15% 32.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 101200175 21.65% 53.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 145769872 31.18% 84.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 63327215 13.55% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6905270 1.48% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 587 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 467317920 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 467492233 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 71905236 52.96% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 30 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.96% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44555950 32.82% 85.78% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19306846 14.22% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 71934630 52.97% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44579938 32.83% 85.80% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 19275701 14.20% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 413151233 67.70% 67.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 351795 0.06% 67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 413246027 67.71% 67.71% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 352054 0.06% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 134217204 21.99% 89.75% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 62535736 10.25% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 134225887 21.99% 89.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 62521608 10.24% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 610255971 # Type of FU issued
-system.cpu.iq.rate 1.304102 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 135768062 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.222477 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1829459960 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 795013485 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 594984726 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 610345579 # Type of FU issued
+system.cpu.iq.rate 1.303783 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 135790299 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.222481 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1829856789 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 795275233 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 595043365 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 297 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 322 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 746023856 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7274448 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 746135699 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 179 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 7278929 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 27646323 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 25541 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 28976 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 11123586 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 27665247 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 25667 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 29087 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 11126882 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 225332 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 22431 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 224857 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 22662 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6982644 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 22928683 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 924923 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 672655804 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 6995464 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 22964751 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 919913 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 672785382 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 143531079 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 67984063 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1489794 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 258689 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 530260 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 28976 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3822816 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3731718 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7554534 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 599400071 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 129576716 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10855900 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 143548530 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 67987102 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1489803 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 257985 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 525401 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 29087 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3817186 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 3742282 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 7559468 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 599464871 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 129581939 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10880708 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1487698 # number of nop insts executed
-system.cpu.iew.exec_refs 190533409 # number of memory reference insts executed
-system.cpu.iew.exec_branches 131373584 # Number of branches executed
-system.cpu.iew.exec_stores 60956693 # Number of stores executed
-system.cpu.iew.exec_rate 1.280903 # Inst execution rate
-system.cpu.iew.wb_sent 596279806 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 594984742 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 349898988 # num instructions producing a value
-system.cpu.iew.wb_consumers 570632014 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.271468 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.613178 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 110042423 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 1487858 # number of nop insts executed
+system.cpu.iew.exec_refs 190527023 # number of memory reference insts executed
+system.cpu.iew.exec_branches 131393815 # Number of branches executed
+system.cpu.iew.exec_stores 60945084 # Number of stores executed
+system.cpu.iew.exec_rate 1.280540 # Inst execution rate
+system.cpu.iew.wb_sent 596341042 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 595043381 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 349946127 # num instructions producing a value
+system.cpu.iew.wb_consumers 570674546 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.271095 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.613215 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 110160125 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6956274 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 450200687 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.218778 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.886375 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 6968998 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 450355888 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.218352 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.886219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 221166453 49.13% 49.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 116327626 25.84% 74.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 43750418 9.72% 84.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 23323090 5.18% 89.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 11527236 2.56% 92.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7779283 1.73% 94.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8247237 1.83% 95.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4226436 0.94% 96.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 13852908 3.08% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 221337598 49.15% 49.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 116324478 25.83% 74.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 43749692 9.71% 84.69% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 23265748 5.17% 89.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 11567595 2.57% 92.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7783316 1.73% 94.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8242109 1.83% 95.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4251497 0.94% 96.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 13833855 3.07% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 450200687 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 506581608 # Number of instructions committed
-system.cpu.commit.committedOps 548694829 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 450355888 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 506578818 # Number of instructions committed
+system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 172745233 # Number of memory references committed
-system.cpu.commit.loads 115884756 # Number of loads committed
+system.cpu.commit.refs 172743503 # Number of memory references committed
+system.cpu.commit.loads 115883283 # Number of loads committed
system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 121548302 # Number of branches committed
+system.cpu.commit.branches 121552863 # Number of branches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 448454354 # Number of committed integer instructions.
+system.cpu.commit.int_insts 448447003 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 375610374 68.46% 68.46% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 115884756 21.12% 89.64% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 56860220 10.36% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 548694829 # Class of committed instruction
-system.cpu.commit.bw_lim_events 13852908 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 1095077893 # The number of ROB reads
-system.cpu.rob.rob_writes 1334621527 # The number of ROB writes
-system.cpu.timesIdled 12496 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 633247 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 505237724 # Number of Instructions Simulated
-system.cpu.committedOps 547350945 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.926200 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.926200 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.079680 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.079680 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 611089815 # number of integer regfile reads
-system.cpu.int_regfile_writes 328120494 # number of integer regfile writes
+system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction
+system.cpu.commit.bw_lim_events 13833855 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 1095367059 # The number of ROB reads
+system.cpu.rob.rob_writes 1334871218 # The number of ROB writes
+system.cpu.timesIdled 12751 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 642058 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 505234934 # Number of Instructions Simulated
+system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 0.926568 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.926568 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.079252 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.079252 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 611137722 # number of integer regfile reads
+system.cpu.int_regfile_writes 328167949 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.cc_regfile_reads 2170189724 # number of cc regfile reads
-system.cpu.cc_regfile_writes 376542500 # number of cc regfile writes
-system.cpu.misc_regfile_reads 217973496 # number of misc regfile reads
+system.cpu.cc_regfile_reads 2170388141 # number of cc regfile reads
+system.cpu.cc_regfile_writes 376631000 # number of cc regfile writes
+system.cpu.misc_regfile_reads 217967292 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2820720 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.629803 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 169353985 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2821232 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 60.028379 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 2817526 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.629948 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 169361200 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2818038 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 60.098977 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 500883000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.629803 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.629948 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 356246516 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 356246516 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 114648880 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114648880 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 51725160 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 51725160 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 2783 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 2783 # number of SoftPFReq hits
+system.cpu.dcache.tags.tag_accesses 356245262 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 356245262 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 114657971 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114657971 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 51723280 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 51723280 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 2781 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 2781 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488558 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 1488558 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 166374040 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 166374040 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 166376823 # number of overall hits
-system.cpu.dcache.overall_hits::total 166376823 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 4844495 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 4844495 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2514146 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2514146 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 166381251 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 166381251 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 166384032 # number of overall hits
+system.cpu.dcache.overall_hits::total 166384032 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 4836633 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 4836633 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2515769 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2515769 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 67 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 67 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 7358641 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 7358641 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 7358653 # number of overall misses
-system.cpu.dcache.overall_misses::total 7358653 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 57544876000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 57544876000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 18904875439 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 18904875439 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 941000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 941000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 76449751439 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 76449751439 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 76449751439 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 76449751439 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 119493375 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 119493375 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2795 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2795 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 7352402 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 7352402 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 7352414 # number of overall misses
+system.cpu.dcache.overall_misses::total 7352414 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 57448748500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 57448748500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 18924298425 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 18924298425 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 887000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 887000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 76373046925 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 76373046925 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 76373046925 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 76373046925 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 119494604 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 119494604 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 2793 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 2793 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 173732681 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 173732681 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 173735476 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 173735476 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040542 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.040542 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046353 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.046353 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004293 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.004293 # miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 173733653 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 173733653 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 173736446 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 173736446 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040476 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.040476 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046383 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.046383 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004296 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.004296 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000045 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000045 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.042356 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.042356 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.042356 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.042356 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11878.405489 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 11878.405489 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7519.402389 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 7519.402389 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14044.776119 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14044.776119 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 10389.112805 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 10389.112805 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 10389.095863 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 10389.095863 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 904831 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.042320 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.042320 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.042319 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.042319 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11877.839088 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 11877.839088 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7522.271888 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 7522.271888 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13238.805970 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13238.805970 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 10387.496076 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 10387.496076 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 10387.479123 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 10387.479123 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 910856 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 221213 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 4.090316 # average number of cycles each access was blocked
+system.cpu.dcache.blocked::no_targets 221280 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 15 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 4.116305 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2820720 # number of writebacks
-system.cpu.dcache.writebacks::total 2820720 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2542826 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2542826 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1994565 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1994565 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 2817526 # number of writebacks
+system.cpu.dcache.writebacks::total 2817526 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2538406 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2538406 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1995936 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1995936 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 67 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4537391 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4537391 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4537391 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4537391 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2301669 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 2301669 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519581 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 519581 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 4534342 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 4534342 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 4534342 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 4534342 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298227 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 2298227 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519833 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 519833 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2821250 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2821250 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2821260 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2821260 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29551116000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 29551116000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4600493494 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4600493494 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 704500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 704500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34151609494 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 34151609494 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34152313994 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 34152313994 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019262 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019262 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009579 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009579 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003578 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003578 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016239 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016239 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.016239 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12838.994660 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12838.994660 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8854.237345 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8854.237345 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70450 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70450 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12105.134070 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 12105.134070 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12105.340874 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 12105.340874 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_misses::cpu.data 2818060 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2818060 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2818070 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2818070 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29530364500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 29530364500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4603208492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4603208492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 671000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 671000 # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 34133572992 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 34133572992 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 34134243992 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 34134243992 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019233 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019233 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003580 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003580 # mshr miss rate for SoftPFReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016221 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016221 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016220 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.016220 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12849.193966 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12849.193966 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8855.167894 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8855.167894 # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67100 # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67100 # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12112.436567 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 12112.436567 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12112.631692 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 12112.631692 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 73492 # number of replacements
-system.cpu.icache.tags.tagsinuse 466.319606 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 236677467 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 74004 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3198.171275 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 115561804500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 466.319606 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.910780 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.910780 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
+system.cpu.icache.tags.replacements 73421 # number of replacements
+system.cpu.icache.tags.tagsinuse 466.150305 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 236720018 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 73932 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3201.861413 # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle 115595672500 # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst 466.150305 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.910450 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.910450 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 473592523 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 473592523 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 236677467 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 236677467 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 236677467 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 236677467 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 236677467 # number of overall hits
-system.cpu.icache.overall_hits::total 236677467 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 81779 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 81779 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 81779 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 81779 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 81779 # number of overall misses
-system.cpu.icache.overall_misses::total 81779 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1323960223 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1323960223 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1323960223 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1323960223 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1323960223 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1323960223 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 236759246 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 236759246 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 236759246 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 236759246 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 236759246 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 236759246 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000345 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000345 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000345 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000345 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000345 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000345 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16189.489025 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 16189.489025 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 16189.489025 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 16189.489025 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 16189.489025 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 155623 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 6523 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 23.857581 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 23.750000 # average number of cycles each access was blocked
+system.cpu.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 17 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 473677631 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 473677631 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 236720018 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 236720018 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 236720018 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 236720018 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 236720018 # number of overall hits
+system.cpu.icache.overall_hits::total 236720018 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 81816 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 81816 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 81816 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 81816 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 81816 # number of overall misses
+system.cpu.icache.overall_misses::total 81816 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1337252702 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1337252702 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1337252702 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1337252702 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1337252702 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1337252702 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 236801834 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 236801834 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 236801834 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 236801834 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 236801834 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 236801834 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16344.635548 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 16344.635548 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 16344.635548 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16344.635548 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 16344.635548 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 158150 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 252 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 6634 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 23.839313 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 50.400000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 73492 # number of writebacks
-system.cpu.icache.writebacks::total 73492 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7746 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 7746 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 7746 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 7746 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 7746 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 7746 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74033 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 74033 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 74033 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 74033 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 74033 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 74033 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1098365314 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 1098365314 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1098365314 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 1098365314 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1098365314 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 1098365314 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14836.158389 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14836.158389 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14836.158389 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14836.158389 # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks 73421 # number of writebacks
+system.cpu.icache.writebacks::total 73421 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7851 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 7851 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 7851 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 7851 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 7851 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 7851 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73965 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 73965 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 73965 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 73965 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 73965 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 73965 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1106045298 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 1106045298 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1106045298 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 1106045298 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1106045298 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 1106045298 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000312 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.000312 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000312 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.000312 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14953.630744 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14953.630744 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14953.630744 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14953.630744 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14953.630744 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14953.630744 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued 8513149 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 8514588 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 439 # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued 8512826 # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified 8514409 # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit 561 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage 743612 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements 395043 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 15130.846704 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3180527 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 410976 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 7.738960 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 170568441000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13790.709252 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 0.000317 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1340.137135 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.841718 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.081795 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.923514 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022 1071 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 14862 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2 25 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 244 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 802 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4899 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6238 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3369 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022 0.065369 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.907104 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 94912633 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 94912633 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 2358534 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 2358534 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 511979 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 511979 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 516918 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 516918 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65874 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 65874 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2140936 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 2140936 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 65874 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2657854 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2723728 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 65874 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2657854 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2723728 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 27 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 27 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 5055 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 5055 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8128 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 8128 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158323 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 158323 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 8128 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 163378 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 171506 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 8128 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 163378 # number of overall misses
-system.cpu.l2cache.overall_misses::total 171506 # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 60000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 60000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 483012500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 483012500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 589814000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 589814000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12070914500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 12070914500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 589814000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 12553927000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 13143741000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 589814000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 12553927000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 13143741000 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 2358534 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 2358534 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 511979 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 511979 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 521973 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 521973 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 74002 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 74002 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2299259 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 2299259 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 74002 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2821232 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2895234 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 74002 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2821232 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2895234 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.964286 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009684 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.009684 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.109835 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.109835 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.068858 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.068858 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109835 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.057910 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.059237 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109835 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.057910 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.059237 # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2222.222222 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2222.222222 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95551.434224 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95551.434224 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72565.698819 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72565.698819 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76242.330552 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76242.330552 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76637.208028 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72565.698819 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76839.764228 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76637.208028 # average overall miss latency
+system.cpu.l2cache.prefetcher.pfSpanPage 743711 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements 395988 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 15132.629454 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3179530 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 411918 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 7.718842 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 170668253000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 13783.431676 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1349.197778 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.841274 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.082348 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.923622 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 1007 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 14923 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::2 36 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3 235 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::4 736 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4874 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6268 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3420 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.061462 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.910828 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 94799517 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 94799517 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 2352015 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 2352015 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 515062 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 515062 # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 517153 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 517153 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 65667 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 65667 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2137304 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 2137304 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 65667 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2654457 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2720124 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 65667 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2654457 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2720124 # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 32 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 32 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 5060 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 5060 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 8262 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 8262 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 158521 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 158521 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 8262 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 163581 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 171843 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 8262 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 163581 # number of overall misses
+system.cpu.l2cache.overall_misses::total 171843 # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 104000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 104000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 481607500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 481607500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 598906500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 598906500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 12080001500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 12080001500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 598906500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 12561609000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 13160515500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 598906500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 12561609000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 13160515500 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 2352015 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 2352015 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 515062 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 515062 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 32 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 32 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 522213 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 522213 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 73929 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 73929 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 2295825 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 2295825 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 73929 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2818038 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2891967 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 73929 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2818038 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2891967 # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009690 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.009690 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.111756 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.111756 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.069048 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.069048 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111756 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.058048 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.059421 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111756 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.058048 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.059421 # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 3250 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 3250 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95179.347826 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95179.347826 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72489.288308 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72489.288308 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76204.424020 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76204.424020 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72489.288308 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76791.369413 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 76584.530647 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72489.288308 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76791.369413 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 76584.530647 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 292085 # number of writebacks
-system.cpu.l2cache.writebacks::total 292085 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1398 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total 1398 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 7 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4146 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4146 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 5544 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 5551 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 5544 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 5551 # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 351023 # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total 351023 # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 27 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 27 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3657 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 3657 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8121 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8121 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154177 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154177 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 8121 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 157834 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 165955 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 8121 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 157834 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 351023 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 516978 # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18646833753 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 389000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 389000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 334746500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 334746500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 540727000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 540727000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10842464500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10842464500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 540727000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11177211000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 11717938000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 540727000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11177211000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18646833753 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 30364771753 # number of overall MSHR miss cycles
+system.cpu.l2cache.writebacks::writebacks 293021 # number of writebacks
+system.cpu.l2cache.writebacks::total 293021 # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1390 # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total 1390 # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5 # number of ReadCleanReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4166 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4166 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5556 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5561 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5556 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5561 # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 350786 # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total 350786 # number of HardPFReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 32 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 32 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3670 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3670 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 8257 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 8257 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 154355 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 154355 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 8257 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 158025 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 166282 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 8257 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 158025 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 350786 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 517068 # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18631455358 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18631455358 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 467000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 467000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 333539000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 333539000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 549061000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 549061000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10851655500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10851655500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 549061000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11185194500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11734255500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 549061000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11185194500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18631455358 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 30365710858 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.964286 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007006 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007006 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.109740 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067055 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067055 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.057320 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109740 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.055945 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007028 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007028 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.111688 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.067233 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.067233 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.056076 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.057498 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111688 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.056076 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.178562 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53121.401598 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14407.407407 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14407.407407 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91535.821712 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91535.821712 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66583.795099 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66583.795099 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70324.785798 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70324.785798 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70609.128981 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66583.795099 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70816.243648 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53121.401598 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58735.133319 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.178795 # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 53113.451956 # average HardPFReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14593.750000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14593.750000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 90882.561308 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 90882.561308 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66496.427274 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66496.427274 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70303.232807 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70303.232807 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70568.404878 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66496.427274 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70781.170701 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 53113.451956 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58726.726191 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5789505 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894253 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23731 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 260682 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244671 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 16011 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 2373290 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2650619 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 535678 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 265254 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 392218 # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests 5782982 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2890992 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 260193 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 244256 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15937 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp 2369788 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2645036 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 538932 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 265577 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 391986 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 521973 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 521973 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 74033 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 2299259 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221525 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8463241 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8684766 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9439488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 361084992 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 370524480 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 949589 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3844850 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.078147 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.283493 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeReq 32 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 32 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 522213 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 522213 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 73965 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295825 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 221313 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453667 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8674980 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9430272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360676160 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 370106432 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 950621 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3842619 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.078093 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.283354 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3560398 92.60% 92.60% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 268441 6.98% 99.58% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 16011 0.42% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 3558474 92.61% 92.61% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 268208 6.98% 99.59% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 15937 0.41% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3844850 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5788964505 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3842619 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5782438005 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 111128336 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 111022344 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 4231881960 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 4227098948 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 419375 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 292085 # Transaction distribution
-system.membus.trans_dist::CleanEvict 98517 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 31 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3653 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3653 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 419376 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1236690 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1236690 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45767232 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 45767232 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 420240 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 293021 # Transaction distribution
+system.membus.trans_dist::CleanEvict 98541 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36 # Transaction distribution
+system.membus.trans_dist::ReadExReq 3666 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3666 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 420241 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1239411 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1239411 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45883328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 45883328 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 813662 # Request fanout histogram
+system.membus.snoop_fanout::samples 815505 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 813662 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 815505 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 813662 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2208946039 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 815505 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2215026289 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2237977923 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2242814920 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/home/stever/m5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
-warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 21:27:50
-gem5 started Mar 15 2016 21:35:29
-gem5 executing on phenom, pid 15976
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Mar 16 2016 22:57:26
+gem5 started Mar 16 2016 22:58:58
+gem5 executing on dinar2c11, pid 24771
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: **info: Increasing stack size by one page.
*******info: Increasing stack size by one page.
-****************************************
+******************************info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+**********
58924 words stored in 3784810 bytes
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 403557300500 because target called exit()
+Exiting @ tick 404911731500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.403557 # Number of seconds simulated
-sim_ticks 403557300500 # Number of ticks simulated
-final_tick 403557300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.404912 # Number of seconds simulated
+sim_ticks 404911731500 # Number of ticks simulated
+final_tick 404911731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114335 # Simulator instruction rate (inst/s)
-host_op_rate 211418 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55801045 # Simulator tick rate (ticks/s)
-host_mem_usage 368712 # Number of bytes of host memory used
-host_seconds 7232.07 # Real time elapsed on the host
-sim_insts 826877109 # Number of instructions simulated
-sim_ops 1528988701 # Number of ops (including micro ops) simulated
+host_inst_rate 59948 # Simulator instruction rate (inst/s)
+host_op_rate 110933 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29356650 # Simulator tick rate (ticks/s)
+host_mem_usage 419644 # Number of bytes of host memory used
+host_seconds 13792.85 # Real time elapsed on the host
+sim_insts 826847303 # Number of instructions simulated
+sim_ops 1530082520 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 163584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24544448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24708032 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 163584 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 163584 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18888768 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18888768 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2556 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 383507 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386063 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 295137 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 295137 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 405355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 60820230 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 61225585 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 405355 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 405355 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 46805665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 46805665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 46805665 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 405355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 60820230 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 108031251 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386063 # Number of read requests accepted
-system.physmem.writeReqs 295137 # Number of write requests accepted
-system.physmem.readBursts 386063 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 295137 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24688384 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 19648 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18886848 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24708032 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18888768 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 307 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bytes_read::cpu.inst 162176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24538048 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24700224 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 162176 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 162176 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18887104 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18887104 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 2534 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 383407 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 385941 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 295111 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 295111 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 400522 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 60600981 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 61001502 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 400522 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 400522 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 46644991 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 46644991 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 46644991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 400522 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 60600981 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 107646493 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 385941 # Number of read requests accepted
+system.physmem.writeReqs 295111 # Number of write requests accepted
+system.physmem.readBursts 385941 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 295111 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24680320 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18885056 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24700224 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18887104 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24073 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26429 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24836 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24494 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23227 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23706 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24492 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23632 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23534 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24801 # Per bank write bursts
-system.physmem.perBankRdBursts::11 23978 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23332 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22938 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24084 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23896 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18613 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19937 # Per bank write bursts
-system.physmem.perBankWrBursts::2 19197 # Per bank write bursts
-system.physmem.perBankWrBursts::3 19026 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18109 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18508 # Per bank write bursts
-system.physmem.perBankWrBursts::6 19135 # Per bank write bursts
-system.physmem.perBankWrBursts::7 19091 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18652 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17959 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18920 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17762 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17406 # Per bank write bursts
-system.physmem.perBankWrBursts::13 17012 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17899 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17881 # Per bank write bursts
+system.physmem.perBankRdBursts::0 24031 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26423 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24936 # Per bank write bursts
+system.physmem.perBankRdBursts::3 24514 # Per bank write bursts
+system.physmem.perBankRdBursts::4 23470 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23659 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24566 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24334 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23673 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23472 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24737 # Per bank write bursts
+system.physmem.perBankRdBursts::11 23939 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23178 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22917 # Per bank write bursts
+system.physmem.perBankRdBursts::14 23861 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23920 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18617 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19947 # Per bank write bursts
+system.physmem.perBankWrBursts::2 19213 # Per bank write bursts
+system.physmem.perBankWrBursts::3 19024 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18187 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18473 # Per bank write bursts
+system.physmem.perBankWrBursts::6 19133 # Per bank write bursts
+system.physmem.perBankWrBursts::7 19079 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18679 # Per bank write bursts
+system.physmem.perBankWrBursts::9 17947 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18901 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17752 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17391 # Per bank write bursts
+system.physmem.perBankWrBursts::13 17019 # Per bank write bursts
+system.physmem.perBankWrBursts::14 17841 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17876 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 403557258500 # Total gap between requests
+system.physmem.totGap 404911622500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386063 # Read request sizes (log2)
+system.physmem.readPktSize::6 385941 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 295137 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 380830 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4573 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 303 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 295111 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 380814 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4468 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 307 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6160 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6563 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17529 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17644 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17643 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17669 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17657 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17710 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17665 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17732 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17685 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17778 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17778 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17761 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17921 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17612 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17541 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 41 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6167 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6528 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 16966 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 17552 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 17613 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 17658 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 17689 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 17680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 17711 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 17661 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 17715 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 17693 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 17766 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 17756 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17868 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17615 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 17553 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 146836 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 296.749026 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 175.460690 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 322.805815 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54147 36.88% 36.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 39842 27.13% 64.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13777 9.38% 73.39% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7669 5.22% 78.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5515 3.76% 82.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3906 2.66% 85.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2997 2.04% 87.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2808 1.91% 88.98% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16175 11.02% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 146836 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17510 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.029754 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 217.905540 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17500 99.94% 99.94% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 147028 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 296.294039 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.908610 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 323.351914 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54375 36.98% 36.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 40100 27.27% 64.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13677 9.30% 73.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7439 5.06% 78.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5510 3.75% 82.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3768 2.56% 84.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3010 2.05% 86.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2924 1.99% 88.96% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16225 11.04% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147028 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17521 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.008789 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 217.166856 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17511 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 5 0.03% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 3 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::7168-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17510 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17510 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.853626 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.775847 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.814458 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17322 98.93% 98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 130 0.74% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 32 0.18% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 9 0.05% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 3 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17521 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17521 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.841447 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.770042 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.569197 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17331 98.92% 98.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 134 0.76% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 31 0.18% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 4 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 3 0.02% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 3 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 1 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 4 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.01% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17510 # Writes before turning the bus around for reads
-system.physmem.totQLat 4294664500 # Total ticks spent queuing
-system.physmem.totMemAccLat 11527589500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1928780000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11133.11 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::116-119 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-211 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 17521 # Writes before turning the bus around for reads
+system.physmem.totQLat 4288044250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11518606750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1928150000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11119.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29883.11 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 61.18 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 46.80 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 61.23 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 46.81 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29869.58 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 60.95 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 46.64 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 61.00 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 46.64 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.84 # Data bus utilization in percentage
system.physmem.busUtilRead 0.48 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.37 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.17 # Average write queue length when enqueuing
-system.physmem.readRowHits 318250 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215762 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.50 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.11 # Row buffer hit rate for writes
-system.physmem.avgGap 592421.11 # Average gap between requests
-system.physmem.pageHitRate 78.43 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 567929880 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 309882375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1525258800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 982361520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 62125312320 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 187636398750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 279505299885 # Total energy per rank (pJ)
-system.physmem_0.averagePower 692.609739 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 311602147750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13475540000 # Time in different power states
+system.physmem.avgWrQLen 21.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 317942 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215725 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.10 # Row buffer hit rate for writes
+system.physmem.avgGap 594538.48 # Average gap between requests
+system.physmem.pageHitRate 78.40 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 570719520 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 311404500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1528168200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 982685520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 62100381375 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 188471152500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 280411157295 # Total energy per rank (pJ)
+system.physmem_0.averagePower 692.529485 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 312985847250 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13520780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 78476140500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 78402005250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 541832760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 295642875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1483138800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 929594880 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 26358156240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 60415771455 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 189135996000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 279160133010 # Total energy per rank (pJ)
-system.physmem_1.averagePower 691.754421 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 314107658000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13475540000 # Time in different power states
+system.physmem_1.actEnergy 540562680 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 294949875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1479324600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 929082960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 26446645680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 59763827970 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 190520760750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 279975154515 # Total energy per rank (pJ)
+system.physmem_1.averagePower 691.452692 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 316410940750 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13520780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 75970627000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 74976935500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 219252380 # Number of BP lookups
-system.cpu.branchPred.condPredicted 219252380 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 8528271 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 123973177 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 121800120 # Number of BTB hits
+system.cpu.branchPred.lookups 219859048 # Number of BP lookups
+system.cpu.branchPred.condPredicted 219859048 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 8758546 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 124148256 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 121897688 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 98.247156 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 27061903 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1407355 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 98.187193 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 27156156 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1403906 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 807114602 # number of cpu cycles simulated
+system.cpu.numCycles 809823464 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 175891157 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1208567118 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 219252380 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 148862023 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 621375374 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 17762469 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 90709 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 718160 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1191 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 35 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 170755406 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2320013 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 806958068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.786744 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.368251 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 176591288 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1214997993 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 219859048 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 149053844 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 622702021 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 18219345 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 230 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 91157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 715943 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 449274 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 28 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 171574494 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2309765 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 809659613 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.796039 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.371227 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 417094848 51.69% 51.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 32452037 4.02% 55.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 31902781 3.95% 59.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 32612026 4.04% 63.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26524373 3.29% 66.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 26910367 3.33% 70.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 35157617 4.36% 74.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 31335613 3.88% 78.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 172968406 21.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 417404830 51.55% 51.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 32671589 4.04% 55.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 32039233 3.96% 59.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 32726753 4.04% 63.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26705475 3.30% 66.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 26911183 3.32% 70.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 35262840 4.36% 74.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 31547344 3.90% 78.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 174390366 21.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 806958068 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.271650 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.497392 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 120421699 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 370368413 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 225215938 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 82070784 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 8881234 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2132047991 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 8881234 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 152579592 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 150649676 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 43646 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 271398208 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 223405712 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2088421237 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 135982 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 138413157 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24833190 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 50057898 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2190635347 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5277929489 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3356932236 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 59989 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 576594493 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3330 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 3150 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 422929221 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 507109788 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 200805340 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 229274294 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 68310404 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2023046060 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27646 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1788955161 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 413315 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 494085005 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 832817551 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 27094 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 806958068 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.216912 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.070634 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 809659613 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.271490 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.500325 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 121391489 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 370091708 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 226645475 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 82421269 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9109672 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2145160206 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 9109672 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 153539670 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 151301355 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 41989 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 272974154 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 222692773 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2099917751 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 135565 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 138360760 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 24932221 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 49265464 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2208208417 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5316744595 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3383996279 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 60226 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 591246845 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3675 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3497 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 423124310 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 508481889 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 201115971 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 229749012 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 68249944 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2031398692 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 54143 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1792547451 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 420919 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 501370315 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 849083500 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 53591 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 809659613 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.213952 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.069729 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 238363650 29.54% 29.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 123779759 15.34% 44.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 118420990 14.67% 59.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 107850309 13.37% 72.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 89928227 11.14% 84.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 60113985 7.45% 91.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 42280336 5.24% 96.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 18948850 2.35% 99.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7271962 0.90% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 239429764 29.57% 29.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 124356019 15.36% 44.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 119082530 14.71% 59.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 108043901 13.34% 72.98% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 89929088 11.11% 84.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 60282735 7.45% 91.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 42261465 5.22% 96.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 18997036 2.35% 99.10% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7277075 0.90% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 806958068 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 809659613 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11501801 42.82% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.82% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12260611 45.64% 88.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3099977 11.54% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11520020 42.79% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12317290 45.76% 88.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3082634 11.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2718189 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1183067002 66.13% 66.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 368893 0.02% 66.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3881187 0.22% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 137 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 38 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 395 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.52% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 428511642 23.95% 90.47% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 170407678 9.53% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2934339 0.16% 0.16% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1185141409 66.11% 66.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 369471 0.02% 66.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 4797462 0.27% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 190 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 20 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 21 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 479 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.57% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 428879813 23.93% 90.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 170424247 9.51% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1788955161 # Type of FU issued
-system.cpu.iq.rate 2.216482 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26862389 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.015016 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4412114486 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2517408815 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1762314892 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 29608 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 69342 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 5559 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1813086388 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12973 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185891278 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1792547451 # Type of FU issued
+system.cpu.iq.rate 2.213504 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26919944 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.015018 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4422066274 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2533070112 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1765468749 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 29104 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 69216 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 5504 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1816520301 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12755 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185916260 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 123009946 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 214354 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 373061 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 51645154 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 124400743 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 210576 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 369684 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 51957776 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 23005 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1152 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 22915 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1100 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 8881234 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 97675937 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6156450 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2023073706 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 372553 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 507112103 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 200805340 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 12025 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1859445 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3396246 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 373061 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4843605 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4134020 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8977625 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1769939059 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 423109380 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 19016102 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 9109672 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 98354510 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6118608 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2031452835 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 404669 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 508484056 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 201115971 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 41229 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1818362 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3401419 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 369684 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4846207 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4373880 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 9220087 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1773318465 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 423351838 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 19228986 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 590326143 # number of memory reference insts executed
-system.cpu.iew.exec_branches 168971977 # Number of branches executed
-system.cpu.iew.exec_stores 167216763 # Number of stores executed
-system.cpu.iew.exec_rate 2.192922 # Inst execution rate
-system.cpu.iew.wb_sent 1766810354 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1762320451 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1339786199 # num instructions producing a value
-system.cpu.iew.wb_consumers 2050074397 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.183482 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.653531 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 494145922 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 590572450 # number of memory reference insts executed
+system.cpu.iew.exec_branches 169222012 # Number of branches executed
+system.cpu.iew.exec_stores 167220612 # Number of stores executed
+system.cpu.iew.exec_rate 2.189759 # Inst execution rate
+system.cpu.iew.wb_sent 1769957940 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1765474253 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1342270213 # num instructions producing a value
+system.cpu.iew.wb_consumers 2056372436 # num instructions consuming a value
+system.cpu.iew.wb_rate 2.180073 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.652737 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 501430525 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8608481 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 739768084 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.066849 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.575796 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 8839580 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 741419902 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.063719 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.574359 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 275719169 37.27% 37.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 172002982 23.25% 60.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 56035372 7.57% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86287676 11.66% 79.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 25889173 3.50% 83.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26492883 3.58% 86.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9844270 1.33% 88.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 9007252 1.22% 89.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 78489307 10.61% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 276552385 37.30% 37.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 172772725 23.30% 60.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 55960386 7.55% 68.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 86390933 11.65% 79.80% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 25906280 3.49% 83.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 26508569 3.58% 86.87% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 9812132 1.32% 88.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 8956469 1.21% 89.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 78560023 10.60% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 739768084 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 826877109 # Number of instructions committed
-system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 741419902 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 826847303 # Number of instructions committed
+system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 533262343 # Number of memory references committed
-system.cpu.commit.loads 384102157 # Number of loads committed
+system.cpu.commit.refs 533241508 # Number of memory references committed
+system.cpu.commit.loads 384083313 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 149758583 # Number of branches committed
+system.cpu.commit.branches 149981740 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions.
+system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions.
system.cpu.commit.function_calls 17673145 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 1819099 0.12% 0.12% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 989721889 64.73% 64.85% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.87% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 3878536 0.25% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.12% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 384102157 25.12% 90.24% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
-system.cpu.commit.bw_lim_events 78489307 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2684413400 # The number of ROB reads
-system.cpu.rob.rob_writes 4113633509 # The number of ROB writes
-system.cpu.timesIdled 1975 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 156534 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 826877109 # Number of Instructions Simulated
-system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.976100 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.976100 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.024485 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.024485 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2722552264 # number of integer regfile reads
-system.cpu.int_regfile_writes 1435774618 # number of integer regfile writes
-system.cpu.fp_regfile_reads 5765 # number of floating regfile reads
-system.cpu.fp_regfile_writes 491 # number of floating regfile writes
-system.cpu.cc_regfile_reads 596650045 # number of cc regfile reads
-system.cpu.cc_regfile_writes 405459285 # number of cc regfile writes
-system.cpu.misc_regfile_reads 971600702 # number of misc regfile reads
+system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction
+system.cpu.commit.bw_lim_events 78560023 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 2694372924 # The number of ROB reads
+system.cpu.rob.rob_writes 4131439321 # The number of ROB writes
+system.cpu.timesIdled 2207 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 163851 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 826847303 # Number of Instructions Simulated
+system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 0.979411 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.979411 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.021022 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.021022 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2730823256 # number of integer regfile reads
+system.cpu.int_regfile_writes 1440512155 # number of integer regfile writes
+system.cpu.fp_regfile_reads 5926 # number of floating regfile reads
+system.cpu.fp_regfile_writes 463 # number of floating regfile writes
+system.cpu.cc_regfile_reads 599968810 # number of cc regfile reads
+system.cpu.cc_regfile_writes 405913106 # number of cc regfile writes
+system.cpu.misc_regfile_reads 971975039 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 2530810 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4087.810337 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 382026213 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2534906 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 150.706264 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 2532888 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4087.837732 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 382237058 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2536984 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 150.665932 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 1673396500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4087.810337 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998001 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998001 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 4087.837732 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.998007 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.998007 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 867 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3177 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 870 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 3173 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 773143076 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 773143076 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 233377627 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 233377627 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148173651 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148173651 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 381551278 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 381551278 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 381551278 # number of overall hits
-system.cpu.dcache.overall_hits::total 381551278 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2766256 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2766256 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 986551 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 986551 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3752807 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3752807 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3752807 # number of overall misses
-system.cpu.dcache.overall_misses::total 3752807 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 58648858500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 58648858500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 30791929995 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 30791929995 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 89440788495 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 89440788495 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 89440788495 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 89440788495 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 236143883 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 236143883 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 385304085 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 385304085 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 385304085 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 385304085 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011714 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.011714 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006614 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006614 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.009740 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.009740 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.009740 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.009740 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21201.529613 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21201.529613 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31211.696096 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 31211.696096 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23833.037109 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23833.037109 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23833.037109 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 10234 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 15 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.354662 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 7.500000 # average number of cycles each access was blocked
+system.cpu.dcache.tags.tag_accesses 773578930 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 773578930 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 233596304 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 233596304 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148199808 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148199808 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 381796112 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 381796112 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 381796112 # number of overall hits
+system.cpu.dcache.overall_hits::total 381796112 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2766458 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2766458 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 958403 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 958403 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 3724861 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3724861 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3724861 # number of overall misses
+system.cpu.dcache.overall_misses::total 3724861 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 58572979000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 58572979000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 29883028996 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 29883028996 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 88456007996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 88456007996 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 88456007996 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 88456007996 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 236362762 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 236362762 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 385520973 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 385520973 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 385520973 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 385520973 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011704 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.011704 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006425 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006425 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.009662 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.009662 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.009662 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.009662 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21172.553135 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21172.553135 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31180.024474 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 31180.024474 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 23747.465475 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23747.465475 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 23747.465475 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 9959 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 9 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1047 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.511939 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 9 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2330455 # number of writebacks
-system.cpu.dcache.writebacks::total 2330455 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1001445 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1001445 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19420 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 19420 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1020865 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1020865 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1020865 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1020865 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764811 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1764811 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 967131 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 967131 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2731942 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2731942 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2731942 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2731942 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33568096500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33568096500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29570460997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 29570460997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63138557497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 63138557497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63138557497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 63138557497 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007473 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007473 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006484 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006484 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.007090 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007090 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.007090 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.788345 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.788345 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30575.445309 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30575.445309 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23111.236438 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23111.236438 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2332013 # number of writebacks
+system.cpu.dcache.writebacks::total 2332013 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 999668 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 999668 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 19404 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 19404 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1019072 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1019072 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1019072 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1019072 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766790 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1766790 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 938999 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 938999 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2705789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2705789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2705789 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2705789 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33605058000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33605058000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 28689647497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 28689647497 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62294705497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 62294705497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62294705497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 62294705497 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007475 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007475 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006295 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006295 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.007019 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.007019 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.007019 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19020.403104 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19020.403104 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30553.437753 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30553.437753 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23022.750664 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23022.750664 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 6689 # number of replacements
-system.cpu.icache.tags.tagsinuse 1037.520443 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 170544686 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 8296 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 20557.459740 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 6016 # number of replacements
+system.cpu.icache.tags.tagsinuse 1043.380208 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 171393952 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 7637 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22442.575881 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1037.520443 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.506602 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.506602 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1607 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 323 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1154 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.784668 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 341716240 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 341716240 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 170547776 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 170547776 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 170547776 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 170547776 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 170547776 # number of overall hits
-system.cpu.icache.overall_hits::total 170547776 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 207629 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 207629 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 207629 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 207629 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 207629 # number of overall misses
-system.cpu.icache.overall_misses::total 207629 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1204990000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1204990000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1204990000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1204990000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1204990000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1204990000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 170755405 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 170755405 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 170755405 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 170755405 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 170755405 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 170755405 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001216 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.001216 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.001216 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.001216 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.001216 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.001216 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5803.572719 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 5803.572719 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 5803.572719 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 5803.572719 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 5803.572719 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 923 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 1043.380208 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.509463 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.509463 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 1621 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.791504 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 343325473 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 343325473 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 171395976 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 171395976 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 171395976 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 171395976 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 171395976 # number of overall hits
+system.cpu.icache.overall_hits::total 171395976 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 178518 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 178518 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 178518 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 178518 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 178518 # number of overall misses
+system.cpu.icache.overall_misses::total 178518 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1062576000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1062576000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1062576000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1062576000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1062576000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1062576000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 171574494 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 171574494 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 171574494 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 171574494 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 171574494 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 171574494 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001040 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.001040 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.001040 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.001040 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.001040 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.001040 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 5952.206500 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 5952.206500 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 5952.206500 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 5952.206500 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 5952.206500 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 68.111111 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 6689 # number of writebacks
-system.cpu.icache.writebacks::total 6689 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2197 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 2197 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 2197 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 2197 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 2197 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 2197 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 205432 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 205432 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 205432 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 205432 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 205432 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 205432 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 915620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 915620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 915620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 915620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 915620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 915620000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001203 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.001203 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001203 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.001203 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4457.046614 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4457.046614 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4457.046614 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 4457.046614 # average overall mshr miss latency
+system.cpu.icache.writebacks::writebacks 6016 # number of writebacks
+system.cpu.icache.writebacks::total 6016 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2032 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2032 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2032 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2032 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2032 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2032 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 176486 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 176486 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 176486 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 176486 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 176486 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 176486 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 805089500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 805089500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 805089500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 805089500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 805089500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 805089500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001029 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.001029 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001029 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.001029 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4561.775438 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4561.775438 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4561.775438 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 4561.775438 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 355320 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 29620.939989 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3892489 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 387653 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 10.041168 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 189331361500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 21024.490956 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.822585 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 8409.626448 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.641617 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.256641 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.903959 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 32333 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
+system.cpu.l2cache.tags.replacements 355100 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 29624.391257 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3897105 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 387449 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 10.058369 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle 189360575500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.occ_blocks::writebacks 21018.110892 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 185.534699 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 8420.745667 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.641422 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005662 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.256981 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.904065 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32349 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13412 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18612 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986725 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 43293695 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 43293695 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 2330455 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 2330455 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 6282 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 6282 # number of WritebackClean hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 1842 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 1842 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 563562 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 563562 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5713 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 5713 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1587786 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1587786 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 5713 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2151348 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2157061 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 5713 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2151348 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2157061 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 195194 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 195194 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 206925 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 206925 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2558 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 2558 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176633 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 176633 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2558 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 383558 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 386116 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2558 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 383558 # number of overall misses
-system.cpu.l2cache.overall_misses::total 386116 # number of overall misses
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12720000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 12720000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16418152000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 16418152000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 210152000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 210152000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14200919500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 14200919500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 210152000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 30619071500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 30829223500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 210152000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 30619071500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 30829223500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 2330455 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 2330455 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 6282 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 6282 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 197036 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 197036 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 770487 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 770487 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8271 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 8271 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1764419 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1764419 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 8271 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2534906 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2543177 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 8271 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2534906 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2543177 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990651 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990651 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268564 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.268564 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.309273 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.309273 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.100108 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.100108 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.309273 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.151311 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.151824 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.309273 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.151311 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.151824 # miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 65.165937 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 65.165937 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79343.491603 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79343.491603 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82154.808444 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82154.808444 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80397.884314 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80397.884314 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79844.459955 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82154.808444 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79829.051930 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79844.459955 # average overall miss latency
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13364 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18670 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987213 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 43097417 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 43097417 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 2332013 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 2332013 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 5708 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 5708 # number of WritebackClean hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 1488 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 1488 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 563712 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 563712 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 5057 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 5057 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1589822 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 1589822 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 5057 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2153534 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2158591 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 5057 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2153534 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2158591 # number of overall hits
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 167317 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 167317 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 206886 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 206886 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2535 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 2535 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 176564 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 176564 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2535 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 383450 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 385985 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2535 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 383450 # number of overall misses
+system.cpu.l2cache.overall_misses::total 385985 # number of overall misses
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 8361500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 8361500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391900500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 16391900500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 208226000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 208226000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14213856500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 14213856500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 208226000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 30605757000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 30813983000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 208226000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 30605757000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 30813983000 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 2332013 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 2332013 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 5708 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 5708 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 168805 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 168805 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 770598 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 770598 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 7592 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 7592 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1766386 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1766386 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 7592 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2536984 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2544576 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 7592 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2536984 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2544576 # number of overall (read+write) accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991185 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991185 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268475 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.268475 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.333904 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.333904 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099958 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099958 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.333904 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.151144 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.151689 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.333904 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.151144 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.151689 # miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 49.974001 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 49.974001 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79231.559893 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79231.559893 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82140.433925 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82140.433925 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 80502.574137 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 80502.574137 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 79832.073785 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82140.433925 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79816.813144 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 79832.073785 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 295137 # number of writebacks
-system.cpu.l2cache.writebacks::total 295137 # number of writebacks
-system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
+system.cpu.l2cache.writebacks::writebacks 295111 # number of writebacks
+system.cpu.l2cache.writebacks::total 295111 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 7 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 7 # number of CleanEvict MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 195194 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 195194 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206925 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 206925 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2557 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2557 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176633 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176633 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2557 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 383558 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 386115 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2557 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 383558 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 386115 # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3766618491 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3766618491 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14348902000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14348902000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 184524501 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 184524501 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12434572036 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12434572036 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 184524501 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26783474036 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 26967998537 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 184524501 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26783474036 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 26967998537 # number of overall MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 167317 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 167317 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206886 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 206886 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2535 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2535 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 176564 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 176564 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2535 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 383450 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 385985 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2535 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 383450 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 385985 # number of overall MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3236471489 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3236471489 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14323040500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14323040500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 182885002 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 182885002 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 12448203030 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 12448203030 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 182885002 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26771243530 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 26954128532 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 182885002 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26771243530 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 26954128532 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990651 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990651 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268564 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268564 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.309152 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100108 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100108 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.151824 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.309152 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151311 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.151824 # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19296.794425 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19296.794425 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69343.491603 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69343.491603 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72164.450919 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72164.450919 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70397.785442 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70397.785442 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72164.450919 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69829.006398 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69844.472598 # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991185 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991185 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268475 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268475 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.333904 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099958 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099958 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.151689 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.333904 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151144 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151689 # mshr miss rate for overall accesses
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19343.351178 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19343.351178 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69231.559893 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69231.559893 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72143.985010 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72143.985010 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70502.497848 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70502.497848 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72143.985010 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69816.778015 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69832.062210 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5474873 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2731236 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 212343 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3595 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3595 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5421179 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2705952 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 181282 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 3493 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3493 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 1969849 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2625592 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 6689 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 260538 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 197036 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 197036 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 770487 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 770487 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 205432 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1764419 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 220390 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7994694 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8215084 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 957312 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311383104 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312340416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 552481 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3292694 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.124385 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.330020 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadResp 1942871 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2627124 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 6016 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 260864 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 168805 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 168805 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 770598 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 770598 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 176486 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766386 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 190093 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7944466 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8134559 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 870848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311615808 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312486656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 523994 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3237375 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.108652 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.311202 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2883132 87.56% 87.56% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 409562 12.44% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2885627 89.13% 89.13% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 351748 10.87% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3292694 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5103271503 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3237375 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5077578963 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 308149990 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 264736482 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3900879073 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3889880082 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 179188 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 295137 # Transaction distribution
-system.membus.trans_dist::CleanEvict 56656 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 195245 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206874 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206874 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 179189 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1319163 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1319163 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1319163 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43596736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43596736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43596736 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 179098 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 295111 # Transaction distribution
+system.membus.trans_dist::CleanEvict 56587 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 167360 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206843 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206843 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 179098 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1290940 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1290940 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1290940 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43587328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43587328 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43587328 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 933101 # Request fanout histogram
+system.membus.snoop_fanout::samples 904999 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 933101 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 904999 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 933101 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2242999911 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2042259250 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 904999 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2207449441 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2041679000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 16 2016 15:38:19
-gem5 started Mar 16 2016 15:38:59
-gem5 executing on dinar2c11, pid 14361
+gem5 compiled Mar 16 2016 22:57:26
+gem5 started Mar 16 2016 22:58:08
+gem5 executing on dinar2c11, pid 24736
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 885256008500 because target called exit()
+Exiting @ tick 885772926000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.885256 # Number of seconds simulated
-sim_ticks 885256008500 # Number of ticks simulated
-final_tick 885256008500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.885773 # Number of seconds simulated
+sim_ticks 885772926000 # Number of ticks simulated
+final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 362789 # Simulator instruction rate (inst/s)
-host_op_rate 670835 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 388389023 # Simulator tick rate (ticks/s)
-host_mem_usage 304128 # Number of bytes of host memory used
-host_seconds 2279.30 # Real time elapsed on the host
-sim_insts 826906380 # Number of instructions simulated
-sim_ops 1529035683 # Number of ops (including micro ops) simulated
+host_inst_rate 376226 # Simulator instruction rate (inst/s)
+host_op_rate 696207 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 403037674 # Simulator tick rate (ticks/s)
+host_mem_usage 304140 # Number of bytes of host memory used
+host_seconds 2197.74 # Real time elapsed on the host
+sim_insts 826847304 # Number of instructions simulated
+sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 8547061720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 2285750420 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10832812140 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 8547061720 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 8547061720 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 991875282 # Number of bytes written to this memory
-system.physmem.bytes_written::total 991875282 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1068382715 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 384117854 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1452500569 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 149164510 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149164510 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9654903935 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2582021921 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12236925856 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9654903935 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9654903935 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1120438915 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1120438915 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9654903935 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3702460837 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13357364772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
+system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
+system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 1770512018 # number of cpu cycles simulated
+system.cpu.numCycles 1771545853 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 826906380 # Number of instructions committed
-system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
+system.cpu.committedInsts 826847304 # Number of instructions committed
+system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1526653037 # number of integer instructions
+system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
+system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
-system.cpu.num_mem_refs 533282319 # number of memory refs
-system.cpu.num_load_insts 384117825 # Number of load instructions
-system.cpu.num_store_insts 149164494 # Number of store instructions
+system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
+system.cpu.num_mem_refs 533241508 # number of memory refs
+system.cpu.num_load_insts 384083313 # Number of load instructions
+system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1770512017.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 149762544 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
-system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
-system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
-system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
-system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
+system.cpu.Branches 149981740 # Number of branches fetched
+system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
+system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
+system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
+system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
+system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1529035683 # Class of executed instruction
-system.membus.trans_dist::ReadReq 1452500569 # Transaction distribution
-system.membus.trans_dist::ReadResp 1452500569 # Transaction distribution
-system.membus.trans_dist::WriteReq 149164510 # Transaction distribution
-system.membus.trans_dist::WriteResp 149164510 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136765430 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 2136765430 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066564728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 1066564728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 3203330158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8547061720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 8547061720 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277625702 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 3277625702 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 11824687422 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.op_class::total 1530082521 # Class of executed instruction
+system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
+system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
+system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
+system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 1601665079 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.667045 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.471271 # Request fanout histogram
+system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.667047 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 533282364 33.30% 33.30% # Request fanout histogram
-system.membus.snoop_fanout::1 1068382715 66.70% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 533241553 33.30% 33.30% # Request fanout histogram
+system.membus.snoop_fanout::1 1068310636 66.70% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1601665079 # Request fanout histogram
+system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 16 2016 15:38:19
-gem5 started Mar 16 2016 15:38:49
-gem5 executing on dinar2c11, pid 14355
+gem5 compiled Mar 16 2016 22:57:26
+gem5 started Mar 16 2016 22:57:56
+gem5 executing on dinar2c11, pid 24718
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 1650600522500 because target called exit()
+Exiting @ tick 1650501252500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 1.650601 # Number of seconds simulated
-sim_ticks 1650600522500 # Number of ticks simulated
-final_tick 1650600522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.650501 # Number of seconds simulated
+sim_ticks 1650501252500 # Number of ticks simulated
+final_tick 1650501252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 236277 # Simulator instruction rate (inst/s)
-host_op_rate 436901 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 471636555 # Simulator tick rate (ticks/s)
-host_mem_usage 314152 # Number of bytes of host memory used
-host_seconds 3499.73 # Real time elapsed on the host
-sim_insts 826906380 # Number of instructions simulated
-sim_ops 1529035683 # Number of ops (including micro ops) simulated
+host_inst_rate 239314 # Simulator instruction rate (inst/s)
+host_op_rate 442851 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 477703969 # Simulator tick rate (ticks/s)
+host_mem_usage 314168 # Number of bytes of host memory used
+host_seconds 3455.07 # Real time elapsed on the host
+sim_insts 826847304 # Number of instructions simulated
+sim_ops 1530082521 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 115776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24258880 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24374656 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24258944 # Number of bytes read from this memory
+system.physmem.bytes_read::total 24374720 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 115776 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 115776 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18765184 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18765184 # Number of bytes written to this memory
+system.physmem.bytes_written::writebacks 18765248 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18765248 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 1809 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 379045 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 380854 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293206 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293206 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 70142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 14697002 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14767144 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 70142 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 70142 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 11368701 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 11368701 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 11368701 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 70142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 14697002 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 26135845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::cpu.data 379046 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 380855 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 293207 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 293207 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 70146 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 14697925 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 14768071 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 70146 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 70146 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 11369424 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 11369424 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 11369424 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 70146 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 14697925 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 26137495 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 3301201045 # number of cpu cycles simulated
+system.cpu.numCycles 3301002505 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 826906380 # Number of instructions committed
-system.cpu.committedOps 1529035683 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1526653037 # Number of integer alu accesses
+system.cpu.committedInsts 826847304 # Number of instructions committed
+system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 35346287 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 92662756 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1526653037 # number of integer instructions
+system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
+system.cpu.num_int_insts 1527470226 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3293861747 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1237389453 # number of times the integer registers were written
+system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 561356848 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 376698535 # number of times the CC registers were written
-system.cpu.num_mem_refs 533282319 # number of memory refs
-system.cpu.num_load_insts 384117825 # Number of load instructions
-system.cpu.num_store_insts 149164494 # Number of store instructions
+system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
+system.cpu.num_mem_refs 533241508 # number of memory refs
+system.cpu.num_load_insts 384083313 # Number of load instructions
+system.cpu.num_store_insts 149158195 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 3301201044.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 3301002504.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 149762544 # Number of branches fetched
-system.cpu.op_class::No_OpClass 1818553 0.12% 0.12% # Class of executed instruction
-system.cpu.op_class::IntAlu 989751625 64.73% 64.85% # Class of executed instruction
-system.cpu.op_class::IntMult 306834 0.02% 64.87% # Class of executed instruction
-system.cpu.op_class::IntDiv 3876352 0.25% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.12% # Class of executed instruction
-system.cpu.op_class::MemRead 384117825 25.12% 90.24% # Class of executed instruction
-system.cpu.op_class::MemWrite 149164494 9.76% 100.00% # Class of executed instruction
+system.cpu.Branches 149981740 # Number of branches fetched
+system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
+system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
+system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
+system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
+system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
+system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1529035683 # Class of executed instruction
-system.cpu.dcache.tags.replacements 2515885 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4086.387052 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 530762383 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2519981 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 210.621581 # Average number of references to valid blocks.
+system.cpu.op_class::total 1530082521 # Class of executed instruction
+system.cpu.dcache.tags.replacements 2517016 # number of replacements
+system.cpu.dcache.tags.tagsinuse 4086.386474 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 530720441 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 8246025500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4086.387052 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 4086.386474 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997653 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1069084709 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1069084709 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 382389020 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 382389020 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148373363 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148373363 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 530762383 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 530762383 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 530762383 # number of overall hits
-system.cpu.dcache.overall_hits::total 530762383 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1728834 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1728834 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 791147 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 791147 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2519981 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2519981 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2519981 # number of overall misses
-system.cpu.dcache.overall_misses::total 2519981 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 30936646500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 30936646500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 20396358500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 20396358500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 51333005000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 51333005000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 51333005000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 51333005000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 384117854 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 384117854 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149164510 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149164510 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 533282364 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 533282364 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 533282364 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 533282364 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004501 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004501 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005304 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005304 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004725 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004725 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004725 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004725 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17894.515321 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17894.515321 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25780.744286 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 25780.744286 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 20370.393666 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20370.393666 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 20370.393666 # average overall miss latency
+system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 382353600 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148366841 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 530720441 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 530720441 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 530720441 # number of overall hits
+system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1729742 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 791370 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2521112 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2521112 # number of overall misses
+system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 30948499500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 30948499500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 20399257500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 20399257500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 51347757000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 51347757000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 51347757000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 51347757000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 384083342 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 533241553 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 533241553 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 533241553 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 533241553 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004504 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004504 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004728 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004728 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004728 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004728 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17891.974352 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17891.974352 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25777.142803 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 25777.142803 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 20367.106658 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20367.106658 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 20367.106658 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2324237 # number of writebacks
-system.cpu.dcache.writebacks::total 2324237 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1728834 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1728834 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791147 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 791147 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2519981 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2519981 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2519981 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2519981 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29207812500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 29207812500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19605211500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 19605211500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48813024000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 48813024000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48813024000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 48813024000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004501 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004501 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005304 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005304 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.004725 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004725 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.004725 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16894.515321 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16894.515321 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24780.744286 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24780.744286 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19370.393666 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 19370.393666 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 2325221 # number of writebacks
+system.cpu.dcache.writebacks::total 2325221 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1729742 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1729742 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791370 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 791370 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2521112 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2521112 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2521112 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2521112 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29218757500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 29218757500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19607887500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 19607887500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 48826645000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 48826645000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 48826645000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 48826645000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004504 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004504 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005306 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005306 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.004728 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004728 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.004728 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16891.974352 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16891.974352 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24777.142803 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24777.142803 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19367.106658 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 19367.106658 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1253 # number of replacements
-system.cpu.icache.tags.tagsinuse 881.377882 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1068379901 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 881.361687 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1068307822 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 379665.920753 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 379640.306326 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 881.377882 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.430360 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.430360 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 881.361687 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.430352 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.430352 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 2136768244 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 2136768244 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1068379901 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1068379901 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1068379901 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1068379901 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1068379901 # number of overall hits
-system.cpu.icache.overall_hits::total 1068379901 # number of overall hits
+system.cpu.icache.tags.tag_accesses 2136624086 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2136624086 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1068307822 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1068307822 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1068307822 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1068307822 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1068307822 # number of overall hits
+system.cpu.icache.overall_hits::total 1068307822 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 2814 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 2814 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 2814 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses
system.cpu.icache.overall_misses::total 2814 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 125256000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 125256000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 125256000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 125256000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 125256000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 125256000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1068382715 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1068382715 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1068382715 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1068382715 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1068382715 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1068382715 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 125255000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 125255000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 125255000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 125255000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 125255000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 125255000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1068310636 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1068310636 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1068310636 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1068310636 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1068310636 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1068310636 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000003 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.727079 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 44511.727079 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 44511.727079 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.727079 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 44511.727079 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44511.371713 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 44511.371713 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 44511.371713 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 44511.371713 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 44511.371713 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122442000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 122442000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122442000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 122442000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122442000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 122442000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 122441000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 122441000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 122441000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 122441000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 122441000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 122441000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.727079 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.727079 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.727079 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.727079 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43511.371713 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43511.371713 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43511.371713 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 43511.371713 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 348437 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 29288.556947 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3849932 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 380797 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 10.110195 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.replacements 348438 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 29288.734166 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 3851952 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 380798 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 10.115473 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 756996028500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 20940.547795 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.260188 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.748964 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.639055 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::writebacks 20940.857984 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.259734 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 8216.616448 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.639064 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004006 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.250755 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.893816 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.250751 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.893821 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32360 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8218 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24062 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24060 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987549 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 41491408 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 41491408 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 2324237 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 2324237 # number of WritebackDirty hits
+system.cpu.l2cache.tags.tag_accesses 41509728 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 41509728 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 2325221 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 2325221 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 1253 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 584791 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 584791 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 585014 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 585014 # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1005 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1005 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1556145 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 1556145 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1557052 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 1557052 # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1005 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 2140936 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2141941 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 2142066 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2143071 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1005 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 2140936 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2141941 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 2142066 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2143071 # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 206356 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1809 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 1809 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172689 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 172689 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 172690 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 172690 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 1809 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 379045 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 380854 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 379046 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 380855 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 1809 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 379045 # number of overall misses
-system.cpu.l2cache.overall_misses::total 380854 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 379046 # number of overall misses
+system.cpu.l2cache.overall_misses::total 380855 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12278185500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 12278185500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107657000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 107657000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275036000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275036000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 107657000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 22553221500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 22660878500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 107657000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 22553221500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 22660878500 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 2324237 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 2324237 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 107656000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 107656000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10275095500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 10275095500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 107656000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 22553281000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22660937000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 107656000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 22553281000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22660937000 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 2325221 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 2325221 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 1253 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 1253 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 791147 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 791147 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 791370 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 791370 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 2814 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 2814 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1728834 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1728834 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1729742 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1729742 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 2519981 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2522795 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2521112 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2523926 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 2519981 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2522795 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260831 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.260831 # miss rate for ReadExReq accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2521112 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2523926 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.260758 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.260758 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.642857 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.642857 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099888 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099888 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.099836 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.099836 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.642857 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.150416 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.150965 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.150349 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.150898 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.642857 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.150416 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.150965 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.150349 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.150898 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500.016961 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500.016961 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.885019 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.885019 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234526 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234526 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59511.332228 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59511.332228 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500.234524 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500.234524 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59500.171982 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.885019 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59500.169356 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59511.332228 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500.116081 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59500.171982 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59500.169356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 293207 # number of writebacks
-system.cpu.l2cache.writebacks::total 293207 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 293208 # number of writebacks
+system.cpu.l2cache.writebacks::total 293208 # number of writebacks
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total 6 # number of CleanEvict MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 206356 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1809 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1809 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172689 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172689 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 172690 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 172690 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 1809 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 379045 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 380854 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 379046 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 380855 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1809 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 379045 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 380854 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 379046 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 380855 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10214625500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10214625500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89567000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89567000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548146000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548146000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89567000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762771500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18852338500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89567000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762771500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18852338500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 89566000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 89566000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8548195500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8548195500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 89566000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18762821000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18852387000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 89566000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18762821000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18852387000 # number of overall MSHR miss cycles
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260831 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260831 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260758 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260758 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.642857 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099888 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099888 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.099836 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.099836 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.150965 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.150898 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.642857 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150416 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.150965 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150349 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.150898 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.016961 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.016961 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.885019 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.885019 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234526 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234526 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49511.332228 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49511.332228 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500.234524 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500.234524 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.885019 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49511.332228 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500.116081 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.171982 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49500.169356 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 5039933 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2517138 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 5042195 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 1729 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1729 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 1731648 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2617444 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1732556 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2618429 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 1253 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 246878 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 791147 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 791147 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 247025 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 791370 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 791370 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1728834 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7555847 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7562728 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 7566121 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310029952 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 310290240 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 348437 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 2871232 # Request fanout histogram
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310165312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 310425600 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 348438 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 2872364 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.000602 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.024532 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.024527 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2869503 99.94% 99.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 2870635 99.94% 99.94% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1729 0.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2871232 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4845456500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 2872364 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4847571500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 4221000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3779971500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3781668000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 174498 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 293206 # Transaction distribution
+system.membus.trans_dist::ReadResp 174499 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 293207 # Transaction distribution
system.membus.trans_dist::CleanEvict 53507 # Transaction distribution
system.membus.trans_dist::ReadExReq 206356 # Transaction distribution
system.membus.trans_dist::ReadExResp 206356 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 174498 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108421 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108421 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1108421 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43139840 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 174499 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1108424 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1108424 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1108424 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43139968 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43139968 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43139968 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 727567 # Request fanout histogram
+system.membus.snoop_fanout::samples 727569 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 727567 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 727569 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 727567 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1900421500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 727569 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1900428000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1904270000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1904275000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 16 2016 15:51:04
-gem5 started Mar 16 2016 17:19:39
-gem5 executing on dinar2c11, pid 17050
+gem5 compiled Mar 16 2016 23:07:21
+gem5 started Mar 16 2016 23:13:40
+gem5 executing on dinar2c11, pid 25474
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.510000
-Exiting @ tick 517287152500 because target called exit()
+Exiting @ tick 517291025500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517287 # Number of seconds simulated
-sim_ticks 517287152500 # Number of ticks simulated
-final_tick 517287152500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.517291 # Number of seconds simulated
+sim_ticks 517291025500 # Number of ticks simulated
+final_tick 517291025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131506 # Simulator instruction rate (inst/s)
-host_op_rate 157879 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 249419657 # Simulator tick rate (ticks/s)
-host_mem_usage 307088 # Number of bytes of host memory used
-host_seconds 2073.96 # Real time elapsed on the host
-sim_insts 272737951 # Number of instructions simulated
-sim_ops 327435116 # Number of ops (including micro ops) simulated
+host_inst_rate 222408 # Simulator instruction rate (inst/s)
+host_op_rate 267009 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 421830266 # Simulator tick rate (ticks/s)
+host_mem_usage 307072 # Number of bytes of host memory used
+host_seconds 1226.30 # Real time elapsed on the host
+sim_insts 272739286 # Number of instructions simulated
+sim_ops 327433744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 269696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 436672 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4214 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6823 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 322792 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 521366 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 844158 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 322792 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 322792 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 322792 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 521366 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 844158 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
+system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 322666 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 522599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 845265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 322666 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 322666 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 322666 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 522599 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 845265 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 191 # Number of system calls
-system.cpu.numCycles 1034574305 # number of cpu cycles simulated
+system.cpu.numCycles 1034582051 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 272737951 # Number of instructions committed
-system.cpu.committedOps 327435116 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 258332236 # Number of integer alu accesses
+system.cpu.committedInsts 272739286 # Number of instructions committed
+system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_func_calls 12449970 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15800021 # number of instructions that are conditional controls
-system.cpu.num_int_insts 258332236 # number of integer instructions
+system.cpu.num_func_calls 12448615 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
+system.cpu.num_int_insts 258331537 # number of integer instructions
system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_int_register_reads 1215886434 # number of times the integer registers were read
-system.cpu.num_int_register_writes 162499715 # number of times the integer registers were written
+system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
+system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1242911540 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 76355719 # number of times the CC registers were written
-system.cpu.num_mem_refs 168105830 # number of memory refs
-system.cpu.num_load_insts 85730232 # Number of load instructions
-system.cpu.num_store_insts 82375598 # Number of store instructions
+system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
+system.cpu.num_mem_refs 168107847 # number of memory refs
+system.cpu.num_load_insts 85732248 # Number of load instructions
+system.cpu.num_store_insts 82375599 # Number of store instructions
system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1034574304.998000 # Number of busy cycles
+system.cpu.num_busy_cycles 1034582050.998000 # Number of busy cycles
system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 30566209 # Number of branches fetched
+system.cpu.Branches 30563503 # Number of branches fetched
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 104315933 31.82% 31.82% # Class of executed instruction
+system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 19652356 5.99% 44.33% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.67% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
-system.cpu.op_class::MemRead 85730232 26.15% 74.87% # Class of executed instruction
-system.cpu.op_class::MemWrite 82375598 25.13% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
+system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 327813586 # Class of executed instruction
-system.cpu.dcache.tags.replacements 1326 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3078.339297 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168357609 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 4469 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37672.322443 # Average number of references to valid blocks.
+system.cpu.op_class::total 327812214 # Class of executed instruction
+system.cpu.dcache.tags.replacements 1332 # number of replacements
+system.cpu.dcache.tags.tagsinuse 3078.335714 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3078.339297 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.751548 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.751548 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 3143 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 3078.335714 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.751547 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.751547 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 678 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 2434 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.767334 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 336728627 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 336728627 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 86231946 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 86231946 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82049814 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82049814 # number of WriteReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168281760 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168281760 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168335819 # number of overall hits
-system.cpu.dcache.overall_hits::total 168335819 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1605 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1605 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2862 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2862 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
+system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 4467 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4467 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4470 # number of overall misses
-system.cpu.dcache.overall_misses::total 4470 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 88066000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 88066000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 176802500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 176802500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 264868500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 264868500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 264868500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 264868500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 86233551 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 86233551 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 82052676 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 82052676 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
+system.cpu.dcache.overall_misses::total 4479 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 88052000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 88052000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 177422500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 177422500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 265474500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 265474500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 265474500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 265474500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168286227 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168286227 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168340289 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168340289 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54869.781931 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54869.781931 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61775.856045 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61775.856045 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 59294.492948 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 59294.492948 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 59254.697987 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 59254.697987 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54895.261845 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54895.261845 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61776.636490 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61776.636490 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 59310.656836 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 59310.656836 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 59270.931011 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 59270.931011 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 997 # number of writebacks
-system.cpu.dcache.writebacks::total 997 # number of writebacks
+system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
+system.cpu.dcache.writebacks::total 998 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1604 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1604 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2862 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2862 # number of WriteReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4466 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4466 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4469 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4469 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86415000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 86415000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 173940500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 173940500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 86402000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 86402000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 174550500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 174550500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 183000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 183000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260355500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 260355500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 260538500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 260538500 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 260952500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 260952500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 261135500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 261135500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53874.688279 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53874.688279 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60775.856045 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60775.856045 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53900.187149 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53900.187149 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60776.636490 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60776.636490 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58297.245858 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 58297.245858 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58299.060192 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 58299.060192 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58313.407821 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58313.407821 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58315.207682 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58315.207682 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 13798 # number of replacements
-system.cpu.icache.tags.tagsinuse 1765.947853 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 348643415 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15605 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 22341.776033 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 13796 # number of replacements
+system.cpu.icache.tags.tagsinuse 1765.948116 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1765.947853 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_blocks::cpu.inst 1765.948116 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.862279 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1522 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 697333645 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 697333645 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 348643415 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 348643415 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 348643415 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 348643415 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 348643415 # number of overall hits
-system.cpu.icache.overall_hits::total 348643415 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 15605 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 15605 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 15605 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 15605 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 15605 # number of overall misses
-system.cpu.icache.overall_misses::total 15605 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 338522000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 338522000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 338522000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 338522000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 338522000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 338522000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 348659020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 348659020 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 348659020 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 348659020 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 348659020 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 348659020 # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses 697336309 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 697336309 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 348644750 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 348644750 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 348644750 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 348644750 # number of overall hits
+system.cpu.icache.overall_hits::total 348644750 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
+system.cpu.icache.overall_misses::total 15603 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 338446000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 338446000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 338446000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 338446000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 338446000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 338446000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 348660353 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 348660353 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 348660353 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 348660353 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21693.175264 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21693.175264 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21693.175264 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21693.175264 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21693.175264 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21691.085048 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21691.085048 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21691.085048 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21691.085048 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21691.085048 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 13798 # number of writebacks
-system.cpu.icache.writebacks::total 13798 # number of writebacks
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15605 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 15605 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 15605 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 15605 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 15605 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 15605 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322917000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 322917000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322917000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 322917000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322917000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 322917000 # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks 13796 # number of writebacks
+system.cpu.icache.writebacks::total 13796 # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 322843000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 322843000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 322843000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 322843000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 322843000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 322843000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20693.175264 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20693.175264 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20693.175264 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20693.175264 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20691.085048 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20691.085048 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20691.085048 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 20691.085048 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 3487.616981 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 3487.622109 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 19775 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.050594 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 341.600605 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.332701 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 738.683674 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 341.605293 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.328378 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 738.688437 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073466 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022543 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1233 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 228016 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 228016 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 997 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 997 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 6213 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 6213 # number of WritebackClean hits
+system.cpu.l2cache.tags.tag_accesses 228106 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 228106 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12996 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 12996 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 239 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 239 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 12996 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 13251 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 12996 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
-system.cpu.l2cache.overall_hits::total 13251 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 2846 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 2846 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2609 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 2609 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 12995 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 254 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 12995 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 254 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13249 # number of overall hits
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 2608 # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368 # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total 1368 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 4214 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 6823 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 4214 # number of overall misses
-system.cpu.l2cache.overall_misses::total 6823 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 169475500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 169475500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155351500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 155351500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.demand_misses::cpu.inst 2608 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 4224 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2608 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 4224 # number of overall misses
+system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 170070500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 170070500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 155292000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 155292000 # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 81591000 # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total 81591000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 155351500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 251066500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 406418000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 155351500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 251066500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 406418000 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 997 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 997 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 6213 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 6213 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2862 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2862 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15605 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 15605 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1607 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 1607 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 15605 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 4469 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 20074 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 15605 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 4469 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 20074 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994410 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.994410 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167190 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167190 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851276 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851276 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167190 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.942940 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.339892 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167190 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.942940 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.339892 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.664793 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.664793 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.461479 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.461479 # average ReadCleanReq miss latency
+system.cpu.l2cache.demand_miss_latency::cpu.inst 155292000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 251661500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 406953500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 155292000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 251661500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 406953500 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 998 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 998 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 6212 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 6212 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 15603 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 1606 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59548.494398 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59548.494398 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59544.478528 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59544.478528 # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59642.543860 # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59642.543860 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59565.880111 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.461479 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59579.140959 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59565.880111 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 59565.793326 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59544.478528 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59578.953598 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 59565.793326 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2846 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 2846 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2609 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2609 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 4214 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 6823 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 4214 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 6823 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141015500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141015500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129261500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129261500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4224 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4224 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 141510500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 141510500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 129212000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 129212000 # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 67911000 # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 67911000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129261500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 208926500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 338188000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129261500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 208926500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 338188000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994410 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994410 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167190 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851276 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851276 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.339892 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167190 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.942940 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.339892 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.664793 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.664793 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.461479 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.461479 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129212000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 209421500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 338633500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129212000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 209421500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 338633500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49548.494398 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49548.494398 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49544.478528 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49544.478528 # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49642.543860 # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49642.543860 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.461479 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49579.140959 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.880111 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49544.478528 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49578.953598 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49565.793326 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 35198 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 15220 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7664 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 35209 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 17212 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 997 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 13798 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 329 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2862 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2862 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15605 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1607 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45008 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10264 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 55272 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881792 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 349824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2231616 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 998 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 13796 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 334 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 55290 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2232000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 20074 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.386570 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.486976 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 20081 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.386335 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.486921 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 12314 61.34% 61.34% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 7760 38.66% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 20074 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 32394000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 20081 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32398500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 23407500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 6703500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 3977 # Transaction distribution
-system.membus.trans_dist::ReadExReq 2846 # Transaction distribution
-system.membus.trans_dist::ReadExResp 2846 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 3977 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13646 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 13646 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 436672 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 436672 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 3976 # Transaction distribution
+system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
+system.membus.trans_dist::ReadExResp 2856 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 3976 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13664 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 6824 # Request fanout histogram
+system.membus.snoop_fanout::samples 6833 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 6824 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 6833 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 6824 # Request fanout histogram
-system.membus.reqLayer0.occupancy 7272500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 6833 # Request fanout histogram
+system.membus.reqLayer0.occupancy 7281500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 34115000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 34160000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 15 2016 19:53:43
-gem5 started Mar 15 2016 20:34:58
-gem5 executing on dinar2c11, pid 10996
+gem5 compiled Mar 16 2016 23:07:21
+gem5 started Mar 16 2016 23:41:21
+gem5 executing on dinar2c11, pid 25849
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 767874998000 because target called exit()
+Exiting @ tick 767851412000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.767875 # Number of seconds simulated
-sim_ticks 767874998000 # Number of ticks simulated
-final_tick 767874998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.767851 # Number of seconds simulated
+sim_ticks 767851412000 # Number of ticks simulated
+final_tick 767851412000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97609 # Simulator instruction rate (inst/s)
-host_op_rate 105159 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48526138 # Simulator tick rate (ticks/s)
-host_mem_usage 342328 # Number of bytes of host memory used
-host_seconds 15823.95 # Real time elapsed on the host
+host_inst_rate 96147 # Simulator instruction rate (inst/s)
+host_op_rate 103584 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47797800 # Simulator tick rate (ticks/s)
+host_mem_usage 342312 # Number of bytes of host memory used
+host_seconds 16064.58 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 64832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 235361472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 63663872 # Number of bytes read from this memory
-system.physmem.bytes_read::total 299090176 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 64832 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 104698048 # Number of bytes written to this memory
-system.physmem.bytes_written::total 104698048 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1013 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3677523 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 994748 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 4673284 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1635907 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1635907 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 84430 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 306510139 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 82909161 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 389503730 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 84430 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 84430 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 136347776 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 136347776 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 136347776 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 84430 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 306510139 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 82909161 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 525851506 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 4673284 # Number of read requests accepted
-system.physmem.writeReqs 1635907 # Number of write requests accepted
-system.physmem.readBursts 4673284 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1635907 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 298596928 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 493248 # Total number of bytes read from write queue
-system.physmem.bytesWritten 104694592 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 299090176 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 104698048 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 7707 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 24 # Number of DRAM write bursts merged with an existing one
+system.physmem.bytes_read::cpu.inst 64960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 235334976 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.l2cache.prefetcher 63685504 # Number of bytes read from this memory
+system.physmem.bytes_read::total 299085440 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 64960 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 64960 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 104625984 # Number of bytes written to this memory
+system.physmem.bytes_written::total 104625984 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 1015 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 3677109 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.l2cache.prefetcher 995086 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 4673210 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1634781 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 1634781 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 84600 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 306485047 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 82939880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 389509527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 84600 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 84600 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 136258112 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 136258112 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 136258112 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 84600 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 306485047 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 82939880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 525767639 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 4673210 # Number of read requests accepted
+system.physmem.writeReqs 1634781 # Number of write requests accepted
+system.physmem.readBursts 4673210 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1634781 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 298595648 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 489792 # Total number of bytes read from write queue
+system.physmem.bytesWritten 104623680 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 299085440 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 104625984 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 7653 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 300421 # Per bank write bursts
-system.physmem.perBankRdBursts::1 298937 # Per bank write bursts
-system.physmem.perBankRdBursts::2 284574 # Per bank write bursts
-system.physmem.perBankRdBursts::3 288248 # Per bank write bursts
-system.physmem.perBankRdBursts::4 288002 # Per bank write bursts
-system.physmem.perBankRdBursts::5 284734 # Per bank write bursts
-system.physmem.perBankRdBursts::6 280770 # Per bank write bursts
-system.physmem.perBankRdBursts::7 278050 # Per bank write bursts
-system.physmem.perBankRdBursts::8 293697 # Per bank write bursts
-system.physmem.perBankRdBursts::9 299275 # Per bank write bursts
-system.physmem.perBankRdBursts::10 291592 # Per bank write bursts
-system.physmem.perBankRdBursts::11 297756 # Per bank write bursts
-system.physmem.perBankRdBursts::12 299138 # Per bank write bursts
-system.physmem.perBankRdBursts::13 298570 # Per bank write bursts
-system.physmem.perBankRdBursts::14 293356 # Per bank write bursts
-system.physmem.perBankRdBursts::15 288457 # Per bank write bursts
-system.physmem.perBankWrBursts::0 103823 # Per bank write bursts
-system.physmem.perBankWrBursts::1 101786 # Per bank write bursts
-system.physmem.perBankWrBursts::2 99158 # Per bank write bursts
-system.physmem.perBankWrBursts::3 99952 # Per bank write bursts
-system.physmem.perBankWrBursts::4 99094 # Per bank write bursts
-system.physmem.perBankWrBursts::5 98779 # Per bank write bursts
-system.physmem.perBankWrBursts::6 102513 # Per bank write bursts
-system.physmem.perBankWrBursts::7 104359 # Per bank write bursts
-system.physmem.perBankWrBursts::8 105182 # Per bank write bursts
-system.physmem.perBankWrBursts::9 104512 # Per bank write bursts
-system.physmem.perBankWrBursts::10 101930 # Per bank write bursts
-system.physmem.perBankWrBursts::11 102694 # Per bank write bursts
-system.physmem.perBankWrBursts::12 102904 # Per bank write bursts
-system.physmem.perBankWrBursts::13 102694 # Per bank write bursts
-system.physmem.perBankWrBursts::14 104057 # Per bank write bursts
-system.physmem.perBankWrBursts::15 102416 # Per bank write bursts
+system.physmem.perBankRdBursts::0 301092 # Per bank write bursts
+system.physmem.perBankRdBursts::1 298585 # Per bank write bursts
+system.physmem.perBankRdBursts::2 284412 # Per bank write bursts
+system.physmem.perBankRdBursts::3 287553 # Per bank write bursts
+system.physmem.perBankRdBursts::4 288019 # Per bank write bursts
+system.physmem.perBankRdBursts::5 285340 # Per bank write bursts
+system.physmem.perBankRdBursts::6 281024 # Per bank write bursts
+system.physmem.perBankRdBursts::7 277791 # Per bank write bursts
+system.physmem.perBankRdBursts::8 293545 # Per bank write bursts
+system.physmem.perBankRdBursts::9 299289 # Per bank write bursts
+system.physmem.perBankRdBursts::10 291195 # Per bank write bursts
+system.physmem.perBankRdBursts::11 297241 # Per bank write bursts
+system.physmem.perBankRdBursts::12 298946 # Per bank write bursts
+system.physmem.perBankRdBursts::13 298565 # Per bank write bursts
+system.physmem.perBankRdBursts::14 293948 # Per bank write bursts
+system.physmem.perBankRdBursts::15 289012 # Per bank write bursts
+system.physmem.perBankWrBursts::0 103815 # Per bank write bursts
+system.physmem.perBankWrBursts::1 101663 # Per bank write bursts
+system.physmem.perBankWrBursts::2 99081 # Per bank write bursts
+system.physmem.perBankWrBursts::3 99729 # Per bank write bursts
+system.physmem.perBankWrBursts::4 98947 # Per bank write bursts
+system.physmem.perBankWrBursts::5 98825 # Per bank write bursts
+system.physmem.perBankWrBursts::6 102537 # Per bank write bursts
+system.physmem.perBankWrBursts::7 104314 # Per bank write bursts
+system.physmem.perBankWrBursts::8 105187 # Per bank write bursts
+system.physmem.perBankWrBursts::9 104412 # Per bank write bursts
+system.physmem.perBankWrBursts::10 101681 # Per bank write bursts
+system.physmem.perBankWrBursts::11 102588 # Per bank write bursts
+system.physmem.perBankWrBursts::12 102740 # Per bank write bursts
+system.physmem.perBankWrBursts::13 102708 # Per bank write bursts
+system.physmem.perBankWrBursts::14 104126 # Per bank write bursts
+system.physmem.perBankWrBursts::15 102392 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 767874956500 # Total gap between requests
+system.physmem.totGap 767851370500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 4673284 # Read request sizes (log2)
+system.physmem.readPktSize::6 4673210 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1635907 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 2762422 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1028983 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 325435 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 231330 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 148884 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 81578 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 37725 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 23665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 18045 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 4249 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1720 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 827 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 441 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 13 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1634781 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 2763298 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 1028318 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 325143 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 231238 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 149204 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 81551 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 37590 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 23700 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 18069 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 4228 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1700 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 454 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 25664 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 28320 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 55851 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 72944 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 84862 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 93771 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 100110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 105539 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 106400 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 107311 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 108333 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 109501 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 111075 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 111603 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 103835 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 101089 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 100454 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 3174 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1324 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 565 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 255 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 26 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 25895 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 28601 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 56060 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 73237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 85035 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 93837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 99991 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 103634 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 105624 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 106179 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 107211 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 108036 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 109230 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 110922 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 111311 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 103575 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 100806 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 100214 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 2991 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1245 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 138 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 4243203 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 95.043673 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 78.954417 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 102.715127 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 3379213 79.64% 79.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 666153 15.70% 95.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 95338 2.25% 97.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 35101 0.83% 98.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 23158 0.55% 98.96% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12215 0.29% 99.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7169 0.17% 99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5140 0.12% 99.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19716 0.46% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 4243203 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 97801 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 47.704328 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 99.639805 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 95408 97.55% 97.55% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 1143 1.17% 98.72% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 693 0.71% 99.43% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 419 0.43% 99.86% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 4241219 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 95.071143 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 78.963204 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 102.762534 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 3377855 79.64% 79.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 665363 15.69% 95.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 95455 2.25% 97.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 35191 0.83% 98.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 22820 0.54% 98.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 12430 0.29% 99.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 7284 0.17% 99.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 5212 0.12% 99.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 19609 0.46% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 4241219 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 97672 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 47.767497 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 100.584321 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-255 95276 97.55% 97.55% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-511 1151 1.18% 98.73% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-767 710 0.73% 99.45% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::768-1023 401 0.41% 99.86% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1279 104 0.11% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535 21 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 6 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 97801 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 97801 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.726342 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.683389 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.248647 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 68568 70.11% 70.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 2029 2.07% 72.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 18244 18.65% 90.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 5739 5.87% 96.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 1897 1.94% 98.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 745 0.76% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 303 0.31% 99.72% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 146 0.15% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 72 0.07% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 32 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 5 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 4 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 97801 # Writes before turning the bus around for reads
-system.physmem.totQLat 128464947947 # Total ticks spent queuing
-system.physmem.totMemAccLat 215944516697 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 23327885000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 27534.63 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::4608-4863 2 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 97672 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 97672 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.737089 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.693249 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 1.262570 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16 68211 69.84% 69.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::17 2039 2.09% 71.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::18 18248 18.68% 90.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::19 5781 5.92% 96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20 2040 2.09% 98.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::21 736 0.75% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::22 303 0.31% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::23 177 0.18% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24 71 0.07% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::25 35 0.04% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::26 22 0.02% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::27 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 97672 # Writes before turning the bus around for reads
+system.physmem.totQLat 128403949042 # Total ticks spent queuing
+system.physmem.totMemAccLat 215883142792 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 23327785000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 27521.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 46284.63 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 388.86 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 136.34 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 389.50 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 136.35 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 46271.68 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 388.87 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 136.26 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 389.51 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 136.26 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 4.10 # Data bus utilization in percentage
system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes
+system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing
-system.physmem.readRowHits 1710553 # Number of row buffer hits during reads
-system.physmem.writeRowHits 347662 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.66 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 21.25 # Row buffer hit rate for writes
-system.physmem.avgGap 121707.36 # Average gap between requests
-system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 15942837960 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 8698969125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 17968828800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5245261920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 415022318100 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 96668804250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 609700698795 # Total energy per rank (pJ)
-system.physmem_0.averagePower 794.012990 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 158294269639 # Time in different power states
-system.physmem_0.memoryStateTime::REF 25640940000 # Time in different power states
+system.physmem.avgWrQLen 24.90 # Average write queue length when enqueuing
+system.physmem.readRowHits 1711348 # Number of row buffer hits during reads
+system.physmem.writeRowHits 347723 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 36.68 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 21.27 # Row buffer hit rate for writes
+system.physmem.avgGap 121726.77 # Average gap between requests
+system.physmem.pageHitRate 32.68 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 15936283440 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 8695392750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 17969468400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5241691440 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 414929915685 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 96735845250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 609660749925 # Total energy per rank (pJ)
+system.physmem_0.averagePower 793.985115 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 158402074288 # Time in different power states
+system.physmem_0.memoryStateTime::REF 25640160000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 583937331861 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 583806871462 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 16135663320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 8804181375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 18422297400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5354961840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 50153678640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 410145276690 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 100946910750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 609962970015 # Total energy per rank (pJ)
-system.physmem_1.averagePower 794.354545 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 165441923935 # Time in different power states
-system.physmem_1.memoryStateTime::REF 25640940000 # Time in different power states
+system.physmem_1.actEnergy 16127249040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 8799590250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 18421525200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5351352480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 50152152960 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 410152468095 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 100926587250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 609930925275 # Total energy per rank (pJ)
+system.physmem_1.averagePower 794.336977 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 165409997970 # Time in different power states
+system.physmem_1.memoryStateTime::REF 25640160000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 576789598565 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 576799157530 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 286279645 # Number of BP lookups
-system.cpu.branchPred.condPredicted 223407155 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 14631310 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 157715633 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 150347717 # Number of BTB hits
+system.cpu.branchPred.lookups 286283871 # Number of BP lookups
+system.cpu.branchPred.condPredicted 223409198 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 14630000 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 157660833 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 150354422 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 95.328354 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 16640366 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 95.365741 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 16641462 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
-system.cpu.numCycles 1535749997 # number of cpu cycles simulated
+system.cpu.numCycles 1535702825 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 13928863 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2067540877 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 286279645 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 166988083 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1507099451 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 29287501 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 190 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 976 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 656956376 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 928 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1535673230 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.442364 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.228170 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 13928194 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 2067545272 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 286283871 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 166995884 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1507053814 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 29284843 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 194 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.IcacheWaitRetryStallCycles 878 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 656961352 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 924 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 1535625501 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.442414 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.228162 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 453232887 29.51% 29.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 465446694 30.31% 59.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 101428513 6.60% 66.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 515565136 33.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 453179554 29.51% 29.51% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 465452437 30.31% 59.82% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 101425758 6.60% 66.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 515567752 33.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1535673230 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.186410 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.346274 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 74702692 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 538196786 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 849939330 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 58191372 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 14643050 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 42203099 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 740 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2037258767 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 52502216 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 14643050 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 139798596 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 457232788 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 14060 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 837861639 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 86123097 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1976450357 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 26748217 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 45311443 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 127280 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1601349 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 25060230 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1985922281 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 9128467759 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2432961586 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 1535625501 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.186419 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.346319 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 74705832 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 538167437 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 849914387 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 58196125 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 14641720 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 42203366 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 738 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 2037249572 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 52491206 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 14641720 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 139798655 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 457197163 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 837846796 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 86126990 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1976444651 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 26741715 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 45304447 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 126733 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 1592000 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 25068959 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1985917884 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 9128448478 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 2432959376 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 311023336 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 153 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 144 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 111484275 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 542573994 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 199309930 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 26884095 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 29108781 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1948029821 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 211 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1857521274 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13507542 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 283997616 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 647442130 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1535673230 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.209581 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.150633 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 311018939 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 156 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 147 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 111499439 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 542575800 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 199311764 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 26984794 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 29485637 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1948029914 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 213 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1857440521 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 13485383 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 283997711 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 647527066 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 43 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1535625501 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.209566 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.150575 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 582693827 37.94% 37.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 326116884 21.24% 59.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 378188392 24.63% 83.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 219675077 14.30% 98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 28992875 1.89% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6175 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 582643896 37.94% 37.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 326148429 21.24% 59.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 378192784 24.63% 83.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 219661214 14.30% 98.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 28973008 1.89% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 6170 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1535673230 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1535625501 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 166036820 40.98% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 1982 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 191468502 47.25% 88.23% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 47685170 11.77% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 166041601 41.02% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 1966 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 191453028 47.29% 88.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 47322574 11.69% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1138261186 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 800987 0.04% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1138257310 61.28% 61.28% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 800951 0.04% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 532140310 28.65% 89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 186318740 10.03% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 532072663 28.65% 89.97% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 186309545 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1857521274 # Type of FU issued
-system.cpu.iq.rate 1.209521 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 405192474 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.218136 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5669415557 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2232040499 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1805727122 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2262713615 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 17816594 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1857440521 # Type of FU issued
+system.cpu.iq.rate 1.209505 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 404819169 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.217945 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 5668810855 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2232040657 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1805715757 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 2262259556 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 17798811 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 84267660 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 66369 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 13310 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 24462885 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 84269466 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 66606 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 13290 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 24464719 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4528039 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4867222 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 4470256 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4868274 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 14643050 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 25368203 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1322817 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1948030107 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 14641720 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 25371637 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 1306573 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1948030205 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 542573994 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 199309930 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 149 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 159427 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1161958 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 13310 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 7700527 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8706121 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 16406648 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1827850066 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 516960251 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29671208 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 542575800 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 199311764 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 151 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 159252 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 1145955 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 13290 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 7700252 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 8704527 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 16404779 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1827784428 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 516894749 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 29656093 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 75 # number of nop insts executed
-system.cpu.iew.exec_refs 698714373 # number of memory reference insts executed
-system.cpu.iew.exec_branches 229541828 # Number of branches executed
-system.cpu.iew.exec_stores 181754122 # Number of stores executed
-system.cpu.iew.exec_rate 1.190200 # Inst execution rate
-system.cpu.iew.wb_sent 1808757098 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1805727191 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1169214999 # num instructions producing a value
-system.cpu.iew.wb_consumers 1689608003 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.175795 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692004 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 258092940 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 78 # number of nop insts executed
+system.cpu.iew.exec_refs 698647521 # number of memory reference insts executed
+system.cpu.iew.exec_branches 229543891 # Number of branches executed
+system.cpu.iew.exec_stores 181752772 # Number of stores executed
+system.cpu.iew.exec_rate 1.190194 # Inst execution rate
+system.cpu.iew.wb_sent 1808752237 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1805715827 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1169206310 # num instructions producing a value
+system.cpu.iew.wb_consumers 1689633446 # num instructions consuming a value
+system.cpu.iew.wb_rate 1.175824 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.691988 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 258099424 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 14630610 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1496181220 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.112186 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.028021 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 14629299 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1496131949 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.112223 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.027889 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 915888142 61.22% 61.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 250644385 16.75% 77.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 110066561 7.36% 85.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 55290971 3.70% 89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 29288855 1.96% 90.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 34073264 2.28% 93.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 24725039 1.65% 94.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 18121984 1.21% 96.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 58082019 3.88% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 915820639 61.21% 61.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 250646763 16.75% 77.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 110056209 7.36% 85.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 55261288 3.69% 89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 29350080 1.96% 90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 34099698 2.28% 93.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 24719772 1.65% 94.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 18148053 1.21% 96.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 58029447 3.88% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1496181220 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 1496131949 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
-system.cpu.commit.bw_lim_events 58082019 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 3360223976 # The number of ROB reads
-system.cpu.rob.rob_writes 3883747904 # The number of ROB writes
-system.cpu.timesIdled 828 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 76767 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.commit.bw_lim_events 58029447 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 3360233761 # The number of ROB reads
+system.cpu.rob.rob_writes 3883762364 # The number of ROB writes
+system.cpu.timesIdled 834 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 77324 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.994294 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.994294 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.005739 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.005739 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2175836515 # number of integer regfile reads
-system.cpu.int_regfile_writes 1261593461 # number of integer regfile writes
+system.cpu.cpi 0.994264 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.994264 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.005769 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.005769 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 2175773439 # number of integer regfile reads
+system.cpu.int_regfile_writes 1261589366 # number of integer regfile writes
system.cpu.fp_regfile_reads 40 # number of floating regfile reads
-system.cpu.fp_regfile_writes 51 # number of floating regfile writes
-system.cpu.cc_regfile_reads 6965846001 # number of cc regfile reads
-system.cpu.cc_regfile_writes 551857157 # number of cc regfile writes
-system.cpu.misc_regfile_reads 675854889 # number of misc regfile reads
+system.cpu.fp_regfile_writes 52 # number of floating regfile writes
+system.cpu.cc_regfile_reads 6965635020 # number of cc regfile reads
+system.cpu.cc_regfile_writes 551858996 # number of cc regfile writes
+system.cpu.misc_regfile_reads 675848866 # number of misc regfile reads
system.cpu.misc_regfile_writes 124 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 17003582 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.964809 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 638071493 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 17004094 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37.524580 # Average number of references to valid blocks.
+system.cpu.dcache.tags.replacements 17003597 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.964807 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 638080633 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 17004109 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 37.525085 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 77932500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.964809 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.964807 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 408 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1335716396 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1335716396 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 469352988 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 469352988 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 168718360 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 168718360 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 1335734207 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1335734207 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 469362265 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 469362265 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 168718228 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 168718228 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 638071348 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 638071348 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 638071348 # number of overall hits
-system.cpu.dcache.overall_hits::total 638071348 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 17416992 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 17416992 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3867687 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3867687 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 638080493 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 638080493 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 638080493 # number of overall hits
+system.cpu.dcache.overall_hits::total 638080493 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 17416613 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 17416613 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3867819 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3867819 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 21284679 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 21284679 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 21284681 # number of overall misses
-system.cpu.dcache.overall_misses::total 21284681 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 412160487500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 412160487500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 148823410876 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 148823410876 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 21284432 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 21284432 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 21284434 # number of overall misses
+system.cpu.dcache.overall_misses::total 21284434 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 412110560500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 412110560500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 148910053049 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 148910053049 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 560983898376 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 560983898376 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 560983898376 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 560983898376 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 486769980 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 486769980 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 561020613549 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 561020613549 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 561020613549 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 561020613549 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 486778878 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 486778878 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 659356027 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 659356027 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 659356029 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 659356029 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035781 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.035781 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022410 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.022410 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 659364925 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 659364925 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 659364927 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 659364927 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022411 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.022411 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.032281 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.032281 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.032281 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.032281 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23664.274951 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 23664.274951 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38478.659435 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38478.659435 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.032280 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.032280 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.032280 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.032280 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23661.923274 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 23661.923274 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38499.747028 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38499.747028 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26356.230149 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26356.230149 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26356.227673 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26356.227673 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 20486404 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 3408907 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 942205 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 67188 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.743043 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 50.736843 # average number of cycles each access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26358.260984 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26358.260984 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26358.258507 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26358.258507 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 20478587 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 3417945 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 942442 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 67202 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.729281 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 50.860763 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 17003582 # number of writebacks
-system.cpu.dcache.writebacks::total 17003582 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150438 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3150438 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130143 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1130143 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 17003597 # number of writebacks
+system.cpu.dcache.writebacks::total 17003597 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150032 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3150032 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130287 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1130287 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4280581 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4280581 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4280581 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4280581 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266554 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 14266554 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737544 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2737544 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 4280319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 4280319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 4280319 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 4280319 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266581 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 14266581 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737532 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 2737532 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 17004098 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 17004098 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 17004099 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 17004099 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331835130000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 331835130000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115624975794 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 115624975794 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 17004113 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 17004113 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 17004114 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 17004114 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331850986000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 331850986000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115586978404 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 115586978404 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447460105794 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 447460105794 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447460173794 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 447460173794 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447437964404 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 447437964404 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447438032404 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 447438032404 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23259.655415 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23259.655415 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42236.755206 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42236.755206 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23260.722804 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23260.722804 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42223.060189 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42223.060189 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26314.839270 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26314.839270 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26314.841721 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 26314.841721 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26313.513937 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26313.513937 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26313.516388 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 26313.516388 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 590 # number of replacements
-system.cpu.icache.tags.tagsinuse 444.554720 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 656954786 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 610552.775093 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 586 # number of replacements
+system.cpu.icache.tags.tagsinuse 444.620453 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 656959766 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 1072 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 612835.602612 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 444.554720 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.868271 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.868271 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 444.620453 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.868399 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.868399 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 440 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 1313913824 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 1313913824 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 656954786 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 656954786 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 656954786 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 656954786 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 656954786 # number of overall hits
-system.cpu.icache.overall_hits::total 656954786 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1588 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1588 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1588 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1588 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1588 # number of overall misses
-system.cpu.icache.overall_misses::total 1588 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 98682987 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 98682987 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 98682987 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 98682987 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 98682987 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 98682987 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 656956374 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 656956374 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 656956374 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 656956374 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 656956374 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 656956374 # number of overall (read+write) accesses
+system.cpu.icache.tags.tag_accesses 1313923770 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 1313923770 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 656959766 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 656959766 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 656959766 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 656959766 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 656959766 # number of overall hits
+system.cpu.icache.overall_hits::total 656959766 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1583 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1583 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1583 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1583 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1583 # number of overall misses
+system.cpu.icache.overall_misses::total 1583 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 101448987 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 101448987 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 101448987 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 101448987 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 101448987 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 101448987 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 656961349 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 656961349 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 656961349 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 656961349 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 656961349 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 656961349 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62142.938917 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 62142.938917 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 62142.938917 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 62142.938917 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 62142.938917 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 17933 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 176 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 194 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 92.438144 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64086.536323 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 64086.536323 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 64086.536323 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 64086.536323 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 64086.536323 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 16918 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 173 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 189 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 89.513228 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 34.600000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::writebacks 590 # number of writebacks
-system.cpu.icache.writebacks::total 590 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 510 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 510 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 510 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 510 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 510 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 510 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1078 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1078 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1078 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1078 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1078 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1078 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74485990 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 74485990 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74485990 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 74485990 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74485990 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 74485990 # number of overall MSHR miss cycles
+system.cpu.icache.writebacks::writebacks 586 # number of writebacks
+system.cpu.icache.writebacks::total 586 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 509 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 509 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 509 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 509 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 509 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 509 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1074 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1074 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1074 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1074 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1074 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74582990 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 74582990 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74582990 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 74582990 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74582990 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 74582990 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69096.465677 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69096.465677 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69096.465677 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 69096.465677 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69444.124767 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69444.124767 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69444.124767 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 69444.124767 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.prefetcher.num_hwpf_issued 11607933 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 11636199 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 19107 # number of redundant prefetches already in prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_issued 11607728 # number of hwpf issued
+system.cpu.l2cache.prefetcher.pfIdentified 11635838 # number of prefetch candidates identified
+system.cpu.l2cache.prefetcher.pfBufferHit 19050 # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage 4655601 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.replacements 4705755 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 16099.742972 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 22830947 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 4721680 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.835344 # Average number of references to valid blocks.
+system.cpu.l2cache.prefetcher.pfRemovedFull 5 # number of prefetches dropped due to prefetch queue size
+system.cpu.l2cache.prefetcher.pfSpanPage 4655842 # number of prefetches not generated due to page crossing
+system.cpu.l2cache.tags.replacements 4705864 # number of replacements
+system.cpu.l2cache.tags.tagsinuse 16099.842459 # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs 22826032 # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 4721788 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 4.834192 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 54104143500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 13103.742170 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 2.284694 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2993.716107 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.799789 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.000139 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182722 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.982650 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022 804 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 15121 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::writebacks 13102.285184 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 2.119304 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2995.437971 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::writebacks 0.799700 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.000129 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.182827 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.982656 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1022 773 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 15151 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1 610 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 461 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2942 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4257 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5586 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1875 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022 0.049072 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.922913 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 552235013 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 552235013 # Number of data accesses
-system.cpu.l2cache.WritebackDirty_hits::writebacks 4829213 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 4829213 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 12153673 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 12153673 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 1758045 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 1758045 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 63 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 63 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520714 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 11520714 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 63 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 13278759 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 13278822 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 63 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 13278759 # number of overall hits
-system.cpu.l2cache.overall_hits::total 13278822 # number of overall hits
+system.cpu.l2cache.tags.age_task_id_blocks_1022::1 599 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1022::3 172 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 469 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2950 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4343 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5551 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1838 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1022 0.047180 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.924744 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 552240776 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 552240776 # Number of data accesses
+system.cpu.l2cache.WritebackDirty_hits::writebacks 4834377 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackDirty_hits::total 4834377 # number of WritebackDirty hits
+system.cpu.l2cache.WritebackClean_hits::writebacks 12148517 # number of WritebackClean hits
+system.cpu.l2cache.WritebackClean_hits::total 12148517 # number of WritebackClean hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 1758217 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 1758217 # number of ReadExReq hits
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11520794 # number of ReadSharedReq hits
+system.cpu.l2cache.ReadSharedReq_hits::total 11520794 # number of ReadSharedReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 13279011 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13279068 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 13279011 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13279068 # number of overall hits
system.cpu.l2cache.UpgradeReq_misses::cpu.data 5 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 5 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 979533 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 979533 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1015 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 1015 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745802 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 2745802 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 1015 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 3725335 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 3726350 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 1015 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 3725335 # number of overall misses
-system.cpu.l2cache.overall_misses::total 3726350 # number of overall misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 979355 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 979355 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1017 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 1017 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2745743 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 2745743 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 1017 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 3725098 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 3726115 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 1017 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 3725098 # number of overall misses
+system.cpu.l2cache.overall_misses::total 3726115 # number of overall misses
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 100500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 100500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98972728500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 98972728500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72952500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 72952500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234172325000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 234172325000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 72952500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 333145053500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 333218006000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 72952500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 333145053500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 333218006000 # number of overall miss cycles
-system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829213 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackDirty_accesses::total 4829213 # number of WritebackDirty accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::writebacks 12153673 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.WritebackClean_accesses::total 12153673 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 98934121000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 98934121000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 73094500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 73094500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234186702000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 234186702000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 73094500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 333120823000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 333193917500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 73094500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 333120823000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 333193917500 # number of overall miss cycles
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 4834377 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackDirty_accesses::total 4834377 # number of WritebackDirty accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::writebacks 12148517 # number of WritebackClean accesses(hits+misses)
+system.cpu.l2cache.WritebackClean_accesses::total 12148517 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 5 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 5 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 2737578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1078 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 1078 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266516 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 14266516 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1078 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 17004094 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 17005172 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1078 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 17004094 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 17005172 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737572 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2737572 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1074 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 1074 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266537 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 14266537 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1074 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 17004109 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 17005183 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1074 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 17004109 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 17005183 # number of overall (read+write) accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357810 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.357810 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.941558 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.941558 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192465 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192465 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941558 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.219085 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.219130 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941558 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.219085 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.219130 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.357746 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.357746 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946927 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946927 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192460 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192460 # miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946927 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.219070 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.219116 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946927 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.219070 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.219116 # miss rate for overall accesses
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20100 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20100 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101040.729103 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101040.729103 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71874.384236 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71874.384236 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85283.762267 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85283.762267 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 89422.090249 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71874.384236 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.871275 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 89422.090249 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 879 # number of cycles access was blocked
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101019.672131 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101019.672131 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 71872.664700 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 71872.664700 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85290.830934 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85290.830934 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 89421.265178 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71872.664700 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89426.056174 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 89421.265178 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 398 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 146.500000 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 1635907 # number of writebacks
-system.cpu.l2cache.writebacks::total 1635907 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3910 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total 3910 # number of ReadExReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 1634781 # number of writebacks
+system.cpu.l2cache.writebacks::total 1634781 # number of writebacks
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3953 # number of ReadExReq MSHR hits
+system.cpu.l2cache.ReadExReq_mshr_hits::total 3953 # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45136 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45136 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45302 # number of ReadSharedReq MSHR hits
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45302 # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 49046 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 49047 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 49255 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 49256 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 49046 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 49047 # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total 1143496 # number of HardPFReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 49255 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 49256 # number of overall MSHR hits
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of HardPFReq MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_misses::total 1144188 # number of HardPFReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 5 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975623 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 975623 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1014 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1014 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700666 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700666 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3676289 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 3677303 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3676289 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1143496 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 4820799 # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72430896209 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 975402 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 975402 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1016 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1016 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2700441 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2700441 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1016 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3675843 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3676859 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1016 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3675843 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1144188 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 4821047 # number of overall MSHR misses
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of HardPFReq MSHR miss cycles
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72422793987 # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 70500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 70500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92751563000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92751563000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66801500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66801500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215184233000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215184233000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66801500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307935796000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 308002597500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66801500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307935796000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72430896209 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 380433493709 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92707545500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92707545500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66931500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66931500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215168959000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215168959000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66931500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307876504500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 307943436000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66931500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307876504500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72422793987 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 380366229987 # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356382 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356382 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.940631 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189301 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189301 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.216246 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.940631 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216200 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356302 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356302 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.945996 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189285 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189285 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.216220 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.945996 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216174 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.283490 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63341.626214 # average HardPFReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.283505 # mshr miss rate for overall accesses
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average HardPFReq mshr miss latency
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63296.236271 # average HardPFReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14100 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95069.061512 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95069.061512 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65879.191321 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65879.191321 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79678.210116 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79678.210116 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83757.742427 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65879.191321 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83762.673718 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63341.626214 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78915.029170 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95045.474071 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95045.474071 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65877.460630 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65877.460630 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79679.192769 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79679.192769 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83751.766385 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65877.460630 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83756.706829 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63296.236271 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78897.017595 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 34009349 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004186 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21286 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2918754 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899783 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18971 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 14267592 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 6465120 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 12174959 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 5771526 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 1434255 # Transaction distribution
+system.cpu.toL2Bus.snoop_filter.tot_requests 34009371 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004197 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2918881 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2900097 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18784 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.trans_dist::ReadResp 14267609 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackDirty 6469158 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WritebackClean 12169806 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 5772538 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::HardPFReq 1435459 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2737578 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2737578 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1078 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266516 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2744 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011789 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 51014533 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176491840 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2176598464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 8841697 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 25846865 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.114483 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.320694 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadExReq 2737572 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2737572 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 1074 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266537 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2732 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011834 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 51014566 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176493760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2176599872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 8842787 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 25847966 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.114476 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.320662 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 22906816 88.63% 88.63% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 2921078 11.30% 99.93% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 18971 0.07% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 22907787 88.63% 88.63% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 2921395 11.30% 99.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 18784 0.07% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 25846865 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 34008846525 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 25847966 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 34008868522 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 13536 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 13530 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1615497 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 1609497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 25506147987 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 25506170491 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 3697520 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1635907 # Transaction distribution
-system.membus.trans_dist::CleanEvict 3001520 # Transaction distribution
+system.membus.trans_dist::ReadResp 3697667 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1634781 # Transaction distribution
+system.membus.trans_dist::CleanEvict 3002759 # Transaction distribution
system.membus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.membus.trans_dist::ReadExReq 975763 # Transaction distribution
-system.membus.trans_dist::ReadExResp 975763 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 3697521 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983999 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 13983999 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403788160 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 403788160 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 975542 # Transaction distribution
+system.membus.trans_dist::ReadExResp 975542 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 3697668 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13983964 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 13983964 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403711360 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 403711360 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 9310716 # Request fanout histogram
+system.membus.snoop_fanout::samples 9310755 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 9310716 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 9310755 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 9310716 # Request fanout histogram
-system.membus.reqLayer0.occupancy 17657125833 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 9310755 # Request fanout histogram
+system.membus.reqLayer0.occupancy 17653458992 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 25413031627 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 25411663187 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 16 2016 15:38:19
-gem5 started Mar 16 2016 15:38:50
-gem5 executing on dinar2c11, pid 14357
+gem5 compiled Mar 16 2016 22:57:26
+gem5 started Mar 16 2016 22:58:08
+gem5 executing on dinar2c11, pid 24733
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re /home/stever/gem5-public/tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 79140979500 # Number of ticks simulated
final_tick 79140979500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 48369 # Simulator instruction rate (inst/s)
-host_op_rate 81071 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28984226 # Simulator tick rate (ticks/s)
-host_mem_usage 336892 # Number of bytes of host memory used
-host_seconds 2730.48 # Real time elapsed on the host
+host_inst_rate 47467 # Simulator instruction rate (inst/s)
+host_op_rate 79560 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28443866 # Simulator tick rate (ticks/s)
+host_mem_usage 336904 # Number of bytes of host memory used
+host_seconds 2782.36 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem_0.preBackEnergy 45310553250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 52987315485 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.541483 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 75375284500 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 75375284000 # Time in different power states
system.physmem_0.memoryStateTime::REF 2642640000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 1122707500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 1122708000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3470040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1893375 # Energy for precharge commands per rank (pJ)
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 884606250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 20604097 # Number of BP lookups
-system.cpu.branchPred.condPredicted 20604097 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 20604101 # Number of BP lookups
+system.cpu.branchPred.condPredicted 20604101 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1328804 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 12707128 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 12016947 # Number of BTB hits
+system.cpu.branchPred.BTBHits 12016946 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 94.568552 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 94.568545 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1442846 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 16873 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.numCycles 158281960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 25261186 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 227540228 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 20604097 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 13459793 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 131194120 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles 25261178 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 227540211 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 20604101 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 13459792 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 131194128 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 3196201 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 1974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 21216 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 47 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 24267792 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 24267790 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 266999 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 158076676 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.380152 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.324971 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.324972 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95737539 60.56% 60.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 95737541 60.56% 60.56% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4758449 3.01% 63.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 3804663 2.41% 65.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 3804662 2.41% 65.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4365114 2.76% 68.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4234763 2.68% 71.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 4816061 3.05% 74.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4706874 2.98% 77.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 4816060 3.05% 74.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4706873 2.98% 77.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3702906 2.34% 79.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 31950307 20.21% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 31950308 20.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.130173 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.437563 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 15410588 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 96165479 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 23286259 # Number of cycles decode is running
+system.cpu.decode.BlockedCycles 96165480 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 23286258 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 21616250 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 1598100 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 336629364 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 336629357 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 1598100 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 23294905 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 31785654 # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles 23294906 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 31785653 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 30420 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 36005072 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 65362525 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 328266719 # Number of instructions processed by rename
+system.cpu.rename.RunCycles 36005070 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 65362527 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 328266704 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1575 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 57713162 # Number of times rename has blocked due to IQ full
+system.cpu.rename.IQFullEvents 57713164 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 7745606 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 167786 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 380441368 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 910027762 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 600617825 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 380441390 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 910027714 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 600617838 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 4182134 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 121011918 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 121011940 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1942 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1920 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 120996232 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 82787391 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 29790688 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 59618216 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 20385329 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 317847109 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.skidInsts 120996238 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 82787388 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 29790681 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 59618218 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 20385333 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 317847098 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 5129 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 259397692 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 259397684 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 74444 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 96488854 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 197170724 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 96488843 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 197170698 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 3884 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 158076676 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.640961 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.524821 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 40037944 25.33% 25.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 47502917 30.05% 55.38% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 40037945 25.33% 25.33% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 47502914 30.05% 55.38% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 33077309 20.92% 76.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17993681 11.38% 87.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 10964078 6.94% 94.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 4766946 3.02% 97.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 2459939 1.56% 99.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 882458 0.56% 99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 17993682 11.38% 87.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 10964082 6.94% 94.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 4766949 3.02% 97.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 2459936 1.56% 99.19% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 882455 0.56% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 391404 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 158076676 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 232299 7.31% 7.31% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 232294 7.31% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.31% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1212757 0.47% 0.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 161810982 62.38% 62.85% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 161810976 62.38% 62.85% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 789695 0.30% 63.15% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 7037932 2.71% 65.86% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1186383 0.46% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 64896242 25.02% 91.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 22463701 8.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 64896241 25.02% 91.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 22463700 8.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 259397692 # Type of FU issued
+system.cpu.iq.FU_type_0::total 259397684 # Type of FU issued
system.cpu.iq.rate 1.638833 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 3176512 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 3176507 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012246 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 675268347 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 410944123 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 253662320 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads 675268326 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 410944101 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 253662317 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4854669 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 3693735 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2339703 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 258916836 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 258916823 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2444611 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 18724074 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 18724072 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 26137804 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 26137801 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 13130 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 303242 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 9274971 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 9274964 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 49888 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 49887 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 39 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 1598100 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 12496396 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 12496395 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 489060 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 317852238 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 317852227 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 92568 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 82787391 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 29790688 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 82787388 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 29790681 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 2962 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 383739 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 63074 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.predictedTakenIncorrect 551670 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 826736 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1378406 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 257339863 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 64084690 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2057829 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 257339859 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 64084689 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2057825 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 86369702 # number of memory reference insts executed
+system.cpu.iew.exec_refs 86369700 # number of memory reference insts executed
system.cpu.iew.exec_branches 14330688 # Number of branches executed
-system.cpu.iew.exec_stores 22285012 # Number of stores executed
+system.cpu.iew.exec_stores 22285011 # Number of stores executed
system.cpu.iew.exec_rate 1.625832 # Inst execution rate
-system.cpu.iew.wb_sent 256690837 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 256002023 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 204396158 # num instructions producing a value
-system.cpu.iew.wb_consumers 369708068 # num instructions consuming a value
+system.cpu.iew.wb_sent 256690834 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 256002020 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 204396152 # num instructions producing a value
+system.cpu.iew.wb_consumers 369708063 # num instructions consuming a value
system.cpu.iew.wb_rate 1.617380 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.552858 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 96496531 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 96496520 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1330625 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 144920748 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 144920750 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.527479 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.956907 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 45508636 31.40% 31.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 57312376 39.55% 70.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 14158342 9.77% 80.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 11991162 8.27% 88.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 4086517 2.82% 91.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2858053 1.97% 93.79% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 45508635 31.40% 31.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 57312379 39.55% 70.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 14158343 9.77% 80.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 11991163 8.27% 88.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 4086516 2.82% 91.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 2858052 1.97% 93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 923800 0.64% 94.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1073191 0.74% 95.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 7008671 4.84% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 1073190 0.74% 95.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 7008672 4.84% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 144920748 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 144920750 # Number of insts commited each cycle
system.cpu.commit.committedInsts 132071192 # Number of instructions committed
system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
-system.cpu.commit.bw_lim_events 7008671 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 455771992 # The number of ROB reads
-system.cpu.rob.rob_writes 648913303 # The number of ROB writes
+system.cpu.commit.bw_lim_events 7008672 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 455771982 # The number of ROB reads
+system.cpu.rob.rob_writes 648913279 # The number of ROB writes
system.cpu.timesIdled 2665 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 205284 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 132071192 # Number of Instructions Simulated
system.cpu.cpi_total 1.198459 # CPI: Total CPI of All Threads
system.cpu.ipc 0.834405 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.834405 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 448575238 # number of integer regfile reads
+system.cpu.int_regfile_reads 448575240 # number of integer regfile reads
system.cpu.int_regfile_writes 232602901 # number of integer regfile writes
system.cpu.fp_regfile_reads 3212636 # number of floating regfile reads
system.cpu.fp_regfile_writes 1997796 # number of floating regfile writes
-system.cpu.cc_regfile_reads 102540240 # number of cc regfile reads
-system.cpu.cc_regfile_writes 59516414 # number of cc regfile writes
-system.cpu.misc_regfile_reads 132474845 # number of misc regfile reads
+system.cpu.cc_regfile_reads 102540235 # number of cc regfile reads
+system.cpu.cc_regfile_writes 59516419 # number of cc regfile writes
+system.cpu.misc_regfile_reads 132474842 # number of misc regfile reads
system.cpu.misc_regfile_writes 1689 # number of misc regfile writes
system.cpu.dcache.tags.replacements 51 # number of replacements
system.cpu.dcache.tags.tagsinuse 1429.115986 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 65747317 # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 65747319 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1995 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 32956.048622 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 32956.049624 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1429.115986 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.348905 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1394 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.474609 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 131501473 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 131501473 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 45233028 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 45233028 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20513911 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20513911 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 65746939 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 65746939 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 65746939 # number of overall hits
-system.cpu.dcache.overall_hits::total 65746939 # number of overall hits
+system.cpu.dcache.tags.tag_accesses 131501477 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 131501477 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 45233030 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 45233030 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20513912 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20513912 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 65746942 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 65746942 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 65746942 # number of overall hits
+system.cpu.dcache.overall_hits::total 65746942 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 980 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 980 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1820 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1820 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2800 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2800 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2800 # number of overall misses
-system.cpu.dcache.overall_misses::total 2800 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 65148000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 65148000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 128547000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 128547000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 193695000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 193695000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 193695000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 193695000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 45234008 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 45234008 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data 1819 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1819 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2799 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2799 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2799 # number of overall misses
+system.cpu.dcache.overall_misses::total 2799 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 65149000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 65149000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 128515000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 128515000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 193664000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 193664000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 193664000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 193664000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 45234010 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 45234010 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 65749739 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 65749739 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 65749739 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 65749739 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 65749741 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 65749741 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 65749741 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 65749741 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66477.551020 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66477.551020 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70630.219780 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70630.219780 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69176.785714 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69176.785714 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69176.785714 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66478.571429 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 66478.571429 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70651.456844 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 70651.456844 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 69190.425152 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.425152 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 69190.425152 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 656 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 70 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked
system.cpu.dcache.overall_mshr_hits::total 528 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 454 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 454 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1818 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1818 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2272 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2272 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2272 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2272 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126583000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 126583000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162646000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 162646000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162646000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 162646000 # number of overall MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1817 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1817 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2271 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2271 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2271 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2271 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36063500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 36063500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 126552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 126552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 162615500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 162615500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 162615500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 162615500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79433.920705 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79433.920705 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69627.612761 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69627.612761 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71587.147887 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 71587.147887 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79435.022026 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79435.022026 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69648.871767 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69648.871767 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71605.239982 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 71605.239982 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5017 # number of replacements
-system.cpu.icache.tags.tagsinuse 1636.801929 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 24258361 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 1636.805094 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 24258360 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 6993 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3468.949092 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3468.948949 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1636.801929 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.799220 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.799220 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 1636.805094 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.799221 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.799221 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1976 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.964844 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 48542851 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 48542851 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 24258362 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 24258362 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 24258362 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 24258362 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 24258362 # number of overall hits
-system.cpu.icache.overall_hits::total 24258362 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 9429 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 9429 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 9429 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 9429 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 9429 # number of overall misses
-system.cpu.icache.overall_misses::total 9429 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 409019999 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 409019999 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 409019999 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 409019999 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 409019999 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 409019999 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 24267791 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 24267791 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 24267791 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 24267791 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 24267791 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 24267791 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000389 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000389 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000389 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000389 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000389 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000389 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43378.937215 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 43378.937215 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 43378.937215 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 43378.937215 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 43378.937215 # average overall miss latency
+system.cpu.icache.tags.tag_accesses 48542846 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 48542846 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 24258361 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 24258361 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 24258361 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 24258361 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 24258361 # number of overall hits
+system.cpu.icache.overall_hits::total 24258361 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 9428 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 9428 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 9428 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 9428 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 9428 # number of overall misses
+system.cpu.icache.overall_misses::total 9428 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 409015499 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 409015499 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 409015499 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 409015499 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 409015499 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 409015499 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 24267789 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 24267789 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 24267789 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 24267789 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 24267789 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 24267789 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000388 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000388 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000388 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000388 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000388 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000388 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43383.060989 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 43383.060989 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 43383.060989 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 43383.060989 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 43383.060989 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 793 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.icache.demand_mshr_hits::total 2159 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 2159 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 2159 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7270 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 7270 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 7270 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 7270 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 7270 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 7270 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311109999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 311109999 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311109999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 311109999 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311109999 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 311109999 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7269 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 7269 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 7269 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 7269 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 7269 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 7269 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311106499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 311106499 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311106499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 311106499 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311106499 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 311106499 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000300 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000300 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000300 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000300 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42793.672490 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42793.672490 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42793.672490 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 42793.672490 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42799.078140 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42799.078140 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42799.078140 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 42799.078140 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2581.252539 # Cycle average of tags in use
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 41 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2611 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118378 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 119261 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 119261 # Number of data accesses
+system.cpu.l2cache.tags.tag_accesses 119253 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 119253 # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total 10 # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks 4917 # number of WritebackClean hits
system.cpu.l2cache.overall_hits::cpu.inst 3531 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 41 # number of overall hits
system.cpu.l2cache.overall_hits::total 3572 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 276 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 276 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 275 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 275 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 1535 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 3460 # number of ReadCleanReq misses
system.cpu.l2cache.overall_misses::total 5414 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115784500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 115784500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 262406500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 150761500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 262406000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 262406000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34977500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 34977500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 262406000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 150762000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 413168000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 262406500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 150761500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 262406000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 150762000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 413168000 # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total 10 # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks 4917 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 4917 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 277 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 277 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 276 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 276 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1541 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 6991 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.overall_accesses::cpu.inst 6991 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 1995 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 8986 # number of overall (read+write) accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996390 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996390 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.996377 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.996377 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.996106 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.494922 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.overall_miss_rate::total 0.602493 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75429.641694 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75429.641694 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75840.028902 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75840.028902 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83477.326969 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83477.326969 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75839.884393 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75839.884393 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83478.520286 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83478.520286 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76314.739564 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75840.028902 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.322416 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75839.884393 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77155.578301 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76314.739564 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 276 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 276 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 275 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 275 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 1535 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3460 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1954 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 5414 # number of overall MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5237000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5237000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5217500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5217500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 100434500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 100434500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131221500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 227816000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 227816000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 30787500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 30787500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 227816000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131222000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 359038000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131221500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 227816000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131222000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 359038000 # number of overall MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996390 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996390 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.996377 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.996377 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996106 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.494922 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.979449 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.602493 # mshr miss rate for overall accesses
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18974.637681 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18974.637681 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18972.727273 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18972.727273 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65429.641694 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65429.641694 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.919075 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.919075 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73477.326969 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73477.326969 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65842.774566 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65842.774566 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73478.520286 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73478.520286 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.919075 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.322416 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65842.774566 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67155.578301 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66316.586627 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 14610 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 5368 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 377 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 14608 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 5367 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 376 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 7723 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7722 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty 10 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 5017 # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict 41 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 276 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 276 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1541 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1541 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 7270 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 7269 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq 454 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19277 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4595 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 23872 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19276 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4593 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 23869 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 768448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128320 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 896768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 279 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 9542 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.070845 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.256579 # Request fanout histogram
+system.cpu.toL2Bus.snoops 278 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 9540 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.070650 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.256253 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 8866 92.92% 92.92% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 676 7.08% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 8866 92.94% 92.94% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 674 7.06% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 9542 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 12332000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 9540 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 12331000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 10903500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 10902000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3131998 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3131498 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadResp 3878 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 276 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 275 # Transaction distribution
system.membus.trans_dist::ReadExReq 1535 # Transaction distribution
system.membus.trans_dist::ReadExResp 1535 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 3878 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11102 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11102 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 11102 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11101 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11101 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11101 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 346432 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 5689 # Request fanout histogram
+system.membus.snoop_fanout::samples 5688 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5689 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 5688 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5689 # Request fanout histogram
-system.membus.reqLayer0.occupancy 6955500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 5688 # Request fanout histogram
+system.membus.reqLayer0.occupancy 6954000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 28681250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:03
-gem5 executing on zizzer, pid 34007
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:56:23
+gem5 executing on phenom, pid 28115
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 37553000 because target called exit()
+Exiting @ tick 37629000 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000038 # Number of seconds simulated
-sim_ticks 37553000 # Number of ticks simulated
-final_tick 37553000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 37629000 # Number of ticks simulated
+final_tick 37629000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 69445 # Simulator instruction rate (inst/s)
-host_op_rate 69425 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 407253641 # Simulator tick rate (ticks/s)
-host_mem_usage 231420 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-sim_insts 6400 # Number of instructions simulated
-sim_ops 6400 # Number of ops (including micro ops) simulated
+host_inst_rate 36642 # Simulator instruction rate (inst/s)
+host_op_rate 36638 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 214955628 # Simulator tick rate (ticks/s)
+host_mem_usage 227692 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
+sim_insts 6413 # Number of instructions simulated
+sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 620349905 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 288019599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 908369504 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 620349905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 620349905 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 620349905 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 288019599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 908369504 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 619096973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 287437880 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 906534853 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 619096973 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 619096973 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 619096973 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 287437880 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 906534853 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 37448500 # Total gap between requests
+system.physmem.totGap 37524500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 444 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 247.290862 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.108272 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 20 23.81% 23.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 22.62% 46.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2 2.38% 73.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5 5.95% 79.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 3.57% 83.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 6 7.14% 90.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8 9.52% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation
-system.physmem.totQLat 3307750 # Total ticks spent queuing
-system.physmem.totMemAccLat 13301500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 388.626506 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 254.752349 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 332.370925 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 19 22.89% 44.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 11 13.25% 57.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 11 13.25% 71.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2 2.41% 73.49% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 5 6.02% 79.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 2.41% 81.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 7 8.43% 90.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8 9.64% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
+system.physmem.totQLat 3516000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13509750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6205.91 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6596.62 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24955.91 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 908.37 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 25346.62 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 906.53 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 908.37 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 906.53 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.10 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.10 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.08 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.08 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 437 # Number of row buffer hits during reads
+system.physmem.readRowHits 438 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 70259.85 # Average gap between requests
-system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 226800 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 123750 # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap 70402.44 # Average gap between requests
+system.physmem.pageHitRate 82.18 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 21178350 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 265500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 25872240 # Total energy per rank (pJ)
-system.physmem_0.averagePower 823.825505 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 346000 # Time in different power states
+system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ)
+system.physmem_0.averagePower 825.080242 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 105750 # Time in different power states
system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 30032750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1544400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 20535390 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 831750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 25491090 # Total energy per rank (pJ)
-system.physmem_1.averagePower 811.591993 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1333500 # Time in different power states
+system.physmem_1.actBackEnergy 20470410 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 886500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 25449690 # Total energy per rank (pJ)
+system.physmem_1.averagePower 810.370642 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1337750 # Time in different power states
system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 29134000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 29041000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 1929 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1187 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 360 # Number of conditional branches incorrect
+system.cpu.branchPred.lookups 1942 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1197 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 362 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1557 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 398 # Number of BTB hits
+system.cpu.branchPred.BTBHits 406 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 25.561978 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 26.075787 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 225 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1369 # DTB read hits
+system.cpu.dtb.read_hits 1372 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1380 # DTB read accesses
+system.cpu.dtb.read_accesses 1383 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
-system.cpu.dtb.data_hits 2253 # DTB hits
+system.cpu.dtb.data_hits 2256 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2267 # DTB accesses
-system.cpu.itb.fetch_hits 2651 # ITB hits
+system.cpu.dtb.data_accesses 2270 # DTB accesses
+system.cpu.itb.fetch_hits 2673 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2668 # ITB accesses
+system.cpu.itb.fetch_accesses 2690 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 75106 # number of cpu cycles simulated
+system.cpu.numCycles 75258 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6400 # Number of instructions committed
-system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1085 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 6413 # Number of instructions committed
+system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 1090 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 11.735312 # CPI: cycles per instruction
-system.cpu.ipc 0.085213 # IPC: instructions per cycle
-system.cpu.tickCycles 12517 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 62589 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 11.735225 # CPI: cycles per instruction
+system.cpu.ipc 0.085214 # IPC: instructions per cycle
+system.cpu.tickCycles 12565 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 62693 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 103.920661 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1972 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 104.289845 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1974 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.668639 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.680473 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 103.920661 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025371 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025371 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 104.289845 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025461 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025461 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4567 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4567 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1232 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1232 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1972 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1972 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1972 # number of overall hits
-system.cpu.dcache.overall_hits::total 1972 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 1974 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1974 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1974 # number of overall hits
+system.cpu.dcache.overall_hits::total 1974 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses
-system.cpu.dcache.overall_misses::total 227 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8311500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8311500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9136500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9136500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17448000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17448000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17448000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17448000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1334 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1334 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 228 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 228 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 228 # number of overall misses
+system.cpu.dcache.overall_misses::total 228 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8381500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8381500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 17546000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 17546000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 17546000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 17546000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2199 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2199 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2199 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2199 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076462 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076462 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077038 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.077038 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.103229 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.103229 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.103229 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.103229 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81485.294118 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 81485.294118 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73092 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 73092 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76863.436123 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76863.436123 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76863.436123 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.103542 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.103542 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.103542 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.103542 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81373.786408 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 81373.786408 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 76956.140351 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 76956.140351 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 76956.140351 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 59 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7818500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7818500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5371500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5371500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13190000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13190000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13190000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13190000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071964 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071964 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7819000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7819000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13204500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13204500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13204500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13204500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076853 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076853 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076853 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81442.708333 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81442.708333 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73582.191781 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73582.191781 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78047.337278 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 78047.337278 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81447.916667 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81447.916667 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78133.136095 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 78133.136095 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 175.815240 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 2286 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 175.465909 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 2308 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 6.263014 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6.323288 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 175.815240 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.085847 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.085847 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 175.465909 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.085677 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.085677 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 5667 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 5667 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 2286 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 2286 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 2286 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 2286 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 2286 # number of overall hits
-system.cpu.icache.overall_hits::total 2286 # number of overall hits
+system.cpu.icache.tags.tag_accesses 5711 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 5711 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2308 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2308 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 2308 # number of overall hits
+system.cpu.icache.overall_hits::total 2308 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
system.cpu.icache.overall_misses::total 365 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 27932500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 27932500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 27932500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 27932500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 27932500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 27932500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2651 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2651 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2651 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2651 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2651 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2651 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.137684 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.137684 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.137684 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.137684 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.137684 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.137684 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76527.397260 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 76527.397260 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 76527.397260 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 76527.397260 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 76527.397260 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 28127000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 28127000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 28127000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 28127000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 28127000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 28127000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2673 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2673 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2673 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2673 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2673 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2673 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.136551 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.136551 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.136551 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.136551 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.136551 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.136551 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77060.273973 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 77060.273973 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 77060.273973 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 77060.273973 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 77060.273973 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27567500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 27567500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27567500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 27567500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27567500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 27567500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137684 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.137684 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137684 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.137684 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75527.397260 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75527.397260 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75527.397260 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 75527.397260 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27762000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 27762000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27762000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 27762000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27762000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 27762000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136551 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.136551 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136551 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.136551 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76060.273973 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76060.273973 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76060.273973 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76060.273973 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 233.452540 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 233.562418 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.828674 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 57.623866 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005366 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.007124 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.479316 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 58.083102 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005355 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.007128 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
system.cpu.l2cache.overall_misses::total 533 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5261000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5261000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27008000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 27008000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 27008000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 12934000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 39942000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 27008000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 12934000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 39942000 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27202500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 27202500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7673500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 7673500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 27202500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 12948500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 40151000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 27202500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 12948500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 40151000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72068.493151 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72068.493151 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74197.802198 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74197.802198 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79927.083333 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79927.083333 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74938.086304 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74197.802198 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76532.544379 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74938.086304 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74732.142857 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74732.142857 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79932.291667 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79932.291667 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 75330.206379 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74732.142857 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76618.343195 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 75330.206379 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4531000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4531000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23368000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23368000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11244000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 34612000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11244000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 34612000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23562500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23562500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6713500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6713500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23562500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11258500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 34821000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23562500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11258500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 34821000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62068.493151 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62068.493151 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64197.802198 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64197.802198 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69927.083333 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69927.083333 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64197.802198 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66532.544379 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64938.086304 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64732.142857 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64732.142857 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69932.291667 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69932.291667 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64732.142857 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66618.343195 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65330.206379 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests 534 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 533 # Request fanout histogram
-system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks)
+system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2833000 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2833750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 13 2016 22:43:13
-gem5 started Mar 13 2016 22:49:02
-gem5 executing on phenom, pid 19909
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:57:45
+gem5 executing on phenom, pid 28188
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 21900500 because target called exit()
+Exiting @ tick 21972500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 21900500 # Number of ticks simulated
-final_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 21972500 # Number of ticks simulated
+final_tick 21972500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 27169 # Simulator instruction rate (inst/s)
-host_op_rate 27167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 93368241 # Simulator tick rate (ticks/s)
-host_mem_usage 228936 # Number of bytes of host memory used
-host_seconds 0.23 # Real time elapsed on the host
-sim_insts 6372 # Number of instructions simulated
-sim_ops 6372 # Number of ops (including micro ops) simulated
+host_inst_rate 66596 # Simulator instruction rate (inst/s)
+host_op_rate 66584 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 229093695 # Simulator tick rate (ticks/s)
+host_mem_usage 228860 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 6385 # Number of instructions simulated
+sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
+system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 481 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 481 # Number of read requests accepted
+system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 902946865 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 503902606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1406849471 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 902946865 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 902946865 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 902946865 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 503902606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1406849471 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 483 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30784 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdBursts::1 32 # Per bank write bursts
system.physmem.perBankRdBursts::2 32 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
-system.physmem.perBankRdBursts::4 41 # Per bank write bursts
+system.physmem.perBankRdBursts::4 42 # Per bank write bursts
system.physmem.perBankRdBursts::5 20 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::12 14 # Per bank write bursts
system.physmem.perBankRdBursts::13 118 # Per bank write bursts
system.physmem.perBankRdBursts::14 45 # Per bank write bursts
-system.physmem.perBankRdBursts::15 12 # Per bank write bursts
+system.physmem.perBankRdBursts::15 13 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 21763000 # Total gap between requests
+system.physmem.totGap 21835000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 481 # Read request sizes (log2)
+system.physmem.readPktSize::6 483 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
-system.physmem.totQLat 3965000 # Total ticks spent queuing
-system.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2405000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 352 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 228.419611 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 324.406987 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 20 26.32% 50.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 9 11.84% 61.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 11 14.47% 76.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 5.26% 81.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 1.32% 82.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 3.95% 86.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
+system.physmem.totQLat 3936250 # Total ticks spent queuing
+system.physmem.totMemAccLat 12992500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 8149.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26899.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1406.85 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1406.85 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.98 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.99 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.99 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 387 # Number of row buffer hits during reads
+system.physmem.readRowHits 392 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45245.32 # Average gap between requests
-system.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 45207.04 # Average gap between requests
+system.physmem.pageHitRate 81.16 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ)
+system.physmem_0.readEnergy 1638000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ)
-system.physmem_0.averagePower 870.058740 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states
+system.physmem_0.totalEnergy 13783005 # Total energy per rank (pJ)
+system.physmem_0.averagePower 870.551397 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 281750 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ)
-system.physmem_1.averagePower 855.521554 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states
+system.physmem_1.actBackEnergy 10134315 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 609750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 13503900 # Total energy per rank (pJ)
+system.physmem_1.averagePower 852.922785 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 945500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 14380750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2551 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 726 # Number of BTB hits
+system.cpu.branchPred.lookups 2618 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1561 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 431 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2031 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 757 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 37.272280 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 391 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2033 # DTB read hits
+system.cpu.dtb.read_hits 2066 # DTB read hits
system.cpu.dtb.read_misses 43 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2076 # DTB read accesses
-system.cpu.dtb.write_hits 1052 # DTB write hits
+system.cpu.dtb.read_accesses 2109 # DTB read accesses
+system.cpu.dtb.write_hits 1060 # DTB write hits
system.cpu.dtb.write_misses 28 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1080 # DTB write accesses
-system.cpu.dtb.data_hits 3085 # DTB hits
+system.cpu.dtb.write_accesses 1088 # DTB write accesses
+system.cpu.dtb.data_hits 3126 # DTB hits
system.cpu.dtb.data_misses 71 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3156 # DTB accesses
-system.cpu.itb.fetch_hits 2086 # ITB hits
-system.cpu.itb.fetch_misses 32 # ITB misses
+system.cpu.dtb.data_accesses 3197 # DTB accesses
+system.cpu.itb.fetch_hits 2136 # ITB hits
+system.cpu.itb.fetch_misses 29 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2118 # ITB accesses
+system.cpu.itb.fetch_accesses 2165 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 43802 # number of cpu cycles simulated
+system.cpu.numCycles 43946 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 14953 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2551 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2086 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 8425 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 15219 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2618 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1148 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 4748 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 944 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 705 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 2136 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.058860 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.441925 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11578 80.55% 80.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 318 2.21% 82.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 240 1.67% 84.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 228 1.59% 86.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 264 1.84% 87.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 210 1.46% 89.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 253 1.76% 91.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 143 0.99% 92.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1139 7.92% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2283 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch
+system.cpu.fetch.rateDist::total 14373 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.059573 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.346311 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8351 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 3116 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2327 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 180 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 399 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 208 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 13836 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2297 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename
+system.cpu.rename.SquashCycles 399 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8502 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1476 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 647 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2338 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1011 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 13352 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full
+system.cpu.rename.IQFullEvents 32 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 10012 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 16699 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 16690 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 571 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5435 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 32 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 599 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2560 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10150 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded 12265 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 10237 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5909 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3249 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 14373 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.712238 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.437631 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10470 72.84% 72.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1281 8.91% 81.76% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 885 6.16% 87.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 672 4.68% 92.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 490 3.41% 96.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 330 2.30% 98.30% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 178 1.24% 99.53% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14373 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 20 14.93% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.93% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 73 54.48% 69.40% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 41 30.60% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 6864 67.05% 67.07% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.08% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.08% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2247 21.95% 89.05% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1121 10.95% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10150 # Type of FU issued
-system.cpu.iq.rate 0.231725 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 132 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10237 # Type of FU issued
+system.cpu.iq.rate 0.232945 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 134 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013090 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 34976 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 18212 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9377 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10358 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1375 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 75 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 399 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1377 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 12377 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewDispLoadInsts 2560 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 21 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute
+system.cpu.iew.branchMispredicts 429 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 9833 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2109 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 84 # number of nop insts executed
-system.cpu.iew.exec_refs 3158 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1540 # Number of branches executed
-system.cpu.iew.exec_stores 1082 # Number of stores executed
-system.cpu.iew.exec_rate 0.222638 # Inst execution rate
-system.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9326 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 4992 # num instructions producing a value
-system.cpu.iew.wb_consumers 6833 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.212913 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 82 # number of nop insts executed
+system.cpu.iew.exec_refs 3199 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1559 # Number of branches executed
+system.cpu.iew.exec_stores 1090 # Number of stores executed
+system.cpu.iew.exec_rate 0.223752 # Inst execution rate
+system.cpu.iew.wb_sent 9541 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9387 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5006 # num instructions producing a value
+system.cpu.iew.wb_consumers 6861 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.213603 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.729631 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 5982 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 358 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13303 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.481245 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.398957 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 10861 81.64% 81.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1165 8.76% 90.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 487 3.66% 94.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 203 1.53% 95.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 129 0.97% 96.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 82 0.62% 97.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 98 0.74% 97.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 84 0.63% 98.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 194 1.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 6389 # Number of instructions committed
-system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 13303 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 6402 # Number of instructions committed
+system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2048 # Number of memory references committed
-system.cpu.commit.loads 1183 # Number of loads committed
+system.cpu.commit.refs 2050 # Number of memory references committed
+system.cpu.commit.loads 1185 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 1050 # Number of branches committed
+system.cpu.commit.branches 1056 # Number of branches committed
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 6307 # Number of committed integer instructions.
+system.cpu.commit.int_insts 6319 # Number of committed integer instructions.
system.cpu.commit.function_calls 127 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
+system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
system.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 24728 # The number of ROB reads
-system.cpu.rob.rob_writes 25475 # The number of ROB writes
-system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 6372 # Number of Instructions Simulated
-system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.874137 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.145473 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12363 # number of integer regfile reads
-system.cpu.int_regfile_writes 7056 # number of integer regfile writes
+system.cpu.rob.rob_reads 25142 # The number of ROB reads
+system.cpu.rob.rob_writes 25845 # The number of ROB writes
+system.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29573 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 6385 # Number of Instructions Simulated
+system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 6.882694 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.882694 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.145292 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.145292 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12434 # number of integer regfile reads
+system.cpu.int_regfile_writes 7099 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 109.593222 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2292 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.248555 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5747 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits
+system.cpu.dcache.tags.occ_blocks::cpu.data 109.593222 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.026756 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.026756 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5805 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5805 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1786 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1786 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits
-system.cpu.dcache.overall_hits::total 2276 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2292 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2292 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2292 # number of overall hits
+system.cpu.dcache.overall_hits::total 2292 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
-system.cpu.dcache.overall_misses::total 512 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses
+system.cpu.dcache.overall_misses::total 524 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 12170500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 12170500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 35821975 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35821975 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35821975 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35821975 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1951 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2816 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2816 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2816 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2816 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084572 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.084572 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.186080 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.186080 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.186080 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.186080 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73760.606061 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 73760.606061 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 68362.547710 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 68362.547710 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 68362.547710 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2432 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 56.558140 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8462500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 8462500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14132000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14132000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14132000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14132000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051768 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051768 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.061435 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061435 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.061435 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83787.128713 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83787.128713 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81687.861272 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 81687.861272 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 157.288732 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1677 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 5.392283 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 157.288732 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.076801 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.076801 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4483 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1627 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1627 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1627 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1627 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits
-system.cpu.icache.overall_hits::total 1627 # number of overall hits
+system.cpu.icache.tags.tag_accesses 4583 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4583 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1677 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1677 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1677 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1677 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1677 # number of overall hits
+system.cpu.icache.overall_hits::total 1677 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses
system.cpu.icache.overall_misses::total 459 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32358000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32358000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 32358000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 32358000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32358000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32358000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2136 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2136 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2136 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2136 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2136 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2136 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.214888 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.214888 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.214888 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.214888 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.214888 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.214888 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70496.732026 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 70496.732026 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 70496.732026 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 70496.732026 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 70496.732026 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23850000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 23850000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23850000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 23850000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23850000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 23850000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145599 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.145599 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145599 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.145599 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76688.102894 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76688.102894 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76688.102894 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 76688.102894 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 219.942323 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 411 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.002433 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 60.394993 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004816 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001843 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006659 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012482 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4337 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4337 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 157.331171 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 62.611152 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004801 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001911 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006712 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012543 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4355 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4355 # Number of data accesses
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 310 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 99 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 99 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 310 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 171 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 310 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 171 # number of overall misses
-system.cpu.l2cache.overall_misses::total 481 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses
+system.cpu.l2cache.overall_misses::total 483 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5558500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5558500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23380000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 23380000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8185000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 8185000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 23380000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 13743500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 37123500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 23380000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 13743500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 37123500 # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23369500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 23369500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8303500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 8303500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 23369500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 13862000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 37231500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 23369500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 13862000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 37231500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 311 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 311 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 99 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 311 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 171 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 311 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 171 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996785 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996785 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.997925 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997934 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996785 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.997934 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75385.483871 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75385.483871 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82212.871287 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82212.871287 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 77083.850932 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75385.483871 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80127.167630 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 77083.850932 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20269500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20269500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7293500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7293500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20269500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12132000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 32401500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20269500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12132000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 32401500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65385.483871 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65385.483871 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72212.871287 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72212.871287 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65385.483871 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70127.167630 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67083.850932 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 412 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 484 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002066 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.045455 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 483 99.79% 99.79% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 484 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 409 # Transaction distribution
+system.membus.trans_dist::ReadResp 411 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 409 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 411 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 481 # Request fanout histogram
+system.membus.snoop_fanout::samples 483 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 483 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 481 # Request fanout histogram
-system.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 483 # Request fanout histogram
+system.membus.reqLayer0.occupancy 588000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2567750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.7 # Layer utilization (%)
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:02
-gem5 executing on zizzer, pid 34000
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:56:00
+gem5 executing on phenom, pid 28087
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 3208000 because target called exit()
+Exiting @ tick 3214500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 3208000 # Number of ticks simulated
-final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 3214500 # Number of ticks simulated
+final_tick 3214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146057 # Simulator instruction rate (inst/s)
-host_op_rate 145971 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 73240755 # Simulator tick rate (ticks/s)
-host_mem_usage 220608 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 21023 # Simulator instruction rate (inst/s)
+host_op_rate 21020 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 10551583 # Simulator tick rate (ticks/s)
+host_mem_usage 216888 # Number of bytes of host memory used
+host_seconds 0.30 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8788 # Number of bytes read from this memory
-system.physmem.bytes_read::total 34388 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 25600 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 25600 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 25652 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8804 # Number of bytes read from this memory
+system.physmem.bytes_read::total 34456 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 25652 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 25652 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.physmem.bytes_written::total 6696 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 6400 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1183 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 7583 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 6413 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1185 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 7598 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.physmem.num_writes::total 865 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7980049875 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2739401496 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10719451372 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7980049875 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7980049875 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 2087281796 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2087281796 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 7980090216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2738839633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 10718929849 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7980090216 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7980090216 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 2083061129 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2083061129 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7980090216 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4821900762 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 12801990978 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6400 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6413 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6417 # ITB accesses
+system.cpu.itb.fetch_accesses 6430 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 6417 # number of cpu cycles simulated
+system.cpu.numCycles 6430 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 6417 # Number of busy cycles
+system.cpu.num_busy_cycles 6430 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
-system.membus.trans_dist::ReadReq 7583 # Transaction distribution
-system.membus.trans_dist::ReadResp 7583 # Transaction distribution
+system.cpu.op_class::total 6413 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7598 # Transaction distribution
+system.membus.trans_dist::ReadResp 7598 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
system.membus.trans_dist::WriteResp 865 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12826 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4100 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 16926 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25652 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15500 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 41152 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8448 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram
+system.membus.snoop_fanout::samples 8463 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.757769 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.428459 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram
-system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2050 24.22% 24.22% # Request fanout histogram
+system.membus.snoop_fanout::1 6413 75.78% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 8448 # Request fanout histogram
+system.membus.snoop_fanout::total 8463 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
+Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:01:33
-gem5 started Jan 21 2016 14:02:10
-gem5 executing on zizzer, pid 44721
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Mar 14 2016 22:00:08
+gem5 started Mar 14 2016 22:01:20
+gem5 executing on phenom, pid 28860
+command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 121460 because target called exit()
+Exiting @ tick 121535 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000121 # Number of seconds simulated
-sim_ticks 121460 # Number of ticks simulated
-final_tick 121460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000122 # Number of seconds simulated
+sim_ticks 121535 # Number of ticks simulated
+final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 58804 # Simulator instruction rate (inst/s)
-host_op_rate 58798 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1117518 # Simulator tick rate (ticks/s)
-host_mem_usage 412400 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 23854 # Simulator instruction rate (inst/s)
+host_op_rate 23852 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 452710 # Simulator tick rate (ticks/s)
+host_mem_usage 387364 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93440 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 93440 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 17728 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1460 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1460 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 769306768 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 769306768 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 145957517 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 145957517 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 915264285 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 915264285 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1460 # Number of read requests accepted
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 769358621 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 769358621 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 145867446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 145867446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 915226067 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 915226067 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1461 # Number of read requests accepted
system.mem_ctrls.writeReqs 277 # Number of write requests accepted
-system.mem_ctrls.readBursts 1460 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 74176 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadDRAM 74240 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 93440 # Total read bytes from the system interface side
+system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 48 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 49 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 121373 # Total gap between requests
+system.mem_ctrls.totGap 121448 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1460 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1461 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1159 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1160 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 361.079070 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 218.518186 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 343.911785 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 62 28.84% 28.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 53 24.65% 53.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 19 8.84% 62.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 18 8.37% 70.70% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 12 5.58% 76.28% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 6 2.79% 79.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 11 5.12% 84.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 8 3.72% 87.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 26 12.09% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 217 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 357.751152 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 214.775071 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 343.064988 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 66 30.41% 30.41% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 51 23.50% 53.92% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 17 7.83% 61.75% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 18 8.29% 70.05% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 15 6.91% 76.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 6 2.76% 79.72% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 12 5.53% 85.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 4 1.84% 87.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 28 12.90% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 217 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 150.200000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 107.544474 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 96.970098 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 150.400000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 107.633945 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 97.202366 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8037 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 30058 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5795 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.93 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 8011 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 30051 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5800 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 6.91 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.93 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 610.70 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 44.26 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 769.31 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 145.96 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 25.91 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 610.85 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 44.23 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 769.36 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 145.87 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 22.44 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 944 # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.45 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 81.29 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes
system.mem_ctrls.avgGap 69.88 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.28 # Row buffer hit rate, read and write combined
+system.mem_ctrls.pageHitRate 80.14 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 66392460 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 11991000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 92751972 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 792.413259 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 22133 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 65986164 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 12347400 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 92702076 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 791.986980 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 22788 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 93571 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 92991 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 78596388 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1285800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 98062908 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 837.786484 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 1555 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 78402132 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 1456200 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 98062572 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 837.783614 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 1811 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 111609 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 121460 # number of cpu cycles simulated
+system.cpu.numCycles 121535 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 121460 # Number of busy cycles
+system.cpu.num_busy_cycles 121535 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 9645 # delay histogram for all message
-system.ruby.delayHist::mean 0.164852 # delay histogram for all message
-system.ruby.delayHist::stdev 1.012053 # delay histogram for all message
-system.ruby.delayHist | 9285 96.27% 96.27% | 0 0.00% 96.27% | 215 2.23% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 9645 # delay histogram for all message
+system.ruby.delayHist::samples 9652 # delay histogram for all message
+system.ruby.delayHist::mean 0.164525 # delay histogram for all message
+system.ruby.delayHist::stdev 1.011525 # delay histogram for all message
+system.ruby.delayHist | 9293 96.28% 96.28% | 0 0.00% 96.28% | 214 2.22% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 9652 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 8449
+system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 8449
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 8448
-system.ruby.latency_hist_seqr::mean 13.377367
-system.ruby.latency_hist_seqr::gmean 2.098947
-system.ruby.latency_hist_seqr::stdev 29.666839
-system.ruby.latency_hist_seqr | 7289 86.28% 86.28% | 1140 13.49% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 5 0.06% 99.89% | 9 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 8448
+system.ruby.latency_hist_seqr::samples 8463
+system.ruby.latency_hist_seqr::mean 13.360747
+system.ruby.latency_hist_seqr::gmean 2.097350
+system.ruby.latency_hist_seqr::stdev 29.565169
+system.ruby.latency_hist_seqr | 7303 86.29% 86.29% | 1141 13.48% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 8 0.09% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 6958
+system.ruby.hit_latency_hist_seqr::samples 6972
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6958 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 6958
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6972 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 6972
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1490
-system.ruby.miss_latency_hist_seqr::mean 71.177181
-system.ruby.miss_latency_hist_seqr::gmean 66.939744
-system.ruby.miss_latency_hist_seqr::stdev 30.560087
-system.ruby.miss_latency_hist_seqr | 331 22.21% 22.21% | 1140 76.51% 98.72% | 4 0.27% 98.99% | 1 0.07% 99.06% | 5 0.34% 99.40% | 9 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1490
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits
+system.ruby.miss_latency_hist_seqr::samples 1491
+system.ruby.miss_latency_hist_seqr::mean 71.160295
+system.ruby.miss_latency_hist_seqr::gmean 66.961050
+system.ruby.miss_latency_hist_seqr::stdev 30.103565
+system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1491
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 5722 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 4.310267
-system.ruby.network.routers0.msg_count.Control::0 1490
+system.ruby.network.routers0.percent_links_utilized 4.310281
+system.ruby.network.routers0.msg_count.Control::0 1491
system.ruby.network.routers0.msg_count.Request_Control::2 1041
-system.ruby.network.routers0.msg_count.Response_Data::1 1490
-system.ruby.network.routers0.msg_count.Response_Control::1 1336
-system.ruby.network.routers0.msg_count.Response_Control::2 799
+system.ruby.network.routers0.msg_count.Response_Data::1 1491
+system.ruby.network.routers0.msg_count.Response_Control::1 1337
+system.ruby.network.routers0.msg_count.Response_Control::2 800
system.ruby.network.routers0.msg_count.Writeback_Data::0 145
system.ruby.network.routers0.msg_count.Writeback_Data::1 141
-system.ruby.network.routers0.msg_count.Writeback_Control::0 291
-system.ruby.network.routers0.msg_bytes.Control::0 11920
+system.ruby.network.routers0.msg_count.Writeback_Control::0 292
+system.ruby.network.routers0.msg_bytes.Control::0 11928
system.ruby.network.routers0.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers0.msg_bytes.Response_Control::1 10688
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers0.msg_bytes.Response_Data::1 107352
+system.ruby.network.routers0.msg_bytes.Response_Control::1 10696
+system.ruby.network.routers0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers1.percent_links_utilized 8.369216
-system.ruby.network.routers1.msg_count.Control::0 2950
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers1.percent_links_utilized 8.369194
+system.ruby.network.routers1.msg_count.Control::0 2952
system.ruby.network.routers1.msg_count.Request_Control::2 1041
-system.ruby.network.routers1.msg_count.Response_Data::1 3227
-system.ruby.network.routers1.msg_count.Response_Control::1 3963
-system.ruby.network.routers1.msg_count.Response_Control::2 799
+system.ruby.network.routers1.msg_count.Response_Data::1 3229
+system.ruby.network.routers1.msg_count.Response_Control::1 3966
+system.ruby.network.routers1.msg_count.Response_Control::2 800
system.ruby.network.routers1.msg_count.Writeback_Data::0 145
system.ruby.network.routers1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers1.msg_bytes.Control::0 23600
+system.ruby.network.routers1.msg_count.Writeback_Control::0 292
+system.ruby.network.routers1.msg_bytes.Control::0 23616
system.ruby.network.routers1.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers1.msg_bytes.Response_Data::1 232344
-system.ruby.network.routers1.msg_bytes.Response_Control::1 31704
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers1.msg_bytes.Response_Data::1 232488
+system.ruby.network.routers1.msg_bytes.Response_Control::1 31728
+system.ruby.network.routers1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers2.percent_links_utilized 4.058949
-system.ruby.network.routers2.msg_count.Control::0 1460
-system.ruby.network.routers2.msg_count.Response_Data::1 1737
-system.ruby.network.routers2.msg_count.Response_Control::1 2627
-system.ruby.network.routers2.msg_bytes.Control::0 11680
-system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
-system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
-system.ruby.network.routers3.percent_links_utilized 5.579477
-system.ruby.network.routers3.msg_count.Control::0 2950
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers2.percent_links_utilized 4.058913
+system.ruby.network.routers2.msg_count.Control::0 1461
+system.ruby.network.routers2.msg_count.Response_Data::1 1738
+system.ruby.network.routers2.msg_count.Response_Control::1 2629
+system.ruby.network.routers2.msg_bytes.Control::0 11688
+system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
+system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
+system.ruby.network.routers3.percent_links_utilized 5.579463
+system.ruby.network.routers3.msg_count.Control::0 2952
system.ruby.network.routers3.msg_count.Request_Control::2 1041
-system.ruby.network.routers3.msg_count.Response_Data::1 3227
-system.ruby.network.routers3.msg_count.Response_Control::1 3963
-system.ruby.network.routers3.msg_count.Response_Control::2 799
+system.ruby.network.routers3.msg_count.Response_Data::1 3229
+system.ruby.network.routers3.msg_count.Response_Control::1 3966
+system.ruby.network.routers3.msg_count.Response_Control::2 800
system.ruby.network.routers3.msg_count.Writeback_Data::0 145
system.ruby.network.routers3.msg_count.Writeback_Data::1 141
-system.ruby.network.routers3.msg_count.Writeback_Control::0 291
-system.ruby.network.routers3.msg_bytes.Control::0 23600
+system.ruby.network.routers3.msg_count.Writeback_Control::0 292
+system.ruby.network.routers3.msg_bytes.Control::0 23616
system.ruby.network.routers3.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers3.msg_bytes.Response_Data::1 232344
-system.ruby.network.routers3.msg_bytes.Response_Control::1 31704
-system.ruby.network.routers3.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers3.msg_bytes.Response_Data::1 232488
+system.ruby.network.routers3.msg_bytes.Response_Control::1 31728
+system.ruby.network.routers3.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.msg_count.Control 8850
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.msg_count.Control 8856
system.ruby.network.msg_count.Request_Control 3123
-system.ruby.network.msg_count.Response_Data 9681
-system.ruby.network.msg_count.Response_Control 14286
+system.ruby.network.msg_count.Response_Data 9687
+system.ruby.network.msg_count.Response_Control 14298
system.ruby.network.msg_count.Writeback_Data 858
-system.ruby.network.msg_count.Writeback_Control 873
-system.ruby.network.msg_byte.Control 70800
+system.ruby.network.msg_count.Writeback_Control 876
+system.ruby.network.msg_byte.Control 70848
system.ruby.network.msg_byte.Request_Control 24984
-system.ruby.network.msg_byte.Response_Data 697032
-system.ruby.network.msg_byte.Response_Control 114288
+system.ruby.network.msg_byte.Response_Data 697464
+system.ruby.network.msg_byte.Response_Control 114384
system.ruby.network.msg_byte.Writeback_Data 61776
-system.ruby.network.msg_byte.Writeback_Control 6984
-system.ruby.network.routers0.throttle0.link_utilization 6.128355
+system.ruby.network.msg_byte.Writeback_Control 7008
+system.ruby.network.routers0.throttle0.link_utilization 6.128687
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers0.throttle1.link_utilization 2.492178
-system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496
+system.ruby.network.routers0.throttle1.link_utilization 2.491875
+system.ruby.network.routers0.throttle1.msg_count.Control::0 1491
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11920
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 292
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11928
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers1.throttle0.link_utilization 8.499094
-system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 799
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers1.throttle0.link_utilization 8.499198
+system.ruby.network.routers1.throttle0.msg_count.Control::0 1491
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 800
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 291
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11920
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18816
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 292
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11928
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105192
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18824
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers1.throttle1.link_utilization 8.239338
-system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers1.throttle1.link_utilization 8.239190
+system.ruby.network.routers1.throttle1.msg_count.Control::0 1461
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1611
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1613
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
-system.ruby.network.routers2.throttle0.link_utilization 2.110983
-system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904
+system.ruby.network.routers2.throttle0.link_utilization 2.110503
+system.ruby.network.routers2.throttle0.msg_count.Control::0 1461
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
-system.ruby.network.routers2.throttle1.link_utilization 6.006916
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
-system.ruby.network.routers3.throttle0.link_utilization 6.128355
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408
+system.ruby.network.routers2.throttle1.link_utilization 6.007323
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624
+system.ruby.network.routers3.throttle0.link_utilization 6.128687
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers3.throttle1.link_utilization 8.499094
-system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 799
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496
+system.ruby.network.routers3.throttle1.link_utilization 8.499198
+system.ruby.network.routers3.throttle1.msg_count.Control::0 1491
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 800
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11920
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18816
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 292
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11928
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105192
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18824
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers3.throttle2.link_utilization 2.110983
-system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336
+system.ruby.network.routers3.throttle2.link_utilization 2.110503
+system.ruby.network.routers3.throttle2.msg_count.Control::0 1461
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11680
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11688
system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9400
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9408
system.ruby.delayVCHist.vnet_0::bucket_size 1 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_0::max_bucket 9 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::samples 2725 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::mean 0.425688 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::stdev 1.795962 # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0 | 2580 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
-system.ruby.delayVCHist.vnet_0::total 2725 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::samples 2728 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::mean 0.425220 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::stdev 1.795029 # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0 | 2583 94.68% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 0 0.00% 94.68% | 145 5.32% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
+system.ruby.delayVCHist.vnet_0::total 2728 # delay histogram for vnet_0
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 5879 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.073142 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.375443 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 5664 96.34% 96.34% | 0 0.00% 96.34% | 215 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 5879 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.072752 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.374480 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 5669 96.36% 96.36% | 0 0.00% 96.36% | 214 3.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::samples 1041 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 1041 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
-system.ruby.LD.latency_hist_seqr::samples 1183
-system.ruby.LD.latency_hist_seqr::mean 33.972105
-system.ruby.LD.latency_hist_seqr::gmean 7.701642
-system.ruby.LD.latency_hist_seqr::stdev 40.478944
-system.ruby.LD.latency_hist_seqr | 802 67.79% 67.79% | 375 31.70% 99.49% | 0 0.00% 99.49% | 0 0.00% 99.49% | 2 0.17% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1183
+system.ruby.LD.latency_hist_seqr::samples 1185
+system.ruby.LD.latency_hist_seqr::mean 33.565401
+system.ruby.LD.latency_hist_seqr::gmean 7.686795
+system.ruby.LD.latency_hist_seqr::stdev 38.515936
+system.ruby.LD.latency_hist_seqr | 803 67.76% 67.76% | 378 31.90% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 600
+system.ruby.LD.hit_latency_hist_seqr::samples 601
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 600 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 600
+system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 601 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 601
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
-system.ruby.LD.miss_latency_hist_seqr::samples 583
-system.ruby.LD.miss_latency_hist_seqr::mean 67.905660
-system.ruby.LD.miss_latency_hist_seqr::gmean 62.953372
-system.ruby.LD.miss_latency_hist_seqr::stdev 32.457951
-system.ruby.LD.miss_latency_hist_seqr | 202 34.65% 34.65% | 375 64.32% 98.97% | 0 0.00% 98.97% | 0 0.00% 98.97% | 2 0.34% 99.31% | 4 0.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 583
+system.ruby.LD.miss_latency_hist_seqr::samples 584
+system.ruby.LD.miss_latency_hist_seqr::mean 67.078767
+system.ruby.LD.miss_latency_hist_seqr::gmean 62.700967
+system.ruby.LD.miss_latency_hist_seqr::stdev 28.185747
+system.ruby.LD.miss_latency_hist_seqr | 202 34.59% 34.59% | 378 64.73% 99.32% | 0 0.00% 99.32% | 0 0.00% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 584
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 15.273988
-system.ruby.ST.latency_hist_seqr::gmean 2.701326
-system.ruby.ST.latency_hist_seqr::stdev 28.276128
-system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 91 10.52% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 15.551445
+system.ruby.ST.latency_hist_seqr::gmean 2.706248
+system.ruby.ST.latency_hist_seqr::stdev 29.831548
+system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 90 10.40% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 216
-system.ruby.ST.miss_latency_hist_seqr::mean 58.162037
-system.ruby.ST.miss_latency_hist_seqr::gmean 53.494090
-system.ruby.ST.miss_latency_hist_seqr::stdev 27.387260
-system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 91 42.13% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 59.273148
+system.ruby.ST.miss_latency_hist_seqr::gmean 53.885554
+system.ruby.ST.miss_latency_hist_seqr::stdev 31.884011
+system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 90 41.67% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 1 0.46% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 216
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 6400
-system.ruby.IFETCH.latency_hist_seqr::mean 9.314219
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.595263
-system.ruby.IFETCH.latency_hist_seqr::stdev 25.608064
-system.ruby.IFETCH.latency_hist_seqr | 5714 89.28% 89.28% | 674 10.53% 99.81% | 4 0.06% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 6400
+system.ruby.IFETCH.latency_hist_seqr::samples 6413
+system.ruby.IFETCH.latency_hist_seqr::mean 9.331826
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.594079
+system.ruby.IFETCH.latency_hist_seqr::stdev 25.833878
+system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 673 10.49% 99.80% | 4 0.06% 99.86% | 1 0.02% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5709
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5722
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5709 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5709
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5722 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5722
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 691
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.005789
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.617268
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.004761
-system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 4 0.58% 98.84% | 1 0.14% 98.99% | 3 0.43% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.325615
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.760449
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.311514
+system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 673 97.40% 98.12% | 4 0.58% 98.70% | 1 0.14% 98.84% | 4 0.58% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 691
-system.ruby.Directory_Controller.Fetch 1460 0.00% 0.00%
+system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00%
system.ruby.Directory_Controller.Data 277 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1460 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1461 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 277 0.00% 0.00%
-system.ruby.Directory_Controller.CleanReplacement 1175 0.00% 0.00%
-system.ruby.Directory_Controller.I.Fetch 1460 0.00% 0.00%
+system.ruby.Directory_Controller.CleanReplacement 1176 0.00% 0.00%
+system.ruby.Directory_Controller.I.Fetch 1461 0.00% 0.00%
system.ruby.Directory_Controller.M.Data 277 0.00% 0.00%
-system.ruby.Directory_Controller.M.CleanReplacement 1175 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 1460 0.00% 0.00%
+system.ruby.Directory_Controller.M.CleanReplacement 1176 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 1461 0.00% 0.00%
system.ruby.Directory_Controller.MI.Memory_Ack 277 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
system.ruby.L1Cache_Controller.Inv 1041 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 1354 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_Exclusive 583 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 1355 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_Exclusive 584 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_all_Acks 907 0.00% 0.00%
-system.ruby.L1Cache_Controller.WB_Ack 436 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00%
+system.ruby.L1Cache_Controller.WB_Ack 437 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Inv 356 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 45 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 25 0.00% 0.00%
system.ruby.L1Cache_Controller.I.L1_Replacement 556 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 5709 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Ifetch 5722 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Inv 325 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 362 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.Load 452 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.Load 453 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Store 71 0.00% 0.00%
system.ruby.L1Cache_Controller.E.Inv 219 0.00% 0.00%
-system.ruby.L1Cache_Controller.E.L1_Replacement 291 0.00% 0.00%
+system.ruby.L1Cache_Controller.E.L1_Replacement 292 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 148 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 578 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Inv 141 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 145 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_Exclusive 583 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_Exclusive 584 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_all_Acks 691 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data_all_Acks 216 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_I.WB_Ack 436 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_I.WB_Ack 437 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GET_INSTR 691 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 583 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 584 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 216 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTX 436 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 437 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 142 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement_clean 1310 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Data 1460 0.00% 0.00%
-system.ruby.L2Cache_Controller.Mem_Ack 1452 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement_clean 1311 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Data 1461 0.00% 0.00%
+system.ruby.L2Cache_Controller.Mem_Ack 1453 0.00% 0.00%
system.ruby.L2Cache_Controller.WB_Data 141 0.00% 0.00%
system.ruby.L2Cache_Controller.Ack_all 900 0.00% 0.00%
-system.ruby.L2Cache_Controller.Exclusive_Unblock 799 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 800 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 686 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 570 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 571 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 204 0.00% 0.00%
system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 5 0.00% 0.00%
system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 681 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 13 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 12 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 134 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement_clean 277 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT.L1_PUTX 436 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement_clean 278 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT.L1_PUTX 437 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L2_Replacement 8 0.00% 0.00%
system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 352 0.00% 0.00%
-system.ruby.L2Cache_Controller.M_I.Mem_Ack 1452 0.00% 0.00%
+system.ruby.L2Cache_Controller.M_I.Mem_Ack 1453 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.WB_Data 6 0.00% 0.00%
system.ruby.L2Cache_Controller.MT_I.Ack_all 2 0.00% 0.00%
system.ruby.L2Cache_Controller.MCT_I.WB_Data 135 0.00% 0.00%
system.ruby.L2Cache_Controller.MCT_I.Ack_all 217 0.00% 0.00%
system.ruby.L2Cache_Controller.I_I.Ack_all 681 0.00% 0.00%
-system.ruby.L2Cache_Controller.ISS.Mem_Data 570 0.00% 0.00%
+system.ruby.L2Cache_Controller.ISS.Mem_Data 571 0.00% 0.00%
system.ruby.L2Cache_Controller.IS.Mem_Data 686 0.00% 0.00%
system.ruby.L2Cache_Controller.IM.Mem_Data 204 0.00% 0.00%
-system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 799 0.00% 0.00%
+system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 800 0.00% 0.00%
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:06:59
-gem5 started Jan 21 2016 14:07:35
-gem5 executing on zizzer, pid 50076
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Mar 14 2016 22:01:23
+gem5 started Mar 14 2016 22:02:29
+gem5 executing on phenom, pid 29128
+command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 108694 because target called exit()
+Exiting @ tick 108878 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000109 # Number of seconds simulated
-sim_ticks 108694 # Number of ticks simulated
-final_tick 108694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 108878 # Number of ticks simulated
+final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 71872 # Simulator instruction rate (inst/s)
-host_op_rate 71865 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1222276 # Simulator tick rate (ticks/s)
-host_mem_usage 417856 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 17471 # Simulator instruction rate (inst/s)
+host_op_rate 17470 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 297052 # Simulator tick rate (ticks/s)
+host_mem_usage 393472 # Number of bytes of host memory used
+host_seconds 0.37 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75648 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 75648 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 12416 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1182 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1182 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 695972179 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 695972179 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 114228936 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 114228936 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 810201115 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 810201115 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1182 # Number of read requests accepted
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 695383824 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 695383824 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 114035893 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 114035893 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 809419717 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 809419717 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1183 # Number of read requests accepted
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
-system.mem_ctrls.readBursts 1182 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 64448 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 75648 # Total read bytes from the system interface side
+system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 82 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 66 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 108642 # Total gap between requests
+system.mem_ctrls.totGap 108826 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1182 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1183 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1007 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 4 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 7 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 202 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 335.524752 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 204.886741 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 324.305016 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 65 32.18% 32.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 47 23.27% 55.45% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 21 10.40% 65.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 14 6.93% 72.77% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 12 5.94% 78.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 11 5.45% 84.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 6 2.97% 87.13% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 5 2.48% 89.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 21 10.40% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 202 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 334.817734 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 202.715946 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 328.878595 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 47 23.15% 55.17% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 25 12.32% 67.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 72.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 11 5.42% 78.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 5 2.46% 85.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 8 3.94% 89.66% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 141.200000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 107.481731 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 78.180560 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 138.600000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 101.703151 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 85.219129 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::168-175 1 20.00% 60.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 6988 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26121 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5035 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 7036 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 26207 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 6.97 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 592.93 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 50.05 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 695.97 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 114.23 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 25.97 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 593.10 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 50.55 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 695.38 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 114.04 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 5.02 # Data bus utilization in percentage
+system.mem_ctrls.busUtil 5.03 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 21.56 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 807 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 77 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 80.14 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 68.75 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 78.95 # Average gap between requests
-system.mem_ctrls.pageHitRate 79.00 # Row buffer hit rate, read and write combined
+system.mem_ctrls.avgWrQLen 21.05 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 80 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 79.88 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 70.80 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 79.03 # Average gap between requests
+system.mem_ctrls.pageHitRate 78.97 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 238464 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 62170812 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 6351000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 81199236 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 800.165908 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 15769 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 61961508 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 6534600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 81183900 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 800.014782 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 16245 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 87863 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 87571 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 67286448 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1863600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 84579504 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 833.476261 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 2630 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 67902048 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 1323600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 84655104 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 834.221250 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 1730 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 95482 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 108694 # number of cpu cycles simulated
+system.cpu.numCycles 108878 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 108694 # Number of busy cycles
+system.cpu.num_busy_cycles 108878 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 8449
+system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 8449
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 8448
-system.ruby.latency_hist_seqr::mean 11.866241
-system.ruby.latency_hist_seqr::gmean 1.974485
-system.ruby.latency_hist_seqr::stdev 27.814086
-system.ruby.latency_hist_seqr | 7440 88.07% 88.07% | 991 11.73% 99.80% | 4 0.05% 99.85% | 1 0.01% 99.86% | 9 0.11% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 8448
+system.ruby.latency_hist_seqr::samples 8463
+system.ruby.latency_hist_seqr::mean 11.865178
+system.ruby.latency_hist_seqr::gmean 1.973283
+system.ruby.latency_hist_seqr::stdev 27.863065
+system.ruby.latency_hist_seqr | 7453 88.07% 88.07% | 995 11.76% 99.82% | 2 0.02% 99.85% | 0 0.00% 99.85% | 9 0.11% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 7027
+system.ruby.hit_latency_hist_seqr::samples 7041
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7027 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 7027
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 7041 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 7041
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1421
-system.ruby.miss_latency_hist_seqr::mean 65.600985
-system.ruby.miss_latency_hist_seqr::gmean 57.082853
-system.ruby.miss_latency_hist_seqr::stdev 33.588801
-system.ruby.miss_latency_hist_seqr | 413 29.06% 29.06% | 991 69.74% 98.80% | 4 0.28% 99.09% | 1 0.07% 99.16% | 9 0.63% 99.79% | 3 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1421
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 1273 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 775 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
+system.ruby.miss_latency_hist_seqr::samples 1422
+system.ruby.miss_latency_hist_seqr::mean 65.663854
+system.ruby.miss_latency_hist_seqr::gmean 57.123275
+system.ruby.miss_latency_hist_seqr::stdev 33.791401
+system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1422
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 1182 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 1421 # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 6.936215
-system.ruby.network.routers0.msg_count.Request_Control::0 1421
-system.ruby.network.routers0.msg_count.Response_Data::2 1182
+system.ruby.network.routers0.percent_links_utilized 6.929545
+system.ruby.network.routers0.msg_count.Request_Control::0 1422
+system.ruby.network.routers0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
-system.ruby.network.routers0.msg_count.Writeback_Data::2 1308
-system.ruby.network.routers0.msg_count.Writeback_Control::0 2708
-system.ruby.network.routers0.msg_count.Unblock_Control::2 1467
-system.ruby.network.routers0.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers0.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers0.msg_count.Writeback_Data::2 1309
+system.ruby.network.routers0.msg_count.Writeback_Control::0 2710
+system.ruby.network.routers0.msg_count.Unblock_Control::2 1468
+system.ruby.network.routers0.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
-system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94176
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21664
-system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11736
-system.ruby.network.routers1.percent_links_utilized 10.417548
-system.ruby.network.routers1.msg_count.Request_Control::0 1421
-system.ruby.network.routers1.msg_count.Request_Control::1 1182
-system.ruby.network.routers1.msg_count.Response_Data::2 2364
+system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
+system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers1.percent_links_utilized 10.407520
+system.ruby.network.routers1.msg_count.Request_Control::0 1422
+system.ruby.network.routers1.msg_count.Request_Control::1 1183
+system.ruby.network.routers1.msg_count.Response_Data::2 2366
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 239
-system.ruby.network.routers1.msg_count.Writeback_Data::2 1502
-system.ruby.network.routers1.msg_count.Writeback_Control::0 2708
+system.ruby.network.routers1.msg_count.Writeback_Data::2 1503
+system.ruby.network.routers1.msg_count.Writeback_Control::0 2710
system.ruby.network.routers1.msg_count.Writeback_Control::1 388
-system.ruby.network.routers1.msg_count.Unblock_Control::2 2649
-system.ruby.network.routers1.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers1.msg_bytes.Request_Control::1 9456
-system.ruby.network.routers1.msg_bytes.Response_Data::2 170208
+system.ruby.network.routers1.msg_count.Unblock_Control::2 2651
+system.ruby.network.routers1.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers1.msg_bytes.Request_Control::1 9464
+system.ruby.network.routers1.msg_bytes.Response_Data::2 170352
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 17208
-system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108144
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21664
+system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
-system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21192
-system.ruby.network.routers2.percent_links_utilized 3.481333
-system.ruby.network.routers2.msg_count.Request_Control::1 1182
-system.ruby.network.routers2.msg_count.Response_Data::2 1182
+system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.routers2.percent_links_utilized 3.477975
+system.ruby.network.routers2.msg_count.Request_Control::1 1183
+system.ruby.network.routers2.msg_count.Response_Data::2 1183
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
system.ruby.network.routers2.msg_count.Writeback_Control::1 388
-system.ruby.network.routers2.msg_count.Unblock_Control::2 1182
-system.ruby.network.routers2.msg_bytes.Request_Control::1 9456
-system.ruby.network.routers2.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers2.msg_count.Unblock_Control::2 1183
+system.ruby.network.routers2.msg_bytes.Request_Control::1 9464
+system.ruby.network.routers2.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
-system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9456
-system.ruby.network.routers3.percent_links_utilized 6.945032
-system.ruby.network.routers3.msg_count.Request_Control::0 1421
-system.ruby.network.routers3.msg_count.Request_Control::1 1182
-system.ruby.network.routers3.msg_count.Response_Data::2 2364
+system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
+system.ruby.network.routers3.percent_links_utilized 6.938347
+system.ruby.network.routers3.msg_count.Request_Control::0 1422
+system.ruby.network.routers3.msg_count.Request_Control::1 1183
+system.ruby.network.routers3.msg_count.Response_Data::2 2366
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 239
-system.ruby.network.routers3.msg_count.Writeback_Data::2 1502
-system.ruby.network.routers3.msg_count.Writeback_Control::0 2708
+system.ruby.network.routers3.msg_count.Writeback_Data::2 1503
+system.ruby.network.routers3.msg_count.Writeback_Control::0 2710
system.ruby.network.routers3.msg_count.Writeback_Control::1 388
-system.ruby.network.routers3.msg_count.Unblock_Control::2 2649
-system.ruby.network.routers3.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers3.msg_bytes.Request_Control::1 9456
-system.ruby.network.routers3.msg_bytes.Response_Data::2 170208
+system.ruby.network.routers3.msg_count.Unblock_Control::2 2651
+system.ruby.network.routers3.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers3.msg_bytes.Request_Control::1 9464
+system.ruby.network.routers3.msg_bytes.Response_Data::2 170352
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 17208
-system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108144
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21664
+system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
-system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21192
-system.ruby.network.msg_count.Request_Control 7809
-system.ruby.network.msg_count.Response_Data 7092
+system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
+system.ruby.network.msg_count.Request_Control 7815
+system.ruby.network.msg_count.Response_Data 7098
system.ruby.network.msg_count.ResponseL2hit_Data 717
-system.ruby.network.msg_count.Writeback_Data 4506
-system.ruby.network.msg_count.Writeback_Control 9288
-system.ruby.network.msg_count.Unblock_Control 7947
-system.ruby.network.msg_byte.Request_Control 62472
-system.ruby.network.msg_byte.Response_Data 510624
+system.ruby.network.msg_count.Writeback_Data 4509
+system.ruby.network.msg_count.Writeback_Control 9294
+system.ruby.network.msg_count.Unblock_Control 7953
+system.ruby.network.msg_byte.Request_Control 62520
+system.ruby.network.msg_byte.Response_Data 511056
system.ruby.network.msg_byte.ResponseL2hit_Data 51624
-system.ruby.network.msg_byte.Writeback_Data 324432
-system.ruby.network.msg_byte.Writeback_Control 74304
-system.ruby.network.msg_byte.Unblock_Control 63576
-system.ruby.network.routers0.throttle0.link_utilization 6.505879
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1182
+system.ruby.network.msg_byte.Writeback_Data 324648
+system.ruby.network.msg_byte.Writeback_Control 74352
+system.ruby.network.msg_byte.Unblock_Control 63624
+system.ruby.network.routers0.throttle0.link_utilization 6.499476
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1354
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10832
-system.ruby.network.routers0.throttle1.link_utilization 7.366552
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1421
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1308
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1354
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1467
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94176
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10832
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11736
-system.ruby.network.routers1.throttle0.link_utilization 12.349348
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1421
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1182
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1308
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1354
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840
+system.ruby.network.routers0.throttle1.link_utilization 7.359614
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 1468
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers1.throttle0.link_utilization 12.338122
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 194
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1467
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85104
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94176
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10832
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 1468
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 85176
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11736
-system.ruby.network.routers1.throttle1.link_utilization 8.485749
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1182
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1182
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers1.throttle1.link_utilization 8.476919
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 194
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1354
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 1355
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 194
-system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1182
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9456
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 1183
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 9464
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10832
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9456
-system.ruby.network.routers2.throttle0.link_utilization 1.979870
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1182
+system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464
+system.ruby.network.routers2.throttle0.link_utilization 1.977443
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
-system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1182
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9456
+system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 1183
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9456
-system.ruby.network.routers2.throttle1.link_utilization 4.982796
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1182
+system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464
+system.ruby.network.routers2.throttle1.link_utilization 4.978508
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers3.throttle0.link_utilization 6.505879
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1182
+system.ruby.network.routers3.throttle0.link_utilization 6.499476
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1354
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85104
+system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10832
-system.ruby.network.routers3.throttle1.link_utilization 12.349348
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1421
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1182
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1308
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1354
+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840
+system.ruby.network.routers3.throttle1.link_utilization 12.338122
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 1355
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 194
-system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1467
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11368
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85104
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94176
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10832
+system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 1468
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 11376
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 85176
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11736
-system.ruby.network.routers3.throttle2.link_utilization 1.979870
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1182
+system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744
+system.ruby.network.routers3.throttle2.link_utilization 1.977443
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
-system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1182
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9456
+system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 1183
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9456
-system.ruby.LD.latency_hist_seqr::bucket_size 64
-system.ruby.LD.latency_hist_seqr::max_bucket 639
-system.ruby.LD.latency_hist_seqr::samples 1183
-system.ruby.LD.latency_hist_seqr::mean 27.265427
-system.ruby.LD.latency_hist_seqr::gmean 5.733715
-system.ruby.LD.latency_hist_seqr::stdev 35.817674
-system.ruby.LD.latency_hist_seqr | 862 72.87% 72.87% | 317 26.80% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1183
+system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464
+system.ruby.LD.latency_hist_seqr::bucket_size 32
+system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::samples 1185
+system.ruby.LD.latency_hist_seqr::mean 27.428692
+system.ruby.LD.latency_hist_seqr::gmean 5.747000
+system.ruby.LD.latency_hist_seqr::stdev 36.091782
+system.ruby.LD.latency_hist_seqr | 775 65.40% 65.40% | 87 7.34% 72.74% | 279 23.54% 96.29% | 40 3.38% 99.66% | 1 0.08% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 658
+system.ruby.LD.hit_latency_hist_seqr::samples 659
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 658
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
-system.ruby.LD.miss_latency_hist_seqr::samples 525
-system.ruby.LD.miss_latency_hist_seqr::mean 60.184762
-system.ruby.LD.miss_latency_hist_seqr::gmean 51.169278
-system.ruby.LD.miss_latency_hist_seqr::stdev 30.689440
-system.ruby.LD.miss_latency_hist_seqr | 204 38.86% 38.86% | 317 60.38% 99.24% | 2 0.38% 99.62% | 1 0.19% 99.81% | 0 0.00% 99.81% | 1 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 525
+system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 659
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::samples 526
+system.ruby.LD.miss_latency_hist_seqr::mean 60.539924
+system.ruby.LD.miss_latency_hist_seqr::gmean 51.393520
+system.ruby.LD.miss_latency_hist_seqr::stdev 31.024435
+system.ruby.LD.miss_latency_hist_seqr | 116 22.05% 22.05% | 87 16.54% 38.59% | 279 53.04% 91.63% | 40 7.60% 99.24% | 1 0.19% 99.43% | 1 0.19% 99.62% | 0 0.00% 99.62% | 0 0.00% 99.62% | 1 0.19% 99.81% | 1 0.19% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 526
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 17.593064
-system.ruby.ST.latency_hist_seqr::gmean 3.080574
-system.ruby.ST.latency_hist_seqr::stdev 34.156278
-system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 108 12.49% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 2 0.23% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 17.057803
+system.ruby.ST.latency_hist_seqr::gmean 3.071194
+system.ruby.ST.latency_hist_seqr::stdev 31.094076
+system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 110 12.72% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 250
-system.ruby.ST.miss_latency_hist_seqr::mean 58.412000
-system.ruby.ST.miss_latency_hist_seqr::gmean 49.053018
-system.ruby.ST.miss_latency_hist_seqr::stdev 41.173185
-system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 108 43.20% 98.40% | 0 0.00% 98.40% | 0 0.00% 98.40% | 2 0.80% 99.20% | 2 0.80% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 56.560000
+system.ruby.ST.miss_latency_hist_seqr::gmean 48.538116
+system.ruby.ST.miss_latency_hist_seqr::stdev 33.930333
+system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 110 44.00% 99.20% | 0 0.00% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 250
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
-system.ruby.IFETCH.latency_hist_seqr::samples 6400
-system.ruby.IFETCH.latency_hist_seqr::mean 8.245781
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.526741
-system.ruby.IFETCH.latency_hist_seqr::stdev 23.776931
-system.ruby.IFETCH.latency_hist_seqr | 5825 91.02% 91.02% | 0 0.00% 91.02% | 525 8.20% 99.22% | 41 0.64% 99.86% | 2 0.03% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 2 0.03% 99.92% | 5 0.08% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 6400
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.latency_hist_seqr::samples 6413
+system.ruby.IFETCH.latency_hist_seqr::mean 8.288944
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.525778
+system.ruby.IFETCH.latency_hist_seqr::stdev 24.342417
+system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 566 8.83% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 6 0.09% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5754
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5767
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5754
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5767
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 646
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 72.784830
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.158480
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.122591
-system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 0 0.00% 10.99% | 525 81.27% 92.26% | 41 6.35% 98.61% | 2 0.31% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 0 0.00% 98.92% | 2 0.31% 99.23% | 5 0.77% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.359133
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.307554
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.276818
+system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 566 87.62% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 6 0.93% 99.54% | 3 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 646
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 984 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 985 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 194 0.00% 0.00%
system.ruby.Directory_Controller.Unblock 466 0.00% 0.00%
-system.ruby.Directory_Controller.Last_Unblock 517 0.00% 0.00%
+system.ruby.Directory_Controller.Last_Unblock 518 0.00% 0.00%
system.ruby.Directory_Controller.Exclusive_Unblock 198 0.00% 0.00%
system.ruby.Directory_Controller.Dirty_Writeback 194 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1182 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1183 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 194 0.00% 0.00%
system.ruby.Directory_Controller.I.GETX 111 0.00% 0.00%
system.ruby.Directory_Controller.I.GETS 466 0.00% 0.00%
system.ruby.Directory_Controller.I.Memory_Ack 194 0.00% 0.00%
system.ruby.Directory_Controller.S.GETX 87 0.00% 0.00%
-system.ruby.Directory_Controller.S.GETS 518 0.00% 0.00%
+system.ruby.Directory_Controller.S.GETS 519 0.00% 0.00%
system.ruby.Directory_Controller.M.PUTX 194 0.00% 0.00%
system.ruby.Directory_Controller.IS.Unblock 466 0.00% 0.00%
system.ruby.Directory_Controller.IS.Memory_Data 466 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Last_Unblock 517 0.00% 0.00%
-system.ruby.Directory_Controller.SS.Memory_Data 518 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Last_Unblock 518 0.00% 0.00%
+system.ruby.Directory_Controller.SS.Memory_Data 519 0.00% 0.00%
system.ruby.Directory_Controller.MM.Exclusive_Unblock 198 0.00% 0.00%
system.ruby.Directory_Controller.MM.Memory_Data 198 0.00% 0.00%
system.ruby.Directory_Controller.MI.Dirty_Writeback 194 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 1125 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 1369 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1126 0.00% 0.00%
system.ruby.L1Cache_Controller.Exclusive_Data 296 0.00% 0.00%
system.ruby.L1Cache_Controller.Writeback_Ack 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack_Data 1308 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 1309 0.00% 0.00%
system.ruby.L1Cache_Controller.All_acks 250 0.00% 0.00%
system.ruby.L1Cache_Controller.Use_Timeout 296 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 525 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 191 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Load 299 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.Ifetch 5754 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Load 300 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Ifetch 5767 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 59 0.00% 0.00%
-system.ruby.L1Cache_Controller.S.L1_Replacement 1059 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 1060 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 79 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 18 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 27 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Exclusive_Data 191 0.00% 0.00%
system.ruby.L1Cache_Controller.SM.Exclusive_Data 59 0.00% 0.00%
system.ruby.L1Cache_Controller.OM.All_acks 250 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 1125 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1126 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Exclusive_Data 46 0.00% 0.00%
system.ruby.L1Cache_Controller.SI.Writeback_Ack 46 0.00% 0.00%
-system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1013 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 1014 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 1171 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1172 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 250 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_PUTX 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_PUTS_only 1059 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 1060 0.00% 0.00%
system.ruby.L2Cache_Controller.All_Acks 198 0.00% 0.00%
-system.ruby.L2Cache_Controller.Data 1182 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 1183 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 295 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Ack 194 0.00% 0.00%
-system.ruby.L2Cache_Controller.Unblock 1171 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 1172 0.00% 0.00%
system.ruby.L2Cache_Controller.Exclusive_Unblock 296 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 1193 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 984 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 1194 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 985 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 132 0.00% 0.00%
system.ruby.L2Cache_Controller.ILS.L1_GETX 57 0.00% 0.00%
-system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.ILX.L1_PUTX 295 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETS 141 0.00% 0.00%
system.ruby.L2Cache_Controller.S.L1_GETX 7 0.00% 0.00%
-system.ruby.L2Cache_Controller.S.L2_Replacement 906 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 907 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L1_GETX 2 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 46 0.00% 0.00%
system.ruby.L2Cache_Controller.SLS.L2_Replacement 93 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 46 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 52 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 194 0.00% 0.00%
-system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1013 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 1014 0.00% 0.00%
system.ruby.L2Cache_Controller.SW.Unblock 46 0.00% 0.00%
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 295 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Data 984 0.00% 0.00%
-system.ruby.L2Cache_Controller.IGS.Unblock 984 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 985 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 985 0.00% 0.00%
system.ruby.L2Cache_Controller.IGM.Data 139 0.00% 0.00%
system.ruby.L2Cache_Controller.IGMLS.Data 59 0.00% 0.00%
system.ruby.L2Cache_Controller.IGMO.All_Acks 198 0.00% 0.00%
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:12:23
-gem5 started Jan 21 2016 14:12:59
-gem5 executing on zizzer, pid 55399
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Mar 14 2016 22:02:54
+gem5 started Mar 14 2016 22:04:07
+gem5 executing on phenom, pid 29513
+command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 108253 # Number of ticks simulated
final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 33873 # Simulator instruction rate (inst/s)
-host_op_rate 33870 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 573730 # Simulator tick rate (ticks/s)
-host_mem_usage 391892 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 39556 # Simulator instruction rate (inst/s)
+host_op_rate 39552 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 668635 # Simulator tick rate (ticks/s)
+host_mem_usage 388512 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75392 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 75392 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 14656 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1178 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1178 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 696442593 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 696442593 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 697033800 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 697033800 # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::ruby.dir_cntrl0 135386548 # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total 135386548 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 831829141 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 831829141 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1178 # Number of read requests accepted
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 832420349 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 832420349 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1179 # Number of read requests accepted
system.mem_ctrls.writeReqs 229 # Number of write requests accepted
-system.mem_ctrls.readBursts 1178 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 65024 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadDRAM 65088 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 10368 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 75392 # Total read bytes from the system interface side
+system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 44 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1178 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1179 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1016 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1017 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 338.600985 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 206.377683 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 325.274619 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 338.916256 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 206.604664 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 325.225174 # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255 46 22.66% 54.68% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383 21 10.34% 65.02% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 156.333333 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 116.994790 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 90.254455 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 156.500000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 117.084065 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 90.391924 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 7316 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26620 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5080 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 7.20 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 7213 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 26536 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5085 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 26.20 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 600.67 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 601.26 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW 56.76 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 696.44 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 697.03 # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys 135.39 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil 5.14 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.69 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilRead 4.70 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 23.01 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 815 # Number of row buffer hits during reads
+system.mem_ctrls.readRowHits 816 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 88 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 80.22 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 80.24 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 75.21 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 76.88 # Average gap between requests
-system.mem_ctrls.pageHitRate 79.70 # Row buffer hit rate, read and write combined
+system.mem_ctrls.avgGap 76.83 # Average gap between requests
+system.mem_ctrls.pageHitRate 79.72 # Row buffer hit rate, read and write combined
system.mem_ctrls_0.actEnergy 521640 # Energy for activate commands per rank (pJ)
system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 57834936 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 10154400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 80827416 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 796.501862 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 21697 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 57840408 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 10149600 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 80828088 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 796.508485 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 21689 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 81524 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 81532 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ)
system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6751680 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 684288 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 67458132 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1721400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 84696780 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 834.516809 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 2421 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 67474548 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 1707000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 84711276 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 834.659638 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 2397 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 95705 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.numCycles 108253 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 108253 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 8449
+system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 8449
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 8448
-system.ruby.latency_hist_seqr::mean 11.814039
-system.ruby.latency_hist_seqr::gmean 1.958059
-system.ruby.latency_hist_seqr::stdev 27.675120
-system.ruby.latency_hist_seqr | 7432 87.97% 87.97% | 995 11.78% 99.75% | 8 0.09% 99.85% | 3 0.04% 99.88% | 6 0.07% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 8448
+system.ruby.latency_hist_seqr::samples 8463
+system.ruby.latency_hist_seqr::mean 11.791327
+system.ruby.latency_hist_seqr::gmean 1.956562
+system.ruby.latency_hist_seqr::stdev 27.556143
+system.ruby.latency_hist_seqr | 7446 87.98% 87.98% | 996 11.77% 99.75% | 8 0.09% 99.85% | 4 0.05% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 8
system.ruby.hit_latency_hist_seqr::max_bucket 79
-system.ruby.hit_latency_hist_seqr::samples 7270
-system.ruby.hit_latency_hist_seqr::mean 1.637552
-system.ruby.hit_latency_hist_seqr::gmean 1.092853
-system.ruby.hit_latency_hist_seqr::stdev 3.762080
-system.ruby.hit_latency_hist_seqr | 7066 97.19% 97.19% | 0 0.00% 97.19% | 19 0.26% 97.46% | 184 2.53% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 7270
+system.ruby.hit_latency_hist_seqr::samples 7284
+system.ruby.hit_latency_hist_seqr::mean 1.635502
+system.ruby.hit_latency_hist_seqr::gmean 1.092626
+system.ruby.hit_latency_hist_seqr::stdev 3.754063
+system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 7284
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1178
-system.ruby.miss_latency_hist_seqr::mean 74.617997
-system.ruby.miss_latency_hist_seqr::gmean 71.587772
-system.ruby.miss_latency_hist_seqr::stdev 28.670099
-system.ruby.miss_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1178
-system.ruby.Directory.incomplete_times_seqr 1177
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 1312 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 736 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
+system.ruby.miss_latency_hist_seqr::samples 1179
+system.ruby.miss_latency_hist_seqr::mean 74.535199
+system.ruby.miss_latency_hist_seqr::gmean 71.564149
+system.ruby.miss_latency_hist_seqr::stdev 28.099799
+system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1179
+system.ruby.Directory.incomplete_times_seqr 1178
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 1195 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 1382 # Number of cache demand accesses
+system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 6.018078
-system.ruby.network.routers0.msg_count.Request_Control::1 1382
-system.ruby.network.routers0.msg_count.Response_Data::4 1178
+system.ruby.network.routers0.percent_links_utilized 6.022466
+system.ruby.network.routers0.msg_count.Request_Control::1 1383
+system.ruby.network.routers0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.msg_count.Response_Control::4 1
-system.ruby.network.routers0.msg_count.Writeback_Data::4 1354
+system.ruby.network.routers0.msg_count.Writeback_Data::4 1355
system.ruby.network.routers0.msg_count.Persistent_Control::3 52
-system.ruby.network.routers0.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers0.msg_bytes.Response_Data::4 84816
+system.ruby.network.routers0.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97488
+system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416
-system.ruby.network.routers1.percent_links_utilized 4.538904
-system.ruby.network.routers1.msg_count.Request_Control::1 1382
-system.ruby.network.routers1.msg_count.Request_Control::2 1195
+system.ruby.network.routers1.percent_links_utilized 4.541676
+system.ruby.network.routers1.msg_count.Request_Control::1 1383
+system.ruby.network.routers1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.msg_count.Response_Control::4 1
-system.ruby.network.routers1.msg_count.Writeback_Data::4 1583
-system.ruby.network.routers1.msg_count.Writeback_Control::4 967
+system.ruby.network.routers1.msg_count.Writeback_Data::4 1584
+system.ruby.network.routers1.msg_count.Writeback_Control::4 968
system.ruby.network.routers1.msg_count.Persistent_Control::3 26
-system.ruby.network.routers1.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers1.msg_bytes.Request_Control::2 9560
+system.ruby.network.routers1.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers1.msg_bytes.Request_Control::2 9568
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
-system.ruby.network.routers1.msg_bytes.Writeback_Data::4 113976
-system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7736
+system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
+system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers2.percent_links_utilized 3.429697
-system.ruby.network.routers2.msg_count.Request_Control::2 1195
-system.ruby.network.routers2.msg_count.Response_Data::4 1178
+system.ruby.network.routers2.percent_links_utilized 3.432237
+system.ruby.network.routers2.msg_count.Request_Control::2 1196
+system.ruby.network.routers2.msg_count.Response_Data::4 1179
system.ruby.network.routers2.msg_count.Writeback_Data::4 229
-system.ruby.network.routers2.msg_count.Writeback_Control::4 967
+system.ruby.network.routers2.msg_count.Writeback_Control::4 968
system.ruby.network.routers2.msg_count.Persistent_Control::3 26
-system.ruby.network.routers2.msg_bytes.Request_Control::2 9560
-system.ruby.network.routers2.msg_bytes.Response_Data::4 84816
+system.ruby.network.routers2.msg_bytes.Request_Control::2 9568
+system.ruby.network.routers2.msg_bytes.Response_Data::4 84888
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
-system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7736
+system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers3.percent_links_utilized 4.662226
-system.ruby.network.routers3.msg_count.Request_Control::1 1382
-system.ruby.network.routers3.msg_count.Request_Control::2 1195
-system.ruby.network.routers3.msg_count.Response_Data::4 1178
+system.ruby.network.routers3.percent_links_utilized 4.665460
+system.ruby.network.routers3.msg_count.Request_Control::1 1383
+system.ruby.network.routers3.msg_count.Request_Control::2 1196
+system.ruby.network.routers3.msg_count.Response_Data::4 1179
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.msg_count.Response_Control::4 1
-system.ruby.network.routers3.msg_count.Writeback_Data::4 1583
-system.ruby.network.routers3.msg_count.Writeback_Control::4 967
+system.ruby.network.routers3.msg_count.Writeback_Data::4 1584
+system.ruby.network.routers3.msg_count.Writeback_Control::4 968
system.ruby.network.routers3.msg_count.Persistent_Control::3 52
-system.ruby.network.routers3.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers3.msg_bytes.Request_Control::2 9560
-system.ruby.network.routers3.msg_bytes.Response_Data::4 84816
+system.ruby.network.routers3.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers3.msg_bytes.Request_Control::2 9568
+system.ruby.network.routers3.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.msg_bytes.Writeback_Data::4 113976
-system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7736
+system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
+system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416
-system.ruby.network.msg_count.Request_Control 7731
-system.ruby.network.msg_count.Response_Data 3534
+system.ruby.network.msg_count.Request_Control 7737
+system.ruby.network.msg_count.Response_Data 3537
system.ruby.network.msg_count.ResponseL2hit_Data 612
system.ruby.network.msg_count.Response_Control 3
-system.ruby.network.msg_count.Writeback_Data 4749
-system.ruby.network.msg_count.Writeback_Control 2901
+system.ruby.network.msg_count.Writeback_Data 4752
+system.ruby.network.msg_count.Writeback_Control 2904
system.ruby.network.msg_count.Persistent_Control 156
-system.ruby.network.msg_byte.Request_Control 61848
-system.ruby.network.msg_byte.Response_Data 254448
+system.ruby.network.msg_byte.Request_Control 61896
+system.ruby.network.msg_byte.Response_Data 254664
system.ruby.network.msg_byte.ResponseL2hit_Data 44064
system.ruby.network.msg_byte.Response_Control 24
-system.ruby.network.msg_byte.Writeback_Data 341928
-system.ruby.network.msg_byte.Writeback_Control 23208
+system.ruby.network.msg_byte.Writeback_Data 342144
+system.ruby.network.msg_byte.Writeback_Control 23232
system.ruby.network.msg_byte.Persistent_Control 1248
-system.ruby.network.routers0.throttle0.link_utilization 5.757346
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1178
+system.ruby.network.routers0.throttle0.link_utilization 5.761503
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 26
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84816
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers0.throttle1.link_utilization 6.278810
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1382
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1354
+system.ruby.network.routers0.throttle1.link_utilization 6.283429
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 26
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97488
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers1.throttle0.link_utilization 6.278810
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1382
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1354
+system.ruby.network.routers1.throttle0.link_utilization 6.283429
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 26
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97488
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers1.throttle1.link_utilization 2.798999
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1195
+system.ruby.network.routers1.throttle1.link_utilization 2.799922
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::4 229
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 967
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9560
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::4 968
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 9568
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7736
-system.ruby.network.routers2.throttle0.link_utilization 1.962532
-system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1195
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744
+system.ruby.network.routers2.throttle0.link_utilization 1.963456
+system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 967
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968
system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 26
-system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9560
+system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7736
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers2.throttle1.link_utilization 4.896862
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1178
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84816
-system.ruby.network.routers3.throttle0.link_utilization 5.745337
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1178
+system.ruby.network.routers2.throttle1.link_utilization 4.901019
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888
+system.ruby.network.routers3.throttle0.link_utilization 5.749494
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84816
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.throttle1.link_utilization 6.278810
-system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1382
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1354
+system.ruby.network.routers3.throttle1.link_utilization 6.283429
+system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 26
-system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11056
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97488
+system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers3.throttle2.link_utilization 1.962532
-system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1195
+system.ruby.network.routers3.throttle2.link_utilization 1.963456
+system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229
-system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 967
+system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968
system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 26
-system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9560
+system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488
-system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7736
+system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 208
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
-system.ruby.LD.latency_hist_seqr::samples 1183
-system.ruby.LD.latency_hist_seqr::mean 28.775148
-system.ruby.LD.latency_hist_seqr::gmean 6.010104
-system.ruby.LD.latency_hist_seqr::stdev 37.379747
-system.ruby.LD.latency_hist_seqr | 842 71.17% 71.17% | 336 28.40% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1183
+system.ruby.LD.latency_hist_seqr::samples 1185
+system.ruby.LD.latency_hist_seqr::mean 28.779747
+system.ruby.LD.latency_hist_seqr::gmean 6.012520
+system.ruby.LD.latency_hist_seqr::stdev 37.360727
+system.ruby.LD.latency_hist_seqr | 843 71.14% 71.14% | 337 28.44% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 4
system.ruby.LD.hit_latency_hist_seqr::max_bucket 39
-system.ruby.LD.hit_latency_hist_seqr::samples 758
-system.ruby.LD.hit_latency_hist_seqr::mean 4.034301
-system.ruby.LD.hit_latency_hist_seqr::gmean 1.520848
-system.ruby.LD.hit_latency_hist_seqr::stdev 7.788579
-system.ruby.LD.hit_latency_hist_seqr | 658 86.81% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 0 0.00% 86.81% | 100 13.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 758
+system.ruby.LD.hit_latency_hist_seqr::samples 759
+system.ruby.LD.hit_latency_hist_seqr::mean 4.030303
+system.ruby.LD.hit_latency_hist_seqr::gmean 1.520008
+system.ruby.LD.hit_latency_hist_seqr::stdev 7.784219
+system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 100 13.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 759
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
-system.ruby.LD.miss_latency_hist_seqr::samples 425
-system.ruby.LD.miss_latency_hist_seqr::mean 72.901176
-system.ruby.LD.miss_latency_hist_seqr::gmean 69.708423
-system.ruby.LD.miss_latency_hist_seqr::stdev 27.218709
-system.ruby.LD.miss_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 425
+system.ruby.LD.miss_latency_hist_seqr::samples 426
+system.ruby.LD.miss_latency_hist_seqr::mean 72.875587
+system.ruby.LD.miss_latency_hist_seqr::gmean 69.678801
+system.ruby.LD.miss_latency_hist_seqr::stdev 27.158723
+system.ruby.LD.miss_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 426
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 14.011561
-system.ruby.ST.latency_hist_seqr::gmean 2.583043
-system.ruby.ST.latency_hist_seqr::stdev 26.009033
+system.ruby.ST.latency_hist_seqr::mean 13.996532
+system.ruby.ST.latency_hist_seqr::gmean 2.581393
+system.ruby.ST.latency_hist_seqr::stdev 26.004028
system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 4
system.ruby.ST.hit_latency_hist_seqr::max_bucket 39
system.ruby.ST.hit_latency_hist_seqr::samples 697
-system.ruby.ST.hit_latency_hist_seqr::mean 2.321377
-system.ruby.ST.hit_latency_hist_seqr::gmean 1.211206
-system.ruby.ST.hit_latency_hist_seqr::stdev 5.179814
-system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 17 2.44% 96.27% | 26 3.73% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean 2.305595
+system.ruby.ST.hit_latency_hist_seqr::gmean 1.210352
+system.ruby.ST.hit_latency_hist_seqr::stdev 5.118132
+system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 21 3.01% 96.84% | 22 3.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 697
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 168
-system.ruby.ST.miss_latency_hist_seqr::mean 62.511905
-system.ruby.ST.miss_latency_hist_seqr::gmean 59.804102
-system.ruby.ST.miss_latency_hist_seqr::stdev 21.242819
+system.ruby.ST.miss_latency_hist_seqr::mean 62.500000
+system.ruby.ST.miss_latency_hist_seqr::gmean 59.782556
+system.ruby.ST.miss_latency_hist_seqr::stdev 21.264516
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 168
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 6400
-system.ruby.IFETCH.latency_hist_seqr::mean 8.381875
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.532979
-system.ruby.IFETCH.latency_hist_seqr::stdev 24.412953
-system.ruby.IFETCH.latency_hist_seqr | 5815 90.86% 90.86% | 571 8.92% 99.78% | 5 0.08% 99.86% | 2 0.03% 99.89% | 4 0.06% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 6400
+system.ruby.IFETCH.latency_hist_seqr::samples 6413
+system.ruby.IFETCH.latency_hist_seqr::mean 8.354748
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.531676
+system.ruby.IFETCH.latency_hist_seqr::stdev 24.237273
+system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 5 0.08% 99.86% | 3 0.05% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5815
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243164
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033952
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.371578
-system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.95% 98.95% | 0 0.00% 98.95% | 2 0.03% 98.99% | 58 1.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5815
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5828
+system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.243480
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.033914
+system.ruby.IFETCH.hit_latency_hist_seqr::stdev 2.376718
+system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.95% 98.95% | 0 0.00% 98.95% | 0 0.00% 98.95% | 60 1.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5828
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 585
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.341880
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.853466
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.381468
-system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.200000
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.837583
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.345532
+system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 585
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7066
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7080
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
-system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7066 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7066
+system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7080 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.720588
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.671773
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.608281
-system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 19 9.31% 9.31% | 184 90.20% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.691176
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.640301
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.636324
+system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1178
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.617997
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.587772
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.670099
-system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.75% 13.75% | 995 84.47% 98.22% | 8 0.68% 98.90% | 3 0.25% 99.15% | 6 0.51% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 1178
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.535199
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.564149
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.099799
+system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 425
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.901176
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.708423
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.218709
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.76% 19.76% | 336 79.06% 98.82% | 2 0.47% 99.29% | 0 0.00% 99.29% | 2 0.47% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 425
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.875587
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.678801
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.158723
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 654
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.418605
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.330941
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.978847
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 17 39.53% 39.53% | 26 60.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.162791
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.076919
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.963115
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 48.84% 48.84% | 22 51.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.511905
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.804102
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.242819
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.500000
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.782556
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.264516
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 8
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 79
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 61
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.180328
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.114482
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.109567
-system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 3.28% 3.28% | 58 95.08% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 24.262295
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.201824
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::stdev 2.048590
+system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 60 98.36% 98.36% | 0 0.00% 98.36% | 1 1.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.341880
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.853466
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.381468
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 2 0.34% 98.80% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.200000
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.837583
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.345532
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585
system.ruby.Directory_Controller.GETX 208 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 1016 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 1017 0.00% 0.00%
system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.Unlockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00%
-system.ruby.Directory_Controller.Ack_Owner_All_Tokens 904 0.00% 0.00%
+system.ruby.Directory_Controller.Ack_Owner_All_Tokens 905 0.00% 0.00%
system.ruby.Directory_Controller.Ack_All_Tokens 34 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1178 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1179 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 229 0.00% 0.00%
system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00%
-system.ruby.Directory_Controller.O.GETS 1010 0.00% 0.00%
+system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00%
system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00%
system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00%
system.ruby.Directory_Controller.NO.Lockdown 2 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 904 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00%
system.ruby.Directory_Controller.L.Unlockdown 13 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00%
system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00%
system.ruby.Directory_Controller.L_NO_W.Memory_Data 11 0.00% 0.00%
system.ruby.Directory_Controller.NO_W.Lockdown 11 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 1167 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data 1168 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_Replacement 1367 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data_All_Tokens 1221 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00%
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 26 0.00% 0.00%
system.ruby.L1Cache_Controller.Request_Timeout 13 0.00% 0.00%
-system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1220 0.00% 0.00%
-system.ruby.L1Cache_Controller.NP.Load 525 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00%
+system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Store 191 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Load 153 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 180 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 3187 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 3194 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_Replacement 945 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch 2236 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch 2242 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 984 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Load 23 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.Store 331 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 4 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1010 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Request_Timeout 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.L1_GETS 1122 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00%
-system.ruby.L2Cache_Controller.L2_Replacement 1265 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00%
-system.ruby.L2Cache_Controller.Writeback_All_Tokens 1270 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00%
system.ruby.L2Cache_Controller.Persistent_GETS 13 0.00% 0.00%
system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.L1_GETS 1010 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1192 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 13 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00%
system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00%
-system.ruby.L2Cache_Controller.M.L2_Replacement 1124 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00%
system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00%
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:56:08
-gem5 started Jan 21 2016 13:56:42
-gem5 executing on zizzer, pid 39359
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Mar 14 2016 21:55:52
+gem5 started Mar 14 2016 21:57:33
+gem5 executing on phenom, pid 28167
+command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 86673 because target called exit()
+Exiting @ tick 86770 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000087 # Number of seconds simulated
-sim_ticks 86673 # Number of ticks simulated
-final_tick 86673 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 86770 # Number of ticks simulated
+final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 58973 # Simulator instruction rate (inst/s)
-host_op_rate 58962 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 799609 # Simulator tick rate (ticks/s)
-host_mem_usage 411856 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 43915 # Simulator instruction rate (inst/s)
+host_op_rate 43910 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 594975 # Simulator tick rate (ticks/s)
+host_mem_usage 388108 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74176 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 74176 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total 14080 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1159 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1159 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 855814383 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 855814383 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 162449667 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 162449667 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1018264050 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1018264050 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1159 # Number of read requests accepted
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 855595252 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 855595252 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 162268065 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 162268065 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1017863317 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1017863317 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1160 # Number of read requests accepted
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
-system.mem_ctrls.readBursts 1159 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 63680 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadDRAM 63744 # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 74176 # Total read bytes from the system interface side
+system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 40 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 86601 # Total gap between requests
+system.mem_ctrls.totGap 86698 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1159 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1160 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 995 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 996 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 190 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 360.757895 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 214.175980 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 351.466789 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 60 31.58% 31.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 43 22.63% 54.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 19 10.00% 64.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 13 6.84% 71.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 11 5.79% 76.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 4 2.11% 78.95% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 8 4.21% 83.16% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 5 2.63% 85.79% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 27 14.21% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 190 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 358.869110 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 215.937059 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 347.377875 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 57 29.84% 29.84% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 46 24.08% 53.93% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 10 5.24% 76.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 2.09% 79.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 7 3.66% 82.72% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 8 4.19% 86.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 25 13.09% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 143.200000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 107.762756 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 83.250826 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 143.400000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 107.861440 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 83.476344 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 6132 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 25037 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4975 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.16 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 6142 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 25066 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4980 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 6.17 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.16 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 734.72 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 63.50 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 855.81 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 162.45 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 25.17 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 734.63 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 63.43 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 855.60 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 162.27 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 6.24 # Data bus utilization in percentage
+system.mem_ctrls.busUtil 6.23 # Data bus utilization in percentage
system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 20.56 # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen 20.55 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.21 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 81.12 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 62.80 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.11 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 461160 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 256200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls.avgGap 62.82 # Average gap between requests
+system.mem_ctrls.pageHitRate 80.04 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 49992876 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 7690200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 69345636 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 807.226922 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 12934 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 50178924 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 7527000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 69392004 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 807.766675 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 12759 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 70523 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 70795 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 975240 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 541800 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.actEnergy 967680 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 537600 # Energy for precharge commands per rank (pJ)
system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ)
system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 57826728 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 818400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 73589736 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 856.630922 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 958 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 57849984 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 798000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 73580832 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 856.527274 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 910 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 82102 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 86673 # number of cpu cycles simulated
+system.cpu.numCycles 86770 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 86673 # Number of busy cycles
+system.cpu.num_busy_cycles 86770 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 8449
+system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 8449
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 8448
-system.ruby.latency_hist_seqr::mean 9.259588
-system.ruby.latency_hist_seqr::gmean 1.841457
-system.ruby.latency_hist_seqr::stdev 22.233278
-system.ruby.latency_hist_seqr | 8216 97.25% 97.25% | 221 2.62% 99.87% | 0 0.00% 99.87% | 3 0.04% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 8448
+system.ruby.latency_hist_seqr::samples 8463
+system.ruby.latency_hist_seqr::mean 9.252865
+system.ruby.latency_hist_seqr::gmean 1.840314
+system.ruby.latency_hist_seqr::stdev 22.282539
+system.ruby.latency_hist_seqr | 8231 97.26% 97.26% | 222 2.62% 99.88% | 0 0.00% 99.88% | 1 0.01% 99.89% | 7 0.08% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 2
system.ruby.hit_latency_hist_seqr::max_bucket 19
-system.ruby.hit_latency_hist_seqr::samples 7289
-system.ruby.hit_latency_hist_seqr::mean 1.278502
-system.ruby.hit_latency_hist_seqr::gmean 1.069062
-system.ruby.hit_latency_hist_seqr::stdev 1.645548
-system.ruby.hit_latency_hist_seqr | 7086 97.21% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 0 0.00% 97.21% | 203 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 7289
+system.ruby.hit_latency_hist_seqr::samples 7303
+system.ruby.hit_latency_hist_seqr::mean 1.277968
+system.ruby.hit_latency_hist_seqr::gmean 1.068925
+system.ruby.hit_latency_hist_seqr::stdev 1.644014
+system.ruby.hit_latency_hist_seqr | 7100 97.22% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 0 0.00% 97.22% | 203 2.78% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 7303
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1159
-system.ruby.miss_latency_hist_seqr::mean 59.452977
-system.ruby.miss_latency_hist_seqr::gmean 56.282360
-system.ruby.miss_latency_hist_seqr::stdev 25.811948
-system.ruby.miss_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1159
-system.ruby.Directory.incomplete_times_seqr 1158
+system.ruby.miss_latency_hist_seqr::samples 1160
+system.ruby.miss_latency_hist_seqr::mean 59.460345
+system.ruby.miss_latency_hist_seqr::gmean 56.276317
+system.ruby.miss_latency_hist_seqr::stdev 26.160126
+system.ruby.miss_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1160
+system.ruby.Directory.incomplete_times_seqr 1159
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 1332 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 716 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 5754 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
-system.ruby.l1_cntrl0.L2cache.demand_misses 1159 # Number of cache demand misses
-system.ruby.l1_cntrl0.L2cache.demand_accesses 1362 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
+system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 5.174045
-system.ruby.network.routers0.msg_count.Request_Control::2 1159
-system.ruby.network.routers0.msg_count.Response_Data::4 1159
+system.ruby.network.routers0.percent_links_utilized 5.172295
+system.ruby.network.routers0.msg_count.Request_Control::2 1160
+system.ruby.network.routers0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
-system.ruby.network.routers0.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers0.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers0.msg_count.Writeback_Control::5 923
-system.ruby.network.routers0.msg_count.Unblock_Control::5 1159
-system.ruby.network.routers0.msg_bytes.Request_Control::2 9272
-system.ruby.network.routers0.msg_bytes.Response_Data::4 83448
+system.ruby.network.routers0.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers0.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers0.msg_count.Writeback_Control::5 924
+system.ruby.network.routers0.msg_count.Unblock_Control::5 1160
+system.ruby.network.routers0.msg_bytes.Request_Control::2 9280
+system.ruby.network.routers0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers0.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9272
-system.ruby.network.routers1.percent_links_utilized 5.173757
-system.ruby.network.routers1.msg_count.Request_Control::2 1159
-system.ruby.network.routers1.msg_count.Response_Data::4 1159
+system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.routers1.percent_links_utilized 5.172006
+system.ruby.network.routers1.msg_count.Request_Control::2 1160
+system.ruby.network.routers1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
-system.ruby.network.routers1.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers1.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers1.msg_count.Writeback_Control::5 923
-system.ruby.network.routers1.msg_count.Unblock_Control::5 1158
-system.ruby.network.routers1.msg_bytes.Request_Control::2 9272
-system.ruby.network.routers1.msg_bytes.Response_Data::4 83448
+system.ruby.network.routers1.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers1.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers1.msg_count.Writeback_Control::5 924
+system.ruby.network.routers1.msg_count.Unblock_Control::5 1159
+system.ruby.network.routers1.msg_bytes.Request_Control::2 9280
+system.ruby.network.routers1.msg_bytes.Response_Data::4 83520
system.ruby.network.routers1.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9264
-system.ruby.network.routers2.percent_links_utilized 5.174045
-system.ruby.network.routers2.msg_count.Request_Control::2 1159
-system.ruby.network.routers2.msg_count.Response_Data::4 1159
+system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
+system.ruby.network.routers2.percent_links_utilized 5.172295
+system.ruby.network.routers2.msg_count.Request_Control::2 1160
+system.ruby.network.routers2.msg_count.Response_Data::4 1160
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
-system.ruby.network.routers2.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers2.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers2.msg_count.Writeback_Control::5 923
-system.ruby.network.routers2.msg_count.Unblock_Control::5 1159
-system.ruby.network.routers2.msg_bytes.Request_Control::2 9272
-system.ruby.network.routers2.msg_bytes.Response_Data::4 83448
+system.ruby.network.routers2.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers2.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers2.msg_count.Writeback_Control::5 924
+system.ruby.network.routers2.msg_count.Unblock_Control::5 1160
+system.ruby.network.routers2.msg_bytes.Request_Control::2 9280
+system.ruby.network.routers2.msg_bytes.Response_Data::4 83520
system.ruby.network.routers2.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9272
-system.ruby.network.msg_count.Request_Control 3477
-system.ruby.network.msg_count.Response_Data 3477
+system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.msg_count.Request_Control 3480
+system.ruby.network.msg_count.Response_Data 3480
system.ruby.network.msg_count.Writeback_Data 660
-system.ruby.network.msg_count.Writeback_Control 9627
-system.ruby.network.msg_count.Unblock_Control 3476
-system.ruby.network.msg_byte.Request_Control 27816
-system.ruby.network.msg_byte.Response_Data 250344
+system.ruby.network.msg_count.Writeback_Control 9636
+system.ruby.network.msg_count.Unblock_Control 3479
+system.ruby.network.msg_byte.Request_Control 27840
+system.ruby.network.msg_byte.Response_Data 250560
system.ruby.network.msg_byte.Writeback_Data 47520
-system.ruby.network.msg_byte.Writeback_Control 77016
-system.ruby.network.msg_byte.Unblock_Control 27808
-system.ruby.network.routers0.throttle0.link_utilization 6.676820
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1159
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83448
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers0.throttle1.link_utilization 3.671270
-system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1159
+system.ruby.network.msg_byte.Writeback_Control 77088
+system.ruby.network.msg_byte.Unblock_Control 27832
+system.ruby.network.routers0.throttle0.link_utilization 6.675118
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers0.throttle1.link_utilization 3.669471
+system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 923
-system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1159
-system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9272
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::5 924
+system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::5 1160
+system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::2 9280
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9272
-system.ruby.network.routers1.throttle0.link_utilization 3.670693
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1159
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280
+system.ruby.network.routers1.throttle0.link_utilization 3.668895
+system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 923
-system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1158
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9272
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::5 924
+system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::5 1159
+system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::2 9280
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9264
-system.ruby.network.routers1.throttle1.link_utilization 6.676820
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1159
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83448
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers2.throttle0.link_utilization 6.676820
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1159
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1143
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83448
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9144
-system.ruby.network.routers2.throttle1.link_utilization 3.671270
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1159
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
+system.ruby.network.routers1.throttle1.link_utilization 6.675118
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers2.throttle0.link_utilization 6.675118
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152
+system.ruby.network.routers2.throttle1.link_utilization 3.669471
+system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1143
-system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 923
-system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1159
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9272
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144
+system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::5 924
+system.ruby.network.routers2.throttle1.msg_count.Unblock_Control::5 1160
+system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::2 9280
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9144
-system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7384
-system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9272
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152
+system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392
+system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280
system.ruby.LD.latency_hist_seqr::bucket_size 32
system.ruby.LD.latency_hist_seqr::max_bucket 319
-system.ruby.LD.latency_hist_seqr::samples 1183
-system.ruby.LD.latency_hist_seqr::mean 21.460693
-system.ruby.LD.latency_hist_seqr::gmean 5.052192
-system.ruby.LD.latency_hist_seqr::stdev 28.940454
-system.ruby.LD.latency_hist_seqr | 852 72.02% 72.02% | 242 20.46% 92.48% | 85 7.19% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1183
+system.ruby.LD.latency_hist_seqr::samples 1185
+system.ruby.LD.latency_hist_seqr::mean 21.677637
+system.ruby.LD.latency_hist_seqr::gmean 5.060853
+system.ruby.LD.latency_hist_seqr::stdev 30.245768
+system.ruby.LD.latency_hist_seqr | 853 71.98% 71.98% | 244 20.59% 92.57% | 84 7.09% 99.66% | 1 0.08% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 2
system.ruby.LD.hit_latency_hist_seqr::max_bucket 19
-system.ruby.LD.hit_latency_hist_seqr::samples 763
-system.ruby.LD.hit_latency_hist_seqr::mean 2.376147
-system.ruby.LD.hit_latency_hist_seqr::gmean 1.390948
-system.ruby.LD.hit_latency_hist_seqr::stdev 3.447211
-system.ruby.LD.hit_latency_hist_seqr | 658 86.24% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 0 0.00% 86.24% | 105 13.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 763
+system.ruby.LD.hit_latency_hist_seqr::samples 764
+system.ruby.LD.hit_latency_hist_seqr::mean 2.374346
+system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347
+system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311
+system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 764
system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
-system.ruby.LD.miss_latency_hist_seqr::samples 420
-system.ruby.LD.miss_latency_hist_seqr::mean 56.130952
-system.ruby.LD.miss_latency_hist_seqr::gmean 52.616261
-system.ruby.LD.miss_latency_hist_seqr::stdev 21.748058
-system.ruby.LD.miss_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 420
+system.ruby.LD.miss_latency_hist_seqr::samples 421
+system.ruby.LD.miss_latency_hist_seqr::mean 56.707838
+system.ruby.LD.miss_latency_hist_seqr::gmean 52.779793
+system.ruby.LD.miss_latency_hist_seqr::stdev 25.484779
+system.ruby.LD.miss_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 421
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 865
system.ruby.ST.miss_latency_hist_seqr::total 158
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 6400
-system.ruby.IFETCH.latency_hist_seqr::mean 6.828750
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.489407
-system.ruby.IFETCH.latency_hist_seqr::stdev 20.190166
-system.ruby.IFETCH.latency_hist_seqr | 6294 98.34% 98.34% | 97 1.52% 99.86% | 0 0.00% 99.86% | 2 0.03% 99.89% | 5 0.08% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 6400
+system.ruby.IFETCH.latency_hist_seqr::samples 6413
+system.ruby.IFETCH.latency_hist_seqr::mean 6.780914
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.487888
+system.ruby.IFETCH.latency_hist_seqr::stdev 19.876102
+system.ruby.IFETCH.latency_hist_seqr | 6306 98.33% 98.33% | 100 1.56% 99.89% | 0 0.00% 99.89% | 1 0.02% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5819
-system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111703
-system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027147
-system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.051067
-system.ruby.IFETCH.hit_latency_hist_seqr | 5754 98.88% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 0 0.00% 98.88% | 65 1.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5819
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5832
+system.ruby.IFETCH.hit_latency_hist_seqr::mean 1.111454
+system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.027086
+system.ruby.IFETCH.hit_latency_hist_seqr::stdev 1.049908
+system.ruby.IFETCH.hit_latency_hist_seqr | 5767 98.89% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 0 0.00% 98.89% | 65 1.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5832
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 581
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.087780
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.562973
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.566480
-system.ruby.IFETCH.miss_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.690189
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.418649
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.087678
+system.ruby.IFETCH.miss_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 581
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7086
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::samples 7100
system.ruby.L1Cache.hit_mach_latency_hist_seqr::mean 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::gmean 1
-system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7086 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7086
+system.ruby.L1Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 7100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7100
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 2
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 19
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 203
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1159
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.452977
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.282360
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 25.811948
-system.ruby.Directory.miss_mach_latency_hist_seqr | 927 79.98% 79.98% | 221 19.07% 99.05% | 0 0.00% 99.05% | 3 0.26% 99.31% | 6 0.52% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 1159
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.460345
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.276317
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 26.160126
+system.ruby.Directory.miss_mach_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 658
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::samples 659
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 658 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 658
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 105
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 420
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.130952
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.616261
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 21.748058
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.19% 21.19% | 242 57.62% 78.81% | 85 20.24% 99.05% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 420
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.707838
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.779793
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.484779
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::samples 674
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5754
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::samples 5767
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::mean 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5754 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5754
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 5767 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::total 5767
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 19
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::samples 65
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.087780
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.562973
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.566480
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 475 81.76% 81.76% | 97 16.70% 98.45% | 0 0.00% 98.45% | 2 0.34% 98.80% | 5 0.86% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.690189
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.418649
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 28.087678
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
-system.ruby.Directory_Controller.GETS 1020 0.00% 0.00%
-system.ruby.Directory_Controller.PUT 1143 0.00% 0.00%
-system.ruby.Directory_Controller.UnblockM 1158 0.00% 0.00%
-system.ruby.Directory_Controller.Writeback_Exclusive_Clean 923 0.00% 0.00%
+system.ruby.Directory_Controller.GETS 1021 0.00% 0.00%
+system.ruby.Directory_Controller.PUT 1144 0.00% 0.00%
+system.ruby.Directory_Controller.UnblockM 1159 0.00% 0.00%
+system.ruby.Directory_Controller.Writeback_Exclusive_Clean 924 0.00% 0.00%
system.ruby.Directory_Controller.Writeback_Exclusive_Dirty 220 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1159 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1160 0.00% 0.00%
system.ruby.Directory_Controller.Memory_Ack 220 0.00% 0.00%
-system.ruby.Directory_Controller.NO.PUT 1143 0.00% 0.00%
+system.ruby.Directory_Controller.NO.PUT 1144 0.00% 0.00%
system.ruby.Directory_Controller.E.GETX 158 0.00% 0.00%
-system.ruby.Directory_Controller.E.GETS 1001 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B.UnblockM 1158 0.00% 0.00%
-system.ruby.Directory_Controller.NO_B_W.Memory_Data 1159 0.00% 0.00%
+system.ruby.Directory_Controller.E.GETS 1002 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B.UnblockM 1159 0.00% 0.00%
+system.ruby.Directory_Controller.NO_B_W.Memory_Data 1160 0.00% 0.00%
system.ruby.Directory_Controller.WB.GETX 27 0.00% 0.00%
system.ruby.Directory_Controller.WB.GETS 19 0.00% 0.00%
-system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 923 0.00% 0.00%
+system.ruby.Directory_Controller.WB.Writeback_Exclusive_Clean 924 0.00% 0.00%
system.ruby.Directory_Controller.WB.Writeback_Exclusive_Dirty 220 0.00% 0.00%
system.ruby.Directory_Controller.WB_E_W.Memory_Ack 220 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1191 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 6411 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1193 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6424 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 892 0.00% 0.00%
-system.ruby.L1Cache_Controller.L2_Replacement 1143 0.00% 0.00%
-system.ruby.L1Cache_Controller.L1_to_L2 1354 0.00% 0.00%
+system.ruby.L1Cache_Controller.L2_Replacement 1144 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_to_L2 1355 0.00% 0.00%
system.ruby.L1Cache_Controller.Trigger_L2_to_L1D 138 0.00% 0.00%
system.ruby.L1Cache_Controller.Trigger_L2_to_L1I 65 0.00% 0.00%
system.ruby.L1Cache_Controller.Complete_L2_to_L1 203 0.00% 0.00%
-system.ruby.L1Cache_Controller.Exclusive_Data 1159 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 1143 0.00% 0.00%
-system.ruby.L1Cache_Controller.All_acks_no_sharers 1159 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 420 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 1160 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 1144 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks_no_sharers 1160 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 421 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 581 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 158 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 304 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 5754 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 305 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 5767 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 60 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L2_Replacement 923 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.L1_to_L2 1061 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L2_Replacement 924 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_to_L2 1062 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1D 68 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Trigger_L2_to_L1I 65 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 354 0.00% 0.00%
system.ruby.L1Cache_Controller.MMR.Load 43 0.00% 0.00%
system.ruby.L1Cache_Controller.MMR.Store 27 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Exclusive_Data 158 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1001 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.All_acks_no_sharers 1002 0.00% 0.00%
system.ruby.L1Cache_Controller.MM_W.All_acks_no_sharers 158 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Exclusive_Data 1001 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 1002 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Load 8 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Ifetch 11 0.00% 0.00%
system.ruby.L1Cache_Controller.MI.Store 27 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 1143 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 1144 0.00% 0.00%
system.ruby.L1Cache_Controller.MT.Complete_L2_to_L1 133 0.00% 0.00%
system.ruby.L1Cache_Controller.MMT.Complete_L2_to_L1 70 0.00% 0.00%
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:00
-gem5 executing on zizzer, pid 33967
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:55:58
+gem5 executing on phenom, pid 28070
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 107210 because target called exit()
+Exiting @ tick 107065 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000107 # Number of seconds simulated
-sim_ticks 107210 # Number of ticks simulated
-final_tick 107210 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 107065 # Number of ticks simulated
+final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 108799 # Simulator instruction rate (inst/s)
-host_op_rate 108769 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1824399 # Simulator tick rate (ticks/s)
-host_mem_usage 416280 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 18652 # Simulator instruction rate (inst/s)
+host_op_rate 18652 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 311861 # Simulator tick rate (ticks/s)
+host_mem_usage 390536 # Number of bytes of host memory used
+host_seconds 0.34 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110720 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 110720 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110464 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 110464 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1730 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1730 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 1726 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 1726 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1032739483 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1032739483 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1030351646 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1030351646 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2063091130 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2063091130 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1730 # Number of read requests accepted
-system.mem_ctrls.writeReqs 1726 # Number of write requests accepted
-system.mem_ctrls.readBursts 1730 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 1726 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 56896 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 53824 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 56448 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 110720 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 110464 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 841 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 814 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 110528 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 1034735908 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 1034735908 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032344837 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 1032344837 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 2067080745 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 2067080745 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1731 # Number of read requests accepted
+system.mem_ctrls.writeReqs 1727 # Number of write requests accepted
+system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 56512 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 54272 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 57856 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 848 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 792 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 82 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 48 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 85 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 66 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 116 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 24 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 47 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 74 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 68 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 31 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 19 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 266 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 17 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 263 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 19 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 81 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 49 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 85 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 62 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 28 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 83 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 47 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 80 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 68 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 133 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 4 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 44 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 29 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 13 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 262 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 79 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 20 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 46 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 28 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 11 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 28 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 107138 # Total gap between requests
+system.mem_ctrls.totGap 106993 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1730 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1731 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 1726 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 889 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 883 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 52 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 56 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 54 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 54 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 54 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 253 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 437.122530 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 269.105572 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 371.515393 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 63 24.90% 24.90% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 51 20.16% 45.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 24 9.49% 54.55% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 18 7.11% 61.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 14 5.53% 67.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 10 3.95% 71.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 18 7.11% 78.26% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 10 3.95% 82.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 45 17.79% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 253 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 54 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 16.203704 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 16.028046 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 2.999243 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 1 1.85% 1.85% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 20 37.04% 38.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 27 50.00% 88.89% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 4 7.41% 96.30% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::20-21 1 1.85% 98.15% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::36-37 1 1.85% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 54 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 54 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.333333 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.311361 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.890198 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 47 87.04% 87.04% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 5.56% 92.59% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 4 7.41% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 54 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 10919 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 27810 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4445 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.28 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 275 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 406.341818 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 258.682678 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 357.059585 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 55 20.00% 20.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 74 26.91% 46.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 37 13.45% 60.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 16 5.82% 66.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 18 6.55% 72.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 12 4.36% 77.09% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 8 2.91% 80.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 6 2.18% 82.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 49 17.82% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 275 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 15.781818 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 15.596648 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 2.973282 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13 4 7.27% 7.27% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 25 45.45% 52.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.436364 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.408895 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.995613 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 45 81.82% 81.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 2 3.64% 85.45% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 2 3.64% 89.09% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 6 10.91% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 10887 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 27664 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4415 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.33 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.28 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 530.70 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 526.52 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1032.74 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1030.35 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.33 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 527.83 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 540.38 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 1034.74 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 1032.34 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 8.26 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.15 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.11 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.12 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 4.22 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.52 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 682 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 829 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 76.72 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 90.90 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 31.00 # Average gap between requests
-system.mem_ctrls.pageHitRate 83.90 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 748440 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 415800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5166720 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 4447872 # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen 26.13 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 670 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 835 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 75.88 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 89.30 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 30.94 # Average gap between requests
+system.mem_ctrls.pageHitRate 82.78 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 876960 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 487200 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 4489344 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 64735128 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 4101600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 86226840 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 849.709691 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 7218 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 63943740 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 4795800 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 86196324 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 849.408975 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 8418 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 91640 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 90483 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1088640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 604800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 5241600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 4167936 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy 1156680 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 642600 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 5366400 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 4385664 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 64577808 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 4239600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 86531664 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 852.713534 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 6460 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 65375352 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 3540000 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 87077976 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 858.097085 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 5471 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 91652 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 107210 # number of cpu cycles simulated
+system.cpu.numCycles 107065 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 107210 # Number of busy cycles
+system.cpu.num_busy_cycles 107065 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 3456 # delay histogram for all message
-system.ruby.delayHist | 3456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 3456 # delay histogram for all message
+system.ruby.delayHist::samples 3458 # delay histogram for all message
+system.ruby.delayHist | 3458 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 3458 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 8449
+system.ruby.outstanding_req_hist_seqr::samples 8464
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8449 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 8449
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8464 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 8448
-system.ruby.latency_hist_seqr::mean 11.690578
-system.ruby.latency_hist_seqr::gmean 2.205273
-system.ruby.latency_hist_seqr::stdev 25.830363
-system.ruby.latency_hist_seqr | 8209 97.17% 97.17% | 184 2.18% 99.35% | 38 0.45% 99.80% | 7 0.08% 99.88% | 6 0.07% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 8448
+system.ruby.latency_hist_seqr::samples 8463
+system.ruby.latency_hist_seqr::mean 11.650951
+system.ruby.latency_hist_seqr::gmean 2.202191
+system.ruby.latency_hist_seqr::stdev 25.742711
+system.ruby.latency_hist_seqr | 8220 97.13% 97.13% | 190 2.25% 99.37% | 41 0.48% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 6718
+system.ruby.hit_latency_hist_seqr::samples 6732
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6718 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 6718
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6732 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 6732
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1730
-system.ruby.miss_latency_hist_seqr::mean 53.204624
-system.ruby.miss_latency_hist_seqr::gmean 47.556283
-system.ruby.miss_latency_hist_seqr::stdev 33.032605
-system.ruby.miss_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1730
-system.ruby.Directory.incomplete_times_seqr 1729
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 6718 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 1730 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8448 # Number of cache demand accesses
+system.ruby.miss_latency_hist_seqr::samples 1731
+system.ruby.miss_latency_hist_seqr::mean 53.073368
+system.ruby.miss_latency_hist_seqr::gmean 47.451096
+system.ruby.miss_latency_hist_seqr::stdev 32.911544
+system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1731
+system.ruby.Directory.incomplete_times_seqr 1730
+system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 8.058950
-system.ruby.network.routers0.msg_count.Control::2 1730
-system.ruby.network.routers0.msg_count.Data::2 1726
-system.ruby.network.routers0.msg_count.Response_Data::4 1730
-system.ruby.network.routers0.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers0.msg_bytes.Control::2 13840
-system.ruby.network.routers0.msg_bytes.Data::2 124272
-system.ruby.network.routers0.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.routers1.percent_links_utilized 8.058950
-system.ruby.network.routers1.msg_count.Control::2 1730
-system.ruby.network.routers1.msg_count.Data::2 1726
-system.ruby.network.routers1.msg_count.Response_Data::4 1730
-system.ruby.network.routers1.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers1.msg_bytes.Control::2 13840
-system.ruby.network.routers1.msg_bytes.Data::2 124272
-system.ruby.network.routers1.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.routers2.percent_links_utilized 8.058950
-system.ruby.network.routers2.msg_count.Control::2 1730
-system.ruby.network.routers2.msg_count.Data::2 1726
-system.ruby.network.routers2.msg_count.Response_Data::4 1730
-system.ruby.network.routers2.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers2.msg_bytes.Control::2 13840
-system.ruby.network.routers2.msg_bytes.Data::2 124272
-system.ruby.network.routers2.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.msg_count.Control 5190
-system.ruby.network.msg_count.Data 5178
-system.ruby.network.msg_count.Response_Data 5190
-system.ruby.network.msg_count.Writeback_Control 5178
-system.ruby.network.msg_byte.Control 41520
-system.ruby.network.msg_byte.Data 372816
-system.ruby.network.msg_byte.Response_Data 373680
-system.ruby.network.msg_byte.Writeback_Control 41424
-system.ruby.network.routers0.throttle0.link_utilization 8.066412
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1730
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.routers0.throttle1.link_utilization 8.051488
-system.ruby.network.routers0.throttle1.msg_count.Control::2 1730
-system.ruby.network.routers0.throttle1.msg_count.Data::2 1726
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13840
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124272
-system.ruby.network.routers1.throttle0.link_utilization 8.051488
-system.ruby.network.routers1.throttle0.msg_count.Control::2 1730
-system.ruby.network.routers1.throttle0.msg_count.Data::2 1726
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13840
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124272
-system.ruby.network.routers1.throttle1.link_utilization 8.066412
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1730
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.routers2.throttle0.link_utilization 8.066412
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1730
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1726
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124560
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13808
-system.ruby.network.routers2.throttle1.link_utilization 8.051488
-system.ruby.network.routers2.throttle1.msg_count.Control::2 1730
-system.ruby.network.routers2.throttle1.msg_count.Data::2 1726
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13840
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124272
+system.ruby.network.routers0.percent_links_utilized 8.074534
+system.ruby.network.routers0.msg_count.Control::2 1731
+system.ruby.network.routers0.msg_count.Data::2 1727
+system.ruby.network.routers0.msg_count.Response_Data::4 1731
+system.ruby.network.routers0.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers0.msg_bytes.Control::2 13848
+system.ruby.network.routers0.msg_bytes.Data::2 124344
+system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers1.percent_links_utilized 8.074534
+system.ruby.network.routers1.msg_count.Control::2 1731
+system.ruby.network.routers1.msg_count.Data::2 1727
+system.ruby.network.routers1.msg_count.Response_Data::4 1731
+system.ruby.network.routers1.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers1.msg_bytes.Control::2 13848
+system.ruby.network.routers1.msg_bytes.Data::2 124344
+system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers2.percent_links_utilized 8.074534
+system.ruby.network.routers2.msg_count.Control::2 1731
+system.ruby.network.routers2.msg_count.Data::2 1727
+system.ruby.network.routers2.msg_count.Response_Data::4 1731
+system.ruby.network.routers2.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers2.msg_bytes.Control::2 13848
+system.ruby.network.routers2.msg_bytes.Data::2 124344
+system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.msg_count.Control 5193
+system.ruby.network.msg_count.Data 5181
+system.ruby.network.msg_count.Response_Data 5193
+system.ruby.network.msg_count.Writeback_Control 5181
+system.ruby.network.msg_byte.Control 41544
+system.ruby.network.msg_byte.Data 373032
+system.ruby.network.msg_byte.Response_Data 373896
+system.ruby.network.msg_byte.Writeback_Control 41448
+system.ruby.network.routers0.throttle0.link_utilization 8.082006
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers0.throttle1.link_utilization 8.067062
+system.ruby.network.routers0.throttle1.msg_count.Control::2 1731
+system.ruby.network.routers0.throttle1.msg_count.Data::2 1727
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344
+system.ruby.network.routers1.throttle0.link_utilization 8.067062
+system.ruby.network.routers1.throttle0.msg_count.Control::2 1731
+system.ruby.network.routers1.throttle0.msg_count.Data::2 1727
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344
+system.ruby.network.routers1.throttle1.link_utilization 8.082006
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers2.throttle0.link_utilization 8.082006
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816
+system.ruby.network.routers2.throttle1.link_utilization 8.067062
+system.ruby.network.routers2.throttle1.msg_count.Control::2 1731
+system.ruby.network.routers2.throttle1.msg_count.Data::2 1727
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2 124344
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 1730 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 1730 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 1730 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 1731 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 1731 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 1731 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 1726 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 1726 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 1726 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::samples 1727 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 1727 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 1727 # delay histogram for vnet_2
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
-system.ruby.LD.latency_hist_seqr::samples 1183
-system.ruby.LD.latency_hist_seqr::mean 31.638208
-system.ruby.LD.latency_hist_seqr::gmean 10.419015
-system.ruby.LD.latency_hist_seqr::stdev 35.065266
-system.ruby.LD.latency_hist_seqr | 1085 91.72% 91.72% | 74 6.26% 97.97% | 18 1.52% 99.49% | 2 0.17% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1183
+system.ruby.LD.latency_hist_seqr::samples 1185
+system.ruby.LD.latency_hist_seqr::mean 31.532489
+system.ruby.LD.latency_hist_seqr::gmean 10.421226
+system.ruby.LD.latency_hist_seqr::stdev 34.906160
+system.ruby.LD.latency_hist_seqr | 1091 92.07% 92.07% | 75 6.33% 98.40% | 15 1.27% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 456
+system.ruby.LD.hit_latency_hist_seqr::samples 457
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 456 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 456
+system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 457 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 457
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
-system.ruby.LD.miss_latency_hist_seqr::samples 727
-system.ruby.LD.miss_latency_hist_seqr::mean 50.855571
-system.ruby.LD.miss_latency_hist_seqr::gmean 45.315147
-system.ruby.LD.miss_latency_hist_seqr::stdev 32.287061
-system.ruby.LD.miss_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 727
+system.ruby.LD.miss_latency_hist_seqr::samples 728
+system.ruby.LD.miss_latency_hist_seqr::mean 50.699176
+system.ruby.LD.miss_latency_hist_seqr::gmean 45.385232
+system.ruby.LD.miss_latency_hist_seqr::stdev 32.101179
+system.ruby.LD.miss_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 728
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 16.483237
-system.ruby.ST.latency_hist_seqr::gmean 3.324735
-system.ruby.ST.latency_hist_seqr::stdev 28.016571
-system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 244 28.21% 96.65% | 18 2.08% 98.73% | 2 0.23% 98.96% | 5 0.58% 99.54% | 2 0.23% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 16.426590
+system.ruby.ST.latency_hist_seqr::gmean 3.318487
+system.ruby.ST.latency_hist_seqr::stdev 28.264983
+system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 242 27.98% 96.42% | 21 2.43% 98.84% | 1 0.12% 98.96% | 4 0.46% 99.42% | 4 0.46% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 273
-system.ruby.ST.miss_latency_hist_seqr::mean 50.058608
-system.ruby.ST.miss_latency_hist_seqr::gmean 44.997273
-system.ruby.ST.miss_latency_hist_seqr::stdev 28.984216
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 49.879121
+system.ruby.ST.miss_latency_hist_seqr::gmean 44.729882
+system.ruby.ST.miss_latency_hist_seqr::stdev 29.942777
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 273
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 6400
-system.ruby.IFETCH.latency_hist_seqr::mean 7.355625
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.565715
-system.ruby.IFETCH.latency_hist_seqr::stdev 21.264557
-system.ruby.IFETCH.latency_hist_seqr | 6288 98.25% 98.25% | 90 1.41% 99.66% | 13 0.20% 99.86% | 4 0.06% 99.92% | 2 0.03% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 6400
+system.ruby.IFETCH.latency_hist_seqr::samples 6413
+system.ruby.IFETCH.latency_hist_seqr::mean 7.333073
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.563492
+system.ruby.IFETCH.latency_hist_seqr::stdev 21.145733
+system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 93 1.45% 99.61% | 18 0.28% 99.89% | 1 0.02% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5670
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5683
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5670 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5670
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5683 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5683
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 730
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.720548
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.941265
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.853032
-system.ruby.IFETCH.miss_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.635616
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.712708
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.440483
+system.ruby.IFETCH.miss_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 730
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1730
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.204624
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.556283
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.032605
-system.ruby.Directory.miss_mach_latency_hist_seqr | 1491 86.18% 86.18% | 184 10.64% 96.82% | 38 2.20% 99.02% | 7 0.40% 99.42% | 6 0.35% 99.77% | 3 0.17% 99.94% | 0 0.00% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 1730
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.073368
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.451096
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.911544
+system.ruby.Directory.miss_mach_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 727
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.855571
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.315147
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.287061
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 629 86.52% 86.52% | 74 10.18% 96.70% | 18 2.48% 99.17% | 2 0.28% 99.45% | 3 0.41% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 727
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.699176
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.385232
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.101179
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 50.058608
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.997273
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 28.984216
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 244 89.38% 89.38% | 18 6.59% 95.97% | 2 0.73% 96.70% | 5 1.83% 98.53% | 2 0.73% 99.27% | 1 0.37% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.879121
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.729882
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 29.942777
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.720548
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.941265
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.853032
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 618 84.66% 84.66% | 90 12.33% 96.99% | 13 1.78% 98.77% | 4 0.55% 99.32% | 2 0.27% 99.59% | 2 0.27% 99.86% | 0 0.00% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.635616
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.712708
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.440483
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730
-system.ruby.Directory_Controller.GETX 1730 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 1726 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1730 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 1726 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 1730 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 1726 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 1730 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 1726 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1183 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 6400 0.00% 0.00%
+system.ruby.Directory_Controller.GETX 1731 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1731 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 1727 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 1731 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 1727 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 1731 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 1727 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1185 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 6413 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 865 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 1730 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 1726 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 1726 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 727 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1731 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 1727 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 1727 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 728 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 730 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 273 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 456 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 5670 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 457 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 5683 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 592 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 1726 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 1726 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 1457 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 1727 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 1727 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1458 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 273 0.00% 0.00%
---------- End Simulation Statistics ----------
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:02
-gem5 executing on zizzer, pid 34003
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:56:12
+gem5 executing on phenom, pid 28101
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 35667500 because target called exit()
+Exiting @ tick 35682500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000036 # Number of seconds simulated
-sim_ticks 35667500 # Number of ticks simulated
-final_tick 35667500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 35682500 # Number of ticks simulated
+final_tick 35682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 102057 # Simulator instruction rate (inst/s)
-host_op_rate 102013 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 569174066 # Simulator tick rate (ticks/s)
-host_mem_usage 230332 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
+host_inst_rate 44587 # Simulator instruction rate (inst/s)
+host_op_rate 44581 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 248411942 # Simulator tick rate (ticks/s)
+host_mem_usage 226904 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+sim_insts 6403 # Number of instructions simulated
+sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 446 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 498829467 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 301450901 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 800280367 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 498829467 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 498829467 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 498829467 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 301450901 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 800280367 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 498619772 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 301324179 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 799943950 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 498619772 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 498619772 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 498619772 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 301324179 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 799943950 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_hits 1185 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.read_accesses 1192 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_hits 2050 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.dtb.data_accesses 2060 # DTB accesses
+system.cpu.itb.fetch_hits 6414 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.fetch_accesses 6431 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 71335 # number of cpu cycles simulated
+system.cpu.numCycles 71365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.committedInsts 6403 # Number of instructions committed
+system.cpu.committedOps 6403 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6329 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6329 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8297 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4575 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_mem_refs 2060 # number of memory refs
+system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 71335 # Number of busy cycles
+system.cpu.num_busy_cycles 71365 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1050 # Number of branches fetched
+system.cpu.Branches 1056 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.30% 0.30% # Class of executed instruction
-system.cpu.op_class::IntAlu 4320 67.50% 67.80% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.81% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.81% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1190 18.59% 86.44% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.56% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4331 67.53% 67.83% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 67.85% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 67.85% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.88% # Class of executed instruction
+system.cpu.op_class::MemRead 1192 18.59% 86.46% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.54% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6400 # Class of executed instruction
+system.cpu.op_class::total 6413 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 103.427155 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 103.763836 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 103.427155 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025251 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025251 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 103.763836 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4268 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4268 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
-system.cpu.dcache.overall_hits::total 1880 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits
+system.cpu.dcache.overall_hits::total 1882 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 10416000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 10416000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 10416000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.080169 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081951 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.081951 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 10248000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10248000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 10248000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 127.519931 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 127.232065 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 6135 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 21.989247 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 127.519931 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.062266 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.062266 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 127.232065 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.062125 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.062125 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.136230 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 13081 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 13081 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 6122 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 6122 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 6122 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 6122 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 6122 # number of overall hits
-system.cpu.icache.overall_hits::total 6122 # number of overall hits
+system.cpu.icache.tags.tag_accesses 13107 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 13107 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 6135 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 6135 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 6135 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 6135 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 6135 # number of overall hits
+system.cpu.icache.overall_hits::total 6135 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 17250500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 17250500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 17250500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 6401 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 6401 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 6401 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043587 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.043587 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 6414 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 6414 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 6414 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 6414 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 6414 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 6414 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043499 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.043499 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.043499 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.043499 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.043499 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.043499 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61829.749104 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61829.749104 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61829.749104 # average overall miss latency
system.cpu.icache.demand_mshr_miss_latency::total 16971500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16971500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 16971500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043499 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.043499 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043499 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.043499 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60829.749104 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60829.749104 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60829.749104 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60829.749104 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 183.843350 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 184.000496 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.517941 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 56.325409 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003892 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001719 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005610 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 127.230075 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 56.770421 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003883 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001732 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005615 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.membus.respLayer1.occupancy 2230000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 6.3 # Layer utilization (%)
+system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 13 2016 22:42:39
-gem5 started Mar 13 2016 22:47:14
-gem5 executing on phenom, pid 19880
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29859
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 22454000 # Number of ticks simulated
final_tick 22454000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 18374 # Simulator instruction rate (inst/s)
-host_op_rate 18373 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 82737910 # Simulator tick rate (ticks/s)
-host_mem_usage 226740 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
-sim_insts 4986 # Number of instructions simulated
-sim_ops 4986 # Number of ops (including micro ops) simulated
+host_inst_rate 22135 # Simulator instruction rate (inst/s)
+host_op_rate 22134 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 99411388 # Simulator tick rate (ticks/s)
+host_mem_usage 226732 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
+sim_insts 4999 # Number of instructions simulated
+sim_ops 4999 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
-system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 934889107 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 401888305 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1336777412 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 399038033 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1333927140 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 934889107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 934889107 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 934889107 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 401888305 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1336777412 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 469 # Number of read requests accepted
+system.physmem.bw_total::cpu.data 399038033 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1333927140 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 468 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 468 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 29952 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 29952 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.perBankRdBursts::11 20 # Per bank write bursts
system.physmem.perBankRdBursts::12 51 # Per bank write bursts
system.physmem.perBankRdBursts::13 29 # Per bank write bursts
-system.physmem.perBankRdBursts::14 78 # Per bank write bursts
+system.physmem.perBankRdBursts::14 77 # Per bank write bursts
system.physmem.perBankRdBursts::15 7 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 469 # Read request sizes (log2)
+system.physmem.readPktSize::6 468 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
-system.physmem.totQLat 4505500 # Total ticks spent queuing
-system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 264.077670 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 182.760997 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 252.156180 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 28 27.18% 27.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 32 31.07% 58.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 20 19.42% 77.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 9 8.74% 86.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 4 3.88% 90.29% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 1.94% 92.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1 0.97% 93.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 0.97% 94.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6 5.83% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation
+system.physmem.totQLat 4465750 # Total ticks spent queuing
+system.physmem.totMemAccLat 13240750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2340000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9542.20 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1336.78 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28292.20 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1333.93 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1336.78 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1333.93 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.44 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.42 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.42 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 355 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 75.85 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 47690.83 # Average gap between requests
-system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 47792.74 # Average gap between requests
+system.physmem.pageHitRate 75.85 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 9540945 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ)
-system.physmem_0.averagePower 784.279760 # Core power per rank (mW)
+system.physmem_0.totalEnergy 12417360 # Total energy per rank (pJ)
+system.physmem_0.averagePower 784.295595 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 13485750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 506520 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 276375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2160600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ)
-system.physmem_1.averagePower 934.618664 # Core power per rank (mW)
+system.physmem_1.totalEnergy 14777865 # Total energy per rank (pJ)
+system.physmem_1.averagePower 933.387968 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 2031 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 605 # Number of BTB hits
+system.cpu.branchPred.lookups 2026 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1358 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 403 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1632 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 603 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 36.948529 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 244 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.numCycles 44909 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered
+system.cpu.fetch.icacheStallCycles 8846 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12312 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2026 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing
-system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Cycles 4822 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 824 # Number of cycles fetch has spent squashing
+system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 254 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 14285 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.861883 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.130483 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11018 77.13% 77.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1489 10.42% 87.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 118 0.83% 88.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 170 1.19% 89.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 281 1.97% 91.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 100 0.70% 92.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 134 0.94% 93.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 151 1.06% 94.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 824 5.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.045225 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.274511 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
+system.cpu.fetch.rateDist::total 14285 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.045113 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.274154 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8398 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2675 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2714 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode
+system.cpu.decode.SquashCycles 372 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 164 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 11356 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles 372 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8537 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 540 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2675 # Number of cycles rename is running
+system.cpu.rename.RunCycles 2681 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 10925 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed
+system.cpu.rename.RenamedOperands 6515 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups
+system.cpu.rename.int_rename_lookups 12681 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 3223 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2297 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 8637 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 7943 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 3648 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1606 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 14285 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.556038 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.275658 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 10995 76.97% 76.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1332 9.32% 86.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 734 5.14% 91.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 438 3.07% 94.50% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 349 2.44% 96.94% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 14285 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 4723 59.46% 59.46% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2145 27.00% 86.55% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1068 13.45% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
-system.cpu.iq.rate 0.176735 # Inst issue rate
+system.cpu.iq.FU_type_0::total 7943 # Type of FU issued
+system.cpu.iq.rate 0.176869 # Inst issue rate
system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate 0.022158 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 30363 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 12303 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 7281 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 8117 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1162 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles 372 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 422 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions
+system.cpu.iew.iewDispatchedInsts 10138 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 138 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2297 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 7674 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2046 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 269 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1483 # number of nop insts executed
-system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1353 # Number of branches executed
+system.cpu.iew.exec_nop 1490 # number of nop insts executed
+system.cpu.iew.exec_refs 3099 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1356 # Number of branches executed
system.cpu.iew.exec_stores 1053 # Number of stores executed
-system.cpu.iew.exec_rate 0.170812 # Inst execution rate
-system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 2832 # num instructions producing a value
-system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.162083 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_rate 0.170879 # Inst execution rate
+system.cpu.iew.wb_sent 7358 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 7283 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 2837 # num instructions producing a value
+system.cpu.iew.wb_consumers 4202 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.162172 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.675155 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 4500 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 13494 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.417964 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.246672 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11340 84.04% 84.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 862 6.39% 90.43% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 508 3.76% 94.19% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 248 1.84% 96.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 152 1.13% 97.15% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 167 1.24% 98.39% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 61 0.45% 98.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 39 0.29% 99.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 117 0.87% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 5623 # Number of instructions committed
-system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 13494 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 5640 # Number of instructions committed
+system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 2033 # Number of memory references committed
-system.cpu.commit.loads 1132 # Number of loads committed
+system.cpu.commit.refs 2036 # Number of memory references committed
+system.cpu.commit.loads 1135 # Number of loads committed
system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 883 # Number of branches committed
+system.cpu.commit.branches 886 # Number of branches committed
system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 4942 # Number of committed integer instructions.
+system.cpu.commit.int_insts 4955 # Number of committed integer instructions.
system.cpu.commit.function_calls 85 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::No_OpClass 641 11.37% 11.37% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 2959 52.46% 63.83% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 2 0.04% 63.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.87% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
-system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 23467 # The number of ROB reads
-system.cpu.rob.rob_writes 21056 # The number of ROB writes
+system.cpu.commit.op_class_0::total 5640 # Class of committed instruction
+system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 23504 # The number of ROB reads
+system.cpu.rob.rob_writes 21078 # The number of ROB writes
system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 30648 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 4986 # Number of Instructions Simulated
-system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 9.007020 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 9.007020 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.111025 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.111025 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 10419 # number of integer regfile reads
-system.cpu.int_regfile_writes 5064 # number of integer regfile writes
+system.cpu.idleCycles 30624 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts 4999 # Number of Instructions Simulated
+system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 8.983597 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 8.983597 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.111314 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.111314 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 10422 # number of integer regfile reads
+system.cpu.int_regfile_writes 5065 # number of integer regfile writes
system.cpu.fp_regfile_reads 3 # number of floating regfile reads
system.cpu.fp_regfile_writes 1 # number of floating regfile writes
-system.cpu.misc_regfile_reads 158 # number of misc regfile reads
+system.cpu.misc_regfile_reads 160 # number of misc regfile reads
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 90.676519 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 90.103369 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2304 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 16.457143 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 90.676519 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.022138 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.022138 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 90.103369 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.021998 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021998 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 5766 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 5766 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits
-system.cpu.dcache.overall_hits::total 2302 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 2304 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2304 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2304 # number of overall hits
+system.cpu.dcache.overall_hits::total 2304 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 164 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 164 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
-system.cpu.dcache.overall_misses::total 510 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 509 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 509 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 509 # number of overall misses
+system.cpu.dcache.overall_misses::total 509 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11628500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11628500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 35643499 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 35643499 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 35643499 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 35643499 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2813 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2813 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2813 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2813 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085774 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085774 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.180946 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.180946 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.180946 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.180946 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70905.487805 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70905.487805 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 70026.520629 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 70026.520629 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 70026.520629 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7490000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7490000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11573499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11573499 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11573499 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11573499 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047071 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047071 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049769 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.049769 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049769 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.049769 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83222.222222 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82667.850000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 82667.850000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82667.850000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 82667.850000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 17 # number of replacements
-system.cpu.icache.tags.tagsinuse 156.413207 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 156.353975 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 1550 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 4.682779 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 156.413207 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.076374 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.076374 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 156.353975 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.076345 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.076345 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 4289 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits
-system.cpu.icache.overall_hits::total 1547 # number of overall hits
+system.cpu.icache.tags.tag_accesses 4295 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 4295 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 1550 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1550 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1550 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1550 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1550 # number of overall hits
+system.cpu.icache.overall_hits::total 1550 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
system.cpu.icache.overall_misses::total 432 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 32422500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 32422500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 32422500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 32422500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 32422500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 32422500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75052.083333 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75052.083333 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75052.083333 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75052.083333 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75052.083333 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32414500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32414500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 32414500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 32414500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32414500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32414500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217962 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.217962 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.217962 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.217962 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.217962 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.217962 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75033.564815 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75033.564815 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75033.564815 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75033.564815 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75033.564815 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75033.564815 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25904500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 25904500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25904500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 25904500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25904500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 25904500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78261.329305 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78261.329305 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78261.329305 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 78261.329305 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25897500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 25897500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25897500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 25897500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25897500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 25897500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167003 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.167003 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167003 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.167003 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78240.181269 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78240.181269 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78240.181269 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 78240.181269 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78240.181269 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 78240.181269 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 215.857139 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 215.242460 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 418 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.047847 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.337319 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 57.519820 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.278087 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 56.964373 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004830 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.006569 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 418 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012756 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 4372 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 4372 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 468 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
-system.cpu.l2cache.overall_misses::total 469 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses
+system.cpu.l2cache.overall_misses::total 468 # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25375000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 25375000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 25375000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 36837500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 25375000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 36837500 # number of overall miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25368000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 25368000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7352000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 7352000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 25368000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 11359500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 36727500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 25368000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 11359500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 36727500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 471 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 471 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.993631 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.993631 # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77362.804878 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77362.804878 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 78544.776119 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77362.804878 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 78544.776119 # average overall miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77341.463415 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77341.463415 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.888889 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.888889 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77341.463415 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81139.285714 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 78477.564103 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77341.463415 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81139.285714 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 78477.564103 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 468 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 468 # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22095000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22095000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22095000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 32147500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22095000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 32147500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22088000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22088000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6452000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6452000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22088000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9959500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 32047500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22088000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9959500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 32047500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.993631 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.993631 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67362.804878 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67362.804878 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67362.804878 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68544.776119 # average overall mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67341.463415 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67341.463415 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71688.888889 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71688.888889 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67341.463415 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71139.285714 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68477.564103 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67341.463415 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71139.285714 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68477.564103 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 421 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 959 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 31296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 472 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 471 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 472 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 471 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 261000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 419 # Transaction distribution
+system.membus.trans_dist::ReadResp 418 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
system.membus.trans_dist::ReadExResp 50 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadSharedReq 418 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 936 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 936 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 469 # Request fanout histogram
+system.membus.snoop_fanout::samples 468 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 468 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 469 # Request fanout histogram
-system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 468 # Request fanout histogram
+system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2487500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:13
-gem5 executing on zizzer, pid 60571
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29858
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 2812000 because target called exit()
+Exiting @ tick 2820500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2812000 # Number of ticks simulated
-final_tick 2812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2820500 # Number of ticks simulated
+final_tick 2820500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70039 # Simulator instruction rate (inst/s)
-host_op_rate 70020 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35000361 # Simulator tick rate (ticks/s)
-host_mem_usage 218484 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 42403 # Simulator instruction rate (inst/s)
+host_op_rate 42398 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21196256 # Simulator tick rate (ticks/s)
+host_mem_usage 214708 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 4289 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26789 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 4301 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26869 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.physmem.bytes_written::total 3601 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6757 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6777 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.physmem.num_writes::total 901 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 8001422475 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1525248933 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9526671408 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 8001422475 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 8001422475 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1280583215 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1280583215 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 8001422475 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2805832148 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 10807254623 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 8001418188 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1524906931 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 9526325120 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 8001418188 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 8001418188 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1276723985 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1276723985 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 8001418188 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2801630917 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 10803049105 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 5625 # number of cpu cycles simulated
+system.cpu.numCycles 5642 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5625 # Number of busy cycles
+system.cpu.num_busy_cycles 5642 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
-system.membus.trans_dist::ReadReq 6757 # Transaction distribution
-system.membus.trans_dist::ReadResp 6757 # Transaction distribution
+system.cpu.op_class::total 5642 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6777 # Transaction distribution
+system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11250 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15316 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22500 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7890 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11284 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4072 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15356 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 22568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7902 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7658 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734526 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441614 # Request fanout histogram
+system.membus.snoop_fanout::samples 7678 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734827 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441454 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2033 26.55% 26.55% # Request fanout histogram
-system.membus.snoop_fanout::1 5625 73.45% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2036 26.52% 26.52% # Request fanout histogram
+system.membus.snoop_fanout::1 5642 73.48% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 7658 # Request fanout histogram
+system.membus.snoop_fanout::total 7678 # Request fanout histogram
---------- End Simulation Statistics ----------
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:13
-gem5 executing on zizzer, pid 60577
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29860
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 100307 because target called exit()
+Exiting @ tick 100232 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000100 # Number of seconds simulated
-sim_ticks 100307 # Number of ticks simulated
-final_tick 100307 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 100232 # Number of ticks simulated
+final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 28982 # Simulator instruction rate (inst/s)
-host_op_rate 28978 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 516775 # Simulator tick rate (ticks/s)
-host_mem_usage 393304 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 20831 # Simulator instruction rate (inst/s)
+host_op_rate 20830 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 370097 # Simulator tick rate (ticks/s)
+host_mem_usage 389556 # Number of bytes of host memory used
+host_seconds 0.27 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory
-system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory
-system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory
-system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory
-system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory
-system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory
-system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory
-system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 937920584 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 937920584 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 935368419 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 935368419 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1873289003 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1873289003 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.readReqs 1470 # Number of read requests accepted
-system.mem_ctrls.writeReqs 1466 # Number of write requests accepted
-system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue
-system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 58560 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 35520 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 59456 # Total number of bytes written to DRAM
-system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side
-system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 555 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 516 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory
+system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory
+system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory
+system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory
+system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory
+system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory
+system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory
+system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.readReqs 1472 # Number of read requests accepted
+system.mem_ctrls.writeReqs 1468 # Number of write requests accepted
+system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue
+system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side
+system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side
+system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 84 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 243 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 97 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 46 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 113 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 44 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 160 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 9 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 12 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 83 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 239 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 97 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 47 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 117 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 44 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 176 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 11 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 100258 # Total gap between requests
+system.mem_ctrls.totGap 100183 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2)
-system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2)
+system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2)
system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
-system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 915 # What read queue length does an incoming req see
+system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2)
+system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 54 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 59 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 61 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 62 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 346 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 337.017341 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 221.831279 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 312.425842 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 75 21.68% 21.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 111 32.08% 53.76% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 54 15.61% 69.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 22 6.36% 75.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 14 4.05% 79.77% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 16 4.62% 84.39% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 11 3.18% 87.57% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 8 2.31% 89.88% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 35 10.12% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 346 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.982456 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.826931 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 2.722205 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.298246 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.275827 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.905635 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 51 89.47% 89.47% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 2 3.51% 92.98% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 12902 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 30287 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4575 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 14.10 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 12638 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 33.10 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 583.81 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 592.74 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 937.92 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 935.37 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 9.19 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.56 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.63 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 25.61 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 627 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 68.52 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 91.05 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 34.15 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.00 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1497600 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 1254528 # Energy for write commands per rank (pJ)
+system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 34.08 # Average gap between requests
+system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ)
system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 47014056 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 14974800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 71631624 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 764.543654 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 25717 # Time in different power states
+system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW)
+system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 71078 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states
system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1950480 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 1083600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 9197760 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 7713792 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ)
system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 63796680 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 253200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 90098232 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 961.642744 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 100 # Time in different power states
+system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW)
+system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states
system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 90486 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states
system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 100307 # number of cpu cycles simulated
+system.cpu.numCycles 100232 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 100307 # Number of busy cycles
+system.cpu.num_busy_cycles 100232 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
+system.cpu.op_class::total 5642 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
-system.ruby.delayHist::samples 2936 # delay histogram for all message
-system.ruby.delayHist | 2936 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
-system.ruby.delayHist::total 2936 # delay histogram for all message
+system.ruby.delayHist::samples 2940 # delay histogram for all message
+system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::total 2940 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
-system.ruby.outstanding_req_hist_seqr::samples 7659
+system.ruby.outstanding_req_hist_seqr::samples 7679
system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
-system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.outstanding_req_hist_seqr::total 7659
+system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.outstanding_req_hist_seqr::total 7679
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
-system.ruby.latency_hist_seqr::samples 7658
-system.ruby.latency_hist_seqr::mean 12.098329
-system.ruby.latency_hist_seqr::gmean 2.138684
-system.ruby.latency_hist_seqr::stdev 27.490264
-system.ruby.latency_hist_seqr | 7348 95.95% 95.95% | 251 3.28% 99.23% | 42 0.55% 99.78% | 5 0.07% 99.84% | 10 0.13% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.latency_hist_seqr::total 7658
+system.ruby.latency_hist_seqr::samples 7678
+system.ruby.latency_hist_seqr::mean 12.054441
+system.ruby.latency_hist_seqr::gmean 2.136034
+system.ruby.latency_hist_seqr::stdev 27.599754
+system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::total 7678
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
-system.ruby.hit_latency_hist_seqr::samples 6188
+system.ruby.hit_latency_hist_seqr::samples 6206
system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
-system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.hit_latency_hist_seqr::total 6188
+system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::total 6206
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
-system.ruby.miss_latency_hist_seqr::samples 1470
-system.ruby.miss_latency_hist_seqr::mean 58.817007
-system.ruby.miss_latency_hist_seqr::gmean 52.469450
-system.ruby.miss_latency_hist_seqr::stdev 35.158300
-system.ruby.miss_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.miss_latency_hist_seqr::total 1470
-system.ruby.Directory.incomplete_times_seqr 1469
-system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 # Number of cache demand hits
-system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses
-system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses
+system.ruby.miss_latency_hist_seqr::samples 1472
+system.ruby.miss_latency_hist_seqr::mean 58.660326
+system.ruby.miss_latency_hist_seqr::gmean 52.389786
+system.ruby.miss_latency_hist_seqr::stdev 35.865583
+system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::total 1472
+system.ruby.Directory.incomplete_times_seqr 1471
+system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits
+system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses
+system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.percent_links_utilized 7.317535
-system.ruby.network.routers0.msg_count.Control::2 1470
-system.ruby.network.routers0.msg_count.Data::2 1466
-system.ruby.network.routers0.msg_count.Response_Data::4 1470
-system.ruby.network.routers0.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers0.msg_bytes.Control::2 11760
-system.ruby.network.routers0.msg_bytes.Data::2 105552
-system.ruby.network.routers0.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.routers1.percent_links_utilized 7.317535
-system.ruby.network.routers1.msg_count.Control::2 1470
-system.ruby.network.routers1.msg_count.Data::2 1466
-system.ruby.network.routers1.msg_count.Response_Data::4 1470
-system.ruby.network.routers1.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers1.msg_bytes.Control::2 11760
-system.ruby.network.routers1.msg_bytes.Data::2 105552
-system.ruby.network.routers1.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.routers2.percent_links_utilized 7.317535
-system.ruby.network.routers2.msg_count.Control::2 1470
-system.ruby.network.routers2.msg_count.Data::2 1466
-system.ruby.network.routers2.msg_count.Response_Data::4 1470
-system.ruby.network.routers2.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers2.msg_bytes.Control::2 11760
-system.ruby.network.routers2.msg_bytes.Data::2 105552
-system.ruby.network.routers2.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.msg_count.Control 4410
-system.ruby.network.msg_count.Data 4398
-system.ruby.network.msg_count.Response_Data 4410
-system.ruby.network.msg_count.Writeback_Control 4398
-system.ruby.network.msg_byte.Control 35280
-system.ruby.network.msg_byte.Data 316656
-system.ruby.network.msg_byte.Response_Data 317520
-system.ruby.network.msg_byte.Writeback_Control 35184
-system.ruby.network.routers0.throttle0.link_utilization 7.325511
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470
-system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.routers0.throttle1.link_utilization 7.309560
-system.ruby.network.routers0.throttle1.msg_count.Control::2 1470
-system.ruby.network.routers0.throttle1.msg_count.Data::2 1466
-system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760
-system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552
-system.ruby.network.routers1.throttle0.link_utilization 7.309560
-system.ruby.network.routers1.throttle0.msg_count.Control::2 1470
-system.ruby.network.routers1.throttle0.msg_count.Data::2 1466
-system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760
-system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552
-system.ruby.network.routers1.throttle1.link_utilization 7.325511
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.routers2.throttle0.link_utilization 7.325511
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728
-system.ruby.network.routers2.throttle1.link_utilization 7.309560
-system.ruby.network.routers2.throttle1.msg_count.Control::2 1470
-system.ruby.network.routers2.throttle1.msg_count.Data::2 1466
-system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760
-system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105552
+system.ruby.network.routers0.percent_links_utilized 7.332987
+system.ruby.network.routers0.msg_count.Control::2 1472
+system.ruby.network.routers0.msg_count.Data::2 1468
+system.ruby.network.routers0.msg_count.Response_Data::4 1472
+system.ruby.network.routers0.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers0.msg_bytes.Control::2 11776
+system.ruby.network.routers0.msg_bytes.Data::2 105696
+system.ruby.network.routers0.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers1.percent_links_utilized 7.332987
+system.ruby.network.routers1.msg_count.Control::2 1472
+system.ruby.network.routers1.msg_count.Data::2 1468
+system.ruby.network.routers1.msg_count.Response_Data::4 1472
+system.ruby.network.routers1.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers1.msg_bytes.Control::2 11776
+system.ruby.network.routers1.msg_bytes.Data::2 105696
+system.ruby.network.routers1.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers2.percent_links_utilized 7.332987
+system.ruby.network.routers2.msg_count.Control::2 1472
+system.ruby.network.routers2.msg_count.Data::2 1468
+system.ruby.network.routers2.msg_count.Response_Data::4 1472
+system.ruby.network.routers2.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers2.msg_bytes.Control::2 11776
+system.ruby.network.routers2.msg_bytes.Data::2 105696
+system.ruby.network.routers2.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.msg_count.Control 4416
+system.ruby.network.msg_count.Data 4404
+system.ruby.network.msg_count.Response_Data 4416
+system.ruby.network.msg_count.Writeback_Control 4404
+system.ruby.network.msg_byte.Control 35328
+system.ruby.network.msg_byte.Data 317088
+system.ruby.network.msg_byte.Response_Data 317952
+system.ruby.network.msg_byte.Writeback_Control 35232
+system.ruby.network.routers0.throttle0.link_utilization 7.340969
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472
+system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers0.throttle1.link_utilization 7.325006
+system.ruby.network.routers0.throttle1.msg_count.Control::2 1472
+system.ruby.network.routers0.throttle1.msg_count.Data::2 1468
+system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776
+system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696
+system.ruby.network.routers1.throttle0.link_utilization 7.325006
+system.ruby.network.routers1.throttle0.msg_count.Control::2 1472
+system.ruby.network.routers1.throttle0.msg_count.Data::2 1468
+system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776
+system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696
+system.ruby.network.routers1.throttle1.link_utilization 7.340969
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers2.throttle0.link_utilization 7.340969
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472
+system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984
+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744
+system.ruby.network.routers2.throttle1.link_utilization 7.325006
+system.ruby.network.routers2.throttle1.msg_count.Control::2 1472
+system.ruby.network.routers2.throttle1.msg_count.Data::2 1468
+system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776
+system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::samples 1470 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 1470 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::total 1470 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
-system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
-system.ruby.LD.latency_hist_seqr::samples 1132
-system.ruby.LD.latency_hist_seqr::mean 33.356007
-system.ruby.LD.latency_hist_seqr::gmean 9.984943
-system.ruby.LD.latency_hist_seqr::stdev 37.413851
-system.ruby.LD.latency_hist_seqr | 465 41.08% 41.08% | 534 47.17% 88.25% | 104 9.19% 97.44% | 3 0.27% 97.70% | 10 0.88% 98.59% | 8 0.71% 99.29% | 4 0.35% 99.65% | 0 0.00% 99.65% | 0 0.00% 99.65% | 4 0.35% 100.00%
-system.ruby.LD.latency_hist_seqr::total 1132
+system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
+system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
+system.ruby.LD.latency_hist_seqr::samples 1135
+system.ruby.LD.latency_hist_seqr::mean 33.525991
+system.ruby.LD.latency_hist_seqr::gmean 10.018050
+system.ruby.LD.latency_hist_seqr::stdev 38.312060
+system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::total 1135
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
-system.ruby.LD.hit_latency_hist_seqr::samples 465
+system.ruby.LD.hit_latency_hist_seqr::samples 466
system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
-system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.LD.hit_latency_hist_seqr::total 465
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
-system.ruby.LD.miss_latency_hist_seqr::samples 667
-system.ruby.LD.miss_latency_hist_seqr::mean 55.913043
-system.ruby.LD.miss_latency_hist_seqr::gmean 49.663893
-system.ruby.LD.miss_latency_hist_seqr::stdev 33.713440
-system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
-system.ruby.LD.miss_latency_hist_seqr::total 667
-system.ruby.ST.latency_hist_seqr::bucket_size 32
-system.ruby.ST.latency_hist_seqr::max_bucket 319
+system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::total 466
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
+system.ruby.LD.miss_latency_hist_seqr::samples 669
+system.ruby.LD.miss_latency_hist_seqr::mean 56.182362
+system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907
+system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867
+system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::total 669
+system.ruby.ST.latency_hist_seqr::bucket_size 64
+system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 901
-system.ruby.ST.latency_hist_seqr::mean 12.753607
-system.ruby.ST.latency_hist_seqr::gmean 2.500911
-system.ruby.ST.latency_hist_seqr::stdev 24.939066
-system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 184 20.42% 96.34% | 28 3.11% 99.45% | 1 0.11% 99.56% | 1 0.11% 99.67% | 2 0.22% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 13.069922
+system.ruby.ST.latency_hist_seqr::gmean 2.509564
+system.ruby.ST.latency_hist_seqr::stdev 28.093942
+system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 901
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 684
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 217
-system.ruby.ST.miss_latency_hist_seqr::mean 49.801843
-system.ruby.ST.miss_latency_hist_seqr::gmean 44.971096
-system.ruby.ST.miss_latency_hist_seqr::stdev 27.840525
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 51.115207
+system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625
+system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021
+system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 217
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
-system.ruby.IFETCH.latency_hist_seqr::samples 5625
-system.ruby.IFETCH.latency_hist_seqr::mean 7.715378
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.529642
-system.ruby.IFETCH.latency_hist_seqr::stdev 23.186705
-system.ruby.IFETCH.latency_hist_seqr | 5481 97.44% 97.44% | 115 2.04% 99.48% | 21 0.37% 99.86% | 1 0.02% 99.88% | 5 0.09% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.latency_hist_seqr::total 5625
+system.ruby.IFETCH.latency_hist_seqr::samples 5642
+system.ruby.IFETCH.latency_hist_seqr::mean 7.572847
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495
+system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339
+system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::total 5642
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
-system.ruby.IFETCH.hit_latency_hist_seqr::samples 5039
+system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056
system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
-system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.IFETCH.hit_latency_hist_seqr::total 5039
+system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.hit_latency_hist_seqr::total 5056
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 586
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.460751
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.138692
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.945521
-system.ruby.IFETCH.miss_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051
+system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 586
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
-system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1470
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.817007
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.469450
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.158300
-system.ruby.Directory.miss_mach_latency_hist_seqr | 1160 78.91% 78.91% | 251 17.07% 95.99% | 42 2.86% 98.84% | 5 0.34% 99.18% | 10 0.68% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.Directory.miss_mach_latency_hist_seqr::total 1470
+system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583
+system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 667
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.913043
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.663893
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 33.713440
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 534 80.06% 80.06% | 104 15.59% 95.65% | 3 0.45% 96.10% | 10 1.50% 97.60% | 8 1.20% 98.80% | 4 0.60% 99.40% | 0 0.00% 99.40% | 0 0.00% 99.40% | 4 0.60% 100.00%
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 667
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.801843
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.971096
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.840525
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 184 84.79% 84.79% | 28 12.90% 97.70% | 1 0.46% 98.16% | 1 0.46% 98.62% | 2 0.92% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.460751
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.138692
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.945521
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 442 75.43% 75.43% | 115 19.62% 95.05% | 21 3.58% 98.63% | 1 0.17% 98.81% | 5 0.85% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586
-system.ruby.Directory_Controller.GETX 1470 0.00% 0.00%
-system.ruby.Directory_Controller.PUTX 1466 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Data 1470 0.00% 0.00%
-system.ruby.Directory_Controller.Memory_Ack 1466 0.00% 0.00%
-system.ruby.Directory_Controller.I.GETX 1470 0.00% 0.00%
-system.ruby.Directory_Controller.M.PUTX 1466 0.00% 0.00%
-system.ruby.Directory_Controller.IM.Memory_Data 1470 0.00% 0.00%
-system.ruby.Directory_Controller.MI.Memory_Ack 1466 0.00% 0.00%
-system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00%
-system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00%
+system.ruby.Directory_Controller.GETX 1472 0.00% 0.00%
+system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00%
+system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00%
+system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00%
+system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00%
+system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00%
+system.ruby.Directory_Controller.MI.Memory_Ack 1468 0.00% 0.00%
+system.ruby.L1Cache_Controller.Load 1135 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 5642 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 901 0.00% 0.00%
-system.ruby.L1Cache_Controller.Data 1470 0.00% 0.00%
-system.ruby.L1Cache_Controller.Replacement 1466 0.00% 0.00%
-system.ruby.L1Cache_Controller.Writeback_Ack 1466 0.00% 0.00%
-system.ruby.L1Cache_Controller.I.Load 667 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1472 0.00% 0.00%
+system.ruby.L1Cache_Controller.Replacement 1468 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 1468 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 669 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Ifetch 586 0.00% 0.00%
system.ruby.L1Cache_Controller.I.Store 217 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Load 465 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 5039 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 466 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 5056 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 684 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Replacement 1466 0.00% 0.00%
-system.ruby.L1Cache_Controller.MI.Writeback_Ack 1466 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Data 1253 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Replacement 1468 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack 1468 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1255 0.00% 0.00%
system.ruby.L1Cache_Controller.IM.Data 217 0.00% 0.00%
---------- End Simulation Statistics ----------
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
+executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
kvmInSE=false
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:13
-gem5 executing on zizzer, pid 60580
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29861
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 33912500 because target called exit()
+Exiting @ tick 33932500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33912500 # Number of ticks simulated
-final_tick 33912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 33932500 # Number of ticks simulated
+final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109628 # Simulator instruction rate (inst/s)
-host_op_rate 109584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 660533411 # Simulator tick rate (ticks/s)
-host_mem_usage 228304 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 42153 # Simulator instruction rate (inst/s)
+host_op_rate 42149 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 253513577 # Simulator tick rate (ticks/s)
+host_mem_usage 224784 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory
system.physmem.num_reads::total 430 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 552952451 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 258547733 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 811500184 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 552952451 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 552952451 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 552952451 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 258547733 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 811500184 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 67825 # number of cpu cycles simulated
+system.cpu.numCycles 67865 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 67825 # Number of busy cycles
+system.cpu.num_busy_cycles 67865 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
+system.cpu.op_class::total 5642 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.067027 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 86.067027 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.021012 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.021012 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
-system.cpu.dcache.overall_hits::total 1896 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
+system.cpu.dcache.overall_hits::total 1899 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13 # number of replacements
-system.cpu.icache.tags.tagsinuse 129.022312 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 129.022312 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.062999 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.062999 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11547 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits
-system.cpu.icache.overall_hits::total 5331 # number of overall hits
+system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 11581 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits
+system.cpu.icache.overall_hits::total 5348 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 183.581605 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.156658 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 53.424948 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003972 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005602 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 13 2016 22:43:13
-gem5 started Mar 13 2016 22:49:02
-gem5 executing on phenom, pid 19910
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:58:29
+gem5 executing on phenom, pid 28223
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
Global frequency set at 1000000000000 ticks per second
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 24832500 because target called exit()
+Exiting @ tick 24794500 because target called exit()
---------- Begin Simulation Statistics ----------
sim_seconds 0.000025 # Number of seconds simulated
-sim_ticks 24832500 # Number of ticks simulated
-final_tick 24832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 24794500 # Number of ticks simulated
+final_tick 24794500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 23208 # Simulator instruction rate (inst/s)
-host_op_rate 23207 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45219113 # Simulator tick rate (ticks/s)
-host_mem_usage 229684 # Number of bytes of host memory used
-host_seconds 0.55 # Real time elapsed on the host
-sim_insts 12744 # Number of instructions simulated
-sim_ops 12744 # Number of ops (including micro ops) simulated
+host_inst_rate 50796 # Simulator instruction rate (inst/s)
+host_op_rate 50792 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 98611945 # Simulator tick rate (ticks/s)
+host_mem_usage 229596 # Number of bytes of host memory used
+host_seconds 0.25 # Real time elapsed on the host
+sim_insts 12770 # Number of instructions simulated
+sim_ops 12770 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 40448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 22016 # Number of bytes read from this memory
-system.physmem.bytes_read::total 62464 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 40448 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 40448 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 632 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 344 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 976 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1628833182 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 886580087 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2515413269 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1628833182 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1628833182 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1628833182 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 886580087 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2515413269 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 976 # Number of read requests accepted
+system.physmem.bytes_read::cpu.inst 40320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 22080 # Number of bytes read from this memory
+system.physmem.bytes_read::total 62400 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 40320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 40320 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 630 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 345 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 975 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1626167094 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 890520075 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2516687169 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1626167094 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1626167094 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1626167094 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 890520075 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2516687169 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 975 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 976 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 62464 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 62464 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 84 # Per bank write bursts
-system.physmem.perBankRdBursts::1 152 # Per bank write bursts
+system.physmem.perBankRdBursts::0 85 # Per bank write bursts
+system.physmem.perBankRdBursts::1 151 # Per bank write bursts
system.physmem.perBankRdBursts::2 78 # Per bank write bursts
system.physmem.perBankRdBursts::3 59 # Per bank write bursts
-system.physmem.perBankRdBursts::4 88 # Per bank write bursts
-system.physmem.perBankRdBursts::5 48 # Per bank write bursts
-system.physmem.perBankRdBursts::6 33 # Per bank write bursts
+system.physmem.perBankRdBursts::4 86 # Per bank write bursts
+system.physmem.perBankRdBursts::5 49 # Per bank write bursts
+system.physmem.perBankRdBursts::6 32 # Per bank write bursts
system.physmem.perBankRdBursts::7 50 # Per bank write bursts
-system.physmem.perBankRdBursts::8 42 # Per bank write bursts
+system.physmem.perBankRdBursts::8 43 # Per bank write bursts
system.physmem.perBankRdBursts::9 39 # Per bank write bursts
system.physmem.perBankRdBursts::10 29 # Per bank write bursts
system.physmem.perBankRdBursts::11 34 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 24688000 # Total gap between requests
+system.physmem.totGap 24650000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 976 # Read request sizes (log2)
+system.physmem.readPktSize::6 975 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 321 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 209 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 78 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 354 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 330 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 71 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 217 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 280.184332 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 175.894103 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 284.655938 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 78 35.94% 35.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 61 28.11% 64.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 19 8.76% 72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 5.07% 77.88% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 14 6.45% 84.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 13 5.99% 90.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 1.84% 92.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 6 2.76% 94.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 11 5.07% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 217 # Bytes accessed per row activation
-system.physmem.totQLat 12728500 # Total ticks spent queuing
-system.physmem.totMemAccLat 31028500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4880000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13041.50 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 215 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 283.088372 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.093050 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 284.959526 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 71 33.02% 33.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 62 28.84% 61.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 23 10.70% 72.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 14 6.51% 79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 10 4.65% 83.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 14 6.51% 90.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 5 2.33% 92.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3 1.40% 93.95% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 13 6.05% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 215 # Bytes accessed per row activation
+system.physmem.totQLat 13049000 # Total ticks spent queuing
+system.physmem.totMemAccLat 31330250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13383.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31791.50 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2515.41 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 32133.59 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2516.69 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2515.41 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2516.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 19.65 # Data bus utilization in percentage
-system.physmem.busUtilRead 19.65 # Data bus utilization in percentage for reads
+system.physmem.busUtil 19.66 # Data bus utilization in percentage
+system.physmem.busUtilRead 19.66 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 2.42 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 749 # Number of row buffer hits during reads
+system.physmem.readRowHits 751 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.74 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 25295.08 # Average gap between requests
-system.physmem.pageHitRate 76.74 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 892080 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 486750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4516200 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 25282.05 # Average gap between requests
+system.physmem.pageHitRate 77.03 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4531800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ)
+system.physmem_0.actBackEnergy 16120170 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 23568270 # Total energy per rank (pJ)
-system.physmem_0.averagePower 997.862715 # Core power per rank (mW)
+system.physmem_0.totalEnergy 23622915 # Total energy per rank (pJ)
+system.physmem_0.averagePower 998.485338 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 22869500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 718200 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 391875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2847000 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2854800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 15524235 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 557250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 21564240 # Total energy per rank (pJ)
-system.physmem_1.averagePower 912.772063 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 830500 # Time in different power states
+system.physmem_1.actBackEnergy 15614010 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 495000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 21576195 # Total energy per rank (pJ)
+system.physmem_1.averagePower 912.216256 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 727500 # Time in different power states
system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 22027750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 22158250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 6978 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3979 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1366 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 5343 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 988 # Number of BTB hits
+system.cpu.branchPred.lookups 6577 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3752 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1243 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4859 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 1038 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 18.491484 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1115 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 21.362420 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1078 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 78 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4756 # DTB read hits
-system.cpu.dtb.read_misses 94 # DTB read misses
+system.cpu.dtb.read_hits 4547 # DTB read hits
+system.cpu.dtb.read_misses 85 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4850 # DTB read accesses
-system.cpu.dtb.write_hits 2093 # DTB write hits
+system.cpu.dtb.read_accesses 4632 # DTB read accesses
+system.cpu.dtb.write_hits 2078 # DTB write hits
system.cpu.dtb.write_misses 69 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2162 # DTB write accesses
-system.cpu.dtb.data_hits 6849 # DTB hits
-system.cpu.dtb.data_misses 163 # DTB misses
+system.cpu.dtb.write_accesses 2147 # DTB write accesses
+system.cpu.dtb.data_hits 6625 # DTB hits
+system.cpu.dtb.data_misses 154 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 7012 # DTB accesses
-system.cpu.itb.fetch_hits 5404 # ITB hits
-system.cpu.itb.fetch_misses 57 # ITB misses
+system.cpu.dtb.data_accesses 6779 # DTB accesses
+system.cpu.itb.fetch_hits 5175 # ITB hits
+system.cpu.itb.fetch_misses 51 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 5461 # ITB accesses
+system.cpu.itb.fetch_accesses 5226 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload0.num_syscalls 17 # Number of system calls
system.cpu.workload1.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 49666 # number of cpu cycles simulated
+system.cpu.numCycles 49590 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 1235 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 39551 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 6978 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2103 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 10833 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1446 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 5404 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 838 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 27534 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.436442 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.801385 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 1137 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 37512 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 6577 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 2116 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 11769 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1328 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.CacheLines 5175 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 779 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 28288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.326075 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.708941 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 20751 75.37% 75.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 584 2.12% 77.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 426 1.55% 79.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 584 2.12% 81.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 571 2.07% 83.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 441 1.60% 84.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 491 1.78% 86.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 560 2.03% 88.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3126 11.35% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 21788 77.02% 77.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 562 1.99% 79.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 445 1.57% 80.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 567 2.00% 82.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 586 2.07% 84.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 389 1.38% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 492 1.74% 87.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 554 1.96% 89.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2905 10.27% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 27534 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.140499 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.796340 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 37297 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 10659 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5112 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 614 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1127 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 528 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 328 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 32206 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 725 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1127 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37872 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 4968 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1226 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5150 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4466 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 30281 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 78 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 324 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 847 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 3132 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 22821 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 37713 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 37695 # Number of integer rename lookups
+system.cpu.fetch.rateDist::total 28288 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.132628 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.756443 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 38487 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 11291 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 4912 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 546 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1060 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 470 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 278 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 30785 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 643 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1060 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 39027 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 4538 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 1512 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 4932 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 5227 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 29058 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 481 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 927 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 3808 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 21804 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 36221 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 36203 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 13681 # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 12650 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 60 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 48 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 2263 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1407 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2862 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1462 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 2 # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 27015 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 22338 # Number of instructions issued
+system.cpu.rename.skidInsts 2095 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2679 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1390 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads 2734 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1411 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 25901 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 21580 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 14320 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 8141 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 27534 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.811288 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.520707 # Number of insts issued each cycle
+system.cpu.iq.iqSquashedInstsExamined 13182 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 7478 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 28288 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.762868 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.484406 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 19179 69.66% 69.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 2638 9.58% 79.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1919 6.97% 86.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 1327 4.82% 91.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1227 4.46% 95.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 711 2.58% 98.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 354 1.29% 99.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 138 0.50% 99.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 41 0.15% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 20144 71.21% 71.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 2630 9.30% 80.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 1862 6.58% 87.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 1311 4.63% 91.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 1169 4.13% 95.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 655 2.32% 98.17% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 329 1.16% 99.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 136 0.48% 99.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 52 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 27534 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 28288 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 32 9.64% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 217 65.36% 75.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 83 25.00% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 37 11.97% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 189 61.17% 73.14% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 83 26.86% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7321 66.01% 66.03% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.06% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2641 23.81% 89.87% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1123 10.13% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7104 66.24% 66.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.27% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.27% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2483 23.15% 89.44% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1132 10.56% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 11090 # Type of FU issued
+system.cpu.iq.FU_type_0::total 10724 # Type of FU issued
system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7446 66.20% 66.22% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.23% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.24% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2645 23.52% 89.76% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1152 10.24% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu 7199 66.31% 66.33% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.34% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.34% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.36% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead 2532 23.32% 89.68% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite 1120 10.32% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 11248 # Type of FU issued
-system.cpu.iq.FU_type::total 22338 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.449764 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 166 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 166 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 332 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.007431 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.007431 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.014863 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 72630 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 41400 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19613 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_1::total 10856 # Type of FU issued
+system.cpu.iq.FU_type::total 21580 0.00% 0.00% # Type of FU issued
+system.cpu.iq.rate 0.435168 # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0 153 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1 156 # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total 309 # FU busy when requested
+system.cpu.iq.fu_busy_rate::0 0.007090 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1 0.007229 # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total 0.014319 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 71845 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 39156 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 19068 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 22644 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 21863 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1651 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 542 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1494 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 525 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 309 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 73 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.cacheBlocked 275 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.forwLoads 81 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1679 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 597 # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads 1549 # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation 25 # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores 546 # Number of stores squashed
system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 327 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread1.cacheBlocked 273 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1127 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2708 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 614 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 27211 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 237 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5696 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2869 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 589 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 37 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 160 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1089 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 21052 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2447 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2411 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4858 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1286 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1060 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 2492 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 405 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 26102 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 214 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 5413 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 2801 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 43 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 158 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1006 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1164 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 20390 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0 2303 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1 2335 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total 4638 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp::0 0 # number of swp insts executed
system.cpu.iew.exec_swp::1 0 # number of swp insts executed
system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 74 # number of nop insts executed
-system.cpu.iew.exec_nop::1 72 # number of nop insts executed
-system.cpu.iew.exec_nop::total 146 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3514 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3522 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 7036 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1644 # Number of branches executed
-system.cpu.iew.exec_branches::1 1639 # Number of branches executed
-system.cpu.iew.exec_branches::total 3283 # Number of branches executed
-system.cpu.iew.exec_stores::0 1067 # Number of stores executed
-system.cpu.iew.exec_stores::1 1111 # Number of stores executed
-system.cpu.iew.exec_stores::total 2178 # Number of stores executed
-system.cpu.iew.exec_rate 0.423871 # Inst execution rate
-system.cpu.iew.wb_sent::0 9939 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 10068 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 20007 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9740 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9893 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19633 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 5189 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5256 # num instructions producing a value
-system.cpu.iew.wb_producers::total 10445 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6868 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6926 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13794 # num instructions consuming a value
-system.cpu.iew.wb_rate::0 0.196110 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.199191 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.395301 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.755533 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.758880 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.757213 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 14447 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop::0 75 # number of nop insts executed
+system.cpu.iew.exec_nop::1 74 # number of nop insts executed
+system.cpu.iew.exec_nop::total 149 # number of nop insts executed
+system.cpu.iew.exec_refs::0 3395 # number of memory reference insts executed
+system.cpu.iew.exec_refs::1 3403 # number of memory reference insts executed
+system.cpu.iew.exec_refs::total 6798 # number of memory reference insts executed
+system.cpu.iew.exec_branches::0 1585 # Number of branches executed
+system.cpu.iew.exec_branches::1 1614 # Number of branches executed
+system.cpu.iew.exec_branches::total 3199 # Number of branches executed
+system.cpu.iew.exec_stores::0 1092 # Number of stores executed
+system.cpu.iew.exec_stores::1 1068 # Number of stores executed
+system.cpu.iew.exec_stores::total 2160 # Number of stores executed
+system.cpu.iew.exec_rate 0.411172 # Inst execution rate
+system.cpu.iew.wb_sent::0 9687 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1 9764 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total 19451 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0 9532 # cumulative count of insts written-back
+system.cpu.iew.wb_count::1 9556 # cumulative count of insts written-back
+system.cpu.iew.wb_count::total 19088 # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0 5025 # num instructions producing a value
+system.cpu.iew.wb_producers::1 5077 # num instructions producing a value
+system.cpu.iew.wb_producers::total 10102 # num instructions producing a value
+system.cpu.iew.wb_consumers::0 6671 # num instructions consuming a value
+system.cpu.iew.wb_consumers::1 6701 # num instructions consuming a value
+system.cpu.iew.wb_consumers::total 13372 # num instructions consuming a value
+system.cpu.iew.wb_rate::0 0.192216 # insts written-back per cycle
+system.cpu.iew.wb_rate::1 0.192700 # insts written-back per cycle
+system.cpu.iew.wb_rate::total 0.384916 # insts written-back per cycle
+system.cpu.iew.wb_fanout::0 0.753260 # average fanout of values written-back
+system.cpu.iew.wb_fanout::1 0.757648 # average fanout of values written-back
+system.cpu.iew.wb_fanout::total 0.755459 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 13275 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1048 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 27467 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465213 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.343088 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 976 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 28256 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.453143 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.335890 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 22438 81.69% 81.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 2371 8.63% 90.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 1089 3.96% 94.29% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 414 1.51% 95.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 277 1.01% 96.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 199 0.72% 97.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 197 0.72% 98.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 154 0.56% 98.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 328 1.19% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 23155 81.95% 81.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 2552 9.03% 90.98% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 1012 3.58% 94.56% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 380 1.34% 95.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 269 0.95% 96.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 177 0.63% 97.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 194 0.69% 98.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 173 0.61% 98.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 344 1.22% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 27467 # Number of insts commited each cycle
-system.cpu.commit.committedInsts::0 6389 # Number of instructions committed
-system.cpu.commit.committedInsts::1 6389 # Number of instructions committed
-system.cpu.commit.committedInsts::total 12778 # Number of instructions committed
-system.cpu.commit.committedOps::0 6389 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1 6389 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::total 12778 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 28256 # Number of insts commited each cycle
+system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
+system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
+system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
+system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
-system.cpu.commit.refs::0 2048 # Number of memory references committed
-system.cpu.commit.refs::1 2048 # Number of memory references committed
-system.cpu.commit.refs::total 4096 # Number of memory references committed
-system.cpu.commit.loads::0 1183 # Number of loads committed
-system.cpu.commit.loads::1 1183 # Number of loads committed
-system.cpu.commit.loads::total 2366 # Number of loads committed
+system.cpu.commit.refs::0 2050 # Number of memory references committed
+system.cpu.commit.refs::1 2050 # Number of memory references committed
+system.cpu.commit.refs::total 4100 # Number of memory references committed
+system.cpu.commit.loads::0 1185 # Number of loads committed
+system.cpu.commit.loads::1 1185 # Number of loads committed
+system.cpu.commit.loads::total 2370 # Number of loads committed
system.cpu.commit.membars::0 0 # Number of memory barriers committed
system.cpu.commit.membars::1 0 # Number of memory barriers committed
system.cpu.commit.membars::total 0 # Number of memory barriers committed
-system.cpu.commit.branches::0 1050 # Number of branches committed
-system.cpu.commit.branches::1 1050 # Number of branches committed
-system.cpu.commit.branches::total 2100 # Number of branches committed
+system.cpu.commit.branches::0 1056 # Number of branches committed
+system.cpu.commit.branches::1 1056 # Number of branches committed
+system.cpu.commit.branches::total 2112 # Number of branches committed
system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
-system.cpu.commit.int_insts::0 6307 # Number of committed integer instructions.
-system.cpu.commit.int_insts::1 6307 # Number of committed integer instructions.
-system.cpu.commit.int_insts::total 12614 # Number of committed integer instructions.
+system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
+system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
+system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
system.cpu.commit.function_calls::0 127 # Number of function calls committed.
system.cpu.commit.function_calls::1 127 # Number of function calls committed.
system.cpu.commit.function_calls::total 254 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
+system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
-system.cpu.commit.op_class_1::IntAlu 4319 67.60% 67.90% # Class of committed instruction
-system.cpu.commit.op_class_1::IntMult 1 0.02% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.91% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction
-system.cpu.commit.op_class_1::MemRead 1183 18.52% 86.46% # Class of committed instruction
-system.cpu.commit.op_class_1::MemWrite 865 13.54% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
+system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
+system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction
+system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
-system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 328 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 129836 # The number of ROB reads
-system.cpu.rob.rob_writes 57114 # The number of ROB writes
-system.cpu.timesIdled 383 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 22132 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0 6372 # Number of Instructions Simulated
-system.cpu.committedInsts::1 6372 # Number of Instructions Simulated
-system.cpu.committedInsts::total 12744 # Number of Instructions Simulated
-system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.794413 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.794413 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.897207 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.128297 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.128297 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.256594 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 26493 # number of integer regfile reads
-system.cpu.int_regfile_writes 14992 # number of integer regfile writes
+system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
+system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
+system.cpu.commit.bw_lim_events 344 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 128366 # The number of ROB reads
+system.cpu.rob.rob_writes 54620 # The number of ROB writes
+system.cpu.timesIdled 375 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 21302 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
+system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
+system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
+system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi::0 7.766641 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 7.766641 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.883320 # CPI: Total CPI of All Threads
+system.cpu.ipc::0 0.128756 # IPC: Instructions Per Cycle
+system.cpu.ipc::1 0.128756 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.257512 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 25695 # number of integer regfile reads
+system.cpu.int_regfile_writes 14528 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.fp_regfile_writes 4 # number of floating regfile writes
system.cpu.misc_regfile_reads 2 # number of misc regfile reads
system.cpu.dcache.tags.replacements::0 0 # number of replacements
system.cpu.dcache.tags.replacements::1 0 # number of replacements
system.cpu.dcache.tags.replacements::total 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 212.222617 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 4769 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 344 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.863372 # Average number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 213.419877 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 4643 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 345 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.457971 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 212.222617 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.051812 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.051812 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_blocks::cpu.data 213.419877 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.052104 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.052104 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.083984 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 11936 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 11936 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 3748 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3748 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4769 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4769 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4769 # number of overall hits
-system.cpu.dcache.overall_hits::total 4769 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses
-system.cpu.dcache.overall_misses::total 1027 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 24395500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 24395500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 50809414 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 50809414 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 75204914 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 75204914 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 75204914 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 75204914 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 4066 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 4066 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.084229 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 11689 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 11689 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 3618 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 3618 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1025 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1025 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 4643 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 4643 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 4643 # number of overall hits
+system.cpu.dcache.overall_hits::total 4643 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 324 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 324 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 705 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 705 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1029 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1029 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1029 # number of overall misses
+system.cpu.dcache.overall_misses::total 1029 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 25567500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 25567500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 52147927 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 52147927 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 77715427 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 77715427 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 77715427 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 77715427 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 3942 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 3942 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5796 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5796 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5796 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 5796 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078210 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.078210 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.177191 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.177191 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.177191 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.177191 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76715.408805 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 76715.408805 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71663.489422 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 71663.489422 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73227.764362 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 73227.764362 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73227.764362 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 5829 # number of cycles access was blocked
+system.cpu.dcache.demand_accesses::cpu.data 5672 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 5672 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 5672 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 5672 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082192 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.082192 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.407514 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.407514 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.181417 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.181417 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.181417 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.181417 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78912.037037 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 78912.037037 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73968.690780 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 73968.690780 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 75525.196307 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 75525.196307 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 75525.196307 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 5306 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 135 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 120 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.177778 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.216667 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 120 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 198 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 198 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 344 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17299000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17299000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12670989 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 12670989 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29969989 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 29969989 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29969989 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 29969989 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048697 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048697 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.059351 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059351 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.059351 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87368.686869 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87368.686869 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86787.595890 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86787.595890 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87122.061047 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 87122.061047 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 123 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 561 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 561 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 201 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17683500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17683500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12260990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 12260990 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29944490 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 29944490 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29944490 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 29944490 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050989 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050989 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060825 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.060825 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060825 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.060825 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87977.611940 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87977.611940 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85145.763889 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85145.763889 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86795.623188 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 86795.623188 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements::0 8 # number of replacements
system.cpu.icache.tags.replacements::1 0 # number of replacements
system.cpu.icache.tags.replacements::total 8 # number of replacements
-system.cpu.icache.tags.tagsinuse 317.014953 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 4463 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 634 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 7.039432 # Average number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 317.233633 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 4245 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 632 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 6.716772 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 317.014953 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.154792 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.154792 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 626 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.305664 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11430 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11430 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 4463 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 4463 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 4463 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 4463 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 4463 # number of overall hits
-system.cpu.icache.overall_hits::total 4463 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 935 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 935 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 935 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 935 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 935 # number of overall misses
-system.cpu.icache.overall_misses::total 935 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 70147997 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 70147997 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 70147997 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 70147997 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 70147997 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 70147997 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5398 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5398 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5398 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5398 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5398 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5398 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.173212 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.173212 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.173212 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.173212 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.173212 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.173212 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75024.595722 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 75024.595722 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 75024.595722 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 75024.595722 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 75024.595722 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 3484 # number of cycles access was blocked
+system.cpu.icache.tags.occ_blocks::cpu.inst 317.233633 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.154899 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.154899 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024 624 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024 0.304688 # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses 10968 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 10968 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 4245 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4245 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4245 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4245 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4245 # number of overall hits
+system.cpu.icache.overall_hits::total 4245 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 923 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses
+system.cpu.icache.overall_misses::total 923 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 69430495 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 69430495 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 69430495 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 69430495 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 69430495 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 69430495 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5168 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5168 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5168 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5168 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5168 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5168 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.178599 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.178599 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.178599 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.178599 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.178599 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.178599 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75222.638137 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 75222.638137 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 75222.638137 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 75222.638137 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 75222.638137 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 3541 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 77 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 68 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 45.246753 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 52.073529 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks::writebacks 8 # number of writebacks
system.cpu.icache.writebacks::total 8 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 301 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 301 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 301 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 301 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 301 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 634 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 634 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 634 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 634 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 634 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 634 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51561499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 51561499 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51561499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 51561499 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51561499 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 51561499 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117451 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.117451 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117451 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.117451 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81327.285489 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81327.285489 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81327.285489 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 81327.285489 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 291 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 291 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 291 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 291 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 291 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 632 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 632 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 632 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 632 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51837997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 51837997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51837997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 51837997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51837997 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 51837997 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.122291 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.122291 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.122291 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.122291 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.122291 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.122291 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82022.147152 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82022.147152 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82022.147152 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82022.147152 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82022.147152 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82022.147152 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements::0 0 # number of replacements
system.cpu.l2cache.tags.replacements::1 0 # number of replacements
system.cpu.l2cache.tags.replacements::total 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 436.545027 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 439.367315 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 0.012048 # Average number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs 831 # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs 0.012034 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.712929 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 118.832098 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009696 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.003626 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.013322 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 326 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 504 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 8864 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 8864 # Number of data accesses
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.958632 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 121.408683 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009703 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.003705 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.013408 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 831 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 509 # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025360 # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses 8855 # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses 8855 # Number of data accesses
system.cpu.l2cache.WritebackClean_hits::writebacks 8 # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total 8 # number of WritebackClean hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
-system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
-system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 632 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadCleanReq_misses::total 632 # number of ReadCleanReq misses
-system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses
-system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 632 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 344 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 976 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 632 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 344 # number of overall misses
-system.cpu.l2cache.overall_misses::total 976 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12444500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 12444500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50583000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 50583000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16994000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 16994000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 50583000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 29438500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 80021500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 50583000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 29438500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 80021500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_misses::cpu.data 144 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 144 # number of ReadExReq misses
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 630 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadCleanReq_misses::total 630 # number of ReadCleanReq misses
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 201 # number of ReadSharedReq misses
+system.cpu.l2cache.ReadSharedReq_misses::total 201 # number of ReadSharedReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 630 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 345 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 630 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 345 # number of overall misses
+system.cpu.l2cache.overall_misses::total 975 # number of overall misses
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12038000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 12038000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50862500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 50862500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17374000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 17374000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 50862500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 29412000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 80274500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 50862500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 29412000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 80274500 # number of overall miss cycles
system.cpu.l2cache.WritebackClean_accesses::writebacks 8 # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total 8 # number of WritebackClean accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 634 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadCleanReq_accesses::total 634 # number of ReadCleanReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 634 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 344 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 978 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 634 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 344 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 978 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 144 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 144 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 632 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadCleanReq_accesses::total 632 # number of ReadCleanReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 201 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.ReadSharedReq_accesses::total 201 # number of ReadSharedReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 632 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 345 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 632 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 345 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996845 # miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996845 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996835 # miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996835 # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996845 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996835 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996845 # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996835 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85236.301370 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85236.301370 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80036.392405 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80036.392405 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85828.282828 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85828.282828 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 81989.241803 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80036.392405 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85577.034884 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 81989.241803 # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83597.222222 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83597.222222 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80734.126984 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80734.126984 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86437.810945 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86437.810945 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80734.126984 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85252.173913 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82332.820513 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80734.126984 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85252.173913 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82332.820513 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 632 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 632 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 632 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 344 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 976 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 632 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 344 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 976 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10984500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10984500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44263000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44263000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15014000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15014000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44263000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25998500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 70261500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44263000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25998500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 70261500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 630 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 630 # number of ReadCleanReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 201 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 201 # number of ReadSharedReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 630 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 345 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 630 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 345 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10598000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10598000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 44562500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 44562500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15364000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15364000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 44562500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25962000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 70524500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 44562500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25962000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 70524500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996845 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996835 # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996845 # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996835 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75236.301370 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75236.301370 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70036.392405 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70036.392405 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75828.282828 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75828.282828 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70036.392405 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75577.034884 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71989.241803 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73597.222222 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73597.222222 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70734.126984 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70734.126984 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76437.810945 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76437.810945 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70734.126984 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75252.173913 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72332.820513 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 986 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.tot_requests 985 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 833 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean 8 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 634 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 1964 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 63104 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 632 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 201 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1272 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 690 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1962 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22080 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 63040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 978 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.002045 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.045198 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.002047 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.045222 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 976 99.80% 99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 975 99.80% 99.80% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 2 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 978 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 501000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 500500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 951000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 948000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 3.8 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 516000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 517500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%)
-system.membus.trans_dist::ReadResp 830 # Transaction distribution
-system.membus.trans_dist::ReadExReq 146 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 830 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1952 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1952 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 62464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadResp 831 # Transaction distribution
+system.membus.trans_dist::ReadExReq 144 # Transaction distribution
+system.membus.trans_dist::ReadExResp 144 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 831 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 976 # Request fanout histogram
+system.membus.snoop_fanout::samples 975 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 976 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 976 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1189000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 975 # Request fanout histogram
+system.membus.reqLayer0.occupancy 1186000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 4.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 5195000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 20.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 5196500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 21.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:15
-gem5 executing on zizzer, pid 34054
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:58:08
+gem5 executing on phenom, pid 28209
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 405501000 because target called exit()
+Exiting @ tick 405365000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000406 # Number of seconds simulated
-sim_ticks 405501000 # Number of ticks simulated
-final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000405 # Number of seconds simulated
+sim_ticks 405365000 # Number of ticks simulated
+final_tick 405365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86197 # Simulator instruction rate (inst/s)
-host_op_rate 86167 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5423806428 # Simulator tick rate (ticks/s)
-host_mem_usage 613516 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 6440 # Number of instructions simulated
-sim_ops 6440 # Number of ops (including micro ops) simulated
+host_inst_rate 83628 # Simulator instruction rate (inst/s)
+host_op_rate 83610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5251060650 # Simulator tick rate (ticks/s)
+host_mem_usage 610048 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+sim_insts 6453 # Number of instructions simulated
+sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.bytes_read::cpu.inst 25800 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 8828 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 34628 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 25800 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 25800 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.inst 25852 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.data 8844 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::total 34696 # Number of bytes read from this memory
+system.mem_ctrl.bytes_inst_read::cpu.inst 25852 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_inst_read::total 25852 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst 6450 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 1188 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 7638 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.inst 6463 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.data 1190 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::total 7653 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 63624997 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 21770600 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 85395597 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 63624997 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 63624997 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data 16512906 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total 16512906 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 63624997 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 38283506 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 101908503 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 7639 # Number of read requests accepted
+system.mem_ctrl.bw_read::cpu.inst 63774623 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 21817374 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 85591997 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 63774623 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 63774623 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data 16518446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total 16518446 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 63774623 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 38335821 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 102110444 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.readReqs 7654 # Number of read requests accepted
system.mem_ctrl.writeReqs 865 # Number of write requests accepted
-system.mem_ctrl.readBursts 7639 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrl.readBursts 7654 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 477632 # Total number of bytes read from DRAM
-system.mem_ctrl.bytesReadWrQ 11264 # Total number of bytes read from write queue
+system.mem_ctrl.bytesReadDRAM 477504 # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadWrQ 12352 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 34632 # Total read bytes from the system interface side
+system.mem_ctrl.bytesReadSys 34700 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side
-system.mem_ctrl.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrl.servicedByWrQ 193 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::3 787 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::4 776 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::3 800 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::4 763 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::10 253 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::15 156 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::15 158 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::4 27 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::5 6 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::4 18 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::5 8 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::10 6 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::13 14 # Per bank write bursts
-system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::13 21 # Per bank write bursts
+system.mem_ctrl.perBankWrBursts::14 43 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 405425000 # Total gap between requests
+system.mem_ctrl.totGap 405289000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 6620 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::3 1019 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::2 6633 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::3 1021 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2)
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 7463 # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0 7461 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 775 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 623.649032 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 407.696259 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 407.140251 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 158 20.39% 20.39% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 63 8.13% 28.52% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 48 6.19% 34.71% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 41 5.29% 40.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 47 6.06% 46.06% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 28 3.61% 49.68% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 28 3.61% 53.29% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 33 4.26% 57.55% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 329 42.45% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 775 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples 762 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 634.288714 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 419.900652 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 405.302633 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 146 19.16% 19.16% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 69 9.06% 28.22% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 39 5.12% 33.33% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 43 5.64% 38.98% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 44 5.77% 44.75% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767 27 3.54% 48.29% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895 31 4.07% 52.36% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023 30 3.94% 56.30% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151 333 43.70% 100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total 762 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean 1159.333333 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean 1053.861325 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev 505.634519 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1344-1407 1 16.67% 66.67% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1792-1855 1 16.67% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean 1203.833333 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean 1052.985580 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev 699.444184 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::512-639 2 33.33% 33.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::896-1023 1 16.67% 50.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1152-1279 1 16.67% 66.67% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1408-1535 1 16.67% 83.33% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::2432-2559 1 16.67% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat 26448250 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 166379500 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 37315000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 3543.92 # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat 26088750 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 165982500 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat 37305000 # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat 3496.68 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 22293.92 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 1177.88 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 15.15 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 85.41 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 16.51 # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat 22246.68 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW 1177.96 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW 15.16 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys 85.60 # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys 16.52 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 23.37 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 6696 # Number of row buffer hits during reads
-system.mem_ctrl.writeRowHits 87 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads
-system.mem_ctrl.writeRowHitRate 73.73 # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 47674.62 # Average gap between requests
-system.mem_ctrl.pageHitRate 89.47 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 3439800 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 1876875 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 37268400 # Energy for read commands per rank (pJ)
-system.mem_ctrl_0.writeEnergy 213840 # Energy for write commands per rank (pJ)
+system.mem_ctrl.avgWrQLen 24.34 # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits 6706 # Number of row buffer hits during reads
+system.mem_ctrl.writeRowHits 88 # Number of row buffer hits during writes
+system.mem_ctrl.readRowHitRate 89.88 # Row buffer hit rate for reads
+system.mem_ctrl.writeRowHitRate 74.58 # Row buffer hit rate for writes
+system.mem_ctrl.avgGap 47574.72 # Average gap between requests
+system.mem_ctrl.pageHitRate 89.64 # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy 3333960 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy 1819125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 37284000 # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.writeEnergy 168480 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 264293325 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 11250750 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 344788110 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 851.023979 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 15542500 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 262765440 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 12591750 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 344407875 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 850.082840 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 17896000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 376096250 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 373743250 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 2419200 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 1320000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_1.readEnergy 20888400 # Energy for read commands per rank (pJ)
-system.mem_ctrl_1.writeEnergy 408240 # Energy for write commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 2426760 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 1324125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.readEnergy 20872800 # Energy for read commands per rank (pJ)
+system.mem_ctrl_1.writeEnergy 453600 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 228585105 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 42573750 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 322639815 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 796.356403 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 69100250 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 229562370 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 41716500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 322801275 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 796.754927 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 67586500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 322538500 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 324052250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1188 # DTB read hits
+system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1195 # DTB read accesses
+system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2053 # DTB hits
+system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2063 # DTB accesses
-system.cpu.itb.fetch_hits 6451 # ITB hits
+system.cpu.dtb.data_accesses 2065 # DTB accesses
+system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6468 # ITB accesses
+system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 405501 # number of cpu cycles simulated
+system.cpu.numCycles 405365 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6440 # Number of instructions committed
-system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
+system.cpu.committedInsts 6453 # Number of instructions committed
+system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6368 # number of integer instructions
+system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2063 # number of memory refs
-system.cpu.num_load_insts 1195 # Number of load instructions
+system.cpu.num_mem_refs 2065 # number of memory refs
+system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 405501 # Number of busy cycles
+system.cpu.num_busy_cycles 405365 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1054 # Number of branches fetched
+system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6450 # Class of executed instruction
-system.membus.trans_dist::ReadReq 7639 # Transaction distribution
-system.membus.trans_dist::ReadResp 7638 # Transaction distribution
+system.cpu.op_class::total 6463 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7654 # Transaction distribution
+system.membus.trans_dist::ReadResp 7653 # Transaction distribution
system.membus.trans_dist::WriteReq 865 # Transaction distribution
system.membus.trans_dist::WriteResp 865 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12901 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 17007 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15524 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 41324 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12927 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4110 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 17037 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25852 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15540 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 41392 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8504 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.758584 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.427967 # Request fanout histogram
+system.membus.snoop_fanout::samples 8519 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.758775 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.427852 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2053 24.14% 24.14% # Request fanout histogram
-system.membus.snoop_fanout::1 6451 75.86% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2055 24.12% 24.12% # Request fanout histogram
+system.membus.snoop_fanout::1 6464 75.88% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 8504 # Request fanout histogram
-system.membus.reqLayer0.occupancy 9369000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 8519 # Request fanout histogram
+system.membus.reqLayer0.occupancy 9384000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 14662500 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 14690750 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3576750 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3574500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:14
-gem5 executing on zizzer, pid 34037
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
+gem5 compiled Mar 14 2016 21:54:46
+gem5 started Mar 14 2016 21:56:34
+gem5 executing on phenom, pid 28126
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 61610000 because target called exit()
+Exiting @ tick 61470000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000062 # Number of seconds simulated
-sim_ticks 61610000 # Number of ticks simulated
-final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000061 # Number of seconds simulated
+sim_ticks 61470000 # Number of ticks simulated
+final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98323 # Simulator instruction rate (inst/s)
-host_op_rate 98283 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 939896452 # Simulator tick rate (ticks/s)
-host_mem_usage 618136 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 6440 # Number of instructions simulated
-sim_ops 6440 # Number of ops (including micro ops) simulated
+host_inst_rate 62593 # Simulator instruction rate (inst/s)
+host_op_rate 62569 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 595804848 # Simulator tick rate (ticks/s)
+host_mem_usage 614668 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 6453 # Number of instructions simulated
+sim_ops 6453 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrl.readReqs 446 # Number of read requests accepted
system.mem_ctrl.writeReqs 0 # Number of write requests accepted
system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 61360000 # Total gap between requests
+system.mem_ctrl.totGap 61220000 # Total gap between requests
system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 180.864884 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 259.243949 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 27 28.42% 28.42% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 31 32.63% 61.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 11 11.58% 72.63% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 8 8.42% 81.05% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
-system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst
-system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s
+system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s
system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage
-system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads
+system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage
+system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
+system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 137578.48 # Average gap between requests
-system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
-system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
+system.mem_ctrl.avgGap 137264.57 # Average gap between requests
+system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined
+system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 43032375 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 785.782110 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 256750 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 52700750 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 214500 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 35929665 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 1341000 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 42928005 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 783.876287 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 2295000 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 51042000 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1188 # DTB read hits
+system.cpu.dtb.read_hits 1190 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1195 # DTB read accesses
+system.cpu.dtb.read_accesses 1197 # DTB read accesses
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2053 # DTB hits
+system.cpu.dtb.data_hits 2055 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2063 # DTB accesses
-system.cpu.itb.fetch_hits 6451 # ITB hits
+system.cpu.dtb.data_accesses 2065 # DTB accesses
+system.cpu.itb.fetch_hits 6464 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6468 # ITB accesses
+system.cpu.itb.fetch_accesses 6481 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 61610 # number of cpu cycles simulated
+system.cpu.numCycles 61470 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6440 # Number of instructions committed
-system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
+system.cpu.committedInsts 6453 # Number of instructions committed
+system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6368 # number of integer instructions
+system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6380 # number of integer instructions
system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
+system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2063 # number of memory refs
-system.cpu.num_load_insts 1195 # Number of load instructions
+system.cpu.num_mem_refs 2065 # number of memory refs
+system.cpu.num_load_insts 1197 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 61610 # Number of busy cycles
+system.cpu.num_busy_cycles 61470 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 1054 # Number of branches fetched
+system.cpu.Branches 1060 # Number of branches fetched
system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
-system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
-system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
-system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
-system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
+system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
+system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
+system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
+system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 6450 # Class of executed instruction
+system.cpu.op_class::total 6463 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1885 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1885 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1885 # number of overall hits
-system.cpu.dcache.overall_hits::total 1885 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits
+system.cpu.dcache.overall_hits::total 1887 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.dcache.overall_misses::total 168 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9733000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9733000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7588000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7588000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17321000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17321000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17321000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17321000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1188 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1188 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2053 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2053 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2053 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2053 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.081831 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.081831 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.081831 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.081831 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102452.631579 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 102452.631579 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103945.205479 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 103945.205479 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 103101.190476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 103101.190476 # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9543000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9543000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7442000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7442000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16985000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 16985000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16985000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 16985000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079966 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079966 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.081831 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.081831 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100452.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100452.631579 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 62 # number of replacements
-system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 13183 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits
-system.cpu.icache.overall_hits::total 6170 # number of overall hits
+system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits
+system.cpu.icache.overall_hits::total 6183 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
system.cpu.icache.overall_misses::total 281 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
-system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use
+system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
system.l2cache.overall_misses::cpu.inst 278 # number of overall misses
system.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.l2cache.overall_misses::total 446 # number of overall misses
-system.l2cache.ReadExReq_miss_latency::cpu.data 7223000 # number of ReadExReq miss cycles
-system.l2cache.ReadExReq_miss_latency::total 7223000 # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26711000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.data 9258000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total 35969000 # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst 26711000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::cpu.data 16481000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total 43192000 # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst 26711000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::cpu.data 16481000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::total 43192000 # number of overall miss cycles
+system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles
+system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles
+system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses)
system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses
system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses
-system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98945.205479 # average ReadExReq miss latency
-system.l2cache.ReadExReq_avg_miss_latency::total 98945.205479 # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96082.733813 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97452.631579 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 96431.635389 # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 96843.049327 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 96843.049327 # average overall miss latency
+system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency
+system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
-system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5763000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadExReq_mshr_miss_latency::total 5763000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21151000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7358000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total 28509000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst 21151000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.data 13121000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total 34272000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst 21151000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.data 13121000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total 34272000 # number of overall MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses
system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses
-system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78945.205479 # average ReadExReq mshr miss latency
-system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78945.205479 # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76082.733813 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77452.631579 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76431.635389 # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency
+system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 373 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
+Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:13
-gem5 executing on zizzer, pid 60583
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29862
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 367783000 because target called exit()
+Exiting @ tick 368887000 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000368 # Number of seconds simulated
-sim_ticks 367783000 # Number of ticks simulated
-final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000369 # Number of seconds simulated
+sim_ticks 368887000 # Number of ticks simulated
+final_tick 368887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91194 # Simulator instruction rate (inst/s)
-host_op_rate 91153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5958550453 # Simulator tick rate (ticks/s)
-host_mem_usage 611392 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 25687 # Simulator instruction rate (inst/s)
+host_op_rate 25686 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1679592961 # Simulator tick rate (ticks/s)
+host_mem_usage 607900 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.mem_ctrl.bytes_read::cpu.inst 22500 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::cpu.data 4289 # Number of bytes read from this memory
-system.mem_ctrl.bytes_read::total 26789 # Number of bytes read from this memory
-system.mem_ctrl.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory
-system.mem_ctrl.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.inst 22568 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::cpu.data 4301 # Number of bytes read from this memory
+system.mem_ctrl.bytes_read::total 26869 # Number of bytes read from this memory
+system.mem_ctrl.bytes_inst_read::cpu.inst 22568 # Number of instructions bytes read from this memory
+system.mem_ctrl.bytes_inst_read::total 22568 # Number of instructions bytes read from this memory
system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory
system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory
-system.mem_ctrl.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::cpu.data 1132 # Number of read requests responded to by this memory
-system.mem_ctrl.num_reads::total 6757 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.inst 5642 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::cpu.data 1135 # Number of read requests responded to by this memory
+system.mem_ctrl.num_reads::total 6777 # Number of read requests responded to by this memory
system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory
system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory
-system.mem_ctrl.bw_read::cpu.inst 61177379 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::cpu.data 11661768 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_read::total 72839147 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::cpu.inst 61177379 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_inst_read::total 61177379 # Instruction read bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::cpu.data 9791100 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_write::total 9791100 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.inst 61177379 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::cpu.data 21452868 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.bw_total::total 82630247 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrl.readReqs 6758 # Number of read requests accepted
+system.mem_ctrl.bw_read::cpu.inst 61178627 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::cpu.data 11659397 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_read::total 72838024 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::cpu.inst 61178627 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_inst_read::total 61178627 # Instruction read bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::cpu.data 9761797 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_write::total 9761797 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.inst 61178627 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::cpu.data 21421194 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.bw_total::total 82599821 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrl.readReqs 6778 # Number of read requests accepted
system.mem_ctrl.writeReqs 901 # Number of write requests accepted
-system.mem_ctrl.readBursts 6758 # Number of DRAM read bursts, including those serviced by the write queue
+system.mem_ctrl.readBursts 6778 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrl.bytesReadDRAM 426368 # Total number of bytes read from DRAM
+system.mem_ctrl.bytesReadDRAM 427648 # Total number of bytes read from DRAM
system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue
system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM
-system.mem_ctrl.bytesReadSys 26793 # Total read bytes from the system interface side
+system.mem_ctrl.bytesReadSys 26873 # Total read bytes from the system interface side
system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side
system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one
system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::9 1211 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::9 1212 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::13 396 # Per bank write bursts
-system.mem_ctrl.perBankRdBursts::14 1409 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::13 398 # Per bank write bursts
+system.mem_ctrl.perBankRdBursts::14 1426 # Per bank write bursts
system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts
system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrl.totGap 367707000 # Total gap between requests
+system.mem_ctrl.totGap 368811000 # Total gap between requests
system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2)
system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2)
-system.mem_ctrl.readPktSize::2 6678 # Read request sizes (log2)
+system.mem_ctrl.readPktSize::2 6698 # Read request sizes (log2)
system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
-system.mem_ctrl.rdQLenPdf::0 6662 # What read queue length does an incoming req see
+system.mem_ctrl.rdQLenPdf::0 6682 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrl.bytesPerActivate::samples 842 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::mean 509.263658 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::gmean 293.556275 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::stdev 414.582189 # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::0-127 268 31.83% 31.83% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::128-255 81 9.62% 41.45% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::256-383 48 5.70% 47.15% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::384-511 49 5.82% 52.97% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::512-639 36 4.28% 57.24% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::640-767 49 5.82% 63.06% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::768-895 19 2.26% 65.32% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::896-1023 21 2.49% 67.81% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::1024-1151 271 32.19% 100.00% # Bytes accessed per row activation
-system.mem_ctrl.bytesPerActivate::total 842 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::mean 506.270907 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::gmean 291.216794 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::stdev 415.367861 # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::0-127 272 32.04% 32.04% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::128-255 76 8.95% 40.99% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::256-383 61 7.18% 48.17% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::384-511 46 5.42% 53.59% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::512-639 36 4.24% 57.83% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::640-767 42 4.95% 62.78% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::768-895 24 2.83% 65.61% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 67.37% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::1024-1151 277 32.63% 100.00% # Bytes accessed per row activation
+system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation
system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::mean 1344.750000 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::gmean 1258.849963 # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::stdev 502.036104 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::mean 1349.750000 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::gmean 1262.645152 # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::stdev 506.185325 # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrl.rdPerTurnAround::1600-1663 1 25.00% 75.00% # Reads before turning the bus around for writes
+system.mem_ctrl.rdPerTurnAround::1664-1727 1 25.00% 75.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes
system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads
-system.mem_ctrl.totQLat 27926000 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 152838500 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrl.totBusLat 33310000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 4191.83 # Average queueing delay per DRAM burst
+system.mem_ctrl.totQLat 28067250 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 153354750 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totBusLat 33410000 # Total ticks spent in databus transfers
+system.mem_ctrl.avgQLat 4200.43 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 22941.83 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgMemAccLat 22950.43 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBW 11.14 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrl.avgWrBW 11.10 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s
-system.mem_ctrl.avgWrBWSys 9.79 # Average system write bandwidth in MiByte/s
+system.mem_ctrl.avgWrBWSys 9.76 # Average system write bandwidth in MiByte/s
system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage
system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads
system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes
system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrl.avgWrQLen 23.24 # Average write queue length when enqueuing
-system.mem_ctrl.readRowHits 5822 # Number of row buffer hits during reads
+system.mem_ctrl.avgWrQLen 23.19 # Average write queue length when enqueuing
+system.mem_ctrl.readRowHits 5834 # Number of row buffer hits during reads
system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes
-system.mem_ctrl.readRowHitRate 87.39 # Row buffer hit rate for reads
+system.mem_ctrl.readRowHitRate 87.31 # Row buffer hit rate for reads
system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes
-system.mem_ctrl.avgGap 48009.79 # Average gap between requests
-system.mem_ctrl.pageHitRate 87.03 # Row buffer hit rate, read and write combined
+system.mem_ctrl.avgGap 48028.52 # Average gap between requests
+system.mem_ctrl.pageHitRate 86.95 # Row buffer hit rate, read and write combined
system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ)
system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ)
-system.mem_ctrl_0.readEnergy 8821800 # Energy for read commands per rank (pJ)
+system.mem_ctrl_0.readEnergy 8806200 # Energy for read commands per rank (pJ)
system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ)
system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_0.actBackEnergy 136778625 # Energy for active background per rank (pJ)
-system.mem_ctrl_0.preBackEnergy 99747000 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_0.totalEnergy 270924525 # Total energy per rank (pJ)
-system.mem_ctrl_0.averagePower 739.798888 # Core power per rank (mW)
-system.mem_ctrl_0.memoryStateTime::IDLE 164402500 # Time in different power states
+system.mem_ctrl_0.actBackEnergy 143993115 # Energy for active background per rank (pJ)
+system.mem_ctrl_0.preBackEnergy 93418500 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_0.totalEnergy 271794915 # Total energy per rank (pJ)
+system.mem_ctrl_0.averagePower 742.175615 # Core power per rank (mW)
+system.mem_ctrl_0.memoryStateTime::IDLE 153996500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_0.memoryStateTime::ACT 189605000 # Time in different power states
+system.mem_ctrl_0.memoryStateTime::ACT 200230500 # Time in different power states
system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ)
-system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ)
+system.mem_ctrl_1.actEnergy 5344920 # Energy for activate commands per rank (pJ)
+system.mem_ctrl_1.preEnergy 2916375 # Energy for precharge commands per rank (pJ)
system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ)
system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ)
system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ)
-system.mem_ctrl_1.actBackEnergy 246879540 # Energy for active background per rank (pJ)
-system.mem_ctrl_1.preBackEnergy 3167250 # Energy for precharge background per rank (pJ)
-system.mem_ctrl_1.totalEnergy 325423935 # Total energy per rank (pJ)
-system.mem_ctrl_1.averagePower 888.617467 # Core power per rank (mW)
-system.mem_ctrl_1.memoryStateTime::IDLE 3404750 # Time in different power states
+system.mem_ctrl_1.actBackEnergy 246623040 # Energy for active background per rank (pJ)
+system.mem_ctrl_1.preBackEnergy 3392250 # Energy for precharge background per rank (pJ)
+system.mem_ctrl_1.totalEnergy 325462545 # Total energy per rank (pJ)
+system.mem_ctrl_1.averagePower 888.722897 # Core power per rank (mW)
+system.mem_ctrl_1.memoryStateTime::IDLE 3452250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states
system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrl_1.memoryStateTime::ACT 350602750 # Time in different power states
+system.mem_ctrl_1.memoryStateTime::ACT 350555250 # Time in different power states
system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 7 # Number of system calls
-system.cpu.numCycles 367783 # number of cpu cycles simulated
+system.cpu.numCycles 368887 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 367783 # Number of busy cycles
+system.cpu.num_busy_cycles 368887 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
-system.membus.trans_dist::ReadReq 6758 # Transaction distribution
-system.membus.trans_dist::ReadResp 6757 # Transaction distribution
+system.cpu.op_class::total 5642 # Class of executed instruction
+system.membus.trans_dist::ReadReq 6778 # Transaction distribution
+system.membus.trans_dist::ReadResp 6777 # Transaction distribution
system.membus.trans_dist::WriteReq 901 # Transaction distribution
system.membus.trans_dist::WriteResp 901 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11251 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 15317 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22500 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7890 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11285 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4072 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 15357 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22568 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7902 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 30470 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 7659 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.734561 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.441596 # Request fanout histogram
+system.membus.snoop_fanout::samples 7679 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.734861 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.441436 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 2033 26.54% 26.54% # Request fanout histogram
-system.membus.snoop_fanout::1 5626 73.46% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 2036 26.51% 26.51% # Request fanout histogram
+system.membus.snoop_fanout::1 5643 73.49% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 7659 # Request fanout histogram
-system.membus.reqLayer0.occupancy 8560000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 7679 # Request fanout histogram
+system.membus.reqLayer0.occupancy 8580000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer0.occupancy 12820000 # Layer occupancy (ticks)
+system.membus.respLayer0.occupancy 12857500 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 3.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3545250 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 3555500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=0
frontend_latency=1
+point_of_coherency=false
response_latency=1
snoop_filter=system.l2bus.snoop_filter
snoop_response_latency=1
clusivity=mostly_incl
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
eventq_index=0
forward_latency=4
frontend_latency=3
+point_of_coherency=true
response_latency=2
snoop_filter=Null
snoop_response_latency=4
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
warn: Sockets disabled, not accepting gdb connections
-warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff
+Redirecting stdout to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:17:41
-gem5 started Jan 21 2016 14:18:14
-gem5 executing on zizzer, pid 60586
-command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
+gem5 compiled Mar 14 2016 22:04:10
+gem5 started Mar 14 2016 22:06:34
+gem5 executing on phenom, pid 29863
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level
Global frequency set at 1000000000000 ticks per second
Beginning simulation!
sim_ticks 58892000 # Number of ticks simulated
final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88343 # Simulator instruction rate (inst/s)
-host_op_rate 88311 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 924415589 # Simulator tick rate (ticks/s)
-host_mem_usage 616028 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
-sim_insts 5624 # Number of instructions simulated
-sim_ops 5624 # Number of ops (including micro ops) simulated
+host_inst_rate 44023 # Simulator instruction rate (inst/s)
+host_op_rate 44007 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 459268108 # Simulator tick rate (ticks/s)
+host_mem_usage 612532 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
+sim_insts 5641 # Number of instructions simulated
+sim_ops 5641 # Number of ops (including micro ops) simulated
system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation
system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation
-system.mem_ctrl.totQLat 3878500 # Total ticks spent queuing
-system.mem_ctrl.totMemAccLat 11941000 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrl.totQLat 3838500 # Total ticks spent queuing
+system.mem_ctrl.totMemAccLat 11901000 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers
-system.mem_ctrl.avgQLat 9019.77 # Average queueing delay per DRAM burst
+system.mem_ctrl.avgQLat 8926.74 # Average queueing delay per DRAM burst
system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.mem_ctrl.avgMemAccLat 27769.77 # Average memory access latency per DRAM burst
+system.mem_ctrl.avgMemAccLat 27676.74 # Average memory access latency per DRAM burst
system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s
system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s
system.cpu.numCycles 58892 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5624 # Number of instructions committed
-system.cpu.committedOps 5624 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses
+system.cpu.committedInsts 5641 # Number of instructions committed
+system.cpu.committedOps 5641 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
-system.cpu.num_func_calls 190 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4944 # number of integer instructions
+system.cpu.num_func_calls 191 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4957 # number of integer instructions
system.cpu.num_fp_insts 2 # number of float instructions
-system.cpu.num_int_register_reads 7054 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3281 # number of times the integer registers were written
+system.cpu.num_int_register_reads 7072 # number of times the integer registers were read
+system.cpu.num_int_register_writes 3291 # number of times the integer registers were written
system.cpu.num_fp_register_reads 3 # number of times the floating registers were read
system.cpu.num_fp_register_writes 1 # number of times the floating registers were written
-system.cpu.num_mem_refs 2034 # number of memory refs
-system.cpu.num_load_insts 1132 # Number of load instructions
+system.cpu.num_mem_refs 2037 # number of memory refs
+system.cpu.num_load_insts 1135 # Number of load instructions
system.cpu.num_store_insts 902 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 58892 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.Branches 883 # Number of branches fetched
-system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction
-system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction
-system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction
-system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction
-system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction
-system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction
+system.cpu.Branches 886 # Number of branches fetched
+system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction
+system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction
+system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction
+system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction
+system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction
+system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction
+system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 5625 # Class of executed instruction
+system.cpu.op_class::total 5642 # Class of executed instruction
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 86.277492 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 86.268662 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 86.277492 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.084255 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.084255 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 86.268662 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.084247 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.084247 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
-system.cpu.dcache.overall_hits::total 1896 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits
+system.cpu.dcache.overall_hits::total 1899 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency
system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 94 # number of replacements
-system.cpu.icache.tags.tagsinuse 110.157629 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 5329 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 110.145403 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 5346 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 17.942761 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 18 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 110.157629 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.430303 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.430303 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 110.145403 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.430255 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.430255 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 11549 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 11549 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 5329 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5329 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5329 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5329 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5329 # number of overall hits
-system.cpu.icache.overall_hits::total 5329 # number of overall hits
+system.cpu.icache.tags.tag_accesses 11583 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 11583 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 5346 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5346 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5346 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5346 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5346 # number of overall hits
+system.cpu.icache.overall_hits::total 5346 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses
system.cpu.icache.overall_misses::total 297 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 30270000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 30270000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 30270000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 30270000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 30270000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 30270000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052791 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.052791 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.052791 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.052791 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.052791 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.052791 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101919.191919 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 101919.191919 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 101919.191919 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 101919.191919 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 30230000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 30230000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 30230000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 30230000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 30230000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 30230000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052632 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.052632 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.052632 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.052632 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.052632 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.052632 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101784.511785 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 101784.511785 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 101784.511785 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 101784.511785 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 101784.511785 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29676000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 29676000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29676000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 29676000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29676000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 29676000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052791 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.052791 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.052791 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99919.191919 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99919.191919 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29636000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 29636000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29636000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 29636000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29636000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 29636000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052632 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.052632 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052632 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.052632 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99784.511785 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99784.511785 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99784.511785 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 99784.511785 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2bus.snoop_filter.tot_requests 528 # Total number of requests made to the snoop filter.
system.l2bus.snoop_filter.hit_single_requests 94 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks)
system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%)
system.l2cache.tags.replacements 0 # number of replacements
-system.l2cache.tags.tagsinuse 183.881600 # Cycle average of tags in use
+system.l2cache.tags.tagsinuse 183.861903 # Cycle average of tags in use
system.l2cache.tags.total_refs 98 # Total number of references to valid blocks.
system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks.
system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2cache.tags.occ_blocks::cpu.inst 130.357827 # Average occupied blocks per requestor
-system.l2cache.tags.occ_blocks::cpu.data 53.523773 # Average occupied blocks per requestor
-system.l2cache.tags.occ_percent::cpu.inst 0.031826 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::cpu.data 0.013067 # Average percentage of cache occupancy
-system.l2cache.tags.occ_percent::total 0.044893 # Average percentage of cache occupancy
+system.l2cache.tags.occ_blocks::cpu.inst 130.345601 # Average occupied blocks per requestor
+system.l2cache.tags.occ_blocks::cpu.data 53.516302 # Average occupied blocks per requestor
+system.l2cache.tags.occ_percent::cpu.inst 0.031823 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::cpu.data 0.013066 # Average percentage of cache occupancy
+system.l2cache.tags.occ_percent::total 0.044888 # Average percentage of cache occupancy
system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id
system.l2cache.overall_misses::total 430 # number of overall misses
system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles
system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28701000 # number of ReadSharedReq miss cycles
+system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28661000 # number of ReadSharedReq miss cycles
system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles
-system.l2cache.ReadSharedReq_miss_latency::total 37176000 # number of ReadSharedReq miss cycles
-system.l2cache.demand_miss_latency::cpu.inst 28701000 # number of demand (read+write) miss cycles
+system.l2cache.ReadSharedReq_miss_latency::total 37136000 # number of ReadSharedReq miss cycles
+system.l2cache.demand_miss_latency::cpu.inst 28661000 # number of demand (read+write) miss cycles
system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles
-system.l2cache.demand_miss_latency::total 42190000 # number of demand (read+write) miss cycles
-system.l2cache.overall_miss_latency::cpu.inst 28701000 # number of overall miss cycles
+system.l2cache.demand_miss_latency::total 42150000 # number of demand (read+write) miss cycles
+system.l2cache.overall_miss_latency::cpu.inst 28661000 # number of overall miss cycles
system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles
-system.l2cache.overall_miss_latency::total 42190000 # number of overall miss cycles
+system.l2cache.overall_miss_latency::total 42150000 # number of overall miss cycles
system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses)
system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses
system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency
system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97955.631399 # average ReadSharedReq miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97819.112628 # average ReadSharedReq miss latency
system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency
-system.l2cache.ReadSharedReq_avg_miss_latency::total 97831.578947 # average ReadSharedReq miss latency
-system.l2cache.demand_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
+system.l2cache.ReadSharedReq_avg_miss_latency::total 97726.315789 # average ReadSharedReq miss latency
+system.l2cache.demand_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
-system.l2cache.demand_avg_miss_latency::total 98116.279070 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency
+system.l2cache.demand_avg_miss_latency::total 98023.255814 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::cpu.inst 97819.112628 # average overall miss latency
system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency
-system.l2cache.overall_avg_miss_latency::total 98116.279070 # average overall miss latency
+system.l2cache.overall_avg_miss_latency::total 98023.255814 # average overall miss latency
system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses
system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22841000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22801000 # number of ReadSharedReq MSHR miss cycles
system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.ReadSharedReq_mshr_miss_latency::total 29576000 # number of ReadSharedReq MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::cpu.inst 22841000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.ReadSharedReq_mshr_miss_latency::total 29536000 # number of ReadSharedReq MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::cpu.inst 22801000 # number of demand (read+write) MSHR miss cycles
system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.demand_mshr_miss_latency::total 33590000 # number of demand (read+write) MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::cpu.inst 22841000 # number of overall MSHR miss cycles
+system.l2cache.demand_mshr_miss_latency::total 33550000 # number of demand (read+write) MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::cpu.inst 22801000 # number of overall MSHR miss cycles
system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles
-system.l2cache.overall_mshr_miss_latency::total 33590000 # number of overall MSHR miss cycles
+system.l2cache.overall_mshr_miss_latency::total 33550000 # number of overall MSHR miss cycles
system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses
system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses
system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency
system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77955.631399 # average ReadSharedReq mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77819.112628 # average ReadSharedReq mshr miss latency
system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency
-system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77831.578947 # average ReadSharedReq mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
+system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77726.315789 # average ReadSharedReq mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
-system.l2cache.demand_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency
+system.l2cache.demand_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77819.112628 # average overall mshr miss latency
system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency
-system.l2cache.overall_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency
+system.l2cache.overall_avg_mshr_miss_latency::total 78023.255814 # average overall mshr miss latency
system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 380 # Transaction distribution
system.membus.trans_dist::ReadExReq 50 # Transaction distribution
projects / gem5.git / commitdiff