[RS6000] Replace -mcpu with -mdejagnu-cpu

	* gcc.target/powerpc/pr93122.c: Replace -mcpu with -mdejagnu-cpu.
	* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/powerpc/pr93122.c b/gcc/testsuite/gcc.target/powerpc/pr93122.c
index 8ea4eb6a48bbe2974bef9ccf1f04191de741f1c2..97bcb0cea5ffe8df458f8653147c7aedf5faea70 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/pr93122.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr93122.c
@@ -1,7 +1,7 @@
 /* PR target/93122 */
 /* { dg-require-effective-target power10_ok } */
 /* { dg-do compile { target lp64 } } */
-/* { dg-options "-fstack-clash-protection -mprefixed -mcpu=power10" } */
+/* { dg-options "-fstack-clash-protection -mprefixed -mdejagnu-cpu=power10" } */
 
 void bar (char *);
 

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 6ac4ed2173f411a9999ec38092d0e292ed3736a3..6aa165c675cd5119874f98d0c725910fd1ff525e 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 05fedf77eb9022f9cade496b4983bd24d27fe1b0..9fdfa4a8b822c24278da0c7b8dad8e4bf31fa233 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index 6e952695905d5a6955d160c591c7aeacec103dea..a038e56c9cdd4d00c498a60306cfc5bc9dbe43f7 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index c2eb53d3bb2331ae522e1fa455c348e083d143b8..6f87e60ea417aae0639db6ee82c99f2e4b26d92b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,6 +1,6 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
-/* { dg-options "-mcpu=power10 -O2" } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 /* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor